EEE 329: VLSI I
VLSI FABRICATION PROCESS
LECTURE 2
AGENDA
• General Fabrication
Steps
• NMOS Fabrication
Process
• CMOS Fabrication
Process
NMOS
TRANSISTOR
STRUCTURE
3D View Cross sectional view
GENERAL FABRICATION STEPS
• Oxidation
• Photolithography
• Diffusion
• Chemical Vapor Deposition (CVD)
• Ion Implantation
• Metallization
OXIDATION
Oxidation is the process by which a thin layer of oxide is grown on the
surface of the semiconductor material.
This process is typically carried out by exposing the material to an oxidizing
gas, such as oxygen or water vapor, at high temperatures.
Two types of oxidation happens in VLSI process:
Thin oxidation (0.1μm)
Thick oxidation (1μm)
PHOTOLITHOGRAPHY
Photolithography (also known as optical lithography) is a process used in the manufacturing of
integrated circuits. It involves using light to transfer a pattern onto a substrate, typically a silicon
wafer.
The photolithography process typically involves the following:
Substrate Preparation: The process begins with preparing a substrate, usually made of silicon, silicon
dioxide, or another suitable material. The substrate is cleaned and may be coated with a thin layer
of photoresist, a photosensitive material that undergoes chemical changes when exposed to light.
Exposure: A photomask featuring a pattern corresponding to the desired features on the substrate,
is placed close to the photoresist-coated substrate. Ultraviolet (UV) or deep ultraviolet (DUV) light is
directed through the photomask, exposing specific regions of the photoresist. The exposure causes a
chemical transformation in the photoresist, rendering it either more soluble or less soluble, depending
on the type of photoresist used.
Development: The exposed photoresist uses a solvent, which selectively dissolves the altered areas,
leaving behind the desired pattern on the substrate.
Material Deposition or Etching: Depending on the application, the substrate may undergo further
processes, such as material deposition or etching. For the placement of gold nanoparticles, deposition
techniques would be of interest.
BASIC PHOTOLITHOGRAPY PROCESS
DIFFUSION
• Diffusion in VLSI is a process that introduces dopant atoms into semiconductor
material to create regions of controlled conductivity.
• Creating p+ region or n+ region on the substrate. By passing a gas with
impurities at high temperature into the substrate.
CHEMICAL VAPOR DEPOSITION (CVD)
• In VLSI manufacturing, Chemical Vapor Deposition (CVD) is a crucial process
used to deposit thin films of various materials like insulators, conductors, and
semiconductors onto a substrate (typically a silicon wafer) by introducing
gaseous precursors that react and decompose on the heated surface, creating
a precise and controlled film deposition at the atomic level.
• To create polysilicon at gate terminal, this CVD technique is used.
ION IMPLANTATION METALLIZATION
• Ion implantation is a process Metallization in VLSI is the
that is used of creating process of depositing metal
channel in the transistor layers on a silicon wafer to
between source and drain. create conductive pathways
• This process is mainly for that connect the circuits.
depletion type MOS.
NMOS FABRICATION PROCESS
• Step 1: Consider P-substrate.
• Step 2: Deposite oxide layer of 1μm using oxidation.
• Step 3: Apply Photoresist layer.
• Step 4: Apply uv rays through mask.
• Step 5: Etching (removing unwanted/soft area).
• Step 6: Using the oxidation, create SiO2 layer of 0.1μm on the substrate.
Using CVD, create polysilicon at the center.
• Step 7: Using photolithography, create window to diffuse n+ regions. Diffuse
n+ regions using diffusion.
• Step 8: Thick oxide layer is grown over all again and is then masked with
photoresist and etched to expose selected areas of polysilicon gate and the
drain and source areas where connections are to be made.
• Step 9: The whole chip then has metal (aluminum) deposited over its surface to
a thickness typically of 1μm. The metal layer is then masked and etched to
form the required interconnection pattern.
CMOS FABRICATION: NWELL PROCESS
CMOS FABRICATION: TWIN-TAB PROCESS
CONTACT DETAILS
Dr. Md. Hasan Maruf
Associate Professor, EEE, GUB
Email: [email protected]
