CS132 Roundup

aka “Step right up; step right up to the fantastical, majestical,

mystical module that is CS132 Computer Organisation and
Architecture!” https://warwick.ac.uk/fac/sci/dcs/teaching/material/cs132/
https://warwick.ac.uk/fac/sci/dcs/teaching/material/cs132/

29/11/2024 ● R0.21 ● Richard Kirk ([email protected])

CS132 Computer Organisation & Architecture
CS132 Computer Organisation & Architecture

Friday, 29 November 2024

Slide 2

01 Introduction to CS132

• Alan Turing and Moore’s Law

• Measure performance in terms of FLoating point Operations Per
second (FLOPs)
• There is a huge variety of processors (some we will see later)
• (Analogue) signals and how they can be converted to digital signals
• Fundamental components such as bits, bytes, words and busses

Bit Signals Bus Key terms to learn (Digital) High

(Digital) Low
FLOPs Byte Word Most Significant Bit (MSB) Least Significant Bit (LSB)
CS132 Computer Organisation & Architecture

Friday, 29 November 2024

Slide 3

02 Numeric Representation

• The difference between numeric representation and value

• How to convert between different bases
• Word sizes affect the range of values we can represent
• How to count in binary/octal/hex
• The different ways negative numbers can be represented
• How to add/subtract binary numbers

Octal Base Key terms to learn Biased Binary (numbers)

Two’s Complement Hexadecimal Overflow Hex Carry Signed Magnitude

CS132 Computer Organisation & Architecture

Friday, 29 November 2024

Slide 4

03 Numeric Representation 2

• The principles behind multiplication of 2 binary integers

• How to multiply 2 unsigned integers
• How to multiply 2 signed integers (using Signed Magnitude or Two’s
Complement)
• How factional numbers can be represented
• How 2 IEEE 754 Floating Point numbers can be added/subtracted

Fixed Point Booth’s Algorithm Key terms to learn Two’s Complement IEEE 754
Mantissa MSB
Exponent LSB Multiplication Sign Rounding Signed Magnitude
CS132 Computer Organisation & Architecture

Friday, 29 November 2024

Slide 5

04 Introduction to Digital Logic

• Applied Boolean functions to our binary data

• Different ways in which each Boolean function
can be represented (symbols, gates, PICs)
• Used Boolean Algebra, Truth Tables and
Karnaugh Maps (K-Maps) to simplify our logic

AND NOT Key terms to learn Truth Tables

OR XOR XNOR Logic Gates
NAND NOR 𝐴ҧ Karnaugh/K Maps
CS132 Computer Organisation & Architecture

Friday, 29 November 2024

Slide 9

05 Computational Logic

• Discussed the construction of logic gates using Universal Gates

• Explored the use of logic gates to build 1-bit half adders and 1-bit
full adders
• Chained 1-bit full adders to make an N-bit full adder
• Extended an N-bit full adder to do subtraction

Universal Gates Carryout Key terms to learn Carryin Z-Line

Overflow 1-bit half adder 1-bit full adder N-bit full adder N-bit full adder/subtactor
CS132 Computer Organisation & Architecture

Friday, 29 November 2024

Slide 10

06 Breadboard Exploration

• Explored what a decoder and an encoder do

• Explored how a decoder could be constructed
• You do not need to know how the breadboards work for the
exam!
• You do not need to know the chip ID’s or anything about them for
the exam!

Key terms to learn

Decoder Encoder
n x m notation
CS132 Computer Organisation & Architecture

Friday, 29 November 2024

Slide 11

07 Computational Logic 2
• Discussed why we might need a decoder/encoder → Addressing
• Discussed the difference between Active High and Active Low
• Explored Multiplexers and Demultiplexers (including there potential construction)
• Discussed 3 state logic, and how they can be used to connect/disconnect components
from the
• Discussed the differences between theory and physical logic gates
• Explored Logic Integrated Circuits

3-state buffers/logic Busses Key terms to learn Active High Multiplexers

PAL “Forbidden region” IC FPGA PLA Addressing Active Low Demultiplexers

CS132 Computer Organisation & Architecture

Friday, 29 November 2024

Slide 12

08 Sequential Logic

• Difference between computational and sequential logic

• Covered Flip-flops and Latches (and the differences)
• Discussed why enable lines are often included in Latches
• Discussed how many different Latches are designed
• Designed circuits to store data in registers and shift registers
• Designed a counter to count up
Enable Clock Latches Key terms to learn JK-type Flip-flops
Shift registers
Registers N-bit counters T-type SR-type D-type
CS132 Computer Organisation & Architecture

Friday, 29 November 2024

Slide 13

09 Introduction To Memory

• Lots of different factors to worry about Registers • Ultra-fast memory

Random Access
• Part of the CPU

when picking types of memory Cache • Very fast memory

• Stores program and data memory

• The Memory Hierarchy • Fast memory

Main Store • Stores program and data memory that can’t fit

• Explored Random Access Memory

in Cache

• Non-volatile memory

Sequential
Magnetic Disk • Stores program and data memory that

• Explored cache performance

Access
can't fit in Main Store

• Large and very s low memory

Tape Optical Disk
• Touched on memory organisation
• Infreq uent access and backup
storage

Capacity

Cache L2 Access Time Tape Key terms to learn PROM Sequential Access Hit Penalty
L1 L3 SRAM Cost per bit/byte Main Store Random Access EEPROM Designer’s Dilemma
DRAM Capacity Miss Penalty Registers Volatile ROM EPROM Coherency Cache Misses
CS132 Computer Organisation & Architecture

Friday, 29 November 2024

Slide 14

10 Long Term Memory

• HDD’s are spinning disks that can be accessed through an arm being
moved to the right place
• There is a collection of different magnetism strategies
• Optical Disks can handle massive errors
• Writing to optical disks can be permanent or rewritable

CD-R Return to Zero (RZ) Spiral Key terms to learn Seek Times
Phase Encoding (PE) Frame
CD-RW Infrared Return to Bias (RB) Non-Return to Zero One (NRZ1) Settle Sector Read Time
CD’s Data Encoding Sectors Rotational Latency Land HDD
DVD’s Lasers Tracks Preamble Pits Symbols
CS132 Computer Organisation & Architecture

Friday, 29 November 2024

Slide 15

11 Errors in Memory
• Noise can come from anywhere, and can effect our memory
• Single Errors can be fixed with Parity Bits (to an extent)
• Burst Errors can be fixed with checksums and ECC
• Hamming Codes allow for an error to be detected and corrected within a word
• Hadamard Codes allow for (potentially) lots of errors to be detected and
corrected

Parity Odd Parity Key terms to learn Hadamard Codes Distance

Noise Burst Errors ECC Hamming Codes [H]2
Even Parity Checksum In-Word Error Correction Codes Hamming(7, 4) [H]2n
CS132 Computer Organisation & Architecture

Friday, 29 November 2024

Slide 16

12 Introduction To Assembly

• Explored the Fetch-Decode-Execute cycle

• Discussed some initial components of a processor
• Explored an example assembly language → RISC-V
• Difference between coding languages, RTL and Assembly
• Different categories of assembly instructions

Fetch → Decode → Execute Key terms to learn Immediate Load

Registers Set Operand
ALU IR Machine Code
CU PC RTL 0x Opcode Store
Absolute Addressing Relative Addressing Shift Rotate Branch Jump Labels
CS132 Computer Organisation & Architecture

Friday, 29 November 2024

Slide 17

13 Introduction To C

• C is developed to be more human-readable and portable than

Assembly
• Only has 4 primitive data types, but does have modifiers
• Doesn’t have objects, but has structs
• Has conditionals (same as Java) and loops (slightly different to Java)
• Stores memory addresses for values and arrays and requires the
developer to do memory management
Segmentation float char Key terms to learn GDB calloc Stack
Fault double int free
public unsigned short malloc
printf Pointer long struct \0 realloc Heap
private signed
CS132 Computer Organisation & Architecture

Friday, 29 November 2024

Slide 18

14 Introduction To I/O

• Covered 2 types of I/O; Memory Mapped I/O and Direct Memory

Access
• Memory Mapped I/O → Particular memory addressed are related
to either an Input or and Output
• Direct Memory Access (DMA) → CPU is a bottleneck, so lets have a
smaller processor to handle this

Memory Mapped I/O DMA Key terms to learn I/O Bus (DMA)
Inputs DMAC Integrated DMA Burst Mode (DMA)
Outputs Busses Detached DMA Cycle Stealing Mode (DMA)
CS132 Computer Organisation & Architecture

Friday, 29 November 2024

Slide 19

15 Synchronous I/O

• Defined why we need synchronisation for I/O in some cases

• Polling → Check that the I/O device is ready to send data
• Handshaking → I/O device and processor communicate when ready
• Interrupts → I/O can tell the processor it is ready to send data,
processor pauses what it was doing and handles I/O device

Polling Handshaking Key terms to learn Interrupts Control Line

“Bust Wait” (Poling) Data Bus Closed-loop Synchronisation Nesting Scheduling
Interleaved Polling Open-ended Synchronisation Valid Line Non-Maskable Interrupts
CS132 Computer Organisation & Architecture

Friday, 29 November 2024

Slide 20

16 Case Study: Ethernet

• Discussed the history and concepts around 802.3 Ethernet
• Explored why Carrier-Sense Multiple Access with Collision Detection (CSMA/CD)
• Discussed copper vs. fibre, and the different categories (cat., straight through vs.
crossover, RJ45 vs. M12)
• Why copper wires use twisted pairs to reduce noise, and how noise can be removed
through shielding
• Discussed the need for Auto MDI-X, and how it works

Ethernet Coaxial cable Backoff Key terms to learn Twisted Pairs RJ45 M12 802.3
Auto MDI-X
Straight Through Copper cable Unshielded
BASE-T Frames Crossover Fibre cable Shielded
Carrier-Sense Multiple Access with Collision Detection (CSMA/CD) Cat EMI Emission EMI Absorption
CS132 Computer Organisation & Architecture

Friday, 29 November 2024

Slide 21

17 Processor Architecture

• Difference between Architecture and Organisation

• Explored key components of the processor, such as
• Arithmetic and Logic Unit (ALU) • Program Counter (PC)
• Control Unit (CU) • Instruction Register (IR)
• Defined and explored Turing completeness
• Defined Macro and Micro instructions
• Explored Hardware-based and Microprogrammed CUs
Macro Instructions Architecture Key terms to learn Organisation Micro Instructions
Program Counter Control Unit Hardware CU Microprogrammed CU Arithmetic and Logic Unit
μIR μinstruction Clock Pulses μaddress μprogram Propagation Delay μPC Instruction Register
Sequencer
CS132 Computer Organisation & Architecture

Friday, 29 November 2024

Slide 22

18 RISC & CISC Processor

• Reduced Instruction Set Computing

• Usually have a small, fixed-length instruction sets
• Will often use Hardware-based Control Units
• ARM processors are often RISC based processors
• Complex Instruction Set Computing → Often use μprogram-based
Control Units, so can have a much larger number of instructions
• Discussed Multithreading and Multicore systems
RISC MIPS x86 x86-64 Key terms to learn Simultaneous Registers CISC
Fixed-Width Instruction Sets Starvation Multithreading Multithreading
Thread Race Conditions Deadlock Multicore Hyperthreading Process Core
CS132 Computer Organisation & Architecture

Friday, 29 November 2024

Slide 23

22 Case Study: 68K

• Explored the structure of the registers and components

• Discussed the differences between RISC-V assembly and 68K assembly
• Many instructions have permutations (such as byte/word/long instructions)
• Differences in using immediate and differing bases
• Explored the instruction set and memory addressing modes for 68K
• Explored subroutines and how they work in the 68K
68008A Registers Key terms to learn .b Addressing Modes Direct
Fetch Stack Addressing
D Registers Stack Pointer CU .w Immediate Addressing
Decode Program Counter (PC) Indirect
68000 MAR IR .l Absolute Addressing
Execute Condition Code Register (CCR) MBR ALU Subroutines Relative Addressing Addressing
CS132 Computer Organisation & Architecture

Friday, 29 November 2024

Slide 24

23 Achieving Performance

• Discussed how performance can be measured, including time, FLOPS

and Memory Bandwidth
• Discussed how benchmarks and benchmark suites aid in the
comparison of processors
• Explored how pipelining can be used to increase the throughput of
instructions, including how to handle hazards
• How cache can be organised to aid in the movement of data
Time
FLOP Benchmarks Pipelining Key terms to learn Bubble Internal Forwarding Set
FLOPs STREAM Instruction Fetch (IF) Execute (E) Hazards Data Dependency Associative
Work LINPACK NAS Parallel Benchmarks Operand Fetch (OF) NOP Direct-Mapped Cache Mapped
CPI Memory Bandwidth Benchmarking Suites Operand Store (OS) Associative-Mapped Cache Cache
CS132 Computer Organisation & Architecture

Friday, 29 November 2024

Slide 25

24 Considerations of Processor Design

• Engineering Limitations → Lasers can only get so small, transistors

are hitting there limits, limits to interconnect sizes
• Energy Limitations → Utilisation Wall and Cooling
• Parallelisation Limitations → Amdahl's Law and difficulties in going
from 2D and 3D
• Quantum Processors → difficulties in verifying and very expensive
Quantum Processors Speedup Key terms to learn Noise Cross-Section

2D Processors Parallelisation Utilisation Wall Components

Interconnects Transistors Power

3D Processors Amdahl’s Law
CS132 Computer Organisation & Architecture

Friday, 29 November 2024

Slide 26

25 The Future of Processors

• Predicting the future is always difficult, especially when looking at

the far future
• High Bandwidth Memory → More data being sent in the same cycle
• Specialist Cores → Different processors for different computation
• GPU’s and FPGAs → Computation can be offloaded
• Heterogeneous Computing → More diverse computers
Heterogeneous Computing FPGA Key terms to learn GPU Homogeneous Computing
Switcher Specialist Cores High Bandwidth Memory Interconnects Cache
Memory-Bound Bottleneck DRAM IRDS Compute-Bound
CS132 Computer Organisation & Architecture

Friday, 29 November 2024

Slide 27

Exam Webpages

https://warwick.ac.uk/services/academicoffice/examinations/students/ https://warwick.ac.uk/services/exampapers?q=CS132&department=CS