Part - A (10 × 2 = 20)
1.How many flipflops are required for designing BCD Counter ?Justify.
2.Distingush sequential logic with combinational logic.
3.Give the excitation table of JK and T FF.
4.Define a latch and a flip flop.
5.Compare mealy and moole models.
6.List the functional units of a digital computer.
7.Interpret the instruction set architecture.
8.Draw the stock diagram of von-neumann architecture.
9.Outline instruction cycle with a diagram.
10.What is the difference between register direct addressing mode and register
indirect addressing mode?
Part – B (5 × 13 = 65)
11. a) Describe JK and TFF with the help of block diagram and characteristic
table.
11.b) (i) Realize DFF using SRFF.
(ii) Construct a 4 bit down counter using logic gates.
12. a) (i) What is an SR Latch ? Outline the design of SR Latch using NOR gates.
Also present the function table for the same.
(ii) Outline the design of a DFF with two D latch and an inverter with a
diagram.
12. b) (i) Which flipflop is called as data flipflop? Explain the operation of same
with its circuit diagram , characteristic table and excitation table.
(ii) What is shift register ? outline the design of a 4-bit shift register.
13. a) (i) Which is called decade counter ? Why ? Explain the operation of the
same in asynchronous mode.
(ii) Explain mealy and moole models with the help of block diagram.
b) (i) Outline von Neumann architecture with a diagram.
(ii) Explain types of operation and operands with examples.
14. a) Explain about instruction sets with examples.
b) Discuss in detail the various measures of performance of a computer
15. a) (i) Explain about functional units in digital computer.
(ii) Discuss about instruction cycle.
b) (i) Explain about encoding in assembly language and types of
instructions.
(ii) Discuss the interaction between assembly language high level
language.
Part – C (1 × 15 = 15)
16. a) Design a mod-7 synchronous counter using JK FF.
b) Explain about addressing modes with examples.