8051 INTERRUPTS AND
INTERFACING
Sampling Low Level-Triggered
Interrupt
• P3.2 and P3.3 are used for normal I/O
– Unless the INT0 and INT1 bits in the IE register are
enabled
• After the hardware interrupts are enabled, the controller
keeps sampling the INTn pin for a low-level signal once
each machine cycle
• The pin must be held in a low state until the start of the
execution of ISR
– If the INTn pin is brought back to a logic high before the start of
the execution of ISR, there will be no interrupt
• If INTn pin is left at a logic low after the RETI instruction of
the ISR, another interrupt will be activated after one
instruction is executed
Sampling Low Level-Triggered
Interrupt (cont.)
• To ensure the activation of the hardware
interrupt at the INTn pin,
– The duration of the low-level signal is around 4
machine cycles, but no more
• This is due to the fact that the level-triggered interrupt is
not latched
• Thus the pin must be held in a low state until the start of
the ISR execution
Edge-Triggered Interrupt
• To make INT0 and INT1 edge-triggered interrupts,
we must program the bits of the TCON register
– The TCON register holds the IT0 and IT1 flag bits
that determine level- or edge-triggered mode of
the
hardware interrupt
• IT0 and IT1 are bits D0 and D2 of TCON
– They are also referred to as TCON.0 and TCON.2 since the TCON
register is bit-addressable
Sampling Edge-Triggered Interrupt
• The external source must be held high for at
least one machine cycle, and then held low for
at least one machine cycle
– The falling edge of pins INT0 and INT1 are latched by
the 8051 and are held by the TCON.1 and TCON.3
bits of TCON register
• Function as interrupt-in-service flags
• It indicates that the interrupt is being serviced now
– On this INTn pin, no new interrupt will be responded to until this
service is finished
Sampling Edge-Triggered Interrupt
(cont.)
• When the ISRs are finished, TCON.1 and TCON.3
are cleared
– The interrupt is finished and the 8051 is ready to
respond to another interrupt on that pin
• During the time that the interrupt service routine is being
executed, the INTn pin is ignored, no matter how many
times it makes a high-to-low transition
– RETI clears the corresponding bit in TCON register
(TCON.1 or TCON.3)
• There is no need for instruction CLR TCON.1 before RETI in
the ISR associated with INT0
Serial Communication Interrupt
• TI (transfer interrupt) is raised when the stop
bit is transferred
– Indicating that the SBUF register is ready to
transfer the next byte
• RI (received interrupt) is raised when the stop
bit is received
– Indicating that the received byte needs to be
picked up before it is lost (overrun) by new
incoming serial data
RI and TI Flags and Interrupts
• In the 8051 there is only one interrupt set aside
for serial communication
– Used to both send and receive data
– If the interrupt bit in the IE register (IE.4) is enabled,
when RI or TI is raised the 8051 gets interrupted
and jumps to memory location 0023H to execute
the ISR
• In that ISR we must examine the TI and RI flags to see
which one caused the interrupt and respond accordingly
Use of Serial COM in 8051
• The serial interrupt is used mainly for receiving
data and is never used for sending data serially
– This is like getting a telephone call in which we need
a ring to be notified
– If we need to make a phone call there are other
ways to remind ourselves and there is no need for
ringing
– However in receiving the phone call, we must
respond immediately no matter what we are doing
or we will miss the call
TRANS: RETI
END
HERE: JNB TI, HERE
CLR TI
SJMP BACK
TRANS: RETI
END
Interrupt Flag Bits
• The TCON register holds four of the interrupt
flags in the 8051
• The SCON register has the RI and TI flags
Interrupt Priority
• When the 8051 is powered up, the
priorities are assigned
– In reality, the priority scheme is nothing but
an internal polling sequence in which the
8051 polls the interrupts in the sequence
listed and responds accordingly
Altering Interrupt Priority
• We can alter the sequence of interrupt priority
by programming a register called IP (interrupt
priority)
– To give a higher priority to any of the interrupts, we
make the corresponding bit in the IP register high
– When two or more interrupt bits in the IP register
are set to high
• While these interrupts have a higher priority than others,
they are serviced according to the sequence of Table 11-
13
External Interrupt 1 (INT1)
Interrupt inside an Interrupt
• In the 8051 a low-priority interrupt can be
interrupted by a higher-priority interrupt but
not by another low priority interrupt
– Although all the interrupts are latched and kept
internally, no low-priority interrupt can get the
immediate attention of the CPU until the 8051 has
finished servicing the high-priority interrupts
Triggering Interrupt by Software
• To test an ISR by way of simulation can be done
with simple instructions to set the interrupts high
– Thereby cause the 8051 to jump to the interrupt
vector table
– ex. If the IE bit for timer 1 is set, an instruction such as
SETB TF1 will interrupt the 8051 in whatever it is
doing and will force it to jump to the interrupt vector
table
• We do not need to wait for timer 1 go roll over to have an
interrupt
Interfacing 8051 to LCD
LCD Data Sheet
• One can put data at any location in the
LCD
– The following shows address locations and
how they are accessed
• AAAAAAA=000_0000 to 010_0111 for line1
• AAAAAAA=100_0000 to 110_0111 for line2
– The upper address range can go as high as 0100111 for
the 40-character-wide LCD
– Corresponds to locations 0 to 39
STEPPER MOTOR
• A stepper motor is an electromechanical device
which converts electrical pulses into discrete
mechanical movements or steps.
• This motor divides a full rotation of 360 degrees into
a number of equal steps.
Interfacing Stepper Motor with 8051
We now want to control a stepper motor in 8051 . It works by
turning ON & OFF a four I/O port lines generating at a
particular frequency.
The 8051 has four numbers of I/O port lines, connected with
I/O Port lines (P0.0 – P0.3) to rotate the stepper motor.
ULN2003 is a high voltage and high current Darlington array
IC.
ULN2003 is used as a driver for port I/O lines, drivers output
connected to stepper motor, connector provided for external
power supply if needed.
Pin Assignment with 8051
References
1. “The 8051 Microcontroller and Embedded Systems – using assembly and C”,
Muhammad Ali Mazidi and Janice Gillespie Mazidi and Rollin D. McKinlay;
PHI, 2006 / Pearson, 2006.
2. “The 8051 Microcontroller”, Kenneth J. Ayala, 3rd Edition, Thomson/Cengage
Learning.
