GREATER KOLKATA COLLEGE OF ENGINEERING AND MANAGEMENT
Report on
Types of Pipeline Hazards in Computer Architecture
Submitted by : Amirul Laskar
Subject : Computer Architecture
Subject Code : PCC CS 402
University Roll : 23600123002
University Reg. : 232360110002
Department : CSE
Year : 2nd
Semester : 4th
Date of Submission : 11/03/2025
Abstract:
Pipeline hazards, also known as pipeline stalls or pipeline bubbles, are situations in pipelined
architectures that prevent the next instruction in the instruction stream from executing during its
designated clock cycle. This report explores the types of pipeline hazards, including structural,
data, and control hazards, and their implications on CPU performance.
Introduction:
In modern computer architecture, pipelining is a technique used to improve the performance of a
CPU by overlapping the execution of multiple instructions. Pipelining divides the process of
executing instructions into separate stages, allowing multiple instructions to be in different stages
of execution simultaneously. However, this approach can lead to pipeline hazards that disrupt the
smooth flow of instructions and degrade overall performance. Pipeline hazards occur when there
is a conflict or dependency between instructions in the pipeline, causing delays or stalls. This report
delves into the various types of pipeline hazards, their causes, and potential solutions to mitigate
their effects.
Description:
Structural Hazards
Structural hazards occur when hardware resources required by the instruction pipeline are not
available. This can happen when multiple instructions compete for the same hardware resource,
such as a memory module or a functional unit. For example, if an instruction requires access to the
memory while another instruction is already using it, a structural hazard arises, leading to delays.
Example: Consider a CPU with a single memory module. If one instruction needs to read from
memory while another instruction needs to write to memory, a structural hazard occurs since the
memory cannot handle both requests simultaneously.
Data Hazards
Data hazards arise when there are dependencies between instructions that affect the flow of data.
They occur in three forms:
1. Read After Write (RAW) Hazard: This occurs when an instruction needs to read a value
that is yet to be written by a previous instruction.
2. Write After Read (WAR) Hazard: This happens when an instruction needs to write a value
before a previous instruction has read it.
3. Write After Write (WAW) Hazard: This occurs when two instructions write to the same
location in a way that the order of writes affects the final value.
Example:
Instruction 1: ADD R1, R2, R3 ; R1 = R2 + R3
Instruction 2: SUB R4, R1, R5 ; R4 = R1 - R5
In this example, Instruction 2 depends on the result of Instruction 1. If Instruction 2 executes before
Instruction 1 completes, a RAW hazard occurs.
Control Hazards
Control hazards, also known as branch hazards, occur when the pipeline makes wrong decisions
on branch prediction, leading to incorrect instructions being fetched and executed. This type of
hazard arises from the uncertainty of branch outcomes (e.g., if-else conditions or loops).
Example:
Instruction 1: BEQ R1, R2, Label ; Branch to Label if R1 == R2
Instruction 2: ADD R3, R4, R5 ; This instruction may be fetched incorrectly if the branch is
taken
If the branch prediction is incorrect, the CPU may fetch and execute the wrong set of instructions,
causing a control hazard and requiring a pipeline flush to correct the error.
Conclusion:
Pipeline hazards in computer architecture present significant challenges to achieving optimal CPU
performance. Understanding the different types of pipeline hazards—structural, data, and control
hazards—helps in designing effective strategies to mitigate their impact. By addressing these
hazards through techniques like pipeline interlocking, forwarding, and branch prediction, modern
CPUs can minimize performance penalties and ensure efficient instruction execution.
References:
• Hennessy, J. L., & Patterson, D. A. (2017). Computer Architecture: A Quantitative
Approach (6th ed.). Morgan Kaufmann.
• Stallings, W. (2018). Computer Organization and Architecture: Designing for
Performance (11th ed.). Pearson.
• Flynn, M. J. (1995). Computer Architecture: Pipelined and Parallel Processor Design.
Jones & Bartlett Learning.
