Data Sheet

MM32F0140
Arm® Cortex®-M0 based 32-bit Microcontrollers

Revision: 1.09

MindMotion has the right to make any changes and releases to

the information contained in this document (including but not
limited to specifications and product descriptions) at any time.
This document will replace all previously published information.
 Contents

1 Introduction ............................................................................................................................................. 1
1.1 Overview ............................................................................................................................................... 1
1.2 Key features .......................................................................................................................................... 1
2 Ordering information .............................................................................................................................. 4
2.1 Ordering table ....................................................................................................................................... 4
2.2 Marking information .............................................................................................................................. 6
2.3 Part identification .................................................................................................................................. 9
3 Functional description ......................................................................................................................... 10
3.1 Block diagram ..................................................................................................................................... 10
3.2 Core introduction ................................................................................................................................. 11
3.3 Bus introduction .................................................................................................................................. 11
3.4 Memory map ....................................................................................................................................... 11
3.5 Flash ................................................................................................................................................... 13
3.6 SRAM .................................................................................................................................................. 13
3.7 NVIC .................................................................................................................................................... 13
3.8 EXTI .................................................................................................................................................... 13
3.9 Clock and boot .................................................................................................................................... 13
3.10 Boot modes ......................................................................................................................................... 14
3.11 Power supply schemes ....................................................................................................................... 14
3.12 Power supply supervisors ................................................................................................................... 14
3.13 Voltage regulator ................................................................................................................................. 15
3.14 Low power mode ................................................................................................................................. 15
3.15 Hardware divider ................................................................................................................................. 16
3.16 DMA .................................................................................................................................................... 16
3.17 Timers and watchdogs ........................................................................................................................ 16
3.18 GPIO ................................................................................................................................................... 19
3.19 UART .................................................................................................................................................. 19
3.20 I2C ....................................................................................................................................................... 19
3.21 SPI ...................................................................................................................................................... 19
3.22 I2S ....................................................................................................................................................... 19
3.23 FlexCAN .............................................................................................................................................. 19
3.24 ADC ..................................................................................................................................................... 20
3.25 COMP ................................................................................................................................................. 20
3.26 CRC .................................................................................................................................................... 20
3.27 SWD .................................................................................................................................................... 21
4 Pinout and assignment ........................................................................................................................ 22
4.1 Pinout diagram .................................................................................................................................... 22
4.1.1 LQFP48 pins layout ................................................................................................................ 22
4.1.2 LQFP32 pins layout ................................................................................................................ 23
4.1.3 QFN32 5x5 mm2 pins layout .................................................................................................. 24
4.1.4 QFN32 4x4 mm2 pins layout .................................................................................................. 25
4.1.5 TSSOP20 pins layout .............................................................................................................. 26
4.2 Pin assignment ................................................................................................................................... 27
4.3 Pin multiplexing ................................................................................................................................... 31
5 Electrical characteristics ..................................................................................................................... 35
5.1 Test condition ...................................................................................................................................... 35
5.1.1 Load capacitor......................................................................................................................... 35
 5.1.2 Pin input voltage...................................................................................................................... 35
5.1.3 Power scheme ........................................................................................................................ 35
5.1.4 Current consumption measurement ....................................................................................... 36
5.2 Absolute maximum rating ................................................................................................................... 36
5.3 Operating conditions ........................................................................................................................... 37
5.3.1 General operating conditions .................................................................................................. 37
5.3.2 Operating conditions at power-up/power-down ...................................................................... 38
5.3.3 Embedded reset and power control block characteristics ...................................................... 39
5.3.4 Built-in voltage reference ........................................................................................................ 40
5.3.5 Supply current characteristics ................................................................................................. 40
5.3.6 External clock source characteristics ...................................................................................... 43
5.3.7 Internal clock source characteristics ....................................................................................... 46
5.3.8 PLL characteristics .................................................................................................................. 47
5.3.9 Memory characteristics ........................................................................................................... 47
5.3.10 EMC characteristics ................................................................................................................ 48
5.3.11 Functional EMS (Electrical Sensitivity) ................................................................................... 49
5.3.12 I/O port characteristics ............................................................................................................ 50
5.3.13 NRST pin characteristics ........................................................................................................ 52
5.3.14 Timer characteristics ............................................................................................................... 53
5.3.15 Communication interfaces ...................................................................................................... 54
5.3.16 FlexCAN interface ................................................................................................................... 59
5.3.17 ADC characteristics ................................................................................................................ 59
5.3.18 Temperature sensor characteristics........................................................................................ 63
5.3.19 Comparator characteristics ..................................................................................................... 64
6 Package dimensions ............................................................................................................................ 65
6.1 LQFP48 ............................................................................................................................................... 65
6.2 LQFP32 ............................................................................................................................................... 67
6.3 QFN32 5x5 mm 2 ................................................................................................................................. 69
6.4 QFN32 4x4 mm 2 ................................................................................................................................. 71
6.5 TSSOP20 ............................................................................................................................................ 73
7 Revision history .................................................................................................................................... 75
 Tables

Table 2-1 MM32F0140 ordering table 1 ................................................................................................................... 4

Table 2-2 MM32F0140 ordering table 2 ................................................................................................................... 5
Table 3-1 Memory map ........................................................................................................................................... 11
Table 3-2 Peripheral status in different power modes ............................................................................................ 16
Table 3-3 Feature summary of advanced, general purpose and basic timers ....................................................... 17
Table 4-1 Pin assignment table .............................................................................................................................. 27
Table 4-2 PA port multiplexing AF0-AF8 ................................................................................................................ 31
Table 4-3 PB port multiplexing AF0-AF8 ................................................................................................................ 32
Table 4-4 PC port multiplexing AF0-AF8 ................................................................................................................ 33
Table 4-5 PD port multiplexing AF0-AF8 ................................................................................................................ 34
Table 5-1 Voltage characteristics ........................................................................................................................... 37
Table 5-2 Current characteristics ............................................................................................................................ 37
Table 5-3 General operating conditions.................................................................................................................. 38
Table 5-4 Operating conditions at power-up/power-down ...................................................................................... 38
Table 5-5 Embedded reset and power control block characteristics ...................................................................... 39
Table 5-6 Build-in voltage reference ....................................................................................................................... 40
Table 5-7 Typical current consumption in Run mode ............................................................................................. 41
Table 5-8 Typical current consumption in Sleep mode .......................................................................................... 41
Table 5-9 Typical and maximum current consumption in stop and Standby modes (1) .......................................... 41
Table 5-10 On-chip peripheral current consumption (1) ........................................................................................... 42
Table 5-11 Wake up time from low power mode .................................................................................................... 43
Table 5-12 High-speed external user clock characteristics .................................................................................... 44
Table 5-13 HSE oscillator characteristics (1)(2) ........................................................................................................ 45
Table 5-14 HSI oscillator characteristics (1)(2).......................................................................................................... 46
Table 5-15 LSI oscillator characteristics (1) ............................................................................................................. 46
Table 5-16 PLL characteristics (1) ........................................................................................................................... 47
Table 5-17 Flash memory characteristics ............................................................................................................... 47
Table 5-18 Flash memory endurance and data retention (1)(2) ................................................................................ 47
Table 5-19 EMS characteristics .............................................................................................................................. 48
Table 5-20 ESD & LU characteristics ..................................................................................................................... 49
Table 5-21 I/O static characteristics ....................................................................................................................... 50
Table 5-22 Output voltage static characteristics ..................................................................................................... 51
Table 5-23 I/O AC characteristics (1)(2)(3) ................................................................................................................. 51
Table 5-24 NRST pin characteristics ...................................................................................................................... 52
Table 5-25 TIMx (1) characteristics .......................................................................................................................... 53
Table 5-26 I2C characteristics ................................................................................................................................ 54
Table 5-27 SPI characteristics (1) ............................................................................................................................ 56
Table 5-28 ADC characteristics .............................................................................................................................. 60
Table 5-29 Maximum RAIN at fADC = 15MHz (1) ........................................................................................................ 61
Table 5-30 ADC static parameters (1)(2)................................................................................................................... 61
Table 5-31 Temperature sensor characteristics (3)(4) .............................................................................................. 63
Table 5-32 Comparator characteristics (1) ............................................................................................................... 64
Table 6-1 LQFP48 package dimension details ....................................................................................................... 66
Table 6-2 LQFP32 package dimension details ....................................................................................................... 68
Table 6-3 QFN32 5x5 mm2 package dimension details ......................................................................................... 70
Table 6-4 QFN32 4x4 mm2 package dimension details ......................................................................................... 72
Table 6-5 TSSOP20 package dimension details .................................................................................................... 74
Table 7-1 Revision history ...................................................................................................................................... 75
 Figures

Figure 2-1 LQFP or QFN32 package marking .......................................................................................................... 6

Figure 2-2 QFN28 package marking ........................................................................................................................ 7
Figure 2-3 TSSOP20 package marking .................................................................................................................... 8
Figure 2-4 Part number naming rule ......................................................................................................................... 9
Figure 3-1 System block diagram ........................................................................................................................... 10
Figure 4-1 LQFP48 pinout diagram ........................................................................................................................ 22
Figure 4-2 LQFP32 pinout diagram ........................................................................................................................ 23
Figure 4-3 QFN32 pinout diagram .......................................................................................................................... 24
Figure 4-4 QFN28 pinout diagram .......................................................................................................................... 25
Figure 4-5 TSSOP20 pinout diagram ..................................................................................................................... 26
Figure 5-1 Load condition of the pin ....................................................................................................................... 35
Figure 5-2 Pin input voltage .................................................................................................................................... 35
Figure 5-3 Power scheme ....................................................................................................................................... 36
Figure 5-4 Current consumption measurement scheme ........................................................................................ 36
Figure 5-5 Power-on and power-down waveforms ................................................................................................. 39
Figure 5-6 High-speed external clock source AC timing diagram .......................................................................... 44
Figure 5-7 Typical application with an 8 MHz crystal ............................................................................................. 46
Figure 5-8 I/O AC characteristics ............................................................................................................................ 52
Figure 5-9 Recommended NRST pin protection .................................................................................................... 53
Figure 5-10 I2C bus AC waveform and measurement circuit (1) ............................................................................. 55
Figure 5-11 SPI timing diagram-slave mode and CPHA = 0, CPHASEL = 1 ......................................................... 57
Figure 5-12 SPI timing diagram-slave mode and CPHA = 1, CPHASEL = 1 (1) ..................................................... 58
Figure 5-13 SPI timing diagram-master mode, CPHASEL = 1 (1) ........................................................................... 59
Figure 5-14 Schematic diagram of ADC static parameters .................................................................................... 62
Figure 5-15 Typical connection diagram using the ADC ........................................................................................ 62
Figure 5-16 Power supply and reference power supply decoupling circuit ............................................................ 63
Figure 6-1 LQFP48 package dimension ................................................................................................................. 65
Figure 6-2 LQFP32 package dimension ................................................................................................................. 67
Figure 6-3 QFN32 5x5 mm2 package dimension.................................................................................................... 69
Figure 6-4 QFN32 4x4 mm2 package dimension.................................................................................................... 71
Figure 6-5 TSSOP20 package dimension .............................................................................................................. 73
Introduction

1 Introduction

1.1 Overview
The MM32F0140 microcontrollers are based on Arm® Cortex®-M0 core. These devices
have a maximum clocked frequency of 72MHz, built-in 64KB Flash storage, and contain
an extensive range of peripherals and I/O ports. These devices contain one 12-bit ADC,
one analog comparator, one 16-bit advanced timer, one 16-bit and one 32-bit general
purpose timers and three 16-bit basic timers, as well as communication interfaces including
one I2C, two SPI or I2S, three UART and one FlexCAN interface.
The operating voltage of this product series is 2.0V to 5.5V, and the operating temperature
range (ambient temperature) includes the industrial tier -40°C to 85°C and the extended
industrial tier -40°C to 105°C. Multiple sets of power-saving modes make the design of low-
power applications possible.
The target applications of this product series include:
 Industrial IoT devices
 PC accessories
 Electronic door lock
 Medical and healthcare devices
 Handheld devices
 Motor drive
 Elevator calling board
 Gaming and entertainment
This product series is available in LQFP48, LQFP32, QFN32 and TSSOP20 packages.

1.2 Key features

 Core and system
– 32-bit Arm® Cortex®-M0.
– Frequency up to 72MHz.
 Memory
– Up to 64KB embedded Flash storage.
– Up to 8KB SRAM.
– Embedded Bootloader to support In-System-Programming (ISP).
 Clock, reset and power management
– Power supply ranges from 2.0 to 5.5V.
– Power-on and Power-down reset (POR/PDR), Programmable voltage detector
(PVD).

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Introduction

– 4 to 24MHz high speed crystal oscillator.

– 8MHz factory-trimmed high speed RC oscillator.
– Integrated PLL to generate up to 72MHz system clock and support multiple
prescaler rate to provide clock sources to bus matrix and peripherals.
– 40KHz low speed oscillator.
 Low power
– Multiple low power modes including Sleep mode, Stop mode, Deep Stop mode
and Standby mode.
 One DMA controller with 5 channels to support peripherals including timers, ADC,
UART, I2C, SPI, and FlexCAN.
 Total 9 timers:
– One 16-bit 4-channel advanced timer (TIM1), each channel providing two PWM
output including one complementary output, supports hardware dead-time
insertion and emergency break when fault detected.
– One 16-bit general purpose timer (TIM3) and one 32-bit general purpose timer
(TIM2), with up to four input capture or output compare channels and can be used
for infrared decode.
– Three 16-bit basic timers (TIM14 / TIM16 / TIM17), with one input capture or
output compare channel and one complementary output, support hardware dead-
time insertion, emergency break when fault detected, and integrated modulator
circuit for infrared control.
– Two watchdog timers, including one independent watchdog (IWDG) and one
window watchdog (WWDG).
– One 24-bit Systick timer.
 Up to 40 fast I/O ports:
– All I/O ports can be mapped to 16 external interrupts.
– All I/O ports can accept input or generate output signal voltage level is not higher
than VDD.
 Up to 7 communication interfaces:
– Three UART.
– One I2C.
– Two SPI (support I2S mode).
– One FlexCAN module supports CAN 2.0B interface.
 One 12-bit Analog-to-Digital converter (ADC), support 1μs conversion duration, with
up to 14 external inputs and 2 internal inputs
– Conversion range: 0 to VDDA.
– Configurable sampling cycles and resolution.
– On-chip temperature sensor.
– On-chip voltage sensor.

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Introduction

 One high speed analog comparator

 32-bit hardware divider
 Embedded CRC engine
 96bit unique chip ID (UID)
 Debug mode
– Serial Wire Debug (SWD).
 Available in LQFP48, LQFP32, QFN32 and TSSOP20 packages

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Ordering information

2 Ordering information

2.1 Ordering table

Table 2-1 MM32F0140 ordering table 1

MM32 MM32 MM32 MM32 MM32 MM32 MM32 MM32 MM32

Part numbers F0141 F0141 F0144 F0141 F0141 F0144 F0141 F0141 F0144
C4N C4Q C4Q(V) B4P C4P C4P(V) B6P C6P C6P(V)
CPU frequency 72 MHz
Flash ­ KB 64 64 64 32 64 64 32 64 64
SRAM ­ KB 8 8 8 8 8 8 8 8 8
16­bit GP 1 1 1 1 1 1 1 1 1
32­bit GP 1 1 1 1 1 1 1 1 1
Timers
Basic 3 3 3 3 3 3 3 3 3
Advance
1 1 1 1 1 1 1 1 1
d
UART 3 3 3 3 3 3 3 3 3
I2C 1 1 1 1 1 1 1 1 1
Interfaces
SPI / I2S 2 2 2 2 2 2 2 2 2
FlexCAN ­ ­ 1 ­ ­ 1 ­ ­ 1
GPIO 28 28 28 26 26 26 40 40 40
Modules 1 1 1 1 1 1 1 1 1
12­bit ADC
Channels 13 13 13 13 13 13 13 13 13
Comparator 1 1 1 1 1 1 1 1 1
Supply voltage 2.0V to 5.5V
Temperature range ­40°C to +85°C / ­40°C to +105°C (Suffix V)
QFN32
QFN32 LQFP32 LQFP48
Package 4x4
5x5 mm2 7x7 mm2 7x7 mm2
mm2

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Ordering information

Table 2-2 MM32F0140 ordering table 2

MM32 MM32 MM32

Part numbers F0141 F0141 F0144
B1T C1T C1T(V)
CPU frequency
Flash ­ KB 32 64 64
SRAM ­ KB 8 8 8
16­bit GP 1 1 1
32­bit GP 1 1 1
Timers
Basic 3 3 3
Advanced 1 1 1
UART 3 3 3

Interface I2C 1 1 1
s SPI / I2S 1 (SPI1/I2S1) 1 (SPI1/I2S1) 1 (SPI1/I2S1)
FlexCAN ­ ­ 1
GPIO 16 16 16

12­bit Modules 1 1 1
ADC Channels 9 9 9
Comparator 1 1 1
Supply voltage 2.0V to 5.5V
Temperature range ­40°C to +85°C / ­40°C to +105°C (Suffix V)
TSSOP20
Package
4.35x6.45 mm2

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Ordering information

2.2 Marking information

Notes about the marking: The purpose of this section is to guide users to identify the
required information from the chip marking, and the format (including font, font size,
alignment, etc.), position, proportion, etc. in the marking figures may be different from the
actual chip marking, and the marking of some packages may not contain MindMotion logo,
such format, position, proportion, logo, etc. information, please refer to the actual chips.

MM32
F014xxxxt
xxxxxxxr
Pin 1 index yyww

Figure 2-1 LQFP or QFN32 package marking

LQFP or QFN32 package has the following topside marking:

 1st line: MM32
– Company logo + first part of product name.
 2nd line: F014xxxxt
– Second part of product name, where “t” represents temperature level. “t” =
“Empty” means -40 to 85°C (industrial), “t” = “V” means -40 to 105°C (extended
industrial).
 3rd line: xxxxxxxr
– Trace code + revision code, the “r” means chip revision. For engineering samples,
the prefix 2 digital of the Trace code is labelled as “ES”.
 4th line: yyww
– Date code, “yy” means year and “ww” means week in date code.

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Ordering information

MM32
F014xxxt
xxxxxxxr
Pin 1 index yyww

Figure 2-2 QFN28 package marking

QFN28 package has the following topside marking:

 1st line: MM32
– Company logo + first part of product name.
 2nd line: F014xxxxt
– Part of product name + temperature level, where “t” represents temperature level.
“t” = “N” means -40 to 85°C (industrial), “t” = “V” means -40 to -105°C (extended
industrial).
 3rd line: xxxxxxxr
– Trace code + revision code, the “r” means chip revision. For engineering samples,
the prefix 2 digital of the Trace code is labelled as “ES”.
 4th line: yyww
– Date code, “yy” means year and “ww” means week in date code.

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Ordering information

F014xxxt
xxxxxxxr
Pin 1 index yyww

Figure 2-3 TSSOP20 package marking

TSSOP20 package has the following topside marking:

 1st line: F014xxxt
– Part of product name + temperature level, where “t” represents temperature level.
“t” = “T” means -40 to 85°C (industrial), “t” = “V” means -40 to -105°C (extended
industrial).
 2nd line: xxxxxxxr
– Trace code + revision code, the “r” means chip revision. For engineering samples,
the prefix 2 digital of the Trace code is labelled as “ES”.
 3rd line: Company logo + yyww
– Date code, “yy” means year and “ww” means week in date code.

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Ordering information

2.3 Part identification

MM32 F 0 1 4 4 C 6 P V

Device family

MM32 = MindMotion's 32-bit Microcontroller

Product type

F = General Purpose & High Performance

Core type
0 = Cortex-M0

Product Series
14 = 14 Series

Interface Configuration
4 = Solo CAN
1 = General Serial Ports

Flash size
C = 64KB
B = 32KB

Pins

6 = 48Pin
4 = 32Pin
3 = 28Pin
1 = 20Pin

Package
Q = QFN, 0.5mm pitch
N = QFN, 0.4mm pitch
P = LQFP
T = TSSOP
Temperature
V = -40℃ ~ 105℃
(blank) = -40℃ ~ 85℃

Figure 2-4 Part number naming rule

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Functional description

3 Functional description

3.1 Block diagram

Figure 3-1 System block diagram

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Functional description

3.2 Core introduction

The Arm® Cortex®-M0 processor provides real-time processing and advanced interrupt
handling system, which is perfect for cost-effective and low-pin-count microcontrollers
targeting real-time control and low power applications.
The Arm® Cortex®-M0 is a 32-bit RISC processor, provides state-of-the-art code efficiency,
which is extremely suitable for small memory size microcontrollers and small code size
applications.
With its embedded Arm core, this product is compatible with all the tools and software for
Arm-based products.

3.3 Bus introduction

The bus matrix includes one AHB inter-connection bus matrix, one AHB bus and two AHB-
to-APB bridges. The bus matrix has arbitration capability for scenarios when both CPU and
DMA send access simultaneously. The peripherals on the AHB bus (e.g., RCC, HWDIV,
GPIO, CRC) are connected to the system bus through the inter-connection matrix. The
data are transferred between AHB and APB bus using an AHB-to-APB bridge. When
there’s 8-bit or 16-bit access to APB registers, the APB bus will extend the access to 32-
bit automatically.

3.4 Memory map

Table 3-1 Memory map

Bus Address range Size Peripheral

Map to main Flash, system
0x0000 0000 ­ 0x0000 FFFF 64 KB memory or SRAM according to
boot configuration
0x0001 0000 ­ 0x07FF FFFF ~128 MB Reserved
0x0800 0000 ­ 0x0800 FFFF 64 KB Main Flash
0x0801 0000 ­ 0x1FFD FFFF ~383 MB Reserved
0x1FFE 0000 ­ 0x1FFE 01FF 0.5 KB Reserved

Flash 0x1FFE 0200 ­ 0x1FFE 0FFF 3 KB Reserved

0x1FFE 1000 ­ 0x1FFE 11FF 0.5 KB Encrypted area
0x1FFE 1200 ­ 0x1FFE 1BFF 2.5 KB Encrypted area
0x1FFE 1C00 ­ 0x1FFF F3FF ~256 MB Reserved
0x1FFF F400 ­ 0x1FFF F7FF 1 KB System memory
0x1FFF F800 ­ 0x1FFF F9FF 0.5KB Option bytes
0x1FFF FA00 ­ 0x1FFF FFFF 1.5KB Reserved
0x2000 0000 ­ 0x2000 1FFF 8 KB SRAM
SRAM
0x2000 2000 ­ 0x2FFF FFFF ~255 MB Reserved
0x4000 0000 ­ 0x4000 03FF 1 KB TIM2
APB1
0x4000 0400 ­ 0x4000 07FF 1 KB TIM3

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Functional description

Bus Address range Size Peripheral

0x4000 0800 ­ 0x4000 2BFF 9 KB Reserved
0x4000 2C00 ­ 0x4000 2FFF 1 KB WWDG
0x4000 3000 ­ 0x4000 33FF 1 KB IWDG
0x4000 3400 ­ 0x4000 37FF 1 KB Reserved
0x4000 3800 ­ 0x4000 3BFF 1 KB SPI2
0x4000 3C00 ­ 0x4000 43FF 2 KB Reserved
0x4000 4400 ­ 0x4000 47FF 1 KB UART2
0x4000 4800 ­ 0x4000 4BFF 1 KB UART3
0x4000 4C00 ­ 0x4000 53FF 2 KB Reserved
0x4000 5400 ­ 0x4000 57FF 1 KB I2C1
0x4000 5800 ­ 0x4000 6FFF 6 KB Reserved
0x4000 7000 ­ 0x4000 73FF 1 KB PWR
0x4000 7400 ­ 0x4000 83FF 4 KB Reserved
0x4000 8400 ­ 0x4000 87FF 1 KB Reserved
0x4000 8800 ­ 0x4000 BFFF 14 KB Reserved
0x4000 C000 ­ 0x4000 FFFF 16 KB FlexCAN
0x4001 0000 ­ 0x4001 03FF 1 KB SYSCFG
0x4001 0400 ­ 0x4001 07FF 1 KB EXTI
0x4001 0800 ­ 0x4001 23FF 7 KB Reserved
0x4001 2400 ­ 0x4001 27FF 1 KB ADC
0x4001 2800 ­ 0x4001 2BFF 1 KB Reserved
0x4001 2C00 ­ 0x4001 2FFF 1 KB TIM1
0x4001 3000 ­ 0x4001 33FF 1 KB SPI1
APB2
0x4001 3400 ­ 0x4001 37FF 1 KB DBGMCU
0x4001 3800 ­ 0x4001 3BFF 1 KB UART1
0x4001 3C00 ­ 0x4001 3FFF 1 KB COMP
0x4001 4000 ­ 0x4001 43FF 1 KB TIM14
0x4001 4400 ­ 0x4001 47FF 1 KB TIM16
0x4001 4800 ­ 0x4001 4BFF 1 KB TIM17
0x4001 4C00 ­ 0x4001 7FFF 13 KB Reserved
0x4002 0000 ­ 0x4002 03FF 1 KB DMA
0x4002 0400 ­ 0x4002 0FFF 3 KB Reserved
0x4002 1000 ­ 0x4002 13FF 1 KB RCC
0x4002 1400 ­ 0x4002 1FFF 3 KB Reserved
AHB
0x4002 2000 ­ 0x4002 23FF 1 KB Flash Interface
0x4002 2400 ­ 0x4002 2FFF 3 KB Reserved
0x4002 3000 ­ 0x4002 33FF 1 KB CRC
0x4002 3400 ­ 0x4002 FFFF 47 KB Reserved

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Functional description

Bus Address range Size Peripheral

0x4003 0000 ­ 0x4003 03FF 1 KB HWDIV
0x4003 0400 ­ 0x47FF FFFF ~127 MB Reserved
0x4800 0000 ­ 0x4800 03FF 1 KB GPIOA
0x4800 0400 ­ 0x4800 07FF 1 KB GPIOB
0x4800 0800 ­ 0x4800 0BFF 1 KB GPIOC
0x4800 0C00 ­ 0x4800 0FFF 1 KB GPIOD

3.5 Flash
This product provides up to 64KB embedded Flash memory available for storing code and
data.

3.6 SRAM
This product provides up to 8KB embedded SRAM.

3.7 NVIC
This product embeds a Nested vector interrupt controller (NVIC), able to handle multiple
maskable interrupt channels (excluding the 16 interrupt lines of the Cortex®-M0) and
manage 4 programmable priority levels.
 Tightly coupled NVIC gives low latency interrupt processing.
 Interrupt entry vector table address passed directly to the core.
 Allow early processing of interrupts.
 Support high priority interrupt preemption.
 Support interrupt tail-chaining.
 Automatically save processor status.
 Automatic restoration when the interrupt returns with no instruction overhead.
This module provides flexible interrupt management with minimal interrupt latency.

3.8 EXTI
The external interrupt/event controller (EXTI) contains multiple edge detectors to capture
the level changes on the I/O ports and generate interrupt/event to CPU. All I/O ports are
connected to 16 external interrupt lines. Each interrupt line can be independently enabled
or disabled and configured to select the trigger mode (rising edge, falling edge or both
edges). A pending register can save all the interrupt request status.
The EXTI can detect a pulse width shorter than the internal APB2 clock period.

3.9 Clock and boot

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Functional description

The system clock can be configured after chip power-on. After the power-on reset, the
default clock is the internal 8MHz high speed oscillator (HSI). User can configure to use
the external 4 to 24MHz crystal oscillator (HSE) as the system clock. The system will
automatically block the external clock source, turn off the PLL and use the internal oscillator
when the external clock is detected to be invalid. Meanwhile, if the clock monitor interrupt
is enabled, an interrupt request will be generated.
The clock system uses multiple pre-dividers to generate the clock for the AHB and APB
(APB1 and APB2) bus. The maximum frequency of the AHB and APB bus clock can reach
up to 72MHz.

3.10 Boot modes

During boot, BOOT0 pin and nBOOT1 bit are used to select one of three boot options:
 Boot from embedded Flash
 Boot from system memory
 Boot from embedded SRAM
The Bootloader code locates in the system memory. Once the chip boots from the system
memory, it will run the bootloader code and user can program the embedded Flash through
UART1 port by using the bootloader.

3.11 Power supply schemes

 VDD = 2.0V ∼ 5.5V: I/O ports and internal voltage regulator are powered by the VDD
Pins.
 VDDA = 2.0V ∼ 5.5V: ADC, reset logic, oscillators, PLL are powered by the VDDA pin.
VDDA and VSSA can either be connected to VDD and VSS respectively or be powered
individually. When powered individually, the power supply should be at the same
voltage level as the VDD and VSS.

3.12 Power supply supervisors

This product integrates the power-on reset (POR) and power-down reset (PDR) circuit.
This circuit is workable in all power modes, to make sure the chip can work above the
lowest power supply voltage. When the VDD is lower than the preset threshold (VPOR/VPDR),
this circuit will put system to reset status.
This product also integrates a programmable voltage monitor (PVD), it can monitor the VDD
and VDDA voltage, and compare it with the preset threshold VPVD. When VDD is lower or
higher than VPVD, an interrupt request can be generated, then the interrupt handler can
send out warning information or put the chip into safe mode. The PVD function can be
configured to be enabled.

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Functional description

3.13 Voltage regulator

The on-chip voltage regulator can regulate the external supply voltage to a lower and stable
supply voltage that used by the internal circuits. The voltage regulator is workable after the
chip power-on reset (POR).

3.14 Low power mode

This product supports multiple low power modes, user can select the low power modes
according to their application to achieve a balance between power consumption, wakeup
time and wakeup source.

Sleep mode
In Sleep mode, only the CPU clock is gated off. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.

Stop mode
In Stop mode, low power consumption can be achieved with all RAM and registers content
in retention. In Stop mode, HSI and HSE are powered off. The microcontroller can be
woken up by the EXTI signals. EXTI signals can come from the 16 external I/O ports or
PVD output.

Deep Stop mode

Similar as Stop mode, but with lower power consumption.

Standby mode
In Standby mode, the lowest power consumption can be achieved. In this mode, the
voltage regulator is powered off, and all the 1.5V domain are shut down. PLL, HSI and
HSE are also powered off. Wakeup sources include rising edge on WKUP pin, active reset
on NRST pin, IWDG reset. SRAM and registers content are lost in this mode. Only standby
circuit are powered.

The peripheral status in each low-power mode is shown in Table 3-2, please note:
 Power Down indicates that the module is powered off and all data except Flash is lost.
 Optional indicates that the peripheral can be turned on or off through software
configuration.
 ON means work.
 OFF indicates that the function is turned off.
 Retention indicates that data is retained but not operational.
 High-z represents a high-impedance state.

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Functional description

Table 3-2 Peripheral status in different power modes

Module/Mode Run Sleep Stop Deep Stop Standby

Max. Freq. 72MHz 72MHz 40KHz 40KHz 40KHz
PVD Optional Optional Optional Optional OFF
POR/BOR ON ON ON ON ON
Power
CPU ON OFF OFF OFF
Down
Power
SRAM ON ON Retention Retention
Down
Deep Power
Flash ON Standby Standby
Standby Down
Power Power
HSI Optional Optional OFF
Down Down
Power Power Power
PLL Optional Optional
Down Down Down
LSI Optional Optional Optional Optional Optional
HSE Optional Optional OFF OFF OFF
ADC Optional Optional OFF OFF OFF
COMP Optional Optional Optional Optional OFF
IWDG Optional Optional Optional Optional Optional
Other Power
Optional Optional OFF OFF
Peripherals Down
I/O Optional Retention Retention Retention High­z (1)
1. NRST maintains the reset function, wakeup I/O (WKUP) can wake up, other I/Os are high
impedance.

3.15 Hardware divider

This product has a hardware divider unit (HWDIV). It can automatically run the 32-bit
signed or unsigned integer division operation. The HWDIV is especially useful in some
high-performance applications.

3.16 DMA
This product has a 5-channel direct memory access (DMA) controller. The DMA controller
can be used to move data from memory to memory, peripherals to memory or memory to
peripherals without CPU intervention. The DMA controller support ring buffer mode, when
data reaches end of the buffer, the ring buffer mode can avoid generating an interrupt.
Each DMA channel has independent DMA request handling logic. All channels can be
triggered by software. For each channel, the data length, source address and destination
address can be independently configured by software.
DMA can be used for peripherals include UART, I2C, SPI, ADC, and general purpose,
advanced, or basic timers.

3.17 Timers and watchdogs

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Functional description

This product has one advanced timer, two general purpose timers, three basic timers, two
watchdog timers and one Systick timer. The table below compares the features of
advanced, general purpose and basic timers.

Table 3-3 Feature summary of advanced, general purpose and basic timers

Counter DMA Capture/compare Complementary

Type Instance Resolution pre-divider
direction request channels output
up, down,
Advanced TIM1 16­bit 1 to 65536 Yes 4 3
up/down
up, down,
TIM2 32­bit 1 to 65536 Yes 4 No
General up/down
purpose up, down,
TIM3 16­bit 1 to 65536 Yes 4 No
up/down
TIM14 16­bit up 1 to 65536 Yes 1 No
Basic TIM16 /
16­bit up 1 to 65536 Yes 1 1
TIM17

Advanced timer (TIM1)

The advanced timer includes a 16-bit counter, four capture/compare channels and three
phases complementary PWM generator. This timer supports hardware dead-time insertion
when using as complementary PWM generator. This timer can also be used as a full-
function general purpose timer. This timer has four independent channels, each channel
can be used for:
 Input capture
 Output compare
 PWM generator (center- or edge-aligned)
 Single pulse output
When this timer is used as a general-purpose timer, it has the same function as the TIM2.
When this timer is used as a 16-bit PWM generator, it can be configured to a broad duty
cycle range from 0% to 100%.
The advanced timer has lots of identical features and internal structures as the general-
purpose timer, in this way the advanced timer can work together with the general-purpose
timer through the link function, to provide synchronization and event trigger function.
In debug mode, the counter can be frozen.

General-purpose timer (TIMx)

This product has two general-purpose timers (TIM2, TIM3). The timer has a 16- or 32-bit
counter, support both up and down counting, with automatically reload. The timer also has
a 16-bit frequency pre-divider and four independent channels. Each channel can be used
as input capture, output compare, PWM or single pulse output.

32-bit general-purpose timer

This timer has a 32-bit up and down counter, a 16-bit prescaler and four independent
channels, each channel can be used as input capture, output compare, PWM or single

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Functional description

pulse output.

16-bit general-purpose timer

This timer has a 16-bit up and down counter, a 16-bit prescaler and four independent
channels, each channel can be used for input capture, output compare, PWM or single
pulse output.
These general-purpose timers can also work together through the timer link function, to
provide synchronization between timers and event trigger function.
Any general-purpose timer can be used to generate PWM output or work as basic timer.
Each timer has independent DMA request.
These timers can also be used to decode incremental encoder signals and can also be
used to decode one to four Hall sensors’ digital output.
In debug mode, the counter can be frozen.

Basic timer (TIM14 / TIM16 / TIM17)

This product has three basic timers (TIM14 / TIM16 / TIM17), each timer has a 16-bit
counter, supports automatic reload, and only supports up-counting. The timer has a 16-bit
prescaler and one independent channel, each channel can be used as input capture,
output compare, PWM or single pulse output. When used in PWM mode, TIM14 has no
complementary output port, TIM16 and TIM17 are equipped with complementary output
port, which can generate complementary PWM pairs and support hardware dead-timer
insertion.

Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit down counter and an 8-bit prescaler. It is
clocked by an internal independent 40KHz oscillator. As it is independent of the main clock,
it can run in Stop and Standby modes. It can be used to reset the entire system when a
system error occurs or as a free timer to provide timeout management for applications. It
can be configured to start the watchdog by software or hardware through the option byte.
In debug mode, the counter can be frozen.

Window watchdog (WWDG)

The window watchdog is based on a 7-bit down counter that can be set as free-running. It
can be used as a watchdog to reset the entire system when an system error occurs. It is
clocked by the main clock and has an early warning interrupt function; in debug mode, the
counter can be frozen.

System tick timer (Systick)

This timer is dedicated to the real-time operating system and can also be used as a general
down counter. It has the following features:
 24-bit down counter
 Auto-reload capability
 A maskable interrupt can be generated when counter value is 0

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Functional description

 Programmable clock source

3.18 GPIO
Each GPIO pin can be configured by software as output (push-pull or open-drain), input
(with or without pull-up or pull-down) or multiplexed peripherals function port. Most GPIO
pins are shared with digital or analog functions. If necessary, the peripheral functions of
the I/O pins can be locked by specific operation to avoid accidental writing to the I/O
register.

3.19 UART
This product has up to three UART interfaces. The UART interface supports configurable
data length of 5-, 6-, 7-, 8-, and 9-bits. The UART interface also supports LIN master and
slave function and ISO7816 smart card mode. All UART interfaces support DMA operation.

3.20 I2C
This product has up to one I2C interface. The I2C bus interface can work in multi-master
mode or slave mode and supports standard and fast mode. The I2C interface supports 7-
bit or 10-bit addressing.

3.21 SPI
This product has up to two SPI interfaces. The SPI interface can be configured as 1 to 32
bits per frame in master or slave mode, allowing up to 36 Mbps in master mode and 18
Mbps in slave mode. All SPI interfaces support DMA operation.

3.22 I2S
This product has up to two I2S interfaces shared with the SPI module. The I2S module
shares three pins with SPI, supports half-duplex communication (transmitter or receiver
only), master or slave operation, underflow flag in transmit mode (only slave), and overflow
flag in receive mode (master and slave mode) and frame error flag in receive and transmit
mode (only slave). 8-bit programmable linear prescaler is used to achieve precise audio
sampling frequency from 8KHz to 192KHz. The data format can be 16-bit, 24-bit or 32-bit,
and the data packet frame is fixed at 16-bit (16-bit data frame) or 32-bit (16-bit, 24-bit or
32-bit data frame).

3.23 FlexCAN
This product has up to one FlexCAN interface. The FlexCAN interface is compatible with
CAN 2.0A and 2.0B (active) standard, with bit rate up to 1Mbps. It can receive and send
standard frames with 11-bit identifiers, as well as extended frames with 29-bit identifiers.

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Functional description

3.24 ADC
This product has one 12-bit analog/digital converter (ADC), with up to 14 external channels
available, supports single-shot single-cycle and continuous scan conversion. In the scan
mode, the conversion of the sampling value on the selected group of analog inputs is
automatically performed. The ADC supports DMA operation.
The analog watchdog function allows the application to monitor one or all selected
channels. When the monitored signal exceeds a preset threshold, an interrupt will be
generated. The triggers generated by the general-purpose timers (TIMx) and the advanced
timers can be selected to trigger the ADC sampling, in this way the ADC sampling can be
synchronized with the timer.

Temperature sensor
The temperature sensor can generate a voltage that varies linearly with temperature. The
temperature sensor is internally connected to the input channel of the ADC to covert the
output of the sensor to a digital value.

3.25 COMP
This product has one build-in analog comparators (COMP), which can be used
independently (applicable to all I/O ports that have comparator function) or combined with
timers. The COMP module can be used for a variety of functions including:
 Low power mode wake-up event triggered by analog signal
 Adjust analog signals
 Combining the PWM output of the timer to form a cycle by cycle current control circuit
 Each comparator has an optional threshold
- Reusable I/O pins
- The internal comparison voltage CRV can be selected as VDDA or the divided
voltage value of the internal reference voltage
 Programmable hysteresis voltage
 Programmable speed and power consumption
 The output can be redirected to one I/O port or multiple timer inputs, which can trigger
the following events:
- Capture events
- OCref_clr event (cycle by cycle current control)
 To achieve fast PWM turn off braking events

3.26 CRC
The cyclic redundancy check (CRC) module uses a fixed polynomial generator to generate
a CRC code from a 32-bit data word. Among many applications, CRC is used to verify the

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Functional description

consistency of data transmission or storage. Within the scope of the EN/IEC60335-1

standard, it provides a method to detect flash memory errors. The CRC module can be
used to calculate the signature of the software package in real time and compare it with
the signature generated when the software is linked and generated.

3.27 SWD
This product equips Arm standard Serial Wire Debug (SWD).

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Pinout and assignment

4 Pinout and assignment

4.1 Pinout diagram

4.1.1 LQFP48 pins layout

PD5-BOOT0

PA15

PA14
VDD

VSS

PB9

PB8

PB7

PB6

PB5

PB4

PB3
48

47

46

45

44

43

42

41

40

39

38

37
NC 1 36 PD3

PC13 2 35 PD2

PC14 3 34 PA13

PC15 4 33 PA12

PD0-OSC_IN 5 32 PA11

PD1-OSC_OUT 6 31 PA10

NRST1 7 30 PA9

VSS 8 29 PA8

VDDA 9 28 PB15

PA0-WKUP 10 27 PB14

PA1 11 26 PB13

PA2 12 25 PB12
13

14

15

16

17

18

19

20

21

22

23

24
VDD
VSS
PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB2

PB10

PB11

Figure 4-1 LQFP48 pinout diagram

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Pinout and assignment

4.1.2 LQFP32 pins layout

PD5-BOOT0

PA15
VSS

PB3
PB7

PB6

PB5

PB4
32

31

30

29

28

27

26

25
VDD 1 24 PA14

PD0-OSC_IN 2 23 PA13

PD1-OSC_OUT 3 22 PA12

NRST1 4 21 PA11

VDDA 5 20 PA10

PA0-WKUP 6 19 PA9

PA1 7 18 PA8

PA2 8 17 VDD
10

11

12

13

14

15

16
9

VSS
PA3

PA4

PA5

PA6

PA7

PB0

PB1

Figure 4-2 LQFP32 pinout diagram

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Pinout and assignment

4.1.3 QFN32 5x5 mm2 pins layout

PD5-BOOT0

PA15
PB8

PB7

PB6

PB5

PB4

PB3
32

31

30

29

28

27

26

25
VDD 1 24 PA14

PD0-OSC_IN 2 23 PA13

PD1-OSC_OUT 3 22 PA12

NRST1 4 21 PA11
Exposed Pad
VDDA 5 20 PA10

PA0-WKUP 6 19 PA9

PA1 7 18 PA8

PA2 8 17 VDD
10

11

12

13

14

15

16
9

VSS
PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB2

Figure 4-3 QFN32 pinout diagram

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Pinout and assignment

4.1.4 QFN32 4x4 mm2 pins layout

PA15
PA14
PB7
PB6
PB5
PB4
PB3
28
27
26
25
24
23
22
PD5-BOOT0 1 21 PA13
PD0-OSC_IN 2 20 PA10
PD1-OSC_OUT 3 19 PA9
NRST1 4 Exposed Pad 18 PA8
VDDA 5 17 VDD
PA0-WKUP 6 16 VSS
PA1 7 10 15 PB1
11
12
13
14
8
9

VSS/VSSA
PA2
PA3
PA4
PA5
PA6
PA7
PB0

Figure 4-4 QFN28 pinout diagram

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Pinout and assignment

4.1.5 TSSOP20 pins layout

PD5-BOOT0 1 20 PA14

PD0-OSC_IN 2 19 PA13

PD1-OSC_OUT 3 18 PA10

NRST1 4 17 PA9

VDDA 5 16 VDD

PA0-WKUP 6 15 VSS

PA1 7 14 PB1

PA2 8 13 PA7

PA3 9 12 PA6

PA4 10 11 PA5

Figure 4-5 TSSOP20 pinout diagram

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Pinout and assignment

4.2 Pin assignment

Table 4-1 Pin assignment table

QFN32 QFN32 I/O

Type Main Additional
LQFP48 LQFP32 5x5 4x4 TSSOP20 Name (1) level Multiplex function
(2) function function
mm2 mm2
1 ­ ­ ­ ­ NC ­ ­ ­ ­ ­

2 ­ ­ ­ ­ PC13 I/O TC PC13 TIM2_CH1 ­

3 ­ ­ ­ ­ PC14 I/O TC PC14 TIM2_CH2 ­

4 ­ ­ ­ ­ PC15 I/O TC PC15 TIM2_CH3 ­

PD0 UART3_TX
5 2 2 2 2 I/O TC PD0 ­
OSC_IN I2C_SDA
PD1 UART3_RX
6 3 3 3 3 I/O TC PD1 ­
OSC_OUT I2C_SCL
7 4 4 4 4 NRST1 I/O ­ NRST1 ­ ­

8 ­ ­ ­ ­ VSS S ­ VSS ­ ­

9 5 5 1 5 VDDA S ­ VDDA ­ ­
UART2_CTS
TIM2_CH1/TIM2_ETR
PA0
10 6 6 5 6 I/O TC PA0 SPI2_NSS/I2S2_WS ADC1_VIN[0]
WKUP
TIM2_CH3
COMP1_OUT
UART2_RTS ADC1_VIN[1]
11 7 7 6 7 PA1 I/O TC PA1
TIM2_CH2 COMP_INP[0]
UART2_TX
ADC1_VIN[2]
12 8 8 7 8 PA2 I/O TC PA2 TIM2_CH3
COMP_INP[1]
SPI2_NSS/I2S2_WS
UART2_RX ADC1_VIN[3]
13 9 9 8 9 PA3 I/O TC PA3
TIM2_CH4 COMP_INP[2]
SPI1_NSS/I2S1_WS
TIM1_BKIN ADC1_VIN[4]
14 10 10 9 10 PA4 I/O TC PA4
TIM14_CH1 COMP_INP[3]
I2C_SDA
SPI1_SCK/I2S1_CK
TIM2_CH1/TIM2_ETR
ADC1_VIN[5]
15 11 11 10 11 PA5 I/O TC PA5 TIM1_ETR
COMP_INM[0]
I2C_SCL
TIM1_CH3N
SPI1_MISO/I2S1_MCK
TIM3_CH1
TIM1_BKIN
UART2_RX ADC1_VIN[6]
16 12 12 11 12 PA6 I/O TC PA6
TIM1_ETR COMP_INM[1]
TIM16_CH1
TIM1_CH3
COMP1_OUT
SPI1_MOSI/I2S1_SD
TIM3_CH2
TIM1_CH1N
ADC1_VIN[7]
17 13 13 12 13 PA7 I/O TC PA7 TIM14_CH1
COMP_INM[2]
TIM17_CH1
TIM1_CH2N
TIM1_CH3N
TIM3_CH3
TIM1_CH2N
18 14 14 13 ­ PB0 I/O TC PB0 ADC1_VIN[8]
TIM1_CH1N
TIM1_CH3
TIM14_CH1
TIM3_CH4
TIM1_CH3N
TIM1_CH4
19 15 15 14 14 PB1 I/O TC PB1 ADC1_VIN[9]
TIM1_CH2N
MCO
TIM1_CH2
TIM1_CH1N
20 ­ 16 15 ­ PB2 I/O TC PB2 ­ ­

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Pinout and assignment

QFN32 QFN32 I/O

Type Main Additional
LQFP48 LQFP32 5x5 4x4 TSSOP20 Name (1) level Multiplex function
(2) function function
mm2 mm2
I2C_SCL
TIM2_CH3
21 ­ ­ ­ ­ PB10 I/O TC PB10 ­
UART3_TX
SPI2_SCK/I2S2_CK
I2C_SDA
22 ­ ­ ­ ­ PB11 I/O TC PB11 TIM2_CH4 ­
UART3_RX
23 16 ­ ­ 15 VSS S ­ VSS ­ ­

24 17 17 ­ 16 VDD S ­ VDD ­ ­
SPI2_NSS/I2S2_WS
SPI2_SCK/I2S2_CK
25 ­ ­ ­ ­ PB12 I/O TC PB12 TIM1_BKIN ­
SPI2_MOSI/I2S2_SD
SPI2_MISO/I2S2_MCK
SPI2_SCK/I2S2_CK
SPI2_MISO/I2S2_MCK
TIM1_CH1N
SPI2_NSS/I2S2_WS
26 ­ ­ 16 ­ PB13 I/O TC PB13 SPI2_MOSI/I2S2_SD ­
I2C_SCL
TIM1_CH3N
TIM2_CH1
UART3_CTS
SPI2_MISO/I2S2_MCK
SPI2_MOSI/I2S2_SD
TIM1_CH2N
SPI2_SCK/I2S2_CK
27 ­ ­ 17 ­ PB14 I/O TC PB14 SPI2_NSS/I2S2_WS ­
I2C_SDA
TIM1_CH3
TIM1_CH1
UART3_RTS
SPI2_MOSI/I2S2_SD
SPI2_NSS/I2S2_WS
TIM1_CH3N
28 ­ ­ ­ ­ PB15 I/O TC PB15 SPI2_MISO/I2S2_MCK ­
SPI2_SCK/I2S2_CK
TIM1_CH2N
TIM1_CH2
MCO
TIM1_CH1
29 18 18 18 ­ PA8 I/O TC PA8 ­
TIM1_CH2
TIM1_CH3
UART1_TX
TIM1_CH2
UART1_RX
I2C_SCL
30 19 19 19 17 PA9 I/O TC PA9 ­
MCO
TIM1_CH1N
TIM1_CH4
CAN_RX
TIM17_BKIN
UART1_RX
TIM1_CH3
UART1_TX
31 20 20 20 18 PA10 I/O TC PA10 ­
I2C_SDA
TIM1_CH1
SPI2_SCK/I2S2_CK
CAN_TX
UART3_TX
UART1_CTS
TIM1_CH4
32 21 21 21 ­ PA11 I/O TC PA11 CAN_RX ­
SPI2_MOSI/I2S2_SD
I2C_SCL
COMP1_OUT

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Pinout and assignment

QFN32 QFN32 I/O

Type Main Additional
LQFP48 LQFP32 5x5 4x4 TSSOP20 Name (1) level Multiplex function
(2) function function
mm2 mm2
UART3_RX
UART1_RTS
TIM1_ETR
33 22 22 22 ­ PA12 I/O TC PA12 CAN_TX ­
SPI2_MISO/I2S2_MCK
I2C_SDA
TIM1_CH2
SWDIO
UART1_TX
SPI2_MISO/I2S2_MCK
34 23 23 23 19 PA13 I/O TC PA13 ­
MCO
TIM1_CH2
TIM1_BKIN
35 ­ ­ ­ ­ PD2 I/O TC PD2 ­ ­

36 ­ ­ ­ ­ PD3 I/O TC PD3 ­ ­

SWDCLK
UART2_TX
37 24 24 24 20 PA14 I/O TC PA14 ­
UART1_RX
SPI1_NSS/I2S1_WS
SPI1_NSS/I2S1_WS
38 25 25 25 ­ PA15 I/O TC PA15 UART2_RX ­
TIM2_CH1/TIM2_ETR
SPI1_SCK/I2S1_CK
TIM2_CH2
UART1_TX
39 26 26 26 ­ PB3 I/O TC PB3 ADC1_VIN[10]
TIM2_CH3
TIM1_CH1
TIM2_CH1
SPI1_MISO/I2S1_MCK
TIM3_CH1
UART1_RX
40 27 27 27 ­ PB4 I/O TC PB4 ADC1_VIN[11]
TIM17_BKIN
TIM1_CH2
TIM2_CH2
SPI1_MOSI/I2S1_SD
TIM3_CH2
TIM16_BKIN
41 28 28 28 ­ PB5 I/O TC PB5 ­
MCO
TIM1_CH3
TIM2_CH3
UART1_TX
I2C_SCL
42 29 29 29 ­ PB6 I/O TC PB6 ­
TIM16_CH1N
TIM2_CH1
UART1_RX
I2C_SDA
43 30 30 30 ­ PB7 I/O TC PB7 ADC1_VIN[12]
TIM17_CH1N
UART2_TX
PD5
44 31 31 ­ 1 I/O TC PD5 ­ ­
BOOT0
I2C_SCL
TIM16_CH1
45 ­ 32 31 ­ PB8 I/O TC PB8 ­
CAN_RX
UART2_RX
I2C_SDA
TIM17_CH1
46 ­ ­ ­ ­ PB9 I/O TC PB9 CAN_TX ­
TIM1_CH4
SPI2_NSS/I2S2_WS
SPI1_MISO/I2S1_MCK
TIM3_CH1
TIM1_BKIN
UART2_RX ADC1_VIN[13]
­ ­ ­ 32 ­ PD6 I/O TC PD6
TIM1_ETR COMP_INM[3]
TIM16_CH1
TIM1_CH3
COMP1_OUT
47 32 ­ ­ ­ VSS S ­ VSS ­ ­

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Pinout and assignment

QFN32 QFN32 I/O

Type Main Additional
LQFP48 LQFP32 5x5 4x4 TSSOP20 Name (1) level Multiplex function
(2) function function
mm2 mm2
48 1 1 1 ­ VDD S ­ VDD ­ ­

1. I = input, O = output, S = power pins, HiZ = high resistance state.

2. TC: standard IO. Input signal level should not exceed VDD.

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 Pinout and assignment

4.3 Pin multiplexing

Table 4-2 PA port multiplexing AF0-AF8

Pin AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8
UART2_CT TIM2_CH1/T SPI2_NSS/I COMP1_OU
PA0 ­ TIM2_CH3 ­ ­ ­
S IM2_ETR 2S2_WS T
UART2_RT
PA1 ­ TIM2_CH2 ­ ­ ­ ­ ­ ­
S
SPI2_NSS/I
PA2 ­ UART2_TX TIM2_CH3 ­ ­ ­ ­ ­
2S2_WS
PA3 ­ UART2_RX TIM2_CH4 ­ ­ ­ ­ ­ ­
SPI1_NSS/I
PA4 ­ ­ TIM1_BKIN TIM14_CH1 I2C_SDA ­ ­ ­
2S1_WS
SPI1_SCK/I TIM2_CH1/T
PA5 ­ TIM1_ETR ­ I2C_SCL TIM1_CH3N ­ ­
2S1_CK IM2_ETR
SPI1_MISO/ COMP1_OU
PA6 TIM3_CH1 TIM1_BKIN UART2_RX TIM1_ETR TIM16_CH1 TIM1_CH3 ­
I2S1_MCK T
SPI1_MOSI/
PA7 TIM3_CH2 TIM1_CH1N ­ TIM14_CH1 TIM17_CH1 TIM1_CH2N TIM1_CH3N ­
I2S1_SD
PA8 MCO ­ TIM1_CH1 ­ ­ ­ TIM1_CH2 TIM1_CH3 ­

PA9 ­ UART1_TX TIM1_CH2 UART1_RX I2C_SCL MCO TIM1_CH1N TIM1_CH4 CAN_RX

SPI2_SCK/I
PA10 TIM17_BKIN UART1_RX TIM1_CH3 UART1_TX I2C_SDA ­ TIM1_CH1 CAN_TX
2S2_CK
UART1_CT SPI2_MOSI/ COMP1_OU
PA11 UART3_TX TIM1_CH4 CAN_RX I2C_SCL ­ ­
S I2S2_SD T
UART1_RT SPI2_MISO/
PA12 UART3_RX TIM1_ETR CAN_TX I2C_SDA ­ TIM1_CH2 ­
S I2S2_MCK
SPI2_MISO/
PA13 SWDIO ­ UART1_TX ­ MCO TIM1_CH2 TIM1_BKIN ­
I2S2_MCK
SPI1_NSS/I
PA14 SWDCLK UART2_TX UART1_RX ­ ­ ­ ­ ­
2S1_WS
SPI1_NSS/I TIM2_CH1/T
PA15 UART2_RX ­ ­ ­ ­ ­ ­
2S1_WS IM2_ETR

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 Pinout and assignment

Table 4-3 PB port multiplexing AF0-AF8

Pin AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8
PB0 ­ TIM3_CH3 TIM1_CH2N TIM1_CH1N TIM1_CH3 ­ ­ ­ ­

PB1 TIM14_CH1 TIM3_CH4 TIM1_CH3N TIM1_CH4 TIM1_CH2N MCO TIM1_CH2 TIM1_CH1N ­

PB2 ­ ­ ­ ­ ­ ­ ­ ­ ­
SPI1_SCK/I
PB3 ­ TIM2_CH2 UART1_TX TIM2_CH3 ­ TIM1_CH1 TIM2_CH1 ­
2S1_CK
SPI1_MISO/
PB4 TIM3_CH1 ­ UART1_RX ­ TIM17_BKIN TIM1_CH2 TIM2_CH2 ­
I2S1_MCK
SPI1_MOSI/
PB5 TIM3_CH2 TIM16_BKIN MCO ­ ­ TIM1_CH3 TIM2_CH3 ­
I2S1_SD
TIM16_CH1
PB6 UART1_TX I2C_SCL ­ TIM2_CH1 ­ ­ ­ ­
N
TIM17_CH1
PB7 UART1_RX I2C_SDA ­ UART2_TX ­ ­ ­ ­
N
PB8 ­ I2C_SCL TIM16_CH1 CAN_RX UART2_RX ­ ­ ­ ­
SPI2_NSS/I
PB9 ­ I2C_SDA TIM17_CH1 CAN_TX TIM1_CH4 ­ ­ ­
2S2_WS
SPI2_SCK/I
PB10 ­ I2C_SCL TIM2_CH3 ­ UART3_TX ­ ­ ­
2S2_CK
PB11 ­ I2C_SDA TIM2_CH4 ­ UART3_RX ­ ­ ­ ­
SPI2_NSS/I SPI2_SCK/I SPI2_MOSI/ SPI2_MISO/
PB12 TIM1_BKIN ­ ­ ­ ­
2S2_WS 2S2_CK I2S2_SD I2S2_MCK
SPI2_SCK/I SPI2_MISO/ SPI2_NSS/I SPI2_MOSI/ UART3_CT
PB13 TIM1_CH1N I2C_SCL TIM1_CH3N TIM2_CH1
2S2_CK I2S2_MCK 2S2_WS I2S2_SD S
SPI2_MISO/ SPI2_MOSI/ SPI2_SCK/I SPI2_NSS/I UART3_RT
PB14 TIM1_CH2N I2C_SDA TIM1_CH3 TIM1_CH1
I2S2_MCK I2S2_SD 2S2_CK 2S2_WS S
SPI2_MOSI/ SPI2_NSS/I SPI2_MISO/ SPI2_SCK/I
PB15 TIM1_CH3N ­ TIM1_CH2N TIM1_CH2 ­
I2S2_SD 2S2_WS I2S2_MCK 2S2_CK

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 Pinout and assignment

Table 4-4 PC port multiplexing AF0-AF8

Pin AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8
PC13 ­ ­ ­ ­ ­ ­ TIM2_CH1 ­ ­

PC14 ­ ­ ­ ­ ­ ­ TIM2_CH2 ­ ­

PC15 ­ ­ ­ ­ ­ ­ TIM2_CH3 ­ ­

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 Pinout and assignment

Table 4-5 PD port multiplexing AF0-AF8

Pin AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8
PD0 UART3_TX I2C_SDA ­ ­ ­ ­ ­ ­ ­

PD1 UART3_RX I2C_SCL ­ ­ ­ ­ ­ ­ ­

PD2 ­ ­ ­ ­ ­ ­ ­ ­ ­

PD3 ­ ­ ­ ­ ­ ­ ­ ­ ­

PD5 ­ ­ ­ ­ ­ ­ ­ ­ ­
SPI1_MISO/I2S1_MC UART2_R TIM1_ET TIM16_CH TIM1_CH COMP1_
PD6 TIM3_CH1 TIM1_BKIN
K X R 1 3 OUT

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Electrical characteristics

5 Electrical characteristics

5.1 Test condition

All voltages are referenced to VSS unless otherwise stated.

5.1.1 Load capacitor

The load conditions for pin parameters measurement are shown in the Figure 5-1.

C = 50 pF

Figure 5-1 Load condition of the pin

5.1.2 Pin input voltage

The measurement of the input voltage on the pin is shown in Figure 5-2.

VIN

Figure 5-2 Pin input voltage

5.1.3 Power scheme

The power supply design scheme is shown in Figure 5-3.

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Electrical characteristics

POR, PVD, HSE

LSI, IWDG

HSI, PLLs

VDD VCORE

n x VDD
VDD
Regulators

Output

Level shifter
Core logic
n x 100 nF IO logic (CPU, digital
+ 1 x 4.7 μF GPIOs circuit circuits &
Input memory)

n x VSS VSS

VDDA
VDDA
VDDA

VREF+
1 x 10 nF
VREF- ADC COMP
+ 1 x 1 μF
VSS VSSA

Figure 5-3 Power scheme

5.1.4 Current consumption measurement

The measurement of the current consumption on the pin is shown in Figure 5-4.

IDD
VDD

VDDA

Figure 5-4 Current consumption measurement scheme

5.2 Absolute maximum rating

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Electrical characteristics

Stresses above the absolute maximum ratings given in "Absolute Group Maximum
Ratings" list (Table 5-1, Table 5-2 and Table 5-3) may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.

Table 5-1 Voltage characteristics

Symbol Description Minimum Maximum Unit

External main supply voltage (including VDDA and
VDDx­VSSx ­0.3 5.8
VSSA) (1) V
VIN (2) Input voltage on other pins VSS­0.3 VDD+0.3
1. All power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the
external power supply system within the permitted range.
2. The maximum value of VIN must be respected. Refer to the table below for the maximum
allowed injected current values.

Table 5-2 Current characteristics

Symbol Description Maximum Unit

IVDD/VDDA (1) Total current through VDD/VDDA power pins (supply current) (1) +120
IVSS/VSSA (1) Total current through VSS/VSSA ground pins (outflow current) (1) ­120
Output sink current on any I/O and control pins +25
IIO
Output current on any I/O and control pins ­25 mA
NRST pin injection current ±5
IINJ(PIN) (2)(3)
HSE OSC_IN pin injection current ±5
∑IINJ(PIN) (5) Other pins injection current (4) ±25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to an
external power supply in the permitted range.
2. This current consumption must be correctly distributed to all I/O and control pins. The total
output current must not be sunk/sourced between two consecutive power supply pins referring
to high pin count LQFP package.
3. The reverse injection current can interfere with the analog performance of the device.

4. When VIN > VDDA, a positive injected current is generated; when VIN < VSS, a reverse injected
current is generated. Do not exceed IINJ(PIN).

5. When there is simultaneous injection current for multiple inputs, the maximum value of ΣIINJ(PIN)
is equal to the sum of the absolute values of the forward injection current and the reverse
injection current (instantaneous value) .

5.3 Operating conditions

5.3.1 General operating conditions

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Electrical characteristics

Table 5-3 General operating conditions

Symbol Parameter Conditions Min. Typ. Max. Unit

fHCLK Internal AHB clock frequency ­ ­ ­ 72
fPCLK2 Internal APB2 clock frequency ­ ­ ­ 72 MHz
fPCLK1 Internal APB1 clock frequency ­ ­ ­ 72
VDD Digital circuit operating voltage ­ 2.0 3.3 5.5
Analog circuit operating voltage
2.5 3.3 5.5 V
(Performance is guaranteed) Must be the same as
VDDA
Analog circuit operating voltage VDD (1)
2.0 ­ 2.5
(Performance is not guaranteed)
LQFP48 ­ ­ 357
Power dissipation LQFP32 ­ ­ 333
PD Temperature: TA = 85°C (2) mW
or: TA = 105°C (2) QFN32 5x5 mm2 ­ ­ 571
TSSOP20 ­ ­ 270
Ambient temperature (industrial
­ ­40 ­ 85 °C
level)
TA
Ambient temperature (extended
­ ­40 ­ 105 °C
industrial level)
Junction temperature (3)
­ ­40 ­ 105 °C
(industrial level)
TJ
Junction temperature (3)
­ ­40 ­ 125 °C
(extended industrial level)
1. It is recommended to use the same power supply for VDD and VDDA, the maximum permissible
difference between VDD and VDDA is 300mVduring power up and normal operation.

2. If TA is low, higher PD values are allowed as long as TJ (TJ=125°C is the absolute maximum
rating value) does not exceed TJmax.

3. In low power dissipation state, TA can be extended to this range as long as TJ (TJ=125°C is the
absolute maximum rating value) does not exceed TJmax.

5.3.2 Operating conditions at power-up/power-down

The parameters given in the table below are provided under the ambient temperature and
the VDD supply voltage listed in Table 5-3.

Table 5-4 Operating conditions at power-up/power-down

Symbol Conditions Min. Typ. Max. Unit

VDD rise time tr 1 ­ ∞
tVDD us
VDD fall time tf 400 ­ ∞
Vft (3) Power­down threshold voltage ­ 0 ­ mV
1. Data based on characterization results, not tested in production.

2. The VDD waveforms of chip power-on and power-down must strictly follow the tr and tf phased
in the following waveform diagram, and no power-down is allowed during power-on process.
3. Note: To ensure the reliability of chip power-on, all power-on should start from 0V.

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Electrical characteristics

Figure 5-5 Power-on and power-down waveforms

5.3.3 Embedded reset and power control block characteristics

The parameters given in the table below are provided under the ambient temperature and
the VDD supply voltage listed in Table 5-3.

Table 5-5 Embedded reset and power control block characteristics

Symbol Parameter Condition Min. (3) Typ. Max. (3) Unit

PLS[3:0]=0000 (Rising
1.62 1.8 1.98
edge)
PLS[3:0]=0000 (Falling
1.53 1.7 1.87
edge)
PLS[3:0]=0001 (Rising
1.89 2.1 2.31
edge)
PLS[3:0]=0001 (Falling
1.80 2.0 2.20
edge)
PLS[3:0]=0010 (Rising
2.16 2.4 2.64
edge)
PLS[3:0]=0010 (Falling
2.07 2.3 2.53
edge)
PLS[3:0]=0011 (Rising
2.43 2.7 2.97
edge)
PLS[3:0]=0011 (Falling
2.34 2.6 2.86
edge)
Level
PLS[3:0]=0100 (Rising
selection of 2.70 3.0 3.30
edge)
VPVD programmable V
PLS[3:0]=0100 (Falling
voltage 2.61 2.9 3.19
edge)
detectors
PLS[3:0]=0101 (Rising
2.97 3.3 3.63
edge)
PLS[3:0]=0101 (Falling
2.88 3.2 3.52
edge)
PLS[3:0]=0110 (Rising
3.24 3.6 3.96
edge)
PLS[3:0]=0110 (Falling
3.15 3.5 3.85
edge)
PLS[3:0]=0111 (Rising
3.51 3.9 4.29
edge)
PLS[3:0]=0111 (Falling
3.42 3.8 4.18
edge)
PLS[3:0]=1000 (Rising
3.78 4.2 4.62
edge)
PLS[3:0]=1000 (Falling
3.69 4.1 4.51
edge)

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Electrical characteristics

Symbol Parameter Condition Min. (3) Typ. Max. (3) Unit

PLS[3:0]=1001 (Rising
4.05 4.5 4.95
edge)
PLS[3:0]=1001 (Falling
3.96 4.4 4.84
edge)
PLS[3:0]=1010 (Rising
4.32 4.8 5.28
edge)
PLS[3:0]=1010 (Falling
4.23 4.7 5.17
edge)
Power­on
VPOR/PDR (1) reset ­ ­ 1.65 ­ V
threshold
PDR
Vhyst_PDR ­ ­ 30 ­ mV
hysteresis
Reset
TRSTTEMPO (2) ­ ­ 3 ­ ms
duration
1. The product behavior is guaranteed by design down to the minimum value V POR/PDR.
2. Guaranteed by design, not tested in production.
3. Drawn from comprehensive evaluation.
Note: The reset duration is measured from power-on (POR reset) to the time when the user
application code reads the first instruction

5.3.4 Built-in voltage reference

The parameters given in the table below are provided under the ambient temperature and
the VDD supply voltage listed in Table 5-3.

Table 5-6 Build-in voltage reference

Symbol Parameter Conditions Min. Typ. Max. Unit

Built­in voltage
VREFINT ­40°C < TA < 105°C ­ 1.2 ­ V
reference
ADC sampling time
Ts_vrefint (1) when readout build­in ­ ­ 11.8 ­ us
voltage reference
1. The sampling time is obtained through multiple tests

5.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, temperature, I/O pin loading, device software configuration, operating
frequencies, I/O pin switching rate, program location in memory and executed binary code.
All Run-mode current consumption measurements given in this section are performed with
a reduced code.

Maximum current consumption

The MCU is placed under the following conditions:
 All I/O pins are in analog input mode, and connected to a static level - VDD or VSS (no
load)
 All peripherals are disabled except when explicitly mentioned

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Electrical characteristics

 The Flash memory access time is adjusted to the fHCLK (0 ~ 24 MHz is 0 waiting cycle,
24 ~ 48 MHz is 1 waiting cycle, 48 ~ 72 MHz is 2 waiting cycles).
 The instruction prefetching function is on. When the peripherals are enabled: f PCLK1 =
fHCLK.
Note: The instruction prefetching function must be set before setting the clock and bus divider.

The parameters given in the table below are based on the ambient temperature and the
VDD supply voltage listed in Table 5-3.

Table 5-7 Typical current consumption in Run mode

Typical Typical
fHCLK All peripherals enabled All peripherals disabled
Symbol Parameters Condition Unit
(Hz)
­40°C 25°C 85°C 105°C ­40°C 25°C 85°C 105°C
72M 16.26 16.22 16.30 16.19 10.15 10.12 10.20 10.10
48M 12.38 12.35 12.32 12.30 8.31 8.27 8.25 8.24
24M 7.81 7.74 7.72 7.71 5.78 5.70 5.68 5.68
8M 2.64 2.62 2.64 2.67 1.96 1.94 1.96 2.00
Supply Internal
IDD current in clock 4M 1.99 1.98 2.01 2.03 1.61 1.60 1.63 1.63 mA
Run mode source
2M 1.21 1.19 1.21 1.25 1.02 1.00 1.02 1.06
1M 0.81 0.79 0.81 0.84 0.72 0.69 0.71 0.75
500K 0.62 0.59 0.61 0.64 0.57 0.54 0.56 0.59
125K 0.47 0.44 0.46 0.49 0.46 0.43 0.45 0.48

Table 5-8 Typical current consumption in Sleep mode

Typical Typical
fHCLK All peripherals enabled All peripherals disabled
Symbol Parameters Condition Unit
(Hz)
­40°C 25°C 85°C 105°C ­40°C 25°C 85°C 105°C
72M 10.25 10.13 10.02 9.92 4.13 4.04 3.99 3.94
48M 7.18 7.06 6.97 6.90 3.09 3.30 2.95 2.92
24M 4.10 4.00 3.94 3.90 2.06 1.97 1.93 1.91
Supply Internal 4M 1.91 1.87 1.80 1.19 1.54 1.51 1.34 0.82
IDD current in clock mA
Sleep mode source 2M 1.16 1.11 1.15 1.18 0.97 0.93 0.96 1.00
1M 0.79 0.74 0.77 0.80 0.70 0.65 0.67 0.71
500K 0.60 0.56 0.58 0.61 0.56 0.51 0.53 0.56
125K 0.46 0.42 0.43 0.49 0.45 0.41 0.42 0.45

Table 5-9 Typical and maximum current consumption in stop and Standby modes (1)

Typical Maximum (2)

Symbol Parameter Conditions Unit
25°C 25°C ­40~105°C
Supply current Enter Stop mode after
IDD 70.22 150 324 μA
in Stop mode reset, VDD=3.3V

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Electrical characteristics

Typical Maximum (2)

Symbol Parameter Conditions Unit
25°C 25°C ­40~105°C
Supply current
Enter Deep Stop mode
in Deep Stop 1.67 5 55
after reset, VDD=3.3V
mode
Supply current
in Standby IWDG disabled 0.41 3 5.62
mode
1. The I/O state is an analog input.
2. Drawn from comprehensive evaluation.

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in the following table. The
MCU is placed under the following conditions:
 All I/O pins are in analog input mode, and connected to a static level - VDD or VSS (no
load) .
 All peripherals are disabled unless otherwise specified.
 The given value is calculated by measuring the current consumption.
– When all peripherals are clocked off
– When only one peripheral is clocked on
 Ambient operating temperature and VDD supply voltage conditions are listed in Table
5-3.

Table 5-10 On-chip peripheral current consumption (1)

Symbol Parameter Bus Typical Unit

CRC 0.95
GPIOA 0.55
GPIOB 0.56
GPIOC AHB 0.52
GPIOD 0.54
DMA 2.1
HWDIV 1.2
TIM1 8.2
IDD uA/MHz
TIM14 2.0
TIM16 2.7
TIM17 2.8
SPI1 APB2 5.7
UART1 4.8
SYSCFG 0.2
MCUDBG 0.2
COMP 0.4

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Electrical characteristics

Symbol Parameter Bus Typical Unit

EXTI 0.1
ADC 4.1
TIM2 5.8
TIM3 4.4
UART2 5.0
UART3 5.0
SPI2 APB1 5.7
IWDG 0.6
I2C1 6.8
WWDG 0.2
FlexCAN 11.1
1. fHCLK = 72MHz，fAPB1 = fHCLK，fAPB2 = fHCLK, the prescale coefficient of each peripheral is the
default value.

Wake up time from low power mode

The wake-up time listed in the table below is measured during the wake-up process of the
internal clock HSI. The clock source used to wake up the chip depends on the current
operating mode:
Stop or Standby mode: the clock source is the oscillator
Sleep mode: the clock source is the clock used when entering the Sleep mode.
The parameters given in the table below are based on the ambient temperature and the
VDD supply voltage listed in Table 5-3.

Table 5-11 Wake up time from low power mode

Symbol Parameter Conditions Typical Unit

Wake up from Sleep
tWUSLEEP System clock is HSI 3 cycles
mode
Wake up from Stop
tWUSTOP mode (regulator is in System clock is HSI 11 μs
Run mode)
Wake up from Deep
tWUDEEPSTOP Stop mode (regulator System clock is HSI 14 μs
is in low power mode)
Wake up from Standby
tWUSTDBY PWR­>CR[15:14] = 0x1 484 μs
mode
Wake up from Standby
tWUSTDBY PWR­>CR[15:14] = 0x2 425 μs
mode
Wake up from Standby
tWUSTDBY PWR­>CR[15:14] = 0x3 363 μs
mode

5.3.6 External clock source characteristics

High-speed external user clock generated from an external source
The characteristic parameters given in the following table are measured by a high-speed

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Electrical characteristics

external clock source, and the ambient temperature and power supply voltage meet
General operating conditions.

Table 5-12 High-speed external user clock characteristics

Symbol Parameter Condition Min. Typ. Max. Unit

User external clock
fHSE_ext ­ ­ 8 32 MHz
source frequency (1)
OSC_IN input high level
VHSEH ­ 0.7VDD ­ VDD V
voltage
OSC_IN input low level
VHSEL ­ VSS ­ 0.3VDD V
voltage
OSC_IN high or low time
tw(HSE) (1) ­ 15 ­ ­ ns

1. Guaranteed by design, not tested in production

External clock source

Figure 5-6 High-speed external clock source AC timing diagram

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 24 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph is based on the design
simulation results obtained with typical external components specified in the table below.
In the application, the resonator and the load capacitors must be placed as close as
possible to the oscillator pins to minimize output distortion and stabilization time at startup.
Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy...).

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Electrical characteristics

Table 5-13 HSE oscillator characteristics (1)(2)

Symbol Parameter Conditions Min. Typ. Max. Unit

Oscillator 2V<VDD<3.6V 4 8 12 MHz

fOSC_IN
frequency (2) 3.0V<VDD<5.5V 8 16 24 MHz
Feedback
RF ­ ­ 1000 ­ kΩ
resistor (4)
Support crystal fOSC_IN =24MHz, VDD=3V ­ ­ 50 Ω
serial
ESR impedance
(CL1 CL2 (3) is fOSC_IN =12MHz, VDD=2V ­ ­ 120 Ω
16pF)
fOSC_IN =24MHz, ESR=30
HSE current
I2 VDD = 3.3V, CL1 CL2 (3) is ­ 1.5 ­ mA
consumption
20pF
Oscillator
gm transconductan Start up ­ 9 ­ mA/V
ce
tSU(HSE) (5) Startup time VDD is stable ­ 3 ­ ms
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer characteristics
Parameter.
2. Guaranteed by design, not tested in production.
3. For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF
to 25 pF range (Typ.), designed for high-frequency applications, and selected to match the
requirements of the crystal or resonator. CL1 and CL2 are usually the same size. The crystal
manufacturer typically specifies a load capacitance which is the series combination of CL1 and
CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate
of the combined pin and board capacitance) when sizing C L1 and CL2.

4. The relatively low value of the RF resistance can be used to avoid problems arising from the
use of wet conditions to provide protection, this environment results in leakage and bias
conditions have changed. However, if the MCU is applied in bad wet conditions, the design
needs to take this parameter into account.
5. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
8 MHz oscillation is reached. This value is measured for a standard crystal resonator, and it
can vary significantly with the crystal manufacturer.

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Electrical characteristics

860676

Figure 5-7 Typical application with an 8 MHz crystal

5.3.7 Internal clock source characteristics

The characteristic parameters given in the table below are measured using ambient
temperature and supply voltage in accordance with general operating conditions.

High-speed internal (HSI) oscillator

Table 5-14 HSI oscillator characteristics (1)(2)

Symbol Parameter Conditions Min. Typ. Max. Unit

fHSI Frequency ­ ­ 8 ­ MHz
TA = ­40°C~ 105°C ­2.5 ­ +2.5 %
HSI oscillator
ACCHSI TA = ­20°C~ 85°C ­2 ­ +2 %
deviation
TA = 25°C ­1 ­ +1 %
HSI oscillator
Tstab(HSI) ­ ­ ­ 20 μs
startup time
HSI oscillator power
IDD(HSI) ­ ­ 80 ­ μA
consumption
1. VDD = 3.3V, TA = - 40°C ∼ 105°C, unless otherwise specified.
2. Guaranteed by design, not tested in production.

Low-speed internal (LSI) oscillator

Table 5-15 LSI oscillator characteristics (1)

Symbol Parameter Conditions Min. Typ. Max. Unit

fLSI (2) Frequency TA = ­40°C~ 105°C 20 40 70 KHz
LSI oscillator startup
tSU(LSI) (3) ­ ­ ­ 100 μs
time
LSI oscillator power
IDD(LSI) (3) ­ ­ 0.26 ­ μA
consumption
1. VDD = 3.3V, TA = -40°C ∼ 105°C, unless otherwise stated.
2. Drawn from comprehensive evaluation, not tested in production.

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Electrical characteristics

3. Guaranteed by design, not tested in production.

5.3.8 PLL characteristics

The relationship between the input clock frequency f PLL_IN and output clock fPLL_OUT
frequency is:
𝑓𝑃𝐿𝐿_𝐼𝑁 𝑓𝑃𝐿𝐿_𝑂𝑈𝑇
=
PLLDIV[2: 0] + 1 PLLMUL[6: 0] + 1
PLLMUL[6:0] and PLLDIV[2:0] are the frequency division ratio settings of the PLL
frequency divider and output frequency divider.
The parameters listed in the following table are provided under ambient temperature and
power supply voltage in accordance with general working conditions.

Table 5-16 PLL characteristics (1)

Symbol Parameter Conditions Min. Typ. Max. Unit

fPLL_IN PLL input clock (2) ­ 4 8 24 MHz

PLL input clock duty
DPLL_IN ­ 20 ­ 80 %
cycle
fvco VCO output clock ­ 80 ­ 200 MHz
fPLL_OUT PLL output clock ­ 40 ­ 100 MHz
PLL current
IDD(PLL) ­ ­ 1550 ­ uA
consumption
1. Guaranteed by design, not tested in production.

2. Use the correct multiplication factor to ensure the f PLL_OUT is within the allowable range
according to the PLL input clock frequency.

5.3.9 Memory characteristics

Table 5-17 Flash memory characteristics

Symbol Parameter Conditions Min. Typ. Max. Unit

16­bit programming
tprog ­ 131.5 ­ 154.5 μs
time
Page (1024 bytes)
tERASE ­ 4 ­ 6 ms
erase time
tME Mass erase time ­ 30 ­ 40 ms
Read mode
­ ­ 2 mA
40MHz
IDD Supply current Write mode ­ ­ 1.2 mA
Erase mode ­ ­ 0.6 mA

Table 5-18 Flash memory endurance and data retention (1)(2)

Symbol Parameter Conditions Min. Typ. Max. Unit

NEND Endurance ­ 100000 ­ ­ Cycles

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Electrical characteristics

Symbol Parameter Conditions Min. Typ. Max. Unit

TA = 105°C 10 ­ ­
Data
TDR TA = 85°C 20 ­ ­ Years
retention
TA = 25°C 100 ­ ­

5.3.10 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports),
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
 Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
 FTB： A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
following table.

Table 5-19 EMS characteristics

Symbol Parameter Conditions Level/Type

VDD = 3.3V, TA = +25°C，
Voltage limit applied to any I/O pin,
VFESD fHCLK = 72MHz. Conforming 2A
resulting in malfunction
to IEC61000­4­2
Fast transient voltage burst limits
VDD = 3.3V，TA = +25°C，
to be applied through 100 pF on
VFEFT fHCLK = 72MHz. Conforming 2A
VDD and VSS pins to induce a
functional disturbance to IEC61000­4­4

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software.
Therefore, it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.

Software recommendations
The software flowchart must include the management of runaway conditions such as:
 Corrupted program counter

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Electrical characteristics

 Unexpected reset
 Critical Data corruption (for example control registers)

Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range
of specification values. When unexpected behavior is detected, the software can be
hardened to prevent unrecoverable errors.

5.3.11 Functional EMS (Electrical Sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device
is stressed to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.

Static latch-up
Two complementary static latch-up tests are required on six parts to assess the latch-up
performance：

 A supply overvoltage is applied to each power supply pin

 A current injection is applied to each input, output, and configurable I/O pin
These tests are compliant with EIA/JESD78E IC latch-up standard.

Table 5-20 ESD & LU characteristics

Symbol Parameter Conditions Maximum Unit

TA = 25°C, conforming
Electrostatic discharge voltage
VESD(HBM) to ESDA/JEDEC JS­ ±6000 V
(Human body model)
001­2017
TA = 25°C, conforming
Electrostatic discharge voltage
VESD(CDM) to ESDA/JEDEC JS­ ±2000 V
(Charging device model)
002­2018
TA = 105°C, conforming
ILU Latch­up current ±300 mA
to JESD78E

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Electrical characteristics

5.3.12 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 5-3 are used for tests. All I/O
ports are CMOS compatible.

Table 5-21 I/O static characteristics

Symbol Parameter Conditions Minimum Typical Maximum Unit

VIL Low level input voltage VDD = 3.3V ­ ­ 0.8 V
VIL Low level input voltage VDD = 5V ­ ­ 0.3 * VDD V
VIH High level input voltage VDD = 3.3V 2.0 ­ ­ V
VIH High level input voltage VDD = 5V 0.7 * VDD ­ ­ V
Vhy Schmitt trigger hysteresis (1) VDD = 3.3V 0.1 * VDD 0.50 ­ V
Vhy Schmitt trigger hysteresis (1) VDD = 5V 0.1 * VDD 0.60 ­ V
Ilkg Input leakage current (2) VDD = 3.3V ­1 ­ 1 μA
Ilkg Input leakage current (2) VDD = 5V ­1 ­ 1 μA
Weak pull­up equivalent
RPU VDD = 3.3V, VIN = VSS 50 60 75 kΩ
resistor (3)
Weak pull­up equivalent
RPU VDD = 5V, VIN = VSS 50 60 75 kΩ
resistor (3)
Weak pull­down equivalent
RPD VDD = 3.3V, VIN = VDD 50 60 75 kΩ
resistor (3)
Weak pull­down equivalent
RPD VDD = 5V, VIN = VDD 50 60 75 kΩ
resistor (3)
CIO I/O pin capacitance ­ ­ ­ 10 pF
1. Drawn from comprehensive evaluation, not tested in production.
2. If there is reverse current in the adjacent pin, the leakage current may be higher than the
maximum value.
3. The pull-up and pull-down resistors are poly resistors.

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±20mA.
In the user application, the number of I/O pins must ensure that the drive current must be
limited to respect the absolute maximum rating specified in Table 5-1:
 The sum of the currents sourced by all the I/O pins on VDD, plus the maximum operating
current that the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD.
 The sum of the currents drawn by all I/O ports and flowing out of V SS, plus the maximum
operating current of the MCU flowing out on VSS, cannot exceed the absolute maximum
rating IVSS.

Output voltage levels

Unless otherwise stated, the parameters listed in the table below are provided under the

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Electrical characteristics

ambient temperature and VDD supply voltage in accordance with the conditions
summarized in Table 5-3. All I/O ports are CMOS compatible.

Table 5-22 Output voltage static characteristics

MODE[1:0] Symbol Parameter Conditions Minimum Typical Maximum Unit

VOL (1) Output low voltage ­ 0.16 ­
|IIO|= 6mA，
Output high VDD=3.3V
VOH (2) ­ 3.11 ­
voltage
VOL (1)(3) Output low voltage ­ 0.2 0.4
|IIO|= 8mA，
11 Output high
VOH (2)(3) VDD=3.3V 2.4 3.05 ­
voltage
VOL (2)(3) Output low voltage ­ 0.57 ­
|IIO|=20mA，
Output high VDD=3.3V
VOH (2)(3) ­ 2.62 ­
voltage
VOL (1) Output low voltage ­ 0.31 ­
|IIO|= 6mA，
Output high V
VOH (2) VDD=3.3V ­ 2.93 ­
voltage
10
VOL (1)(3) Output low voltage ­ 0.42 ­
|IIO|= 8mA，
Output high VDD=3.3V
VOH (2)(3) ­ 2.79 ­
voltage
VOL (1) Output low voltage ­ 0.31 ­
|IIO|= 6mA，
Output high VDD=3.3V
VOH (2) ­ 2.93 ­
voltage
01
VOL (1)(3) Output low voltage ­ 0.42 ­
|IIO|= 8mA，
Output high VDD=3.3V
VOH (2)(3) ­ 2.79 ­
voltage
1. The current IIO drawn by the chip must always follow the absolute maximum ratings given in the
table, and the sum of IIO (all I/O pins and control pins) cannot exceed I VSS.

2. The current IIO output by the chip must always follow the absolute maximum ratings given in
the table, and the sum of IIO (all I/O pins and control pins) cannot exceed IVDD.
3. Resulted from comprehensive evaluation.

Input/output AC characteristics
The definitions and values of the input and output AC characteristics are given in the
following figure and table, respectively.
Unless otherwise stated, the parameters listed in the following table are provided under
the ambient temperature and supply voltage in accordance with the condition Table 5-3.

Table 5-23 I/O AC characteristics (1)(2)(3)

MODE[1:0] Symbol Parameter Conditions Minimum Typical Maximum Unit

tf(IO)out Output fall time 3.34 4.4 9.27 ns
11
tr(IO)out Output rise time 3.34 4.4 9.27 ns
CL = 50pF
tf(IO)out Output fall time 5.91 10.9 17.0 ns
10 VDD=3.3V
tr(IO)out Output rise time 5.91 10.6 17.0 ns
01 tf(IO)out Output fall time 6.06 10.9 17.4 ns

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Electrical characteristics

MODE[1:0] Symbol Parameter Conditions Minimum Typical Maximum Unit

tr(IO)out Output rise time 6.06 10.8 17.4 ns
1. The speed of the I/O port can be configured through MODEx[1:0]. Refer to the description of
the GPIO port configuration register in this chip user manual.
2. The maximum frequency is defined in Figure 5-8.
3. Guaranteed by design, not tested in production.

External output
load is 50pF

If ((tr + tf) ≤ 2/3)T, and duty cycle is (45 ~ 55%)

when load is 50pF, can achieve maximum efficiency.

Figure 5-8 I/O AC characteristics

5.3.13 NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent
pullup resistor, RPU.
Unless otherwise stated, the parameters listed in the table below are measured under the
ambient temperature and VDD supply voltage in accordance with the condition summarized
in Table 5-3.

Table 5-24 NRST pin characteristics

Symbol Parameter Conditions Min. Typ. Max. Unit

VIL(NRST) (1) NRST input low voltage VDD=3.3V ­ ­ 1.4 V
VIH(NRST) (1) NRST input high voltage VDD=3.3V 2.0 ­ ­ V
NRST Schmitt trigger
Vhys(NRST) VDD=3.3V 0.6 V
voltage hysteresis
Weak pull­up equivalent
RPU VIN = VSS 50 60 75 kΩ
resistor (1)
VF(NRST) (1) NRST input filtered pulse ­ ­ ­ 1.0 uS
VNF(NRST) (1) NRST input not filtered pulse ­ 4.0 ­ ­ uS

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Electrical characteristics

1. Guaranteed by design, not tested in production.

(1)

368560

Figure 5-9 Recommended NRST pin protection

1. The reset network is to prevent parasitic reset

2. The user must ensure that the potential of the NRST pin is below the maximum V IL(NRST) listed
in Table 5-24, otherwise the MCU cannot be reset.

5.3.14 Timer characteristics

The parameters listed in the following table are guaranteed by design.
For details on the characteristics of the input and output multiplex function pins (output
compare, input capture, external clock, PWM output), see section 5.3.12 I/O port
characteristics.

Table 5-25 TIMx (1) characteristics

Symbol Parameter Condition Minimum Maximum Unit

­ 1 ­ tTIMxCLK
tres(TIM) Timer resolution fTIMxCLK =
13.89 ­ ns
72MHz
External clock ­ 0 ­
fEXT frequency of fTIMxCLK = MHz
channel 1 to 4 0 72
72MHz
ResTIM Timer resolution ­ ­ 16 bit
­ 1 65536 tTIMxCLK
16­bit counter
tCOUNTER fTIMxCLK =
period 0.01389 910.2 μs
72MHz
tMAX_COUNT ­ ­ 65536*65536 tTIMxCLK

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Electrical characteristics

Symbol Parameter Condition Minimum Maximum Unit

Maximum
possible
fTIMxCLK =
counter value ­ 59.7 S
72MHz
(TIM_PSC
adjustable)
TIM maximum
tMAX_IN ­ ­ 144 MHz
input frequency
1. Guaranteed by design, not tested in production.

5.3.15 Communication interfaces

I2C interface characteristics
Unless otherwise specified, the parameters given in the following table are derived from
tests performed under the ambient temperature, f PCLK1 frequency and supply voltage
conditions summarized in Table 5-3.
The I2C interface conforms to the standard I2C communication protocol but has the
following limitations: SDA and SCL are not true open-drain pins. When configured as open-
drain output, the PMOS transistor between the pin and VDD is disabled, but still present.
The I2C characteristics are listed in the following table. Refer to section 5.3.12 I/O port
characteristics for details on the characteristics of input/output alternate function pins (SDA
and SCL).

Table 5-26 I2C characteristics

Standard I2C (1) Fast mode I2C (1)

Symbol Parameter Unit
Minimum Maximum Minimum Maximum
tw(SCLL) SCL clock low time 8*tPCLK ­ 8*tPCLK ­ μs
tw(SCLH) SCL clock high time 6*tPCLK ­ 6*tPCLK ­ μs
tsu(SDA) SDA setup time 2*tPCLK ­ 2*tPCLK ­ ns
SDA data retention
th(SDA) 0 (3) ­ (4) 0 (3) ­ (4) ns
time
tr(SDA) SDA and SCL rising
­ 1000 ­ 300 ns
tr(SCL) time
tf(SDA) SDA and SCL fall
­ 300 ­ 300 ns
tf(SCL) time
tvd(DAT) (5) Data valid time ­ 6*tPCLK – 1 (4) ­ 6*tPCLK ­ 0.3 (4) μs
Data valid
tvd(ACK) (6) ­ 6*tPCLK – 1 (4) ­ 6*tPCLK ­ 0.3 (4) μs
acknowledge time
Start condition hold
th(STA) 8*tPCLK ­ 8*tPCLK ­ μs
time
Start condition setup
tsu(STA) 6*tPCLK ­ 6*tPCLK ­ μs
time
Stop condition setup
tsu(STO) 6*tPCLK ­ 6*tPCLK ­ μs
time
Time from Stop
tw(STO:STA) condition to Start 5*tPCLK ­ 5*tPCLK ­ μs
condition (bus idle)
Capacitive load of
Cb 4.7 ­ 1.2 ­ pF
each bus
1. Guaranteed by design, not tested in production.

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Electrical characteristics

2. fPCLK1 must be at least 3MHz to achieve standard mode I2C frequencies. It must be at least
12MHz to achieve fast mode I2C frequencies.
3. Ensure SCL drops below 0.3VDD on falling edge before SDA crosses into the indeterminate
range of 0.3VDD to 0.7VDD.
NOTE: For controllers that cannot observe the SCL falling edge then independent
measurement of the time for the SCL transition from static high (VDD) to 0.3VDD should be used
to insert a delay of the SDA transition with respect to SCL.

4. The maximum th(SDA) could be 3.45 us and 0.9 us for Standard mode and Fast mode, but must
be less than the maximum of tvd(DAT) or tvd(ACK) by a transition time. This maximum must only
be met if the device does not stretch the LOW period (t w(SCLL))of the SCL signal. If the clock
stretches the SCL, the data must be valid by the setup time before it releases the clock.
5. tvd(DAT) = time for data signal from SCL LOW to SDA output.

6. tvd(ACK) = time for Acknowledgement signal from SCL LOW to SDA output.

VDD

4.7K 4.7K

100
SDA

I2C BUS
100
SCL

tf（SDA） tr（SDA） tsu（SDA）

70% 70%
SDA
30% 30%

tvd（DAT）

tf（SCL） th（SDA） tr（SCL） tw（SCLH）

70% 70% 70% 70%

SCL
30% 30% 30% 30%

tw（SCLL） 9th clock

th（STA）

START 1st clock cycle

tw（STO:STA）

SDA

tsu（STA） th（STA） tvd（ACK） tsu（STO）

SCL

RESTART 9th clock STOP START

Figure 5-10 I2C bus AC waveform and measurement circuit (1)

1. Measurement point is set to the CMOS level： 0.3VDD and 0.7VDD.

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Electrical characteristics

SPI characteristics
Unless otherwise specified, the parameters given in the following table are derived from
tests performed under the ambient temperature, f PCLKx frequency and VDD supply voltage
conditions summarized in Table 5-3.
Refer to section 5.3.12 I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO).

Table 5-27 SPI characteristics (1)

Symbol Parameter Conditions Minimum Maximum Unit

Master mode, TA =
fSCK SPI clock ­ 36 (4)
25°C MHz
1/tc(SCK) frequency
Slave mode, TA = 25°C ­ 18
Load capacitance: C =
tr(SCK) SPI clock rise time ­ 6 ns
15pF
Load capacitance: C =
tf(SCK) SPI clock fall time ­ 6 ns
15pF
tsu(NSS)(1) NSS setup time Slave mode 10 ­ ns
th(NSS) (1) NSS hold time Slave mode 10 ­ ns
tw(SCKH) (1) SCK high time ­ tc(SCK)/2­ 6 tc(SCK)/2+ 6 ns
tw(SCKL) (1) SCK low time ­ tc(SCK)/2­ 6 tc(SCK)/2+ 6 ns
Master mode, fPCLK =
tsu(MI) (1) Data input setup 48MHz, prescaler = 2, 15 ­ ns
time high speed mode
tsu(SI) (1) Slave mode 5 ­ ns
Master mode, fPCLK =
th(MI) (1) Data input hold 48MHz, prescaler = 2, 0 ­ ns
time high speed mode
th(SI) (1) Slave mode 5 ­ ns
Data output valid Master mode (after
tv(MO) (1) ­ 15 ns
time enable edge)
Data output valid Slave mode (after
tv(SO) (1) ­ 15 ns
time enable edge)
1. Data based on characterization results. Not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time
to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum
time to put the data in Hi-Z.
4. When the SPI works at its limit speed, it is recommended to connect a serial matching resistor
to the SCK wire to ensure the stability of transmission; and ensure that the SCK wire of the SPI
Master and SPI Slave are as short as possible.

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Electrical characteristics

679527

Figure 5-11 SPI timing diagram-slave mode and CPHA = 0, CPHASEL = 1

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Electrical characteristics

429658

Figure 5-12 SPI timing diagram-slave mode and CPHA = 1, CPHASEL = 1 (1)

1. Measurement points are set at CMOS levels: 0.3VDD and 0.7VDD

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Electrical characteristics

184118

Figure 5-13 SPI timing diagram-master mode, CPHASEL = 1 (1)

1. Measurement points are set at CMOS levels: 0.3VDD and 0.7VDD.

5.3.16 FlexCAN interface

For details on the characteristics of the input and output alternate function pins (CAN_TX
and CAN_RX), see section 5.3.12 I/O port characteristics.

5.3.17 ADC characteristics

Unless otherwise specified, the parameters in the table below are measured under the
ambient temperature, fPCLK2 frequency and VDDA supply voltage in accordance with the
conditions summarized in Table 5-3.

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Electrical characteristics

Table 5-28 ADC characteristics

Symbol Parameter Conditions Min. Typ. Max. Unit

VDDA Supply voltage ­ 2.5 3.3 5.5 V
ADC clock
fADC ­ ­ ­ 16 MHz
frequency
Sampling
fS (1) ­ ­ ­ 1 MHz
frequency
External trigger fADC = 16MHz ­ ­ 1 MHz
fTRIG (1)
frequency (3) ­ ­ ­ 16 1/fADC
Conversion
VAIN (2) ­ 0 ­ VDDA V
voltage range
External input
RAIN (1) ­ See equation 2 kΩ
impedance
Sampling switch
RADC (1) ­ ­ ­ 1.5 kΩ
resistance
Internal sample
CADC (1) and hold ­ ­ ­ 10 pF
capacitance
tSTAB (1) Stabilization time ­ ­ ­ 10 μs
Delay between
tlatr (1) trigger and ­ ­ ­ ­ 1/fADC
conversion start
fADC = 16MHz 0.156 ­ 15.031 μs
tS (1) Sampling time
2.5 ­ 240.5 1/fADC
fADC = 16MHz 0.9375 ­ 15.8125 μs
Total conversion
tCONV (1) time (including 15 ~ 253 (sampling tS +
sampling time) ­ successive approximation 1/fADC
12.5)
Effective number
ENOB ­ ­ 10.7 ­ bit
of bits
1. Guaranteed based on test during characterization. Not tested in production.
2. Guaranteed by design, not tested in production.
3. In this product, VREF+ is internally connected to VDDA， VREF− is internally connected to
VSSA.
4. Guaranteed by design, not tested in production.
5. For external trigger, a delay of 1/fADC must be added.

Input impedance
Equation 2
𝑇𝑆
𝑅𝐴𝐼𝑁 < − 𝑅𝐴𝐷𝐶
𝑓𝐴𝐷𝐶 ×𝐶𝐴𝐷𝐶 ×ln(2𝑛+2 )
The formula above is used to determine the maximum external impedance allowed for an
error below 1/4 of LSB. Here N = 12 (12-bit resolution), is derived from tests under fADC =
15MHz.

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Electrical characteristics

Table 5-29 Maximum RAIN at fADC = 15MHz (1)

TS (cycles) tS (μs) Maximum RAIN (kΩ)

2.5 0.156 0.1
8.5 0.531 4.0
14.5 0.906 7.8
29.5 1.844 17.5
42.5 2.656 25.9
56.5 3.531 34.9
72.5 4.531 45.2
240.5 15.031 153.4
1. Guaranteed by design. Not tested in production.

Table 5-30 ADC static parameters (1)(2)

Symbol Parameter Conditions Typical Unit

Comprehensive
ET ­6/+3
error
EO Offset error fPCLK1 = 24MHz, ­2/+3
fADC = 12MHz,
EG Gain error RAIN < 0.1 kΩ, +3
LSB
Differential VDDA = 3.3V,
ED ­1/+2
linearity error TA = 25°C
Integral
EL ­3/+3
linearity error
1. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any standard (non-
robust) analog input pins should be avoided as this significantly reduces the accuracy of the
conversion being performed on another analog input. It is recommended to add a Schottky
diode (pin to ground) to standard analog pins which may potentially inject negative current. Any
positive injection current within the limits specified for I INJ(PIN) and ΣIINJ(PIN) in section 5.2
Absolute maximum rating does not affect the ADC accuracy.
2. Guaranteed based on characterization. Not tested in production.
The implications of the ADC static parameters are seen below, and the corresponding schematic
diagram is shown in Figure 5-14.

 ET = Total unadjusted error: The maximum deviation between the actual and ideal
transmission curves.
 EO = Offset error: The deviation between the first actual conversion and the first ideal
conversion.
 EG = Gain error: The deviation between the last ideal transition and the last actual
transition.
 ED = Differential linearity error: The maximum deviation between the actual step and
the ideal value.
 EL = Integral linearity error: The maximum deviation between any actual conversion
and the associated line of the endpoint.

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Electrical characteristics

ADC output
EG

4095

4094

4093 Ideal transfer curve

4092

4091 ET End points

correlation line

Actual transfer
curve
5 EL

EO
4

3
ED
2
1 LSB ideal
1

VAIN / VREFH * 4095

0
1 2 3 4 5 6 4092 4093 4094 4095

Figure 5-14 Schematic diagram of ADC static parameters

12-bit
converter

Parasitic
capacitance

Figure 5-15 Typical connection diagram using the ADC

1. See Table 5-28 for the values of RAIN, RADC and CADC.

2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality)
plus the pad capacitance (roughly 7pF). A high Cparasitic value will downgrade conversion
accuracy. To remedy this, fADC should be reduced.

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Electrical characteristics

PCB design recommendations

The power supply must be connected as shown below. The 10nF capacitor in the figure
must be a ceramic capacitor (good quality), and they should be as close as possible to the
MCU chip.

326818

Figure 5-16 Power supply and reference power supply decoupling circuit

5.3.18 Temperature sensor characteristics

The temperature sensor is calculated using the formula below:

Temperature formula
𝑉𝑎𝑙𝑢𝑒 ∗ 𝑉𝐷𝐷𝐴 − 𝑜𝑓𝑓𝑠𝑒𝑡 ∗ 3300
𝑇𝑆𝑎𝑑𝑐 = 25 +
4096 ∗ 𝐴𝑣𝑔_𝑆𝑙𝑜𝑝𝑒
Where offset is recorded in the lower 12bits of 0x1FFFF7F6

Table 5-31 Temperature sensor characteristics (3)(4)

Symbol Parameter Minimum Typical Maximum Unit

VSENSE linearity
TL (1) with respect to ­10 ­ +10 °C
temperature
Avg_Slope (2) Average slope 4.4 4.955 5.313 mV/°C
V25 (1) Voltage at 25°C 1.086 1.465 1.744 V
tSTART (2) Setup time ­ ­ 10 µS
ADC sampling time
tS_temp (2) when reading ­ 11.8 ­ µS
temperature
1. Guaranteed based on characterization. Not tested in production.
2. Guaranteed by design. Not tested in production.
3. The shortest sampling time can be determined by application through multiple iterations.
4. VDD = 3.3V

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5.3.19 Comparator characteristics

Table 5-32 Comparator characteristics (1)

Symbol Parameter Condition Minimum Typical Maximum Unit

HYST = 00, MODE = 00 ­ 0 ­ mV
HYST = 01, MODE = 00 15 22 43 mV
HYST = 10, MODE = 00 32 45 92 mV
HYST = 11, MODE = 00 55 85 182 mV
tHYST Hysteresis
HYST = 00, MODE != 00 ­ 0 ­ mV
HYST = 01, MODE != 00 13 15 23 mV
HYST = 10, MODE != 00 25.2 32 46.7 mV
HYST = 11, MODE != 00 25.5 60 83.9 mV
HYST = 00 ­ ±6 ±10.4 mV

Offset HYST = 01 ­ ±5.5 ±10 mV

VOFFSET
voltage HYST = 10 ­ ±5 ±9 mV
HYST = 11 ­ ±4 ±7 mV
MODE = 00 3.7 10.7 43 ns

Propagation MODE = 01 10.5 34.9 83 ns

tDELAY
delay MODE = 10 13.8 49 114 ns
MODE = 11 22.2 86 194.5 ns
MODE = 00 6.5 45 89.2 uA
Average MODE = 01 3.3 8.6 24.7 uA
Iq working
current MODE = 10 2.6 6 25.4 uA
MODE = 11 1.7 4.6 16 uA
1. Guaranteed by design, not tested in production.

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Package dimensions

6 Package dimensions

6.1 LQFP48

Figure 6-1 LQFP48 package dimension

1. The figure is not drawn to scale.

2. Dimensions are in millimeters.

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Package dimensions

Table 6-1 LQFP48 package dimension details

Millimeters
ID
Minimum Typical Maximum
A ­ ­ 1.6
A1 0.05 ­ 0.15
A2 1.35 1.4 1.45
A3 0.59 0.64 0.69
b 0.18 ­ 0.27
b1 0.17 0.20 0.23
c 0.13 ­ 0.18
c1 0.12 0.127 0.134
D 8.80 9.00 9.20
D1 6.90 7.00 7.10
E 8.80 9.00 9.20
E1 6.90 7.00 7.10
e ­ 0.50 ­
L 0.45 0.60 0.75
L1 1.00REF
L2 0.25BSC
R1 0.08 ­ ­
R2 0.08 ­ 0.2
S 0.2 ­ ­
θ 0◦ 3.5 ◦ 7◦
θ1 0◦ ­ ­
θ2 11 ◦ 12 ◦ 13 ◦
Θ3 11 ◦ 12 ◦ 13 ◦

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Package dimensions

6.2 LQFP32

D A2
A3
D1 0.61BSC

E1
E
PIN1
IDENTIFICATION
e b 0.20

b
b1
0.25BSC

A
c1
c

L
L1
0.10

989913

Figure 6-2 LQFP32 package dimension

1. The figure is not drawn to scale.

2. Dimensions are in millimeters.

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Package dimensions

Table 6-2 LQFP32 package dimension details

Millimeters
ID
Minimum Typical Maximum
A ­ ­ 1.60
A1 0.05 ­ 0.15
A2 1.35 1.40 1.45
A3 0.59 0.64 0.69
b 0.33 ­ 0.42
b1 0.32 0.35 0.38
c 0.13 ­ 0.18
c1 0.117 0.127 0.137
D 8.80 9.00 9.20
D1 6.90 7.00 7.10
E 8.80 9.00 9.20
E1 6.90 7.00 7.10
e ­ 0.80 ­
H 8.14 8.17 8.20
L 0.50 ­ 0.70
L1 1.00REF
R1 0.08 ­ ­
R2 0.08 ­ 0.20
S 0.20 ­ ­
θ 0◦ 3.5 ◦ 7◦
θ1 11 ◦ 12 ◦ 13 ◦
θ2 11 ◦ 12 ◦ 13 ◦

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Package dimensions

6.3 QFN32 5x5 mm2

D A2

e A1
A3

C2

R
c1
e

E2 b
E1 E
H

1
L
32
L
PIN 1 Identifier
D2

978941

Figure 6-3 QFN32 5x5 mm2 package dimension

1. The figure is not drawn to scale.

2. Dimensions are in millimeters.

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Package dimensions

Table 6-3 QFN32 5x5 mm2 package dimension details

Millimeters
ID
Minimum Typical Maximum
A 0.7 0.75 0.80
A1 0.00 0.02 0.05
A2 0.50 0.55 0.60
A3 0.20REF
b 0.20 0.25 0.30
D 4.90 5.00 5.10
E 4.90 5.00 5.10
D2 3.40 3.50 3.60
E2 3.40 3.50 3.60
e ­ 0.5 ­
H 0.30REF
K 0.35REF
L 0.35 0.40 0.45
R 0.09 ­ ­
c1 ­ 0.08 ­
c2 ­ 0.08 ­
N Pin count = 32

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Package dimensions

6.4 QFN32 4x4 mm2

Figure 6-4 QFN32 4x4 mm2 package dimension

1. The figure is not drawn to scale.

2. Dimensions are in millimeters.

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Package dimensions

Table 6-4 QFN32 4x4 mm2 package dimension details

Millimeters
ID
Minimum Typical Maximum
A 0.70 0.75 0.80
A1 0.00 0.02 0.05
A3 0.203REF
b 0.15 0.20 0.25
D 3.90 4.00 4.10
E 3.90 4.00 4.10
D2 2.55 2.70 2.85
E2 2.55 2.70 2.85
e ­ 0.40 ­
K 0.30REF
H 0.35REF
L 0.30 0.35 0.40
R 0.075REF

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Package dimensions

6.5 TSSOP20

e
b

(2°~13°)

E E1

L Θ1
L2 L1
4 ­ Θ3

D
PIN1
IDENTIFICATION

b
b1
A3
A2 A
A1

618013

Figure 6-5 TSSOP20 package dimension

1. The figure is not drawn to scale.

2. Dimensions are in millimeters.

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Package dimensions

Table 6-5 TSSOP20 package dimension details

Millimeters
ID
Minimum Typical Maximum
A ­ ­ 1.20
A1 0.05 ­ 0.15
A2 ­ ­ 1.05
A3 0.34 ­ 0.54
b 0.20 ­ 0.28
c 0.10 ­ 0.19
c1 0.10 ­ 0.15
D 6.40 6.45 6.60
E 6.20 6.40 6.60
E1 ­ 4.35 4.50
e 0.65BSC
L 0.45 0.60 0.75
L2 0.25BSC
L1 1.0REF
R 0.09 ­ ­
θ1 0◦ ­ 8◦

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Revision history

7 Revision history
Table 7-1 Revision history

Date Revision Description

2024/05/14 Rev1.09 1. Update orderable information
2023/09/18 Rev1.08 1. Add QFN32 4x4 mm2 package
1. Added frequency deviation data across ­20°C
to 85°C in HSI oscillator characteristics (1)(2)
2. Added Peripheral status in different power
2023/06/21 Rev1.07
modes table
3. Updated the format of ordering table
4. Fixed the Power scheme figure
2022/11/28 Rev1.06 1. Added QFN28 package
1. Added package power dissipation value
2. Added the limit value of each gear of PVD
3. Added the power consumption limit value of low
power modes
4. Added the LSI frequency limit value
5. Added the limit value of temperature sensor V25
2022/08/10 Rev1.05 and slope
6. Updated SPI maximum speed
7. Updated COMP characteristics table, added
limit value
8. Updated GPIO pull­up and pull­down
equivalent resistor values
9. Added the limit value of IO characteristics
2022/06/27 Rev1.04 Added F0141C
1. Updated NRST & OSC application diagram
2. Added temperature range description in the
marking information
3. Added ENOB to ADC parameters
2022/04/26 Rev1.03 4. Added AF8 to GPIO multiplexing table
5. Modified maximum value at room temperature
in low power mode
6. Newly added the schematic diagram of ADC
static parameters
2022/03/31 Rev1.02 Added power consumption in Sleep mode
Fixed the maximum value of voltage
2022/01/21 Rev1.01
characteristics
1. Fixed I2C communication diagram wrong
description
2022/01/04 Rev1.0
2. Updated COMP pin name to be compatible with
the description on User Manual
2021/12/06 Rev0.6 First public release

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