eres ae mTUnt i 12 13 14 15 1é 17 1g 20 21 22 23 24 25 26 27 28 23 30 31 @ module GrayCounter_tbr reg clky reg reset wire [3:0] GrayOuty // Wadi vgo module GrayCounter a GrayCounter uut ( «clk (clk), «reset (reset), «GrayOut (GrayOut) roo f/ Tgo tin higu clock véi chu ky 10 don vj chéi gian Fo initial begin clk = 6; forever #5 clk = ~clk; — Fo initial begin // Thiét lap test case va nién thi két qué Sdisplay("Time\tclk\treset\tGrayout”) : Smonitor("S$q\tSb\LEb\teb", Stime, clk, reset, GrayOut): // Cac truéng hop test : reset = 1; #10 // Dat lai bé dém Gray reset = 0; $100; {/ 3% be dém Gray chay trong 100 don vi thoi gian reset = 1; #10; // Dat lai mot lan ofa reset = 0; #507 // dé bé dém Gray chey trong 50 don vi thei gian ¢¢ Ket thic md phéng nish;Oh Oe whe ‘o 10 12 AS. 14 i 16 17 module GrayCounter (clk, reset, GrayOut); input clk, reset; output reg [3:0] GrayOut; reg [3:0] binary count; always @(posedge clk or posedge reset) begin if (reset) binary count <= 4'boo00; else binary_count <= binary count + 1; end always @(*) begin GrayOut = (bimary_count >> 1) * binary count; end endaciuiemodule RippleCarryCounter_tb; reg clk: reg reset; wire [3:0] @: // ®néi tao module RippleCarryCounter RippleCarryCounter uut { -clk (clk) , -reset (reset), +0(Q) Ve f// Tao tin hiéu clock véi chu ky 10 don vi théi gian initial begin clk = 0; forever #5 clk = -clk: end initial begin /é Thiét lap test case va hidn thi két qué Sdisplay ("Time\relk\treser\ to") > fmonitor("Sg\téb\ttb\tib”, time, clk, reset, 0); // Cac trung hop test . reset = 17 #107 // 28 lai bé aém reset #100; «= // BE bO dém chay trong 100 don vi thei gian reset = 1; #10; 7 Dat lai mot lan nia reset = 0; #507 ¢/ 28 bé aém chay trong 50 don vi théi gian y/ 8ét tic md phdéng ish;module TEF (clk, reset, T, Q); input clk, reset, I; output reg QO; always @(posedge clk or posedge reset) begin if (reset) Q<- or else if (T) Q<= end endmodule module RippleCarryCounter (clk, reset, OQ); input clk, reset: output [3:0] Q7 wire QO, Q1, 02, 037 TEF tff0 (clk, reset, 1"bl, Q0)+ TEE tffl (QO, reset, 1'bl, Ql); TEE t£iz (Ql, reset, 1'bl, 02); TEE tff3 (02, reset, 1'bl, 03); assign Q = (03, 02, 01, QO}; endmodule| module CLA_4bit({A, B, Cin, Sum, Cout); input [3:0] A, B; f/ Dau wao 4 bit input Cin; ‘/ Carry dau vao output [3:0] Sum; // Bau ra 4 bit output Cout; f/ Carry dau za wire [3:0] B, G, C: // Tao cdc tin higu Propagate va Generate // Tinh toan F ya 6 assign P = A * B; assign G = As B; // Tinh toam cdc bit carry assign C[0] = Cin; assign C[1] = G[0] | (PI9] © C{O]): assign C[2] = G[1] | (P[1] © C{1]): assign C[3] = G[2] | (P[2] © C[2]): assign Cout = G[3] | (F[3] © C[3]): // Tinh toén Sum assign Sum = P * C; endmodule IDs/BVID/CLA1_TB.v - Default ine _| 1 Elmodule CLA_lébit_tb; 2 reg [15:0] A, Bz 3 reg Cin; 4 wire [15:0] Sum; 5 wire Cout 7 // €néi tao module CLA_Lebit 8 Cia lepit wut { 3 AIA), 1a -B(B), iL -Cin{Cin), 12 -Sum (Sum), oe) -Cout (Cout) u r we 15 je a initial begin . 17 // Thiet lap test case va hién thi két qua 8 $display ("Time\tA\c\tB\t\cCin\ cSum\t\tCout™) 2 15 monitor ("Sg\csh\tth\téb\cth\csb", stime, A, B, Cin, Sum, Cout); 20 21 1 Cac trudng ngp vest 22 A = le"n0000; B= 16"n0001; Cin = 0; $10; tra carry khéng 23 R= Le’hFFFF; B = 16"nO001; Cin = 0; #10 tra overflow 24 A= 1lé'hOFOR; B = 1é"hEOFO; Cin = 1; $10; tra véi carry in 25 A= 1€'HARAR; B = 16"hS555; Cin = 0; #107 tra mau bit xen 26 - 27 // Két thie mé phéng 1s $timish: 29 vf end 30 | endmodule1 AG frodule bed_to_sseg_th; 2 3 4 wire [7:0] out; 5 é 7 A bed_to_sseg sseq( 8 «dem (dem), g -dp (dp), 10 «seg (out) aa: | (lt 12 13 14 initial 1s Smonitor("$t input = $b dp = #b output = %b", $time, 16 17 @ A initial begin 13 dp = 0; 20 dom = 4'pooo; al #10 dem = 4'po00 22 #10 dem = 4'b001 23 #10 dem = 4'bO01 2a #10 dem = 4'b0100; 25 #10 dem = 4'b010 26 #10 dem = 4"bO1107 27 #10 dem = 4'b011 28 #10 dem = 4"b1000; as #10 dom = 4"b10017 30 al #10 dp = 1; a2 + send 33 endmodule dom, dp, out):Lné 10 cBe 12 13 1d 15 16 17 18 1g 20 ai 22 23 module bed_to_sseg(input wire [3:0] dom, always @* begin case (dom) default: endcase sseg[7] = end endmodule 1 sseglé sseg[é: sseg[é sseg[é: sseg[é sseg[é: sseg[é sseg[é sseg[é aseg[6: sseg[ 6:0] dp: 7 panononl: 7"pLOO11IL 7"poo10o1o 7"po000110 7 p1oo1100 7*poLoo1g 7"paLooN 7pO001111 7 pan00000 J poo00Lo; J paLllooo; input wire dp, output reg [7:0] 5589);