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Digicomm Exp5

The document outlines an experiment on Quadrature Phase Shift Keying (QPSK) modulation and demodulation conducted at IIT Kharagpur. It details the objectives, required components, theoretical background, circuit design, and observations/results from the experiment. The study emphasizes the implementation of QPSK for transmitting digital information efficiently and the challenges encountered during demodulation.

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Chiradip Biswas
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0% found this document useful (0 votes)
39 views15 pages

Digicomm Exp5

The document outlines an experiment on Quadrature Phase Shift Keying (QPSK) modulation and demodulation conducted at IIT Kharagpur. It details the objectives, required components, theoretical background, circuit design, and observations/results from the experiment. The study emphasizes the implementation of QPSK for transmitting digital information efficiently and the challenges encountered during demodulation.

Uploaded by

Chiradip Biswas
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Digital Communications Lab

EC39002

Experiment-5 : Quadrature Phase Shift Keying (QPSK)


Modulation and Demodulation

IIT Kharagpur

Name : Chiradip Biswas


Roll No : 22EC30016
Grp No : 5
Date: March 29, 2025
1 Aim:
• TASK-1: To implement QPSK modulation for a random bit sequence(Generate the PN
sequence because the clock source information is needed to convert the serial bits into parallel
bits).

• TASK-2 :For the obtained modulated signal, design a demodulator,using simulation.

2 Components required
• IC LM741 op-amp (7x)

• IC M4016 (JFET based switch) (2x)

• Resistor (10x 1kΩ)

• IC 7404 NOT gate (1X)

• pn-junction diode (1N4007) (1x)

• Connecting wires

• Oscilloscope

• Signal Generator

• DC power supply (5v,-5v GND).

3 Theory
3.1 PSK (Phase shift Keying):
PSK is the digital modulation technique in which the phase of the carrier signal is changed by
choosing either the sine and cosine signals at a particular time. PSK technique is widely used for
wireless LANs, biometric, contactless operations, along with RFID and Bluetooth communications.

3.2 QPSK (Quadrature Phase shift Keying):


• The Quadrature Phase Shift Keying (QPSK) is a variation of BPSK, and it is also a Double
Side Band Suppressed Carrier (DSBSC) modulation scheme, which sends two bits of digital
information at a time, called as digits.

• Instead of the conversion of digital bits into a series of digital stream, it converts them into
bit pairs. This decreases the data bit rate to half, which allows space for the other users.

3.3 QPSK Modulator:


The QPSK Modulator uses a bit-splitter, two multipliers with local oscillator, a 2-bit serial to parallel
converter, and a summer circuit.

1
Figure 1: The typical QPSK modulator

At the modulator’s input, the message signal’s even bits (i.e., 2nd bit, 4th bit, 6th bit, etc.) and
odd bits (i.e., 1st bit, 3rd bit, 5th bit, etc.) are separated by the bits splitter and are multiplied
with the same carrier to generate odd BPSK (called as PSKI) and even BPSK (called as PSKQ).
The PSKQ signal is phase shifted by 90° before being modulated. The QPSK waveform for two-bits
input is as follows, which shows the modulated result for different instances of binary inputs:

Figure 2: The typical QPSK modulated signal and message using sinusoid carrier

The modulator’s output is either sine or cos wave and is either the original carrier signal or its
inverted version, phase-shifted by 180°, depending on the data signal. Intuitively, the system’s
robustness improves with greater phase separation between the two states. Since a full phase cycle
is 360°, the maximum possible difference between the phases representing binary 0 and 1 is 180°.
However, shifting a sinusoidal wave by 180° is equivalent to inverting it. As we have both sine and
cosine waves, there will be 2 such pairs (180 degree separation) at 90 degree separation from each
other.

2
Figure 3: The typical QPSK modulation constellation

3.4 Demodulation:
The Demodulation of the QPSK modulated wave is a bit tedious. As we are using the signals sin,-
sin,cos,-cos, we take help of multiplication for demodulation.We may utilize the following circuit to
achieve demodulation:

Figure 4: The theoretical demodulator circuit

3
The modulated wave was sent through 4 multipliers parallely,where in each stream it was being
multiplied by the waves,corresponding to each of the constellation points. For eg: if 00→sin(ωt),
the multiplier used in 1st (0th) multiplier stream was that same sine wave.

Thereafter the dc component of multiplied waves were found for a fixed duration (till 1 set of symbol
persists), like windowed averaging. For each multiplication the dc values were:

• sin(θ) · sin(θ) = 0.5(1 − cos(2θ))

• sin(θ) · −sin(θ) = −0.5(1 − cos(2θ))

• sin(θ) · cos(θ) = 0.5sin(2θ)

• sin(θ) · −cos(θ) = −0.5sin(2θ)

• cos(θ) · sin(θ) = 0.5sin(2θ)

• cos(θ) · −sin(θ) = −0.5sin(2θ)

• cos(θ) · cos(θ) = 0.5(1 + cos(2θ))

• cos(θ) · −cos(θ) = −0.5(1 + cos(2θ))

Now if we observe carefully, for any single wave (sin(θ)) when multiplied with sin(θ) gives a positive
dc value, rest all multiplications yielded either 0 or negative dc values. So the maximum dc level after
multiplication was for same function multiplication only. This is the basis of our symbol prediction
for each time-segment (the duration for which a pair of bits in data-stream persists).

Some important measures in demodulation:

• Symbol Error Rate: The ratio of number of times the predicted symbol from demodulator
is not matching with actual symbol and the total number of symbols demodulator predicted.

• Bit-error Rate: The similar definition when even a single bit in the predicted symbol does
not match with the actual symbol. This error rate is different for each of the bits, so it is to
be computed separately for each bit index.

4
4 Approach to Make Circuits :
We used same frequency for modulator sine wave and data-rate frequency. This condition was
necessary to get proper result of modulation.

Modulator Circuit:

Figure 5: The circuit used for modulating the signal

The blocks used in this circuit are:

• Bit-splitter: This block considers each group of 2 consecutive bits and splits them into 2
halves (each containing 1 bit). The circuit realization of this component was as follows.The
CLK frequency was chosen to be same as the data-rate.

5
Figure 6: Bit splitter circuit

• Inverting Amplifier: These amplifiers were a necessity to obtain 180 degree phase differ-
ence for each modulating signal. The same circuit was also needed for making a buffer that
completely prevents the loading effect on the switching IC.

Figure 7: Inverting Amplifier circuit (provides a gain of -1)

• Voltage Adder: Needed to add the individual signals containing 1 particular modulator wave
for 1 particular ordered pair of splitted-bits. The output gives final QPSK modulated wave.

6
Figure 8: The op-amp based adder

5 Observations and Results


Part-1: Bit-splitter

Figure 9: 2 streams of bit-splitter’s output

7
Figure 10: Yellow: splitted bit-stream 0, Blue: The data stream

Figure 11: Yellow: splitted bit-stream 1, Blue: The data stream

8
Part-2:Modulated Signal In the modulation the symbol to signal mappings we considered are:

• 11 → sin

• 00 → -cos

• 01 → -sin

• 10 → cos

Figure 12: Yellow: the modulated signal, Blue: Original data signal

The demodulation Observations The same constellations used in modulation,were used here as
well.

Figure 13: Green:MSB data, Red:LSB data, Blue: Modulated signal

Upon sweeping the standard deviation of the additive white gaussian noise, the following graphs
were obtained:

9
Figure 14: Symbol error rate vs the SNR

Figure 15: LSB Bit Error Rate vs the SNR

Figure 16: MSB Bit Error Rate vs the SNR

10
6 Discussions 22EC30016
1) MODULATION:

• In this experiment we performed QPSK Modulation using sinusoidal waves (sin and cos). So
the phase differences were 90,180,270,360 degrees.

• Ideally the constellation would have appeared like the following:

Figure 17: The typical QPSK modulation constellation

This contains modulated waves sin, with 45 degree phase difference,with 135 degree phase
difference,with 225 degree phase difference,with 315 degree phase difference.

But in our implementation we used sin with 0,90,180 and 270 degree phase differences. This
constellation produces modulated output with no difference from the 45 degree offset one.

• In the bit-splitter circuit, using the last stage d-flip flops is mandatory to divide the bit-stream
(down-sampling it and providing the consecutive bits together, side by side). This was achieved
by halving the clock frequency and feeding it to the clock of each of the d-flip flops in 1st stage
and the clock of next stage flip-flop is given by the original clock signal, to give a delay of 1/2
clock cycle of the half frequency clock produced.

• The decoder was used to make an one-hot encoding type output to control the signal mul-
tiplexing operation while adding the signals. This ensures that at any period only 1 switch
remains on and only 1 signal is non-zero and the rest are 0.

• We took the sin and cos waveforms directly from signal generator and fed to the switch IC.
In case of producing -sin or -cos, we passed the output of switching IC for the corresponding
wave input was passed through an inverting op-amp based amplifier (giving a gain of -1). For
normal sin and cos waveforms the signal was passed through 2 such inverting amplifiers (acting

11
as buffers). This was done to avoid loading effect on the switching IC.

• Another precaution was taken, by using only 2 switches in each of the switching IC. The
switches used in each of the switching ICs were producing the,as it is wave, and the 180 degree
phase shifted wave.

• One observation made was that, depending upon the sampling time, the sinusoid waveform
used can get phase delayed and may also appear like cos (as it is 90 degree phased shifted
version of the sin). So the mapping of symbols to waveforms can vary.

• the Data stream was produced using a 4 bit shift register with the last 2 bits exor-ed and fed
to the serial data input of the shift register (PN sequence of length 15 generation).

• As we observed in the modulated waveform, compared with the data waveform, the modulation
comes after 1 data bit delay. This is caused at the bit-splitter while obtaining 2 consecutive
bits parallely. So the demodulation is tedious.

2) DEMODULATION:

• The modulated wave was sent through 4 multipliers parallely,where in each stream it was
being multiplied by the waves,corresponding to each of the constellation points. For eg: if
00→sin(ωt), the multiplier used in 1st (0th) multiplier stream was that same sine wave. There-
after the dc component of multiplied waves were found for a fixed duration (till 1 set of symbol
persists), like windowed averaging. The different dc levels in the multiplied signals are clear
from the following graphs:

Figure 18: The modulated wave after being multiplied by each of the sin,cos,-sin,-cos

12
Figure 19: The multiplied signals after computing the window based averages

• At a time, only 1 of the above signals will be high. So from there we can extract the most
similar signal via taking argmax.

• The noise used on the modulated signal is additive gaussian noise, the variance of which can
be changed.

• The Signal-to-Noise Ratio (SNR) is defined as:

Psignal
SNR =
Pnoise

In decibels (dB), it is given by:

 
Psignal
SNRdB = 10 log10
Pnoise

where:

– Psignal is the power of the signal.

– Pnoise is the power of the noise.

The power of each signal is calculated by taking sum of squared values of each of the signal
values.

• From the snr sweep based graphs, we can observe that as the SNR decreases, the symbol error
probability increases.

13
• The Bit error occurs when even a single bit mismatch occurs. This quantity is different for
each bit and can depend on the constellation as well. Generally, we take the 180 degree phase
difference signals at diametrically opposite points on the circle perimeter.

14

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