SIEMENS EDA

Try It: Tessent™ Visualizer

Quick Start and Example
Kit
Sample Data Included
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 Table of Contents

Chapter 1
Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Tessent Visualizer Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Tutorial Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Chapter 2
Tessent Visualizer Tutorials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Tutorial 1: Analyzing and Improving Test Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Tutorial 2: Troubleshooting Problems With an HDL File. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Third-Party Information

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 Table of Contents

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 Chapter 1
Getting Started

The purpose of this document and the example design data is to introduce you to Tessent™
Visualizer. Before performing the tutorials, you should review the information in this chapter.
Tessent Visualizer Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Tutorial Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Tessent Visualizer Overview

Tessent Visualizer is a graphical user interface for Tessent Shell. Tessent Visualizer provides
schematics, browsers, tables, and other reports to help you analyze and understand DFT issues.
Cross-referencing between these ways to visualize your design data can reduce the amount of
time spent on debugging DFT issues, such as low test coverage, DRC analysis, and tracing.

Tutorial Prerequisites
The tutorials in this document require installed design data and access to a Tessent software tree
and applicable software licenses.
Before performing the tutorials in this document, you must ensure the following:

• If you obtained this document by means other than download from Support Center, you
have downloaded an installed the Example Kit (eKit) from Support Center as described
in “Accessing Tutorials for Tessent Visualizer” in the Tessent Shell User’s Manual.
• You have access to a Tessent software tree for the release specified on the title page of
this document.
• You have added the path of your Tessent tree’s bin directory to your $PATH
environment variable.
• Your environment can access all required software licenses.
For configuration and licensing information, see Managing Mentor Tessent Software.

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Getting Started
Tutorial Prerequisites

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 Chapter 2
Tessent Visualizer Tutorials

The tutorials in this chapter demonstrate some basic operations you can perform with Tessent
Visualizer.

Tutorial 1: Analyzing and Improving Test Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Tutorial 2: Troubleshooting Problems With an HDL File . . . . . . . . . . . . . . . . . . . . . . . 13

Tutorial 1: Analyzing and Improving Test

Coverage
This tutorial demonstrates how to analyze test coverage and explore areas of the design that
need coverage improvement.
This tutorial includes the following operations:

• Invoking Tessent Visualizer

• Using the Instance Browser to navigate a design
• Adding data columns to a table
• Sorting and filtering data
• Examining DRC violations and locating a violation on a schematic
• Using the Cell Library Browser to examine a library module
Prerequisites
• You have satisfied the requirements in “Tutorial Prerequisites” on page 5.
Procedure
1. Change the directory to your tutorial location:
$ cd <path>/tesvis_qs_ekit

2. Run the tutorial shell script to prepare your design data:

$ ./tutorial1.sh

The script invokes Tessent Shell on the design data and runs a dofile that sets up the
design. Ignore any errors or warnings.

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Tessent Visualizer Tutorials
Tutorial 1: Analyzing and Improving Test Coverage

3. At the Tessent Shell prompt, invoke Tessent Visualizer:

ANALYSIS> open_visualizer

The Tessent Visualizer GUI opens on the design data.

4. Set the tool to a default state by choosing the Settings > Restore defaults menu item.
Tessent Visualizer opens the Instance Browser and also displays the DRC Browser and
Transcript tabs. The Instance Browser displays the instance hierarchy of the design and
enables you to conveniently navigate. By default, the Tree View selects the top of the
design, and the table lists statistics for test coverage and ATPG Untestable (AU) faults
for the entire design.
The table shows that the Test Coverage is for this design is 85.73%.

5. Determine test coverage loss by adding the “TC Loss” column to the table:

a. Click the Columns and Filters Editor button ( ) to open the Columns and Filters
Editor.
b. Type “loss” in the Filter box in the Name column, and enable the “TC Loss”
checkbox
c. Click OK.

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Tutorial 1: Analyzing and Improving Test Coverage

The “TC Loss” column displays 14.27%, which is the remaining test coverage across the
entire design. To see all of the columns in the table, collapse the right pane of the
Instance Browser by clicking this button in the pane divider:

6. Examine the next level of design hierarchy for test coverage loss:
a. Expand the Tree View and select <top>.

b. Filter for non-zero values in the TC Loss column by entering “>0” in the Filter field
and press Enter.

There is now a funnel icon in the column header that indicates an active filter. You can
sort any column by clicking the header.
Instance U_3 has the highest TC Loss in the design, accounting for 13.03% of coverage
loss.
7. Remove the “>0” filter by clearing the field.

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Tessent Visualizer Tutorials
Tutorial 1: Analyzing and Improving Test Coverage

8. To understand the issue with instance U_3, perform the following steps:
a. Select the U_3 instance in the Tree View.

b. Click the Columns and Filters Editor button ( ) to open the Columns and Filters
Editor and add columns to display statistics for several likely ATPG Untestable fault
sub-classes: AU.EDT, AU.IJTAG, AU.OCC, AU.SEQ, AU.TC, and AU.UNC.

Tip
A quick way to find these sub-classes is to type “au” in the Name column’s Filter
box.

The Columns and Filters Editor describes what each sub-class means. You may need
to scroll to the right or drag the pane boundary to see the new columns.
The AU.SEQ and AU.UNC sub-classes are dominant. These are untestable sequential
depth and unclassified faults. This suggests that the faults in U_3 are untestable due to
limited sequential depth, which is typically associated with non-scan cells.
9. Examine the results of design rule checks run by the dofile at the beginning of this
tutorial:
a. Add the “Total DRC violations” column to the table and remove unnecessary AU
columns by unchecking the names.
b. Select the <top> instance in the Tree View.
c. Sort the “Total DRC violations” column by clicking the column header.
There are 847 total DRC violations for instance U_3.
d. Automatically adjust column widths by clicking the Resize columns to contents
button in the toolbar.

At this point, Tessent Visualizer should look something like this:

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 Tessent Visualizer Tutorials
Tutorial 1: Analyzing and Improving Test Coverage

10. Examine design rule violations with the DRC Browser:

a. Click the DRC Browser tab.
By default, the DRC Browser lists all of the rules that detected violations. Selecting
a rule in the left pane lists the individual violations on the right side of the display.
There are a high number of violations due to non-scan memory elements (D5).
b. To understand where the D5 violations are located, click Group by Instance in the
toolbar.
c. Filter the “Hierarchical name” column with “U_3/*” to display only violations for
U_3.
d. Select a few cell names on the left side to verify the associated violations.
By default, all Tessent Visualizer tables display only the first 250 rows of data,
which is indicated by “250+” on the right side of the pane’s banner. When there are
fewer than 250 rows of data, the actual number is shown without the plus sign (“+”).
e. Scroll to the bottom of the left table to reveal that there are 521 rows of data.
All 521 instances have a D5 violation (non-scan memory element), and the first 361
instances have an additional E5 violation (X-state propagation). The number of non-
scan cells reported suggests that there may have been a problem with scan insertion such
that the cells in U_3 did not convert to scan cells as expected.

11. Select the third cell in the left pane (out_reg[4]) and then double-click the D5-32
violation in the right pane.

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Tutorial 1: Analyzing and Improving Test Coverage

This displays the violating cell (an instance of dff) in the Flat Schematic with a message
about the DRC violation. There are X values on the D and OUT pins.

12. The next step is to determine if the problem is in the library cell itself. Open the Cell
Library Browser with the Open > Cell Library Browser menu item.
The Cell Library Browser lists all of the modules (library cells) in the design, along with
the number of times each module is instantiated. The table also lists the coverage
statistics that the Instance Browser displayed earlier.

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Tutorial 2: Troubleshooting Problems With an HDL File

13. Sort the “Module name” column and select the dff cell.
The average test coverage is only 9.84%, but the maximum test coverage is 100%. This
suggests that the dff cell is correctly modeled but that the dff instances are incorrectly
configured in the design. Typically, any cell with high maximum coverage and low
average coverage suggests potential scan insertion problems.
14. Review the scan insertion scripts and logfiles to determine if the scan chain was properly
inserted in U_3. The actual problem with this tutorial design is that U_3 is incorrectly
specified as a non-scan instance, and thus excluded from scan insertion.
15. Exit Tessent Visualizer by clicking the X in the upper-right corner.
16. Exit Tessent Shell without saving the current test pattern set:
ANALYSIS> quit -f

Results
This concludes the first tutorial.

Tutorial 2: Troubleshooting Problems With an

HDL File
Tessent Visualizer is useful for troubleshooting problems with HDL code because of its tight
integration between the HDL view and the Instance Browser, Cell Library Browser, and
schematic views.
This tutorial shows how to use Tessent Visualizer to troubleshoot a problem with a Verilog
design file. The troubleshooting process includes the following operations:

• Examining the source of a DRC violation on a schematic

• Troubleshooting an error with scan chain insertion
• Tracing a signal path on a schematic
• Recognizing problems on a schematic
• Locating the problem source in HDL code
• Determining the number of times a library module is instantiated in a design
Prerequisites
• You have satisfied the requirements in “Tutorial Prerequisites” on page 5.
Procedure
1. Change the directory to your tutorial location:
$ cd <path>/tesvis_qs_ekit

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Tutorial 2: Troubleshooting Problems With an HDL File

2. Run the tutorial shell script to prepare your design data:

$ ./tutorial2.sh

The script invokes Tessent Shell on the design data and runs a dofile that sets up the
design. However, the dofile does not complete due to a problem with a scan chain
blocked at gate /U_0/CSEEblock. Ignore this error for now. This tutorial shows how to
find the cause of the problem.
3. At the Tessent Shell prompt, invoke Tessent Visualizer:
SETUP> open_visualizer

The Tessent Visualizer GUI opens on the design data.

4. Set the tool to a default state by choosing the Settings > Restore Defaults menu item.
Tessent Visualizer opens the Instance Browser and also displays the DRC Browser and
Transcript tabs.
5. Click the DRC Browser tab and select the T3 rule, which detects when a scan path is
blocked.
The violation message is almost identical to the error message in Step 2.

6. Double-click the T3-1 violation in the right pane.

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Tutorial 2: Troubleshooting Problems With an HDL File

This opens the Flat Schematic on a TIEX gate and an sffr cell. The TIEX gate has a red
outline, which indicates a problem.

7. Before examining the TIEX gate, trace forward from the last scan element traced (as
indicated by the yellow gate outline) to see the next scan cell in the chain. Click the
orange trace marker on the DFF cell’s OUT pin.
This opens the Tracer table at the bottom of the Flat Schematic. The table lists all
connections from the OUT pin of the DFF cell.
8. Add the “Gate data” column for the End pin to the table by using the Columns and
Filters Editor.
If you are not sure how to do this, see Step 5 of Tutorial 1: Analyzing and Improving
Test Coverage.

The (SSS) data in the “Gate data (end)” column indicates which of the two connections
traces to the next scan cell. If the list of connections was long, you could filter for (SSS)
data with the string “*SSS*”.
9. Double-click the table row that lists Gate data (end) = (SSS).

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Tutorial 2: Troubleshooting Problems With an HDL File

This adds the next trace element, a BUF gate, to the Flat Schematic.
10. Click the orange trace marker on the Q pin to continue tracing forward.
The Tracer table updates with 10 new connections. The TIEX gate, where the scan chain
trace stopped, is part of the flat model created during design flattening.
To better understand exactly where the problem exists in the hierarchical design, add the
last MUX traced (the one connected to the OUT pin of the TIEX gate) to the
Hierarchical Schematic.
11. Right-click the MUX symbol and choose Show on Hierarchical Schematic.

The MUX displays in the Hierarchical Schematic as an instantiation of the sffr model.
There is a red triangle on the SI input pin, which indicates a problem. Hovering over the
red triangle displays a tooltip that explains that the pin connection is inconsistent with its
declared direction in Verilog, a condition known as coercion.
12. Click the red triangle on the SI input pin, which opens the Tracer table and lists all of the
connections.
13. Double-click the table entry to trace backwards to the ts_0_intno38 pin in the
CSEEblock_0 module.

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Tutorial 2: Troubleshooting Problems With an HDL File

There are now several red triangles on the schematic. These indicate that the SI input pin
on the state_reg is connected to output port ts_0_intno38. This is likely to be a problem
in the netlist.

14. To examine the netlist, right-click the CSEEblock_0 instance and choose the Show
HDL definition item from the popup menu.
This action opens the Text/HDL Viewer with the CSEEblock_0 module declaration
highlighted. Line 118268 declares port ts_0_intno38 as an output. Line 118284
incorrectly connects the SI port of state_reg to that output port.

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Tutorial 2: Troubleshooting Problems With an HDL File

15. To confirm that the SI pin of the state_reg is declared as an input, right-click the
state_reg symbol in the Hierarchical Schematic and choose the Show HDL definition
item from the popup menu.
This action displays the Text/HDL Viewer and highlights the model declaration. Line
2512 correctly declares the SI port as an input, thus confirming that the problem is with
the CSEEblock_0 module.
16. Determine the extent of the problem; that is, how many times the CSEEblock_0 module
is instantiated in the design:
a. Choose the Search > Search – Instances menu item.
b. Enter CSEEblock_0 in the Filter box for the “Module name” column.
The results indicate that only one instance of this module exists in the entire design.
The incorrect port direction in the module definition is the root cause of the scan
chain issue in this tutorial.
17. Exit Tessent Visualizer by clicking the X in the upper-right corner.
18. Exit Tessent Shell:
SETUP> quit

Results
This concludes the second tutorial.

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 Third-Party Information
Details on open source and third-party software that may be included with this product are available in the
<your_software_installation_location>/legal directory.

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