Proceedings of ESSCIRC, Grenoble, France, 2005

Analog/RF circuit design techniques

for nanometerscale IC technologies
Bram Nauta and Anne-Johan Annema

IC-Design, MESA+ Research Institute,University of Twente, Enschede, The Netherlands

[email protected], [email protected]

In order to analyze the need from a circuit point of view

Abstract: we first look at the trends in systems and then at the
trends in CMOS technology. It's the task of the circuit
CMOS evolution introduces several problems in analog designer to bridge the widening analog gap between the
design. Gate-leakage mismatch exceeds conventional system demands and the available CMOS technology.
matching tolerances requiring active cancellation
techniques or alternative architectures. One strategy to 2. Systems
deal with the use of lower supply voltages is to operate
critical parts at higher supply voltages, by exploiting The trend in system design is twofold. On one hand there
combinations of thin- and thick-oxide transistors. is a trend to integrate more functionality in a single
Alternatively low voltage circuit techniques are multi-purpose device; examples of this include PC’s,
successfully developed. In order to benefit from palmtop computers or mobile telephones. These systems
nanometer scale CMOS technology, more functionality consist of a general purpose digital calculation core, with
is shifted to the digital domain, including parts of the RF a reconfigurable user interface and with a limited amount
circuits. At the same time, analog control for digital and of dedicated I/O functionality. Using these systems, a
digital control for analog emerges to deal with current multitude of different task can be carried out. These tasks
and upcoming imperfections. range from the bare functionality (e.g. making a phone
call) to playing music, playing games, playing movies,
1. Introduction playing… Functionality can easily be added by adding
software. In this first class of systems software is run and
In the past decade electronic systems have popped up signals are processed in the digital domain. The digital
everywhere in our society. They are very cheap in core of these systems is therefore preferably
relation to their (added) functionality and sometimes manufactured in advanced CMOS technology to get low
even just become fashion items, like mobile phones and cost per computation and at the same time low power per
MP3 players. Mass production using Integrated Circuits computation.
is the key to low cost systems. Thanks to integration, On the other hand there is the trend to make more
board design becomes easier and with the right software, distributed, invisible electronic systems that target at
systems can be produced at low cost. Today systems are collecting or delivering data. In general these (for the
highly digitized, enabling this integration in CMOS user) invisible systems are used to control other systems
technology. and as such are highly optimized for one specific task,
The evolution in CMOS technology is motivated by such as sensing the oil pressure in a car or RFID. These
decreasing price-per-performance for digital circuitry; its systems can be seen as sensors or I/O devices for a larger
pace is determined by Moore’s Law. To ensure system. The core of this larger system usually is a
sufficient lifetime for digital circuitry and to keep power programmable multi-purpose device: a system of the first
consumption at an acceptable level, the dimension-shrink kind. The sensory electronics contain dedicated sensors
is accompanied by lowering of nominal supply voltages. and communication hardware and little intelligence; they
While this evolution in CMOS technology is by can be produced in a technology which is optimized for
definition very beneficial for digital, this is not so for these functions which typically is not advanced CMOS
analog circuits [1,2,3]. because of cost reasons and the little need for a big
Contemporary IC’s are mixed-signal systems consisting digital core.
of a large digital core including amongst others a CPU or
DSP and memory, often surrounded by several analog Analog in systems
interface blocks such as I/O, D/A and A/D converters, Almost all systems need to interface with the real analog
RF front ends and more. From an integration point of world. Since the signal processing mainly is done in the
view all these functions would ideally be integrated on a digital domain for efficiency reasons, the required AD
single die. In this case the analog electronics must be converters and DA converters are moving to the edge of
realized on the same die as the digital core and the system. At the same time, traditionally digital blocks
consequently must cope with the CMOS evolution such as I/O are becoming more and more analog due to
dictated by the digital circuit. either high-speed requirements or to high-voltage
requirements. Just like for any analogish circuit, AD

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Proceedings of ESSCIRC, Grenoble, France, 2005

converter performance comes at the cost of area and

power consumption. For this reasons it remains 400
beneficial to put analog preprocessing circuits like 250nm
amplifiers, filters and frequency translation circuits in 300
front to the ADC to relax its performance demands. 180nm
Since the 70s researchers try to integrate these circuits in 200 90nm
CMOS technology, which is primarily developed for gm/gds 120nm
digital circuits. The advantage of integrating analog with 100
digital circuits is the resulting compact and low-cost
single chip solution. During the eighties analog video 0
baseband circuits were integrated in CMOS, covering the -0.25 0 0.25
low MHZ frequency range. In the nineties also RF vGT [V]
circuits for the low GHz range could be designed in
CMOS because the speed of the technology became 1.25
sufficient meanwhile. While companies were reluctant to 90nm
put RF circuits in CMOS, universities continued research 1
and developed new techniques. Today fully integrated
RF transceivers, including digital baseband and MAC IP3 0.75 250nm
layers can be produced on one single CMOS die [4,5,6]. [V] 0.5
Maybe single chip CMOS transceivers are not the best
performing or most cost effective solutions today, but 0.25
thanks to a lot of research effort, the problems are solved
bit by bit. 0
-0.25 0 0.25
Analog challenge from a system point of view vGT [V]
The next challenge for the analog designers form a
system point of view can be split into two directions. The Figure 1: Various DC-properties of transistors as a
first one is to use the technology advances, and move to function of the gate-overdrive voltage with VDS =0.3V
higher frequencies, like 60GHz communications and and L=1um for 4 technologies: (a) the gain, and (b) the
radar. The second direction is to digitize the RF sections output IP3
to achieve both higher programmability and higher
flexibility for multiple standards RF. This trend is In ultra-deep sub-micron (UDSM) CMOS technologies,
towards e.g. software radio [7,8]. the transistor gain is lower-limited by requirements of
the digital circuitry. For its robustness at least a voltage
3. Technology issues gain of about 10 is required using the minimum-length
devices which also results in the relatively weak relation
In the past few decades of technology evolution, planar between output conductance and technology shown in
bulk CMOS was scaled to lower and lower dimensions, Figure 1. However, scaling conventional planar bulk
breaking foreseen limits to scaling all the time. However, devices will stop because of the problems associated
there is a consensus that scaling of planar bulk CMOS with getting sufficient (digital) gain below the 45nm
will stop in the near future, around the 45nm node. In technology node. A discussion of the foreseen solutions
this section first some issues concerning more or less is presented in section 4.
conventional CMOS scaled down to the 45nm node are
3.2 Gate leakage effects
addressed. In section 6, a number of items related to the
successor of the planar bulk device are reviewed. One of the relatively new effects in ultra-deep submicron
CMOS is the significant gate-leakage. One of the first
areas where this became eminent was in low-frequency
3.1 Output conductance effects applications such as PLL-loopfilters and hold-circuits
One of the major issues in analog design is transistor with long time constants. In nowadays UDSM CMOS
gain, and its linearity aspects. As shown in [3] these are gate-leakage may be a serious problem for analog circuit
improving with newer CMOS technologies provided the design because:
voltage headroom and the transistor length are not scaled x it poses a lower limits to the usable frequency
down. This is illustrated in Figure 1: the gain and the IP3 range for integrator circuits; e.g. for filters and
do not change significantly with newer technologies at hold-circuits
constant transistor length L and at constant voltage x it introduces a strong relation between DC-
headroom. With lower voltage headroom the current gain and transistor length, which
performance of transistors decreases. effectively limits accuracy
x its mismatch introduces a new limit to
achievable accuracy
x shotnoise is due to gate-current

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Proceedings of ESSCIRC, Grenoble, France, 2005

All these effect can easily be estimated using the fgate of a 180nm technologies, which is usually sufficient.
MOS transistor. This area-independent and fairly vDS- However the maximum hold time decreases rapidly with
independent parameter is for conventional MOS newer technologies, down to a typical value in the low
transistors [3]: nano-second range for standard 65nm technologies. To
g tunnel get an acceptable hold-time in 65nm CMOS, either thick
f gate oxide transistors or inter-metal capacitances must be
2S C in
used; similar conclusions hold for PLL loop filters.
vGS 13.6
# 1.5 ˜ 10 16 ˜ v GS
2
˜ e tox NMOST Leaky gates result in DC-input current, which sets a
vGS 13.6 lower bound on the current gain of a MOS transistor; as a
# 0.5 ˜ 10 16 ˜ v GS
2
˜ e tox PMOST rough estimation this DC gain is:
2
t ox in [ nm ] vGS in [ V ] iD 1 P ˜ vGT  VT
| 2 ˜ with E igs | 1V
iGS L 2 ˜ E igs ˜ f gate
Figure 2 shows fgate–bands for 4 technologies as derived For a typical 65nm CMOS generation and at low
from measurements. This figure shows that fgate ranges effective gate-overdrive voltages, the current gain is
from roughly 0.1Hz in 180nm technologies to about about unity for L | 30 Pm .
1MHz in 65nm CMOS; for PMOS-transistors, fgate is
roughly a factor 3 lower. This fgate can be used to easily The impact of gate-leakage on matching
estimate the impact of gate leakage on other relevant Gate leakage is caused by quantum-mechanical
properties of MOS transistors. tunnelling and depends on the layer-thickness and the
1GHz
1E+09 field-strength. It therefore exhibits spread that can limit
the achievable level of performance of analog circuits.
65nm Because spread and mismatch are DC effects, they do
1MHz
1E+06 90nm not (from a fundamental point of view) require any
additional power. However, the typically way to
fgate 1E+03 120nm
1kHz minimization is spending area [9,10] which in turn
increases power consumption at a given speed, because
1Hz
1E+00 larger capacitances have to be charged [11].
Gate-leakage mismatch is an extra mismatch source [3]
180nm with an area-dependency different from that of
1mHz
1E-03 conventional matching [9,10,12]. Mismatch of gate
technology leakage current is proportional to the gate current level
with in 65nm CMOS a proportionality constant
Figure 2: fgate ranges for typical analog applications, for X IGS | 0.03 / Area , where Area is the transistor’s gate
NMOS-transistors in different CMOS technologies. For area in square-micron. The total relative mismatch of a
PMOS-transistors fgate is roughly a factor 3 lower. transistor’s drain current is roughly given by the
following relation; current factor mismatch of the
The impact of gate-leakage on filters, integrators and transistors is neglected, which is allowed for practical
hold circuits values of vGT [10].
The fgate by definition gives the frequency below which
the input impedance appears to be mainly resistive. For V id2 V id2 ,conventional V id2 ,gate leakage
frequencies higher than fgate the gate appears to be mainly 
capacitive. For filters this simply implies that a MOS- i D2 i D2 i D2
capacitance can be used as capacitance only for 2 2
§ AVT g m · §X i ·
frequencies much higher than the fgate. For lower ¨ ˜ ¸  ¨ IGS ˜ G ¸
¨ ¸ ¨ ¸
frequencies a (loop-)filter using MOS capacitances © WL i D ¹ © WL i D ¹
effectively is a (non-linear) resistive divider. This leaky
behavior of gates also severely limits applications in
switched-current circuits and sample-and-hold circuits. The first term is the conventional mismatch due to
The droop-rate of MOS-capacitances is as a good mismatch in threshold voltage, with AVT the matching
approximation given by: coefficient. This AVT is a technology-related factor that
dvC ªV º is roughly proportional to the gate-oxide thickness,
| J dvdt ˜ f gate « » with J dvdt | 1V
dt ¬s¼ saturating in UDSM technologies around 2-3mVPm
which relation implies that when accepting a droop of [12]. The second term is the gate current mismatch. The
'V , the maximum (hold-)time is impact of gate-leakage mismatch on the overall
'V mismatch is best illustrated using the square-law relation
't | >s@ which relation is sufficient for rough estimation
J dvdt ˜ f gate purposes. It follows that:
Allowing, e.g., 1mV drop on a sampled-and-held value,
the maximum usable hold-time is in the ms-range in

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Proceedings of ESSCIRC, Grenoble, France, 2005

2 2
§ ] ˜ f gate ˜ L2 ·
2 x the suppression of short channel effects is
V ID § AVT g m ·
¨ ˜ ¸ ¨ ¸ relatively good
i D2 ¨ i ¸ ¨ ¸
© WL D ¹ © WL ¹ x the output conductance can be relatively low
In this relation 9 is a constant that is independent of area x the sub-threshold slope of these devices is near
ideal: about 60mV/decade
and (almost) independent of technology. It follows
x the junctions are small because of the thin-body
directly that high values of fgate result in a large impact of
enclosed by oxide
gate-leakage related mismatch. The previous relation
The fully depleted transistors are basically thin-film SOI
also shows that by linearly scaling of transistors
transistors that come in many flavours. Figure 4b shows
(increasing the width and the length proportionally), with
the type that resembles the planar bulk device in Figure
constant power consumption, the classical mismatch
4a the most. The double-gate variant that probably is the
term decreases while at the same time the gate-leakage
successor or the planar bulk devices is the FinFET
term increases. This yields a maximum usable area and a
[17,19,20,21,22] shown in Figure 4c and 4d. The naming
lower limit on attainable mismatch. With width-scaling
of the FinFET originates from its appearance, see also
and a proportional power-scaling there is no minimum in
Figure 4d for a simplified view; the device resembles a
the reachable mismatch figure. It’s also clear that the fgate
silicon fin on top of a SiO2 layer, with the gate draped
has a significant impact on the minimum attainable
over it to effectively form a gate on (usually only) both
mismatch figure: for maximum matching therefore low-
sides of the fin.
leakage devices should be used.
As conduction takes place on the two sides of the fin, the
10%
gm/ID IG/ID
W of the FinFET is twice the height of a fin (this fin-
height is therefore denoted as W/2 in Figure 4d). The fin–
1% VGT=500mV
VID/ID VGT=200mV
width is small in order to get fully depleted devices with
L
VGT= 50mV decent properties: as a rule of thumb the fin-width is
0.10%
smaller than L/4 which amounts to only 10nm wide fins
W
for 40nm long transistors [23]. Taking into account the
0.01%
1E+0 1E+2 1E+4 1E+6
current shape of the fins [24], the W of FinFETs is
area >Pm2@ heavily discretized at about W # 2 N ˜ Lmin with
10%
N=1,2,3,… and with Lmin the minimum transistor length.
gm/ID There are many differences between the conventional
1% VGT= 50mV planar bulk MOS transistors and the (FD SOI) FinFETs.
L VID/ID VGT=200mV Below a short summary is given, focussing on some
VGT= 500mV
0.10% analog aspects not listed in the previous list.
W
x The body of the FinFET will be almost
0.01% undoped, while the threshold voltage will be
1E+0 1E+2 1E+4 1E+6
area >Pm2@
determined by the workfunction between the
silicon and the metal gate [25]. As a result both
Figure 3: The spread of an MOS transistor in 65nm gate depletion and threshold voltage spread due
CMOS with a) linear scaling of W and L at constant to dopant number fluctuations in the body are
power consumption b) W-scaling, and proportional essentially absent.
powerscaling x Vt-spread will be determined by the spread in
the fin-width [25] and by the spread in the
3.2.1 The impact of gate-leakage on noise workfunction. There’s not yet good data of
expected mismatch and area-scaling relations.
Just as any current across a junction, gate leakage x Conduction takes place on the sidewalls of the
exhibits shot-noise with current density S IG 2 q ˜ I G . As fin, which are formed by etching: this surface is
such, it is equivalent to base-currents in bipolar rough which probably gives rise to excess
transistors. This shot noise comes on top of the induced flicker noise.
gate noise [13,14]. Noise in the gate current therefore x The gate-leakage of FinFETs is reduced by
limits noise performance in analog circuits in UDSM about one order of magnitude compared to that
CMOS [15]. in planar devices because of reduced fields and
quantum confinement effects [26].
4. Future CMOS transistors x The mobility and hence the transistor’s current
factor is orientation dependent in FinFETs
In the past few decades, the transistors in mainstream because of the conduction on the sidewalls of
CMOS technology were planar bulk devices. Scaling of the fin: the crystal orientation can be anything
these planar bulk devices is expected to end around the ranging from (1 0 0) to (1 1 0) [21,27] which
45nm technology node [16,17]. The most likely significantly affects carrier mobility. This
successors are fully depleted (FD) thin-body transistors orientation dependency is expected to give no
[17,18]. These FD thin-body transistors have a number problems in analog circuit design as it is good
of advantages over conventional UDSM transistors: practice to layout matching sensitive transistors
in the same orientation.

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Proceedings of ESSCIRC, Grenoble, France, 2005

x Heat transfer of transistors is lower in SOI

transistors compared to bulk devices: the 1. Pure digital circuits
thermal conductivity of SiO2 is about two orders Pure digital circuits will continue to grow in complexity.
of magnitude lower than that of Si. For typical Driven by Moore’s law the number of gates will grow
analog applications of transistors, with a exponentially, and cost effective ICs will exploit the high
relatively low gate-source overdrive voltage and gate count. Such complex ICs are hard to oversee and
drain-source voltage, this may result in heating this is one of the reasons why digital ICs will contain
of transistors. Heating results in shifted multiple cores (or tiles) of processors, memory, and
transistor parameters that may result in dedicated digital hardware. The cores can operate in
mismatch or thermal hysteresis effects [28, 29]. parallel [30], at locally high speeds and relatively slow
For accurate analog models, the temperature networking over the "large distances". The pure digital
may have to be included as a state-variable. design work is highly automated, and higher order
G G description languages like VHDL are common practice
S D
today. Digital designers don't have to worry much about
S D SOI
SiO2
gate level design anymore; however the challenge is to
oversee such a complex system. To develop a complex
Si Si
IC in a modern technology is very expensive and
a) b) therefore it is beneficial to use the same IC (hardware) in
L different applications by programming its functionality
G in software. One of the great challenges is to program
L S
such a system in an effective way since parallel
G processing is badly supported by todays programming
S SOI D languages.
D
W Digital ways to increase the robustness of essentially
G 2 digital systems include parity checks and ECC (error
SiO2 checking and correcting) [31] which are mainly found in
c) d) fin-width memories and in communication channels.

Figure 4 Upcoming evolution in CMOS transistor 2. Analog circuits for digital

structure a) the conventional planar bulk device b) the Pure digital ICs contain a few basic true analog functions
single-gate thin-body SOI transistor c) top-view of a like power-on-reset and a PLL for internal high speed
FinFET d) side-top view of a FinFET low jitter clock generation which obviously cope with
classical analog implementation problems. However also
the "pure digital" circuits face analog problems. One of
All together, the FinFETs have a number of parameters the first problems encountered was signal integrity [32]:
that are better than those of conventional devices: output digital switching itself creates bounce on supplies and
conductance, gate-leakage and junction capacitances are substrate nodes in such a way that gate speed drops
lower. A number of new effects are introduced; most significantly and even functional errors result. Proper on-
notably new mismatch effects, heating effects and flicker chip decoupling can solve these problems at the cost of
noise which introduce many unknowns in circuit design. area [32].
With the current design aspects of UDSM CMOS The power consumption of digital ICs strongly depends
technologies [3] this gives many new research on the supply voltage and the clock frequency. To
opportunities. minimize power consumption, adaptive supply voltages
and clocks can be used. To implement this, DC-DC
5. Circuit design challenges and converters can be used in control systems where both the
opportunities clock frequency and the supply are lowered in such a
way that the calculation is done just in time. This
From a system point of view analog/RF moves to either adaptive supply can yield significant power savings in
higher speeds or higher flexibility, enabling software practical ICs [33, 34].
signal processing. From a technology point of view the Another application of emerging analog control for
speed of the transistors increases, digital properties digital circuits is the inclusion of many analog circuits as
improve, while at the same time the analog properties get sensors in large digital ICs. Doing so, immunity towards
worse. With this in mind the role of analog circuits for process variation and temperature margin does not need
the future can be predicted. In order to do so, we propose to be taken into account in the design, which may save a
to classify 4 types of electronic circuits: considerable amount of overhead and power
consumption. Examples include measuring the local
1. Pure digital circuits supply voltage [35], the local temperature [36], jitter etc
2. Analog circuits for digital and adapting to them. Another application of sensory
3. Digital circuits for analog electronics in combination with actuators is the
4. Pure analog circuits cancellation of unwanted disturbances [37].
Another issue related to power supply of digital ICs is
the compatibility of new products with old ones. The

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Proceedings of ESSCIRC, Grenoble, France, 2005

internal supply voltage of ICs has been dropping the past idealities caused by capacitor mismatch and finite
decade from 5V down to 1 V today. However lagging operational amplifier (opamp) gain both in the pipelined
behind, the PCB board designs still use higher voltage ADC and the algorithmic ADC.
swings and supplies as standards. For this reason the Digital calibration is also used in RF circuits: for
modern digital ICs should sometimes still look, from the example in [47] calibration techniques are presented that
outside, as if they operate on a higher supply voltage suppress the carrier leakage and enable the direct-
than used internally. This is especially the case for upconversion architecture to meet WCDMA
commodity products like microcontrollers. For this specifications.
reason fully integrated supply voltage regulators [38,39] Another example is found in [6] where a closed-loop RF
and high voltage IO buffers [40] have been developed in calibration is used in a fully integrated transceiver,
modern CMOS technologies. These circuits are designed including digital MAC layers. An RF loop-back path is
at a higher than nominal supply voltage, but by carefully used from the output of the transmit mixer to the input of
stacking devices the circuits can withstand the high the receive mixer. During calibration, a known digital
voltages. sequence is transmitted and looped back to the receiver
The on-chip communication is getting more attention, as and the received digital signal is used to correct for
(global) interconnects are rapidly becoming a speed, analog and RF non-idealities such as DC offset, I/Q
power and reliability bottleneck for digital systems [41]. mismatch, and RF carrier leak. This way matching
Technological advances such as copper interconnects requirements are relaxed and area and power can be
and low-k dielectrics are not sufficient to let the saved.
interconnect bandwidth keep up with the advances in If we observe this trend, then we can foresee analog
transistor speeds. circuits, with many calibration points. Smart algorithms
From a circuit-design perspective, a general solution is can locate the error sources in the digital domain and
the use of repeaters, which is expensive in term of area correct for it. These way at least static errors (gain,
and power. Another proposed solution [42] uses low- mismatch, and even linearity) can be compensated.
swing signaling over differential 10mm aluminum However, noise cannot be compensated for in the digital
interconnects. In [43], it is proposed to use 16µm-wide domain due to its wide band nature: it remains an analog
differential wires (20mm long) and exploit the LC problem. On the system level, however, detection
regime (transmission line behavior) of these wires. algorithms can be improved so that less signal-to-noise is
In [44], it is shown that pulse-width pre-emphasis in needed for the required bit error rate. For example in RF
combination with resistive termination can increase the circuits, inductors are used today to improve the signal to
data-rate to 3Gb/s/ch, using 10mm-long, 0.4µm-wide noise ratio. If we realize that an inductor of a few nH -
differential interconnects. Without the proposed which is necessary for the low GHz range - occupies the
techniques, these interconnects can achieve only same die area as a simple baseband processor in 65nm
0.55Gb/s/ch. So by using analog equalizers which still technology, it is clear that smart digital detection
comply with pure digital swing, a factor 6 in speed techniques can help to overcome noise problems as well.
increase can be achieved over large distances.
4. Pure analog circuits
3. Digital circuits for analog Analog once was the field in which the main chunk of
Analog CMOS circuits typically reside on an IC that has signal processing was done. Since a few decades a
digital signal processing circuits. Since digital circuits continuous shift towards digital signal processing with
have become very compact, analog circuits can some analog processing (or conditioning) of the inputs
nowadays receive help from digital circuits: the analog and outputs of the digital core is apparent. However, still
circuits can be calibrated and can be corrected for the analog circuits are required to get meaningful data into
non ideal behaviour. This calibration can be online, and out of the digital core in an area-efficient and power-
while normal signals are processed, or offline in a special efficient way. Although the area where pure analog is
calibration mode. This correction in turn can be done in applied will inevitably shrink to a (non-zero) minimum,
the analog domain (where typically a DA converter the requirements on analog circuits will continue to
injects a static signal in the analog circuit) or in the increase while the CMOS implementation environment
digital domain (where an error can be subtracted). Below gets worse and worse.
some examples of calibrated circuits are given. One fundamental problem for analog CMOS circuits is
This trend of calibrating is clearly observable in AD the lowering supply voltage. This problem can be tackled
converters. In pipeline ADC's amplifier non-linearities in 2 ways. Design analog circuits that operate at a low
are a major concern and in [45] background calibration voltage or design analog circuits that can withstand
was implemented to correct for these sources of higher than nominal supply voltages.
impairment. This allows the use of simple power- The first approach was popular during the past 15 years
efficient open-loop residue amplifiers, which are more where the supply dropped from 5V down to 1.2 V today.
compatible with modern CMOS technologies. Many new circuit techniques have been developed
ADCs can even be calibrated on line in background, with recently, for example the switched opamp technique [48]
a calibrated auxiliary ADC. In [46] a pipelined analog- where switches in switched capacitor are moved from the
to-digital converter (ADC) is calibrated in background signal path to the supply path, where they need less gate
using an algorithmic ADC, which is itself calibrated in drive. Recently a similar approach has been
foreground. The calibration overcomes the circuit non- demonstrated for Gilbert type of mixers [49]

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Proceedings of ESSCIRC, Grenoble, France, 2005

Despite all the research effort, today the bare minimum Wrap up
supply for an analog circuit seems to be VGS+VDSSAT+ In the past decades, much functionality shifted from the
vswing, where vswing is the signal swing. If still enough (traditional) analog domain to the digital domain because
SNR is needed then the noise has to be lowered. This can of (area and power) efficiency reasons. Apart from this
simply be done via impedance level scaling, and the shift, there is also a clear trend towards mixing analog
result is that 10dB less noise will result in 10 times more and digital. In the near future high-performance digital
power consumption (for the same supply voltage, blocks include analog sensory and control systems, while
SINAD, bandwidth, etc). analog circuits tend to include more and more digital
Thermal noise can even be cancelled [50] but also at the compensation and control.
cost of power dissipation. 1/f noise is a major concern as
well since the corner frequency, where thermal noise controlled:
dominates the 1/f noise seems to be proportional to ft in a analog digital
given technology. So since ft is usually chosen high, to
benefit from the bandwidth, 1/f noise will be large as adaptive clock
well. Chopping and double correlated sampling can adaptive supply voltage
remove 1/f noise for low frequency application. measure temperature

digital
Switched bias technique can reduce the intrinsic 1/f noise measure local variations
of transistors [51] decrease local noise redundancy
The second approach is to design circuits that can multi-level I/O parity bit
withstand higher than nominal supply voltages. This is on-chip modems ECC
usually done via stacking of transistors while taking care
function:
that each transistor does not breakdown, including during
transients and startup.
These circuits at higher supply were first found in chopping digital calibration
interfacing drivers [40] and later in (RF) PAs [52,53], but switched circuits pre-distortion
nowadays also normal "internal" analog circuits need to switched bias post-processing
analog

use these techniques to get performance at todays 1V noise cancelling

supply voltage. This can be done, but careful simulation “high-voltage” circuits
has to be done by the designers, because moderate analog calibration
breakdown effects are hard to see during production test DEM
and may show up during the lifetime of the IC.

Analog circuits will operate at higher frequencies as

well. At high frequencies it’s beneficial to use inductors In the limiting case, every digital subblock has its own
for high Q circuits, like oscillators and tuned amplifiers analog control block to eliminate e.g. interference and
Inductor quality factors (Q) increase with frequency and the effects of spread in components and operating
at frequencies beyond say 40GHz Q factors of integrated conditions. At the same time every analog subblock
spiral inductors are higher than the Q factors of the (down to single transistors) comes with its own digital
resonating capacitors. Realizing this, the designer does control to compensate for things like spread and low-
not have to take care for max Q of inductors, and also frequency noise.
since that the values of inductances are small for high
frequencies, the inductors can be laid out in a very 6. Conclusions
compact way: for example in a compact U shape instead
of a circle [54]. So for very high frequencies inductors The evolution of CMOS technology will continue for
can be used at many nodes in a circuit. many years to come, which is benificial for digital
circuits but which is not so for analog. An extensive
discussion of relatively new non-ideal effects such as
gate-leakage and output conductance is given in this
paper, as is a discussion of the probably successor of the
conventional MOS transistor.
On system level, there has been a longlasting trend
towards shifting as much functionality from the purely
analog domain to the purely digital domain. From a high
level of abstraction this trend will continue, but at closer
look the purely analog and digital blocks will disappear:
the strive towards more circuit performance out of less
perfect transistors yields a clear trend towards analog
control for digital and towards digital control for analog.
In both ways, analog design knowledge becomes crucial
for modern ICs, even if they are "purely" digital.

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[15] A. Stek, G.W. de Jong, T.P.H.G. Jansen, J.R.M.

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