HANOI UNIVERSITY OF SCIENCE AND TECHNOLOGY

School of Electrical and Electronic Engineering

PROJECT REPORT
DIGITAL DESIGN USING VHDL

Image processing on FPGA using Verilog

Bui Vu Hai 20213608

Nguyen Ngoc Minh 20210588
Dao Minh Quang 20213636

Class: ET5080E - 152294

Instructor: PhD. Vo Le Cuong

Hanoi, 12/2024
 TABLE OF CONTENTS

ABBREVIATIONS i

LIST OF FIGURES ii

Acknowledgement iii

Task Assignment iv

Abstract 1

1 Introduction 2
1.1 Project Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 Image Theory Review 4

2.1 Digital Images as Pixel Grids . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Color Representation (RGB) . . . . . . . . . . . . . . . . . . . . . . . 4
2.3 Image File Formats (BMP) . . . . . . . . . . . . . . . . . . . . . . . . 4
2.4 Basic Image Processing Operations . . . . . . . . . . . . . . . . . . . . 5
2.5 Hexadecimal Representation . . . . . . . . . . . . . . . . . . . . . . . 8

3 Design and Implementation 9

3.1 System Overall Design . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Code Flow and Implementation . . . . . . . . . . . . . . . . . . . . . . 10
3.2.1 Image Input (Reading Module - image_read.v) . . . . . . . . . 11
3.2.2 Image Processing Module (within image_read.v) . . . . . . . . 15
3.2.3 Image Output (Writing Module - image_write.v) . . . . . . . . 15
3.2.4 Parameter File (parameter.v) . . . . . . . . . . . . . . . . . . . 17
3.2.5 Testbench (tb_simulation.v) . . . . . . . . . . . . . . . . . . . 17
4 Experimental Results 19
4.1 Simulation Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5 Conclusion 26
 ABBREVIATIONS

B Blue
BMP Bitmap
BGR Blue Green Red
CPU Central Processing Unit
FPGA Field Programmable Gate Array
FSM Finite State Machine
G Green
GPU Graphic Processing Unit
HDL Hardware Design Language
Hex Hexadecimal
I/O In/Out
JPG Joint Photographic Experts Group
ms Microsecond
ns Nanosecond
PNG Portable Network Graphics
R Red
RAM Randon Access Memory
RGB Red Green Blue

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 LIST OF FIGURES

Figure 2.1 Original Image . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2.2 Image with lower brightness . . . . . . . . . . . . . . . . . . . . 6
Figure 2.3 Image with higher brightness . . . . . . . . . . . . . . . . . . . 6
Figure 2.4 Image with color inversion . . . . . . . . . . . . . . . . . . . . 7
Figure 2.5 Image with threshold editing . . . . . . . . . . . . . . . . . . . 8
Figure 3.6 Data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3.7 Image processing dataflow . . . . . . . . . . . . . . . . . . . . 10
Figure 3.8 Image Conversion (Matlab) . . . . . . . . . . . . . . . . . . . . 12
Figure 3.9 Verilog Module for Reading and Processing Image Code Flow . 14
Figure 3.10 Image Output (Writing Module - image_write.v) . . . . . . . . . 16
Figure 3.11 Testbench (tb_simulation.v) . . . . . . . . . . . . . . . . . . . . 17
Figure 4.12 Original Image . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 4.13 Image with lower brightness . . . . . . . . . . . . . . . . . . . . 20
Figure 4.14 Lower brightness waveform . . . . . . . . . . . . . . . . . . . . 20
Figure 4.15 Image with higher brightness . . . . . . . . . . . . . . . . . . . 21
Figure 4.16 Higher brightness waveform . . . . . . . . . . . . . . . . . . . . 21
Figure 4.17 Image with color inversion . . . . . . . . . . . . . . . . . . . . 22
Figure 4.18 Color inversion waveform . . . . . . . . . . . . . . . . . . . . . 22
Figure 4.19 Image with threshold editing . . . . . . . . . . . . . . . . . . . 23
Figure 4.20 Threshold waveform . . . . . . . . . . . . . . . . . . . . . . . . 23

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 Acknowledgement

The successful completion of this work would not have been possible without the
invaluable guidance and support of several individuals. We would like to express our
sincere gratitude to our professor, Dr. Vo Le Cuong, for his exceptional teaching and for
sharing his profound knowledge in this field. His inspiring teaching style and emphasis
on the importance of research have been instrumental in shaping our understanding and
approach to this project. We are particularly thankful for his meticulous feedback and
guidance during the report writing process.
Furthermore, we extend our appreciation to our Teaching Assistant, Mr. Nguyen
Trong Hung, for his remarkable friendliness and unwavering enthusiasm in supporting
us throughout the course. His comfortable and easy-to-understand teaching style has
made complex concepts accessible, and he has been one of the most impressive TAs we
have had the pleasure of learning from.
Finally, we would like to thank our classmates for their collaborative spirit and
support. Studying alongside such a dedicated and encouraging group has been a truly
enjoyable experience, and we value the camaraderie we have shared. We love studying
with them.

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 Task Assignment

Member Assigned Tasks

Nguyen Ngoc Minh Planning, Task Assignment, Report Content, PowerPoint,
Image Theory and FPGA/Verilog Research, Code
Dao Minh Quang Report Content, Latex, Graph Plotting, Image Theory and
FPGA/Verilog Research, Code
Bui Vu Hai Report Content, Latex, Powerpoint, Verilog/FPGA Re-
search, Code, Simulation

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 Abstract

This report details the development and verification of an image processing system
implemented in Verilog Hardware Description Language (HDL). The project focuses
on demonstrating the fundamental principles of handling and manipulating image data
within a simulation environment using ModelSim. While not targeted for direct hard-
ware implementation, the system effectively models an image processing pipeline con-
sisting of image input, basic image enhancement, and image output stages. The image
input stage, simulated by a Verilog module, reads pre-processed hexadecimal image
data, mimicking the behavior of an image sensor by generating synchronized pixel
data and control signals. Image processing operations, including inversion, brightness
control, and thresholding, are implemented within the input module, selectable via
a parameter file. The image output stage utilizes a Verilog module to write the pro-
cessed pixel data, along with the necessary header information, into a standard Bitmap
(BMP) image file for visual verification. Simulation results demonstrate the functional
correctness of the implemented algorithms, showcasing the successful generation of
output images corresponding to each processing operation. This project highlights the
importance of simulation and modular design in the FPGA development flow for im-
age processing applications and provides a valuable foundation for understanding the
translation of image processing concepts into hardware descriptions. The limitations
of the current design for direct hardware synthesis, particularly regarding memory
management, are also discussed. Our code and relevant files are inspired from [1] [2]

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 1 Introduction

1.1 Project Overview

Image processing is essential in fields like computer vision, medical imaging,
robotics, and autonomous systems, enabling tasks such as object detection, pattern recog-
nition, and image restoration. While widely applicable, traditional hardware like CPUs
and GPUs often struggle with real-time performance and computational efficiency. Sim-
ilarly, using Python for image processing, though ideal for prototyping, can face limita-
tions in speed and scalability for intensive tasks.
Field-Programmable Gate Arrays (FPGAs) provide an attractive alternative for
overcoming these challenges. With their reconfigurable hardware and inherent paral-
lelism, FPGAs excel in high-speed, real-time processing while maintaining energy effi-
ciency. These advantages make them ideal for demanding image processing applications
where low latency and optimized performance are critical.
This project details an image processing system implemented in Verilog Hardware
Description Language (HDL), emphasizing simulation and functional verification using
ModelSim. While not targeted for direct implementation on a physical FPGA, the project
effectively demonstrates the fundamental principles of handling and manipulating image
data within a hardware description language context.

1.2 Motivation
Developing and verifying complex FPGA designs can be a time-intensive and chal-
lenging process. This project is motivated by the need to provide a clear and accessible
understanding of how to represent, process, and manipulate image data using Verilog,
specifically within a simulation environment. The focus on simulation allows for rapid
prototyping and validation of image processing algorithms, enabling designers to iter-
ate and refine their designs efficiently before committing to resource-intensive hardware
implementation. By concentrating on the design and compilation within ModelSim, this
work aims to offer valuable insights into the practical aspects of designing and verifying
image processing algorithms in Verilog.

1.3 Objectives
The primary goal of this project is to demonstrate the fundamental steps involved
in processing image data using Verilog HDL within a simulated FPGA environment.
The specific objectives include:

• Developing a Verilog-based workflow for reading image data from a file, simulating

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 the behavior of an image source.

• Implementing basic image enhancement algorithms, such as inversion, brightness

control, and thresholding, in Verilog.

• Designing the necessary control logic and data flow within the Verilog modules to
perform the image processing operations.

• Developing a Verilog module to write the processed image data back to a file for
visual verification of the results.

• Utilizing ModelSim for simulation and functional verification of the implemented

image processing pipeline.

• By achieving these objectives, this project lays the groundwork for understanding
the design and verification of image processing algorithms in Verilog, providing a
solid foundation for future FPGA-based implementations.

3
 2 Image Theory Review

This section reviews basic concepts in image theory, focusing on simple topics such
as image representations and basic operations. These fundamental ideas are straightfor-
ward, yet essential, for understanding and implementing more advanced image process-
ing techniques. By emphasizing simplicity, we aim to provide a clear starting point for
the project’s technical focus.

2.1 Digital Images as Pixel Grids

• Pixels: The most fundamental unit of a digital image. Think of them as tiny squares
of color that, when arranged together, form the image. The word "pixel" is a con-
traction of "picture element."

• Image Dimensions: Images have a width and a height, representing the number
of pixels horizontally and vertically, respectively. The code uses WIDTH and
HEIGHT parameters.

• Raster Scan Order: Image data is often processed and stored in a sequential manner,
typically row by row, from left to right. This is called raster scan order. You can see
this in the nested for loops in both the MATLAB and Verilog code. The MATLAB
code specifically handles the BMP’s bottom-up row order.

2.2 Color Representation (RGB)

• RGB Color Model: The most common way to represent colors in digital images. It
uses three primary color components: Red, Green, and Blue.

• Color Depth (Bit Depth): Determines the number of bits used to represent each
color component. The code mentions a 24-bit BMP image (RGB888). This means
8 bits are used for Red, 8 for Green, and 8 for Blue.

• Value Range: With 8 bits per component, each color component can have values
from 0 to 255. 0 represents the absence of that color, and 255 represents its maxi-
mum intensity. The code frequently checks for values exceeding 255 or going below
0 to prevent color overflow/underflow.

• Pixel Value: A single pixel in a 24-bit RGB image is represented by three values
(R, G, B), defining its color

2.3 Image File Formats (BMP)

• Bitmap (BMP): A common raster graphics image file format. It stores image data
pixel by pixel.

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 • BMP Header: BMP files have a header that contains metadata about the image,
such as:

– File Size: The total size of the BMP file.

– Image Dimensions (Width and Height): As mentioned before.
– Color Depth: The number of bits per pixel (e.g., 24 for RGB888).
– Data Offset: The starting address of the actual pixel data within the file.
– Other information: Compression methods (often none for simple BMPs), color
palettes (for indexed color images, not directly used here).
– Pixel Data Storage in BMP: For 24-bit BMPs, the pixel data is typically stored
in BGR order (Blue, Green, Red) for each pixel, and the rows are stored from
bottom to top. This is why the MATLAB code iterates the rows in reverse and
the Verilog code compensates for this when reading.

Figure 2.1 Original Image

2.4 Basic Image Processing Operations

The code implements three fundamental image processing techniques

• Brightness Control

– Concept: Modifying the overall lightness or darkness of an image by adding or

subtracting a constant value from each pixel’s color components (R, G, B)
– Implementation: The code adds (SIGN == 1) or subtracts (SIGN == 0) the
VALUE parameter from each R, G, and B component

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 – Clipping: Important to prevent color values from going outside the valid 0-255
range. If a value exceeds 255, it’s clipped to 255; if it goes below 0, it’s clipped
to 0.

Figure 2.2 Image with lower brightness

Figure 2.3 Image with higher brightness

• Inversion (Negative)

– Concept: Converts an image into a binary (black and white) image based on a

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 threshold value. Pixels with intensity values above the threshold are set to one
color (usually white), and those below are set to another (usually black).
– Implementation: The code calculates the average intensity of the R, G, and B
components and compares it to the THRESHOLD parameter. If the average is
greater than the threshold, the pixel is set to white (255, 255, 255); otherwise,
it’s set to black (0, 0, 0).

Figure 2.4 Image with color inversion

– Thresholding

* Concept: Converts an image into a binary (black and white) image based
on a threshold value. Pixels with intensity values above the threshold are
set to one color (usually white), and those below are set to another (usually
black).
* Implementation: The code calculates the average intensity of the R, G, and
B components and compares it to the THRESHOLD parameter. If the av-
erage is greater than the threshold, the pixel is set to white (255, 255, 255);
otherwise, it’s set to black (0, 0, 0).

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 Figure 2.5 Image with threshold editing

2.5 Hexadecimal Representation

• Hexadecimal (Base-16): A number system using 16 distinct symbols (0-9 and A-F).
It’s commonly used in computer science to represent binary data in a more human-
readable format.

• Why Hex? Verilog’s $readmemh system task is designed to read data from a text
file where values are represented in hexadecimal format. This is why the initial
BMP needs to be converted to hex. Each pair of hexadecimal digits represents one
byte (8 bits) of data.

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 3 Design and Implementation

This section details the design and implementation of the image processing system,
covering the system architecture and the individual Verilog modules developed for image
input, processing, and output.

3.1 System Overall Design

The image processing system is designed as a modular pipeline consisting of three
primary stages: image input, image processing, and image output.

Start

Input
.hex file

Image Reading (image_read.v)

Image Processing (image_read.v)

Image Writing (image_write.v)

Output
.bmp file

End

Figure 3.6 Data flow

The Image Reading module (image_read.v) is responsible for reading the pre-
processed hexadecimal representation of the input image from a file. It simulates the
behavior of an image sensor by providing synchronized pixel data along with horizon-
tal and vertical sync signals. The Image Processing stage is integrated within the im-
age_read.v module for this project. It performs the selected image enhancement opera-

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tion (inversion, brightness control, or thresholding) on the incoming pixel data. Finally,
the Image Writing module (image_write.v) receives the processed pixel data and assem-
bles it, along with the necessary BMP header information, into an output bitmap image
file. The flow of data is unidirectional, moving sequentially through these three stages.
The image processing can also be demonstrated in the figure below:

Start

BMP Image

Hex File

Operation ?

Invert Operation Brightness Operation Threshold Operation

Processed BMP Image

End

Figure 3.7 Image processing dataflow

3.2 Code Flow and Implementation

The purpose of this section is to provide a detailed explanation of the implementa-
tion process, focusing specifically on the code and its functionality. By breaking down
each component, we aim to ensure a clear understanding of how the system was devel-
oped and operates.

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3.2.1 Image Input (Reading Module - image_read.v)
The image_read.v module is designed to mimic the behavior of an image sensor,
providing a stream of pixel data synchronized with control signals.
Image Conversion (Matlab) As Verilog cannot directly interpret image files like
BMPs, a preliminary conversion step is essential. The provided Matlab script (im-
age_to_hex.m) performs this conversion. It reads the input image (BMP, PNG, or JPG)
using the imread function. The script then iterates through the image pixels, extracting
the Red, Green, and Blue (or grayscale) values. Crucially, the iteration proceeds from
the bottom row to the top row, mirroring the pixel storage order in BMP files. The ex-
tracted pixel values are then written to a .hex file in hexadecimal format, with each value
on a new line. This .hex file serves as the input for the image_read.v module.

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 Start Check Number of Channels

Display Error: Store

Store R, G, B
Unsupported Grayscale
Input values
Channels Value
Image Path
No
and Output Increment Counter
Hex Path?

End Column Loop

Yes
Display Error:
Get Image Dimensions
Missing Input
(rows, cols, channels) End Row Loop
/Output Paths

Initialize Pixel Data Array

Open Output Hex File

Loop through Rows

(Bottom to Top) Write Pixel Data Array to Hex File

Loop through Columns

(Left to Right) Close Output Hex File

Display Success
Message

End

Figure 3.8 Image Conversion (Matlab)

Explanation:

• The flowchart starts by checking if the input and output paths are provided.

• It reads the image file using imread, which handles different image formats.

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 • It gets the dimensions to iterate through pixels.

• Nested loops process pixels row by row (bottom to top) and column by column.

• It checks the number of color channels to handle RGB and grayscale images.

• Pixel values are stored in an array.

• Finally, the pixel data is written to the output hex file.

Verilog Reading Module Design The image_read.v module is parameterized to

allow for flexibility in image dimensions and file paths. The key parameters include
WIDTH, HEIGHT, and INFILE, specifying the image dimensions and the path to the
input .hex file, respectively. Other parameters control the timing of the simulated sen-
sor signals (START_UP_DELAY, HSYNC_DELAY) and the parameters for the image
processing operations (VALUE, THRESHOLD, SIGN). The module’s input and output
ports include:

• Inputs: HCLK (clock), HRESETn (active-low reset).

• Outputs: VSYNC (vertical sync pulse), HSYNC (horizontal sync pulse), DATA_R0,
DATA_G0, DATA_B0, DATA_R1, DATA_G1, DATA_B1 (RGB data for two par-
allel pixels), and ctrl_done (flag indicating completion).

Internally, the module utilizes several key signals and memory structures:

• total_memory: A large register array to store the entire image data read from the
.hex file using the $readmemh system task within an initial block.

• temp_BMP: A temporary array to hold the data from total_memory.

• org_R, org_G, org_B: Integer arrays used to store the separated Red, Green, and
Blue color components of the image pixels in row-major order. The pixel data from
temp_BMP is reordered and separated into these arrays, accounting for the bottom-
up row order in the BMP format.

• A Finite State Machine (FSM) with states ST_IDLE, ST_VSYNC, ST_HSYNC,

and ST_DATA controls the reading process. The FSM transitions through these
states to simulate the vertical sync, horizontal sync, and data transmission periods.

• Counters (ctrl_vsync_cnt, ctrl_hsync_cnt, row, col, data_count) are used to track

the timing and pixel positions during the reading and processing stages.

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 HSYNC Done
Start

FSM State: ST_DATA

Initialization: Read ḣex file into memory No
(Data Processing)

Not Wait for Start Signal

Calculate Pixel Address
Received (triggered by Reset)
Received
Read Pixel Data from Memory
FSM State: ST_VSYNC (Vertical Sync)
(org_R, org_G, org_B)

Perform Image Processing

VSYNC Timing and Counting
(selected operation)
VSYNC Done
FSM State: ST_HSYNC Output Processed Pixel Data
(Horizontal Sync) (DATA_R0/G0/B0, DATA_R1/G1/B1)

HSYNC Timing and Counting Increment Column Counter

Check if End of Row

Yes

FSM State: ST_HSYNC

Figure 3.9 Verilog Module for Reading and Processing Image Code Flow

Explanation

• The module starts by reading the hex file into memory during initialization.

• It waits for a start signal, typically triggered by the reset going high.

• A Finite State Machine (FSM) controls the reading and processing.

• States include VSYNC, HSYNC, and DATA processing.

• During the DATA state, it calculates the memory address, reads pixel data, performs
the selected image processing, and outputs the processed data.

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 • Counters manage the row and column progression.

3.2.2 Image Processing Module (within image_read.v)

For this project, the image processing logic is integrated directly within the im-
age_read.v module. The specific processing operation is selected using conditional
compilation directives (bsed on the definitions in the parameter.v‘ file.

• Brightness Control: When BRIGHTNESS_OPERATION is defined, the code im-

plements either brightness addition or subtraction based on the SIGN parameter. If
SIGN is 1, the VALUE is added to each color component (R, G, B). If SIGN is
0, the VALUE is subtracted. Saturation logic is implemented to ensure the color
component values remain within the valid range of 0 to 255.

• Inversion: If INVERT_OPERATION is defined, the code calculates the inverse

of each pixel’s intensity. For simplicity, it calculates the average of the R, G, and
B components and then subtracts this average from 255 for each color component,
effectively inverting the grayscale representation.

• Threshold Operation: When THRESHOLD_OPERATION is defined, the code

converts the image to a binary image. It calculates the average intensity of each
pixel. If the average intensity is greater than the THRESHOLD parameter, the pixel
is set to white (255 for R, G, and B); otherwise, it is set to black (0 for R, G, and B).

The processing is performed on two pixels in parallel to potentially speed up simulation.

The processed pixel data is outputted through the DATA_R0, DATA_G0, DATA_B0,
DATA_R1, DATA_G1, and DATA_B1 output ports.

3.2.3 Image Output (Writing Module - image_write.v)

The image_write.v module is responsible for taking the processed pixel data and
constructing a valid BMP image file.

• The module is parameterized with WIDTH, HEIGHT, and INFILE, specifying the
image dimensions and the desired output file name. BMP_HEADER_NUM defines
the size of the BMP header (54 bytes).

• The module receives the processed pixel data (DATA_WRITE_R0, DATA_WRITE_G0,

DATA_WRITE_B0, DATA_WRITE_R1, DATA_WRITE_G1, DATA_WRITE_B1)
and the horizontal sync pulse (hsync) as inputs. The output is a Write_Done signal
indicating the completion of the writing process.

• An initial block defines the BMP_header register array with the appropriate values
for a 24-bit uncompressed BMP image of the specified dimensions. These header

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 values include the file signature, file size, image dimensions, bits per pixel, and
other relevant information as described in Section 2.1.

• Another initial block opens the output file (INFILE) in write-binary mode using the
$fopen system task.

• An always block, triggered by the Write_Done signal, writes the BMP header to
the file using $fwrite, followed by the processed pixel data. The pixel data is writ-
ten in BGR order, consistent with the BMP format. The loop iterates through the
processed pixel data, writing the RGB components for the two parallel pixels.

Start

Initialization: Define BMP Header Loop through Image Pixels

Write Processed Pixel Data

Initialization: Open Output .bmp File
(R0B0G0, R1B1G1) to File

Not Wait for Write_Done

End Pixel Loop
Received Signal from Processing
Received
Write BMP Header to File Close Output .bmp File

End

Figure 3.10 Image Output (Writing Module - image_write.v)

Explanation:

• The module initializes by defining the BMP header data.

• It opens the output BMP file.

• It waits for a Write_Done signal from the processing module (in this case, the im-
age_read module).

• Once Write_Done is received, it writes the BMP header to the file.

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 • It then iterates through the processed pixel data and writes it to the file in the correct
BMP format (BGR order).

• Finally, it closes the output file.

3.2.4 Parameter File (parameter.v)

The parameter.v file acts as a configuration file, simplifying the process of select-
ing the input and output file names and choosing the desired image processing operation.
The user can easily switch between the different processing algorithms without modify-
ing the main Verilog code. The file also defines the input and output file names using
INPUTFILENAME and OUTPUTFILENAME.

3.2.5 Testbench (tb_simulation.v)

The tb_simulation.v file provides the necessary stimuli to simulate the designed
image processing system. It instantiates the image_read and image_write modules, con-
necting their inputs and outputs. A clock signal (HCLK) is generated using an initial
block with a forever loop. An active-low reset signal (HRESETn) is also generated with
a specific timing sequence. The testbench overrides the INFILE parameters of both
modules using the definitions from parameter.v. The simulation is run for a sufficient
duration to process the entire image, allowing the image_write module to generate the
output BMP file.

Start

Instantiate image_read Module

Instantiate image_write Module

Generate Clock Signal

Generate Reset Signal

Run Simulation for Specified Time

End

Figure 3.11 Testbench (tb_simulation.v)

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 Explanation

• The testbench starts the simulation.

• It instantiates the image_read and image_write modules, connecting their ports.

• It generates the necessary clock and reset signals for the design.

• The simulation runs for a predetermined time period, allowing the modules to pro-
cess the image.

• The simulation ends.

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 4 Experimental Results

4.1 Simulation Setup

We will use ModelSim to simulate the image editing operation in FPGA. It is
a strong and effective software for testing Verilog and Verilog HDL code. Module
tb_simulation in tb_simulation.v file will be run for 6ms, then we can observe the output
picture in BMP format, and also the waveform generated by ModelSim simulation.
For the image used for simulation, we use Fig. 4.12 since it is an image with many
different colors and brightness in each pixel, making it suitable for the experiment.

Figure 4.12 Original Image

4.2 Simulation Results

Here is the results, after the simulation. We have the image and waveform after
each processing scenario:

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 Figure 4.13 Image with lower brightness

Figure 4.14 Lower brightness waveform

With lower brightness operation, the values in each channel R, G and B are reduced
(in this simulation, they are all reduced by 100). So it is expectable to see in the output
waveform, almost all data will have small values. So the output data can be considered
accurate.

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 Figure 4.15 Image with higher brightness

Figure 4.16 Higher brightness waveform

Similarly, the values in each channel R, G, B are increased with the higher bright-
ness adjustment. The simulation has returned the results with value mostly larger than
128. It should be an accurate result.

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 Figure 4.17 Image with color inversion

Figure 4.18 Color inversion waveform

In this operation, when looking at the waveform, we can see similar values in the
data of all three channels. That is because our code has processed the image in two
steps: convert the image into grayscale and then invert the color. Grayscale conversion
will result in the similar in all three value of R, G and B in a pixel. That should explain
the values in the waveform.

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 Figure 4.19 Image with threshold editing

Figure 4.20 Threshold waveform

Lastly, with the threshold operation, the image will be turned into a black-and-
white image. With the previous explanation, we know that a white pixel contains value
255, alongside with a black pixel contains value 0 in all three channels RGB. That should
bring a clear explanation for how all the data of a pixel is similar in the threshold wave-
form, and all of them are either 00000000 (value 0) or 11111111 (value 255).

4.3 Discussion
The simulation results, showcasing the successful generation of output images for
inversion, brightness control, and thresholding, strongly indicate the functional correct-
ness of the implemented Verilog modules. By visually comparing the output images

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with the expected outcomes for each processing operation, we can confirm that the algo-
rithms were accurately translated into hardware description language. The inverted im-
age clearly demonstrates the reversal of pixel intensities, while the brightness-adjusted
images show the intended shift in overall luminance. The thresholded image effectively
segments the image into foreground and background based on the defined threshold
value.
The functionality of the image_read module as a model for an image sensor is a
key aspect of this project. The successful generation of HSYNC and VSYNC signals,
along with the sequential output of pixel data, mimics the behavior of a real-world image
sensor. This approach proves valuable for functional verification, allowing designers to
test downstream image processing logic in a simulated environment before integrating
with actual hardware. The ability to control parameters like HSYNC_DELAY allows for
simulating different sensor characteristics and testing the robustness of the processing
pipeline to timing variations.
The image_write module serves as an equally crucial component for verification.
By writing the processed pixel data into a standard BMP format, it enables a direct visual
assessment of the processing results. This is significantly more intuitive and efficient
than analyzing raw numerical data from the simulation waveforms. The correct imple-
mentation of the BMP header ensures that the output image is rendered accurately by
standard image viewers. This capability greatly simplifies the debugging and validation
process for image processing algorithms.
Several important considerations arise from the design and implementation of this
project. Firstly, the current implementation, while effective for simulation, relies on
large memory arrays to store the entire image. This approach is not directly synthe-
sizable for efficient hardware implementation on an FPGA. For real-world FPGA de-
ployments, these memory arrays would need to be replaced with Block RAM (BRAM)
resources, requiring the design of address generators and memory controllers to manage
data access.
Secondly, the parallel processing of two pixels, while intended to speed up simu-
lation, introduces a level of complexity in the indexing and data handling. Depending
on the target FPGA architecture and the complexity of the processing algorithm, the
degree of parallelism can be further optimized for improved hardware performance and
resource utilization.
Finally, while this project focuses on basic image enhancement operations, the
modular design allows for the integration of more complex algorithms. The image_read
module can be seen as a generic data source, and the processing logic within it can
be replaced or expanded to implement a wide range of image processing tasks. The

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image_write module provides a consistent mechanism for verifying the output of any
such processing pipeline.
In conclusion, this project successfully demonstrates the fundamental principles of
image processing using Verilog HDL within a simulation environment. The modular
design and the inclusion of image reading and writing modules provide a comprehen-
sive framework for developing and verifying image processing algorithms. While direct
hardware synthesis requires further design considerations, this work provides a valuable
foundation for understanding the translation of image processing concepts into hardware
descriptions and highlights the importance of simulation and verification in the FPGA
design flow.

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 5 Conclusion

This project has successfully demonstrated the implementation of a fundamental

image processing pipeline on an FPGA using Verilog HDL. The design encompasses
the complete flow from reading a bitmap image, performing selected image processing
operations (inversion, brightness adjustment, and thresholding), to writing the processed
data back into a bitmap format for verification. The use of a finite state machine to con-
trol the process flow, along with the generation of VSYNC and HSYNC signals, effec-
tively mimics the behavior of a real-time image processing system. While the focus of
this work has been on basic image manipulation, the principles and techniques presented
are directly applicable to more complex algorithms and applications. The Verilog model
of an image sensor developed in this project serves as a valuable tool for functional
verification in larger, more sophisticated image and video processing designs.
It is important to acknowledge that the provided code is optimized for simulation
and verification purposes. For direct implementation on an FPGA, modifications are
necessary, particularly concerning memory management, address generation, and file
I/O. Specifically, the large integer arrays should be replaced with block RAMs, and a
mechanism for loading the image data into the FPGA’s memory during configuration
or runtime must be implemented. Nevertheless, this project provides a solid foundation
for further exploration and development in the field of FPGA-based image processing.
Future work could involve implementing more advanced image processing algorithms,
optimizing the design for real-time processing of camera input, and exploring techniques
for resource optimization on the FPGA. The flexibility and performance advantages of
FPGAs, combined with the detailed understanding of image processing in Verilog pre-
sented in this report, pave the way for the development of high-performance, customized
image and video processing solutions for a wide range of applications.

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 REFERENCE

[1] V. L. Le, “Image processing on FPGA using Verilog HDL.” [Online]. Available:
https://www.fpga4student.com/2016/11/image-processing-on-fpga-verilog.html

[2] Yuri, “Tổng quan về FPGA và bài viết về phần cứng

đầu tiên trên Viblo.” [Online]. Available: https://viblo.asia/p/
tong-quan-ve-fpga-va-bai-viet-ve-phan-cung-dau-tien-tren-viblo-0gdJz7eALz5

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