Electronics Hardware Architecture
Electronics Hardware Architecture
HARDWARE ARCHITECTURE
GKX-14-0042-SP_B2
2 July 2014
GKX-14-
0042-SP_B1
Prepared by: Alastair Smith Document reference:
1 DOCUMENT CONTROL 4
1.1 Document Revision 4
1.2 Document Authorisation 4
2 INTRODUCTION 3
7 TEST STRATEGY 9
7.1 Introduction 9
7.2 Manual test 9
7.3 Manufacturing tests 9
7.4 Equipment requirements 10
APPENDICES 11
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A.1 Introduction 13
A.2 Options 13
A.3 Assessment of USB module approach 13
A.4 Low power module on main PCB 14
A.5 Low power module on mezzanine PCB 14
A.6 Custom low power module 14
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2 INTRODUCTION
This electronics hardware architecture document sets out the architectural design for
the RU2 and MK3 units. This describes
The key components of the system and rationale for choosing them;
How the electronic components are interfaced with one another;
How the electronic components will integrate into the mechanical hardware;
How the processor subsystem will be programmed and debugged;
Detailed appendices of calculations and experimentation that has gone in to reaching the
conclusions presented.
The design assumes the ‘Best Choice design’ under consideration in Stage Gate 2 of the project. This
architecture should supply the perceived best user experience within hard constraints and decisions
made during the design process between the design authority (PA Consulting) and the client (BDR
Thermea).
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3 HARDWARE DESIGN OVERVIEW
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3.2.2 Diagrams
The overall architecture picture is shown below. Individual components are listed later in this
document.
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Thermally Isolated RU-2 Main PCB
region of PCB
Temperature
sensor
ADC
Proximity
CS_BOOT NAND Flash OSRAM SFH
push button MT29F1G08ABADAH4 4650-Z irLED
MMU
Room Bus Circuit SiLabs Si1141
DDR2 RAM Proximity sensor
MT47H32M16NF-25E I2C
500kHz
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MK-3 Main PCB
Coin cell battery holder
and replaceable coin cell
battery
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4 KEY ELECTRONIC COMPONENTS
This section outlines the key functional features of each electronic component or function. Power
consumption issues are discussed later in this document.
4.2 Display
4.2.1 RU2: Densitron DSN43600 LCD TFT 4.3in display
The key features of this display are:
4.3 inch display
480x272 pixels
16.7M pixels
White LED backlight
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4.3 Random Access Memory (RAM)
Recommended part is manufactured by Micron Technology with part number MT47H32M16NF-25E.
Key features are:
512 Mbit
DDR2
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1KB ISP flash memory
32B SRAM
4 general purpose I/O lines
Region of PCB
Super cap
24V to 5V 5V to 3.3V
3.3V Wi-Fi
regulator LDO
regulator
enable
Super capacitor
24V to 3.3V
uC LDO 3.3V supply for microcontroller
regulator
enable
24V - 3.6V
Switching
24V in
regulator 12V LCD
LM25010 LED Driver 12V LED
RT9293B
1.8V memory
ACT8865
1.2V core
Regulator
3.3V processor peripheral
and encoder
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Figure 3: Power supply architecture for the RU-2 device
Region of PCB
24V - 3.6V
Switching
24V in
regulator 12V LCD
LM25010 LED Driver 12V LED
RT9293B
1.8V memory
ACT8865
1.2V core
Regulator
3.3V processor peripheral
and encoder
24V - 5V
Switching
5V CAN controller chip
regulator
LM25010
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5 MECHANICAL DESIGN
CONSIDERATIONS
5.1 Introduction
This section describes the key considerations of the electronics design that are impacted by the
mechanical design. Specifically:
Temperature sensing
The optical encoder
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5.4 EMC Precautions
Processor subsystems and wireless telecommunications devices typically run at high operating
frequencies with many clock speeds. A consequence of this is that electromagnetic interference
issues may prevent the product from being certified.
There are two main methods that will be employed to minimise EMC issues:
A ‘Screening can’ will be placed above the processor and memory subsystem to act as a Faraday
cage and prevent transmission of EM waves. A screening tin has already been used for the
Gainspan module, which will be soldered directly onto the main PCB.
Placement of high frequency signals between power and ground planes, which will prevent
resonant effects across of through the PCB.
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6 PROGRAMMING AND DEBUG
ARCHITECTURE
6.1 Introduction
Appendix B provides an overview of the ARM A5 boot sequence. The boot and debug architecture
takes advantage of ARM A5 features, which include an advanced boot ROM that enables debug to be
performed using a USB interface.
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7 TEST STRATEGY
7.1 Introduction
The test strategy considers the various stages of the project and of the manufacturing process. This
process will be developed into a separate manufacturing test document in later stages of this project.
Before the DUT is powered up, FULL in-circuit component testing must take place. Where possible
the following should be tested:
All passive components where possible must be tested for tolerances;
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All tantalum capacitors must be tested for correct insertion;
All active components must be tested for correct insertion using visual or diode testing techniques;
All diodes and transistors must be tested for correct forward and reverse voltage drops.
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APPENDICES
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WI-FI MODULE DECISION JUSTIFICATION
A.1 Introduction
This section describes the options and trade-offs involved in the options for 802.11n connectivity.
A.2 Options
USB Module
– This option involved using a standard USB connector to attach a low-cost COTS USB Wi-Fi
dongle as an expansion option.
Low power module on main PCB
– This option involves employing a COTS Wi-Fi module and soldering it to the main board of the
RU2 unit.
Low power module on mezzanine PCB
– This option involves employing a COTS Wi-Fi module and soldering it to the main board of the
RU2 unit.
Custom low-power module
– This option involves designing a custom low power Wi-Fi module, purchasing a Wi-Fi chipset
from an OEM company, developing the analogue antenna circuit, and ensuring Wi-Fi
certification of the product.
A.3.2 Recommendation
This approach should not be used without significant investment into assessing a low power dongle
mode. This would carry risk of it not working.
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A.4 Low power module on main PCB
A.4.1 Summary of approach
Advantages
Low power: A super capacitor arrangement will provide for peak current scenarios.
Low risk: hardware and software exists, minimal integration required.
Disadvantages
High cost: assuming there is a module on every unit, this approach has the highest BOM cost of over
€7.
Show stopper
Cost is prohibitive.
Steps to make option more viable
See mezzanine PCB option.
A.4.2 Recommendation
This approach should not be used without significant investment into assessing a low power dongle
mode. This would carry risk of it not working.
A.5.2 Recommendation
This approach should not be used without significant investment into assessing a low power dongle
mode. This would carry risk of it not working.
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Long development time.
Risk is high due to:
potential infringement and licensing. For example one module supplier has 9 patent relating to low
power Wi-Fi.
Cost of existing Wi-Fi solutions may reduce by time of high volumes, eating away at original
business case
Must sell over 400k units to see ROI, based on estimates, this will be in Y3/Y4
A.6.2 Recommendation
This approach should not be used without significant investment into assessing a low power dongle
mode. This would carry risk of it not working.
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ARM A5 BOOT AND DEBUG STRATEGIES
B.1 Introduction
This section describes the available and recommended strategies for booting and debugging the
candidate ARM 5 processor.
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Figure 5: The boot sequence for the Atmel ARM A5 processor
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Figure 6: The debug mode state diagram for the Atmel ARM A5 processor
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USB WI-FI MODULE POWER
CHARACTERISTICS
C.1 Introduction
This appendix describes the experimental procedure used in assessing the viability of the Wi-Fi USB
module approach to connect the RU2 unit to the public internet.
C.2 Experimentation
C.2.1 Experimental setup
The experimental setup uses the following:
Raspberry pi computer running raspbian OS
USB male to female extension cable, with wires exposed to allow current probe on power rail
Standard 802.11n Wi-Fi USB dongle (unbranded)
Lecroy wavejet 324 oscilloscope
Tektronix TCPA300 Current probe
The Wi-Fi module was chosen due to its reported low power characteristics. Various raspberry pi
forums reported that other solutions were too power hungry to work effectively with the raspberry pi
chip.
The figures below show the experimental setup.
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C.2.2 Results
The figures below demonstrate the results from the experiment. The average current consumed by the
Wi-Fi chip us 83mA, which translates to a power of 415mW. The peak current was 248mA, translating
to 1240mW (1.24W).
The settings for the measurements below are:
Oscilloscope scope 20mV per division (vertical)
Current probe: 1A/V
Higher resolution photos are available in the electronics working directory.
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C.2.3 Conclusions
The USB Wi-Fi modular approach in this form consumes too much power. In order to develop this
solution further, a custom TCP/IP and USB driver combination should be considered.
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OPTICAL ENCODER EXPERIMENTATION
D.1 Introduction
This section describes the experimentation performed in order to develop a proof of concept
electronics design for an accurate rotating dial that will be used to control the menu on the RU-2 and
MK-3 devices. This should prove the concept and then feed into development for the Stage 3 full
device prototypes.
D.2 Experimentation
D.2.1 Experimental setup
The experimental setup contains four key components:
Avago optical encoder AEDR-8300-1W0;
Prototype dials (with vertically mounted and horizontally designed ‘ribs’ used to trigger the optical
encoder output);
Two vices, used to experiment with the positioning of the encoder and dial; and
Oscilloscope for testing the clarity of the optical encoder output.
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Figure 7: The experimental setup
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Figure 8: The dial with horizontally mounted ribs
Figure 10: The optical encoder, control wheel arrangement with clean output observed on the
oscilloscope
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There is a relatively tight tolerance on the distance of the wheel ribs from the encoder. The
tolerance is as stated in the Avago datasheet, and is achievable with mechanical fixings.
Some mechanical and electronic debug of the design is expected in stage 3. However, the proof of
concept is demonstrated in the figure below. This figure shows the electronic signals output from a fine
rotation of the dial (approximately 3 degrees).
Figure 11: The optical encoder output with a 3 degree movement of the dial.
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PROXIMITY AND AMBIENT LIGHT
SENSOR EXPERIMENTATION
E.1 Introduction
This section describes the experimentation done to test the recommended proximity and ambient light
sensors. The purpose is to prove the concept, uncover any considerations for completing the
electronics design and identify any mechanical and other considerations.
E.2 Experimentation
The experimentation employs a Silicon Labs Infrared Multi-Function Board Evaluation Kit IRMFB-EK.
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Additional comments:
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Given this dynamic range, it should be feasible to design a simple software algorithm to detect the
lighting conditions and alter the LCD screen brightness.
The diagrams of each scenario are presented below. Higher resolution diagrams that display the
graphed screen outputs in more detail are stored in the project directory.
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POWER CONSUMPTION CALCULATION
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Figure 12: Efficiency of the multiple rail voltage regulator
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Total Power without 1306mW This includes a 20% inefficiency overhead
Wi-Fi
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The standard equation that governs this behaviour is t=0.5C(Vo^2-V1^2)/P. Therefore the
arrangement we have designed should operate for approximately 1 second before the circuit fails.
This 1 second figure is 100 times greater than the requirement, and should therefore provide ample
room to transmit all necessary data when all components are in operation. Furthermore, it will allow for
significant supercapacitor degradation over time.
This calculation is outlined in the table below.
5.5 V V0
0.22 F Capacitance
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MECHANICAL DESIGN
CONSIDERATIONS
G.1 Introduction
This appendix outlines existing solutions and design considerations that feed into the electronic and
mechanical design of the RU-2 and MK3 devices. This includes the arrangement of the temperature
sensor.
Thermistor
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Figure 13: Honeywell device temperature sensor and mechanical fixing
The Nest device employs a similar mechanical design with four additional features:
4. The device has a hole to the external environment;
5. The casework is more carefully designed to fit on top and in contact with the PCB. This is
achieved more accurately by placing the thermistor next to the fixing hole that attaches the unit to
the wall. Therefore allowing the screw to tighten the casework onto the PCB.
6. A thermally insulating coating has been applied to the surface of the PCB.
7. The high-end processor subsystem and screen have been place on a separate PCB with
insulating casework between the two printed circuit boards.
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WI-FI MODULE TESTING
H.1 Introduction
This appendix discusses the testing conducted with the candidate Wi-Fi module. The key aspects
required of the Wi-Fi module are:
Low power consumption, in line with numbers quoted by the manufacturer’s marketing material;
and
Sufficient communications range from the module, allowing connection to the internet from within a
house or flat environment.
H.2 Experimentation
H.2.1 Setup
The module tested was the gainspan GS2100MIE, which is fitted to a Gainspan development board:
EVB3, revision 2.0. This setup employs an external antenna. Despite presence of a PCB antenna, a
separate module must be used to test this functionality (the GS2100MIP), but no development
environment is available for this configuration.
The development environment allows a PC to communicate with the board using a serial terminal. We
have used teraterm via a standard COM port. The development board uses FTDI USB to serial
converter chips to allow the PC to communicate via a USB to serial emulator/driver.
H.2.3 Range
Some basic tests were performed with the GS2100MIE. This was done by querying the RSSI
measured by the Gainspan module at various points around the PA office environment and by
comparing to mobile phone RSSI measurements. The teste were as follows:
1. Test within 2 metres of a Wi-FI router.
2. Test 60 metres from the Wi-Fi router (not line-of-sight), this is at far end of range.
3. Comparative test with smartphone Samsung Note 3.
4. Comparative test with Wi-Fi dongle Ralink 5370.
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Corporate headquarters
123 Buckingham Palace Road
London SW1W 9SR
United Kingdom
Tel: +44 20 7730 9000
paconsulting.com
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