RISC-V Processor Datapath
Module Outline
● RISC-V datapath implementation
– Register File, Instruction memory, Data memory
● Instruction interpretation and execution.
● Combinational control
● Assignment: Datapath design and Control Unit
design using a HDL.
Sequential Elements
●
Register: stores data in a circuit
– Uses a clock signal to determine when to update
the stored value
– Edge-triggered: update when Clk changes from 0
to 1
Clk
D Q
D
Clk
Q
Sequential Elements
●
Register with write control
– Only updates on clock edge when write control
input is 1
– Used when stored value is required later
Sequential Elements
●
Register with write control
– Only updates on clock edge when write control
input is 1
– Used when stored value is required later
Clk
Write
D Q
Write D
Clk
Q
Clocking Methodology
●
Combinational logic transforms data during
clock cycles
–
Clocking Methodology
●
Combinational logic transforms data during
clock cycles
– Between clock edges
– Input from state elements, output to state element
–
Clocking Methodology
●
Combinational logic transforms data during
clock cycles
– Between clock edges
– Input from state elements, output to state element
–
Clocking Methodology
●
Combinational logic transforms data during
clock cycles
– Between clock edges
– Input from state elements, output to state element
– Longest delay determines clock period
Building a Datapath
●
Datapath
–
Building a Datapath
●
Datapath
– Elements that process data and addresses
in the CPU
●
●
Building a Datapath
●
Datapath
– Elements that process data and addresses
in the CPU
●
Registers, ALUs, muxes, memories, …
●
Building a Datapath
●
Datapath
– Elements that process data and addresses
in the CPU
●
Registers, ALUs, muxes, memories, …
●
We will build a RISC-V datapath incrementally
A Basic RISC-V Implementation
● Memory-reference instructions – Load
doubleword (ld) and Store doubleword (sd)
● ALU instructions – add, addi, sub, and, or
● Branch on equal (beq)
Instruction Execution – Steps
Instruction Execution – Steps
● Instruction Fetch
Instruction Execution – Steps
● Instruction Fetch
● Instruction Decode/Register Fetch
Instruction Execution – Steps
● Instruction Fetch
● Instruction Decode/Register Fetch
● Execute
– ALU
– Effective Address Calculation
Instruction Execution – Steps
● Instruction Fetch
● Instruction Decode/Register Fetch
● Execute
– ALU
– Effective Address Calculation
● Memory Access
Instruction Execution – Steps
● Instruction Fetch
● Instruction Decode/Register Fetch
● Execute
– ALU
– Effective Address Calculation
● Memory Access
● Write back (Update RF)
Instruction Fetch – Actions
Instruction Fetch – Actions
● Read Program Counter
Instruction Fetch – Actions
● Read Program Counter
● Fetch instruction from Instruction memory
pointed to by the PC
Instruction Fetch – Actions
● Send Program Counter to Instruction Memory
● Fetch instruction from IM
● Increment PC
Instruction Fetch – Elements
Instruction Fetch – Elements
Instruction Fetch
ALU Instructions – Operations
ADD x5, x6, x7
ALU Instructions – Operations
● Read x6 and x7 from Register file
– Send 6 and 7 to RF
– RF reads contents of x6 and x7
ADD x5, x6, x7
ALU Instructions – Operations
● Read x6 and x7 from Register file
– Send register numbers (6 and 7) to RF
– RF reads contents of x6 and x7
● Add contents of x6 and x7 in the ALU
ADD x5, x6, x7
ALU Instructions – Operations
● Read x6 and x7 from Register file
– Send 6 and 7 to RF
– RF reads contents of x6 and x7
● Add contents of x6 and x7 in the ALU
● Feed the sum to the RF; Ask it to write into x5
ADD x5, x6, x7
ALU Operations – Elements
ADD x5, x6, x7
ALU Operations – Elements
Addr
Data
REGISTER
REGISTER
FILE
FILE
Data
Write
ADD x5, x6, x7
ALU Operations – Elements
ADD x5, x6, x7
ALU Operations – Elements
ADD x5, x6, x7
ALU Operations – Datapath
ADD x5, x6, x7
ALU Operations – Datapath
● How will the design change for ADDI?
ADDI x5, x6, -13
ALU Operations – Datapath
● How will the design change for ADDI?
● How is the immediate value treated?
ADDI x5, x6, -13
ALU Operations – Datapath
● How will the design change for ADDI?
● How is the immediate value treated?
32 64
ADDI x5, x6, -13
ALU Operations – Datapath
REGISTER
REGISTER
FILE
FILE
32 64
ADDI x5, x6, -13
ALU Operations – Datapath
32 64
ADDI x5, x6, -13
Loads and Stores – Actions
LW x5, -8(x6)
Loads and Stores – Actions
● Calculate full address
– Sum of -8 (offset) and contents of x6 (base)
– Size of offset? Size of contents of x6?
LW x5, -8(x6)
Loads and Stores – Actions
● Calculate full address
– Sum of -8 (offset) and contents of x6 (base)
– Size of offset? Size of contents of x6?
● Send the address to Data memory
LW x5, -8(x6)
Loads and Stores – Actions
● Calculate full address
– Sum of -8 (offset) and contents of x6 (base)
– Size of offset? Size of contents of x6?
● Send the address to Data memory
● DM reads out the contents of Mem[x6+(-8)]
LW x5, -8(x6)
Loads and Stores – Actions
● Calculate full address
– Sum of -8 (offset) and contents of x6 (base)
– Size of offset? Size of contents of x6?
● Send the address to Data memory
● DM reads out the contents of Mem[x6+(-8)]
● Feed the value from memory to the RF; Ask it
to write the value into x5
LW x5, -8(x6)
Loads and Stores – Elements
32 64
LW x5, -8(x6)
Memory and R-type Instructions
32 64
Memory Instruction – Load
32 64
LW x5, -8(x6)
Memory Instruction – Load
32 64
LW x5, -8(x6)
Memory Instruction – Load
66
55
32 64
LW x5, -8(x6)
Memory Instruction – Load
66
R[x6]
R[x6]
55
-8-8(2s
(2s64b)
64b)
32 64
LW x5, -8(x6)
Memory Instruction – Load
ADD
66
R[x6]
R[x6]
55
-8-8(2s
(2s64b)
64b)
32 64
LW x5, -8(x6)
Memory Instruction – Load
ADD
66
R[x6]
R[x6]
55
-8-8(2s
(2s64b)
64b)
32 64
R[x6]-8
R[x6]-8
LW x5, -8(x6)
Memory Instruction – Load
ADD
66
R[x6]
R[x6]
55
R[x6]-8
R[x6]-8
-8-8(2s
(2s64b)
64b)
32 64
R[x6]-8
R[x6]-8
LW x5, -8(x6)
Memory Instruction – Load
ADD
66
R[x6]
R[x6]
55
R[x6]-8
R[x6]-8
-8-8(2s
(2s64b)
64b)
32 64
R[x6]-8
R[x6]-8 M[R[x6]-8]
M[R[x6]-8]
LW x5, -8(x6)
Memory Instruction – Load
ADD
66
R[x6]
R[x6]
55
R[x6]-8
R[x6]-8
-8-8(2s
(2s64b)
64b)
32 64
M[R[x6]-8] R[x6]-8
R[x6]-8 M[R[x6]-8]
M[R[x6]-8]
M[R[x6]-8]
LW x5, -8(x6)
Memory Instruction – Load
32 64
Control
ControlSignals:
Signals:RegWrite;
RegWrite;ALUSrc;
ALUSrc;ALUoperation;MemRead;MemWrite;
ALUoperation;MemRead;MemWrite;MemToReg;
MemToReg;
Memory Instruction – Load
32 64
Control
ControlSignals:
Signals:RegWrite=1;
RegWrite=1;ALUSrc=1;
ALUSrc=1;ALUoperation=ADD;
ALUoperation=ADD;
MemRead=1;MemWrite=0;
MemRead=1;MemWrite=0;MemToReg=1;
MemToReg=1;
Memory Instruction – Store
32 64
SW x5, -8(x6)
Memory Instruction – Store
SW x5, -8(x6)
Memory Instruction – Store
32 64
Control
ControlSignals:
Signals:
Memory Instruction – Store
32 64
Control
ControlSignals:
Signals:RegWrite=0;
RegWrite=0;ALUSrc=1;
ALUSrc=1;ALUoperation=ADD;
ALUoperation=ADD;
MemRead=0;MemWrite=1;
MemRead=0;MemWrite=1;MemToReg=X;
MemToReg=X;
R Type Instruction – ADD
32 64
ADD x5, x6, x7
R Type Instruction – ADD
ADD x5, x6, x7
R Type Instruction – ADD
32 64
Control
ControlSignals:
Signals:
R Type Instruction – ADD
32 64
Control
ControlSignals:
Signals:RegWrite=1;
RegWrite=1;ALUSrc=0;
ALUSrc=0;ALUoperation=ADD;
ALUoperation=ADD;
MemRead=X;MemWrite=0;
MemRead=X;MemWrite=0;MemToReg=0;
MemToReg=0;
I Type Instruction – ADDI
32 64
ADDI x5, x6, 13
I Type Instruction – ADDI
ADDI x5, x6, 13
I Type Instruction – ADDI
32 64
Control
ControlSignals:
Signals:
I Type Instruction – ADDI
32 64
Control
ControlSignals:
Signals:RegWrite=1;
RegWrite=1;ALUSrc=1;
ALUSrc=1;ALUoperation=ADD;
ALUoperation=ADD;
MemRead=X;MemWrite=0;
MemRead=X;MemWrite=0;MemToReg=0;
MemToReg=0;
BEQ – Actions
BEQ
BEQx5,
x5,x6,
x6,-16
-16
if(R[x5] = R[x6]); then
PC = PC + {-16,1’b0}
= PC + {-32} # -16 << 1
BEQ – Actions
BEQ
BEQx5,
x5,x6,
x6,-16
-16
if(R[x5] = R[x6]); then
PC = PC + {-16,1’b0}
= PC + {-32} # -16 << 1
BEQ – Actions
BEQ
BEQx5,
x5,x6,
x6,-16
-16
if(R[x5] = R[x6]); then
PC = PC + {-16,1’b0} Operations?
Operations?
= PC + {-32} # -16 << 1
BEQ – Actions
BEQ
BEQx5,
x5,x6,
x6,-16
-16
if(R[x5] = R[x6]); then
PC = PC + {-16,1’b0}
= PC + {-32} # -16 << 1
32 Imm
Imm 64 64 Shift
Shift 64
Gen
Gen Left
Left11
BEQ – Actions
● Read x5 and x6 from Register file
– Send 5 and 6 to RF
– RF reads contents of x5 and x6
●
BEQ x5, x6, -16
BEQ – Actions
● Read x5 and x6 from Register file
– Send 5 and 6 to RF
– RF reads contents of x5 and x6
● Send to ALU to Subtract
BEQ x5, x6, -16
BEQ – Actions
● Read x5 and x6 from Register file
– Send 5 and 6 to RF
– RF reads contents of x5 and x6
● Send to ALU to Subtract
● Read out Zero flag from ALU
BEQ x5, x6, -16
BEQ – Actions
● Read x5 and x6 from Register file
– Send 5 and 6 to RF
– RF reads contents of x5 and x6
● Send to ALU to Subtract
● Read out Zero flag from ALU
● If Z flag == 0; then PC = (PC + imm<<1)
BEQ x5, x6, -16
BEQ – Actions
● Read x5 and x6 from Register file
– Send 5 and 6 to RF
– RF reads contents of x5 and x6
● Send to ALU to Subtract
● Read out Zero flag from ALU
● If Z flag == 0; then PC = (PC + imm<<1)
● Else if Z flag == 1; then PC = PC + 4
BEQ x5, x6, -16
Branches – Elements
BEQ x5, x6, LABEL BEQ x5, x6, -16
Branches – Elements
BEQ x5, x6, LABEL BEQ x5, x6, -16
RISC-V Datapath – BEQ
RISC-V Datapath – BEQ
RISC-V Datapath – BEQ
RISC-V Datapath – BEQ
RISC-V Datapath – BEQ
RISC-V Datapath – BEQ
RISC-V Datapath – BEQ
RISC-V Datapath – BEQ
Control
ControlSignals
Signals::
RISC-V Datapath – BEQ
Control
ControlSignals
Signals::RegWrite=0;
RegWrite=0;ALUSrc=0;
ALUSrc=0;ALUoperation=SUB;
ALUoperation=SUB;
MemRead=X;MemWrite=X;
MemRead=X;MemWrite=X;MemToReg=X;
MemToReg=X;
PCSrc=Condition
PCSrc=Condition
RISC-V Datapath and Control Lines
Module Outline
● MIPS datapath implementation
– Register File, Instruction memory, Data memory
● Instruction interpretation and execution.
● Combinational control
● Assignment: Datapath design and Control Unit
design using HDL.
