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DataType Synthesis Quiz - Solution

The document discusses digital system design using high-level synthesis in FPGA, specifically focusing on data type synthesis. It includes a comparison of a function's representation before and after synthesis, highlighting a reduction in levels from four to three when optimized for performance in Vivado-HLS. The author is Mohammad Hosseinabady, and contact information is provided.

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Thiện Nguyễn Minh

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0% found this document useful (0 votes)

18 views1 page

DataType Synthesis Quiz - Solution

The document discusses digital system design using high-level synthesis in FPGA, specifically focusing on data type synthesis. It includes a comparison of a function's representation before and after synthesis, highlighting a reduction in levels from four to three when optimized for performance in Vivado-HLS. The author is Mohammad Hosseinabady, and contact information is provided.

Uploaded by

Thiện Nguyễn Minh

Copyright

© © All Rights Reserved

We take content rights seriously. If you suspect this is your content, claim it here.

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Download as PDF, TXT or read online on Scribd

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1 Digital System Design with High-Level Synthesis in FPGA

DataType-Synthesis: Quiz Solution www.highlevel-synthesis.com

The following graph represents the function before synthesis. It consists of

four gates scheduled in four levels.

If we synthesis the code for performance (which is the default assumption in

Vivado-HLS), then the following graph represents the function. It consists of
four gates organised into three levels.

Mohammad Hosseinabady 1 [email protected]

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