International Journal of Engineering and Advanced Technology (IJEAT)

ISSN: 2249 – 8958, Volume-9 Issue-1, October 2019

Pulsating STM – The in-memory Optimistic

Concurrency Control Technique for Multi Core
Systems
Sana Jafar, Ranjana Rajnish, Pankaj Kumar

 when the workload is too large. Concurrency in parallel

Abstract: In the world of ever increasing parallelism, the programming is the main issue which is both desirous as well
problem of deadlock-free concurrency control is inevitable. As the as which leads to concurrency control problems if left
number of processing cores is increasing, the number of
processing threads is also increasing, and with this increase in the
unhandled. If concurrency is left uncontrolled, it will lead to
number of processing threads, there is a good chance of problems problems like, dirty read, race condition, unrepeatable reads,
arising due to lack of proper concurrency control. The application lost update problem, lack of inter thread communication and
areas under the domain of advanced graphics, cryptography, deep deadlocks to name a few. If concurrency is restricted by over
learning, embedded system programming, artificial intelligence control, then the parallel program will lose its essence.
and networking are prone to the problems of heavy uncontrolled
Therefore, designing an efficient concurrency control
concurrency of threads. This paper presents a novel Software
Transactional Memory (STM) based optimistic concurrency algorithm is essentially important which could secure
control technique that is deadlock free for threads accessing the maximum parallelism as well as maximally optimized to
in-memory data structure for the purpose of reading as well as guard the algorithm from the above problems.
writing. The technique is lock free and is based upon Parallel programming works both for in-memory data
timestamping. Threads involved in the proposed approach possess structures as well as for OLTP Transactions. This paper
the transactional properties of atomicity, concurrency and
isolation. Durability is not expected as the threads are working on
focuses on algorithms that work on in-memory data
an in-memory data source. The approach involves lazy conflict structures. One such data structure that is used in this work is a
detection that ensures minimum aborts and restarts as well as one dimensional array.
maximum concurrency among transactions. Being lock free, the Several techniques are there in literature that control
algorithm is better than the existing lock-based techniques. The concurrency. Some of them are lock based techniques, TM
technique is tested on Sniper-6.1 multi core simulator simulating
approach, timestamp based techniques, optimistic
64 CPU cores and running 16, 32, 40 and 50 threads in our case.
The results show significant improvement in throughput with the concurrency control, multi version concurrency control. Lock
increasing number of threads over the existing lock-based based techniques have the biggest con of limiting the
techniques as well as other STM techniques based on optimistic concurrency by allowing only one thread to enter the critical
concurrency control. section at a time. Also, they are most probable of causing a
deadlock. So they are the least popular techniques.
Keywords : Concurrency Control, Optimistic Concurrency
Transactional Memory(TM) is an alternative approach for
control, multi core, Software Transactional Memory, parallel
programming, in-memory data structure, Sniper multi core lock free concurrency control[1]. This approach works for
simulator, Cycles Per Instructions. shared in-memory objects. The threads of execution inhibit
the ACI properties of transaction, viz. Atomicity, Consistency,
I. INTRODUCTION Isolation and access the read/write set of the shared in
memory data objects. Two transactions are said to conflict if
The era of multi core processing is advancing at a they access the same object and one of the access is a write
access. Transactional memory is said to provide higher level
lightning speed towards an era where the number of cores will
of programming abstraction. There are three approaches
be extraordinarily higher. That demands for a most efficient
supporting Transactional Memory:
and highly optimized parallel algorithm. Parallel
(i)SoftwareTransactionalMemory(STM), (ii)approach
programming is generally not as simple as serial
providing hardware support to accelerate the STM, (iii)
programming but it is much more efficient than the latter
Hardware Transactional Memory (HTM)[2]. Rest of the three
concurrency control techniques are based on Transactional
Revised Manuscript Received on October 15, 2019 Memory.
* Correspondence Author
Timestamp based technique is better than the lock based
Sana Jafar*, Amity Institute of Information Technology, Amity
University Uttar Pradesh, Lucknow Campus, Lucknow(India), India. Email: techniques as there are no locks so no fear of deadlocks and
[email protected] works on TM. The concurrency is controlled via schemes that
Ranjana Rajnish, Amity Institute of Information Technology, Amity allot and compare the timestamps of the elements in the read
University Uttar Pradesh, Lucknow Campus, Lucknow(India), India. Email:
[email protected] and write set of the systems with the timestamp of the current
Pankaj Kumar, Department of Computer Science and Engineering, Sri transaction. Accordingly it is
Ram Swaroop College of Engineering and Management, Lucknow, India. decided whether the transaction
Email: [email protected]
has to proceed reading or writing

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DOI: 10.35940/ijeat.A9525.109119 1966 & Sciences Publication
 Pulsating STM – The in-memory Optimistic Concurrency Control Technique for Multi Core Systems

the elements in the read/ write set respectively or it has to based validation and timestamp based validation. It involves
abort and restart. Aborting and restarting is a costlier affair. the use of global version locks. The second characteristic is
Also having a centralized timestamp manager may become encounter time lock sorting. This feature is introduced in
the reason of bottlenecks in a highly loaded system. order to avoid livelocks. The third characteristic is coalesced
Timestamping alone, is therefore not a very good solution read/write set organization in which the read/write set of all
always. Optimistic concurrency control is as the name transactions within a warp are merged for reducing the
suggests, optimistic in its approach towards accessing and overhead of transaction bookkeeping.
writing the elements in a shared datastructure. This technique In [6], the authors have studied that prior ways to amortize
assumes that initially all the transactions are allowed to access the commit latencies in GPU SIMT applications, for example
and update the data elements in the shared datastructure and reducing the transactional warps to very few per SIMT core,
then the validity of the transaction is decided later before the aborting and restating the transactions; have resulted in poor
final commit. Being optimistic, this technique ensures performance and not actual reduction in commit latencies.
maximum threads or transactions participating in the system The authors have thus, proposed a new GPU Hardware TM
thus increasing the concurrency. However, in a highly called GETM (GPU TM) based on eager conflict detection
contended workload there will still be a number of aborts and and lazy version management. The solution is based on
restarts. The challenge of a good concurrency control timestamping and lock mechanism.
algorithm is to minimize these aborts and restarts and to In [7], the authors have presented APUTM, a transactional
ensure maximum concurrency among transactions or threads. memory approach for Accelerated Processing Units (APUs).
Multi version concurrency control is an Optimistic Here they have deployed the concept of minimizing the access
concurrency control technique. In this, the in memory data to the shared memory for reducing the conflicts among
objects are assumed to have multiple versions each. This is transactions. They have adopted a lazy conflict detection and
done to ensure maximum concurrency. The transactions have lazy version management approach. One implementation is
freedom to update as many versions as they want concurrently based on global sequence lock for reducing the commit
if they happen to pass the validity test. latency of the transactions and the other implementation
checks the transactional conflicts by using a private read set.
II. RELATED WORK In [8], the authors have reviewed the currently existing
Lot of work has been done on Transactional Memory and concurrency control techniques for in-memory databases.
much is still going on. Some of the relevant study made is Three such techniques have been discussed with their pros
mentioned below: and cons. These are Cicada[9], MOCC[10], TicToc[11].
In[3], Nir Shavit and Dan Touitou invented a Software MOCC is based on optimistic concurrency control with a
Transactional Memory as a novel method towards translating slight variation by using the concept of temperature to acquire
sequential implementations of objects into highly concurrent selective read locks and minimize aborts. TicToc is a
non-blocking ones using k-word compare&swap timestamp ordering scheme and is optimistic in nature. The
STM-transaction. The work was based on multi-processors. commit timestamp for a transaction is calculated dynamically
Mohammed El-Shambakey and Binoy Ravindran have and is allotted just before the commit point. Cicada is
studied the SoftwareTransactional Memory approach in real optimistic, multi version and multi clock concurrency control
time embedded system in [1]. They have analytically scheme.
established the upper bounds on the transactional retry and In [12], the authors of NEMO, a NUMA-aware TM
response time. algorithm have proposed a well optimized solution for
Bratin Saha et.al. have presented a novel high performance providing scalability to applications running in NUMA
software transactional memory system for a multi-core architectures. NEMO is tested using well-known and
runtime in [4]. This paper has done detailed study of the synthetic OLTP transactional workloads. The authors have
various STM tradeoffs like optimistic concurrency control performed two tests whose results form the basis of the design
versus pessimistic concurrency control; undo logging versus of NEMO. In the first test various STM algorithms TL2[13],
write buffering and object based versus cache line based SwissTM[14], TinySTM[15], RingSTM[16], and NOrec[17],
conflict detection. Also the authors have developed the novel implementing a version of the Bank benchmark, partition the
STM designs that works in cooperation with other accounts across different NUMA zones and threads operate
components of McRT system to prevent blocking of active only on accounts stored in their local NUMA zones. The test
transactions through inactive transactions. The McRT STM is shows that on incrementing the number of threads beyond 16,
read versioning and undo-logging system and implements the algorithms cease to scale and the cost of updating the
both object-based conflict detection and cache-line based global metadata at this point also goes up significantly. In the
conflict detection. The scheme is based on locking and second test, the authors have calculated the latency required
versioning of the locks. for incrementing the logically shared timestamp through
Yunlong Xu et.al. have developed a STM based technique Compare-and-Swap. They have deployed two configurations:
for GPU based systems in [5]. The authors claim that their one in which there is a single timestamp in one NUMA zone
technique is free from livelocks and is scalable. The technique incremented by multiple threads; the second configuration in
involves three characteristics. The first characteristic is which there are 8 timestamps
Hierarchical validation that implements the conflict detection. located in 8 different NUMA
Hierarchical validation is said to be the combination of value zones and incremented by 8

Retrieval Number: A9525109119/2019©BEIESP Published By:

DOI: 10.35940/ijeat.A9525.109119 Blue Eyes Intelligence Engineering
1967 & Sciences Publication
 International Journal of Engineering and Advanced Technology (IJEAT)
ISSN: 2249 – 8958, Volume-9 Issue-1, October 2019

threads in their local NUMA zones. The result shows that the a) sets the read and write timestamps of its write set to its own
former configuration provides almost no scalability due to commit timestamp.
heavy traffic in case of high number of threads. The latter b) Copies the write set to the shared memory.
configuration, on the other hand provides better scalability
even when CAS primitive is used. IV. DESIGN OF PULSATINGSTM
PulsatingSTM is a timestamp based optimistic concurrency
III. PULSATINGSTM
control system. The main features of this design are:
In an effort for developing a more efficient concurrency 1. Avoids deadlock as there are no locks.
control scheme for in-memory data structures, the authors 2. Being optimistic, it allows all the threads to access and
have developed PulsatingSTM. This STM approach is lock as update the copy of the element in the datastructure without
well as deadlock free scheme. It is primarily inspired from worrying about any conflicts, thus increases the concurrency
TicToc[11], the timestamp ordering scheme for in-memory among threads.
databases. But it is better than TicToc as there are no locks in 3. Each element maintains a metadata. This metadata stores
it. Also TicToc is for in-memory databases, whereas the read and write timestamps of the element, data held in the
PulsatingSTM is for in-memory data structures. element and a pointer in the original data structure. A thread
PulsatingSTM is primarily based upon the optimistic (transaction) accessing this element will use its metadata.
concurrency control scheme and is free from the overheads of 4. Every transaction has certain timestamp associated with
centralized timestamp manager. Here the commit timestamp itself which the unique value allotted to it when it enters the
of a transaction is computed not early than the commit phase. system.
The authors have adopted lazy conflict detection[6]. The 5. Every transaction has a read and write set associated with
three phases in this scheme are: (i) Read phase, (ii) Validation itself. The read set contains all the copies of elements that the
phase and (iii) Write phase. transaction has read and write set contains all the copies of
elements that it has updated along with their updated values.
A. Read Phase
6. The commit timestamp of the transaction is computed late
In this phase the threads as transactions are allowed to read in the execution just before commit from the read and write
the elements from the shared memory into their private read/ timestamps of elements in its read/ write set.
write set based upon the purpose of access. If the access is Due to the property of Isolation of Transaction, they do not
read access, the thread reads that element in its private read interfere with each other’s read/write sets. Since the write
set. It notes down the read and write timestamp of that element operation is atomic in nature, the transaction will roll back on
in the set, displays the element and sets the pointer to the reading an invalid version or incorrect data. Consistency is
element in the shared array. If the access is the write access, maintained as the transactions are serializable.
the thread reads the element in its private write set, notes Each node of the in-memory datastructure has some metadata
down read and write timestamps of the element, updates the associated with it which gives information about the
element in the write set, and sets the pointer to the element in read/write timestamp, a pointer to the node in original data
the shared array. structure and the data value of the node, as mentioned above.
B. Validation Phase The read/ write timestamp associated with the elements of the
datastructure is the timestamp value of the last committed
In this phase the commit timestamp of the transaction is
transaction that read or wrote that element. These metadata
calculated based upon the read and write timestamps of the
are tabulated in table1.
elements in its read/write set. It has following three major
Table- I: Metadata of a node and of a transaction in
steps:
PulsatingSTM
a) Firstly, the transaction’s current timestamp is checked
rtime Read timestamp
against the read and write timestamps of the element in the
wtime Write timestamp
read set of that transaction. The transaction’s timestamp must
be greater than write timestamp and less than read timestamp. point Pointer to the node in the original data
If not then it is adjusted to some value abiding this constraint. structure
b) Secondly, the validation is done against the read set. If the data Data value of the node
transaction’s timestamp is in between write timestamp and tranread [ ] An array maintaining read set of the transaction
read timestamp for every element in the read set, then it is tranwrite [ ] An array maintaining write set of the
assumed that the transaction has read a valid version, else it is transaction
assumed that the version read by the transaction is invalid. In
timestamp Timestamp associated with the transaction
that case the changes made by the transaction in its write set
when it enters the system
are rolled back.
c) Thirdly, if the transaction has read a valid version, then its
final commit timestamp is calculated which should be greater
than the read timestamp of all the elements in the write set.
Algorithm 1 shows the BeginTX, ReadTX, ValidateTX,
C. Write Phase
and WriteTX procedures of
After successful validations, each transaction does the pulsatingSTM.
following: BeginTX begins by allotting

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DOI: 10.35940/ijeat.A9525.109119 1968 & Sciences Publication
 Pulsating STM – The in-memory Optimistic Concurrency Control Technique for Multi Core Systems

each thread or transaction a unique value that is calculated by 51: end if

the autoinc procedure (Algorithm 4). 52: end if
53: commit timestamp is timestamp
Algorithm 1 PulsatingSTM algorithm 54: end procedure
1: procedure BeginTX 55: procedure WriteTX
2: timestamp autoinc() 56: for j=0 , j<p do
3: end procedure 57: tranwrite[j].wtime timestamp
58: tranwrite[j].rtime timestamp
4 procedure ReadTX
59: *(tranwrite[j].point) tranwrite[j]
5: p write(tranwrite, (arr+i),i,p,timestamp) 60: j j+1
6: s read(tranread,(arr+i),i,s,timestamp) 61: end for
7: end procedure 62: end procedure
8: procedure ValidateTX
9: k 0 Here, arr is a globally shared array which the transactions
access for the purpose of reading and writing. It is an array of
10: if tranread[k].rtime!=tranread[k].wtime do
structure wherein each element holds the read and write
11: while k<s do timestamp of the integer element, its data value and a pointer
12: while timestamp<=tranread[k].wtimeOR pointing to itself. tranwrite and tranread are the write and
timestamp>=tranread[k].rtime do read sets respectively of every transaction which are
13: if timestamp<=tranread[k].wtimedo implemented as dynamic arrays. Variable i is holding the
timestamp++;
index for arr. Variables p and s are the size of the write and
14: elseif timestamp>=tranread[k].rtime do
read set respectively for each transaction. Variable
timestamp--;
timestamp is the unique timestamp allotted by procedure
15: end if
16: end while BeginTX ( line numbers 1 to 3) to each transaction entering
17: k k+1 into the system.
18: end while The Read Phase begins by every transaction calling the
19: end if functions write( ) and read ( ) in parallel (line numbers 4 to
20: k 0 7).
21: while k<s do
Algorithms 2, 3 and 4 show the functions associated with
read operation, write operation and auto increment
22: if timestamp >tranread[k].wtime AND
respectively as used in Algorithm 1. The read( ) and write( )
timestamp<tranread[k].rtime do functions are as explained under the sub-section A of section
23: flag 1; III above. Here the variables TR, TW v, i, size and
24: else timestamp are the formal arguments of the functions read( )
25: flag 0; break; and write( ). TR and TW are pointing to the tranread and
26: end if tranwrite sets as used in Algorithm 1.
27: k k+1 The validation phase in Algorithm 1 is shown under
28: end while
procedure ValidateTX that starts from line number 8 and
29: if flag == 0 do
extends till 54. The procedure begins by ensuring that the read
30: Transaction has read invalid version and has to
and write timestamps of each and every element in the
roll back
transaction’s read set is different. Once this is ensured, the
31: for j 0, j< p do
transaction’s timestamp is checked whether it is lying between
32 if tranread[k].point==tranwrite[j].point do
33: for l j, l<p-1 do the read and write time stamps of the elements in the read set.
34: tranwrite[j] tranwrite[j++]; If not then its adjusted to abide this constraint ( line numbers
35: l l+1 11 to 18). After this, the validation is done against the read set
36: end for as explained in the sub-section B of section III above (line
37: p p -1; break numbers 20 to 41). Here, the variable point is a pointer to the
38: end if element in the shared data structure. The third part of
39: end for validation phase where the transaction has read a valid
40: else do version and its final commit time stamp is calculated is from
41: Transaction has read a valid version line number 42 to 51.
42: k 0 The write phase in Algorithm 1 is shown through procedure
43: while k < p do WriteTX that starts from line number 55 and extends till 62.
44: if timestamp<tranwrite[k].rtime do Line numbers 57 to 58, assign the valid transaction’s
45: timestamp tranwrite[k].rtime timestamp to the read and write timestamp of every element in
46: end if its write set. Finally line number 59, copies this element to the
47: k k+1 shared memory as explained
48: end while
under the write phase of sub-
49: if k == p do
section C of section III.
50: timestamp timestamp +1

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DOI: 10.35940/ijeat.A9525.109119 Blue Eyes Intelligence Engineering
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 International Journal of Engineering and Advanced Technology (IJEAT)
ISSN: 2249 – 8958, Volume-9 Issue-1, October 2019

Following observations can be deduced from the Fig. 1.

Algorithm 2 Read operation algorithm The total time consumed by the algorithm is 509
1: procedure read (struct element *TR, struct element microseconds. Most of the CPI percentage per time is
synchronization. Only towards the last fourth part of
*v,int i,int size, int timestamp)
execution time, the CPI is spent on computation. A spike in
2: TR[i] *v; between the graph shows the read phase. Towards the end is
3: size size+1; the validation and write phase that covers around 25% of the
4: TR[i].rtime v->rtime;
CPI. The spike also covers around 25% of the CPI.
5: TR[i].wtime v->wtime;
6: TR[i].point v;
7: return size;
8: end procedure

Algorithm 3 Write operation algorithm

1: procedure write (struct element *TW, struct
element *v,int i,int size, int timestamp)
Fig. 2. Average CPI graph for the algorithm running 32
2: size size+1; threads on 64 simulated cores
3: TW[i] *v; In Fig. 2, the algorithm is run using 32 threads. The total
4: update (TW[i].data); time consumed by the algorithm is 786.7 microseconds. The
5: TW[i].rtime v->rtime; spike in the graph is a little more than that seen in the graph
6: TW[i].wtime v->wtime; for 16 threads. It is now covering around 45% of CPI. Also, as
7: TW[i].point v; the number of threads has doubled, more computation is done
8: return size; and that is shown towards the end of the graph, with the
9: end procedure validation and write phase that covers around 50% of CPI
now.
Algorithm 4 autoinc algorithm
1: procedure autoinc
2: static int c 1;
3: c c +1;
4: return c;
5: end procedure

V. EXPERIMENTAL TEST BED

Fig. 3. Average CPI graph for the algorithm running 40
The above experiments are performed on multi core
threads on 64 simulated cores
simulator the Sniper-6.1[18] simulating 64 CPU cores using
the gainestown configuration file for Xeon X5550. The Fig. 3 shows the result of running the algorithm using 40
configuration has following settings: threads on 64 cores. With 40 threads, the read phase spikes up
• Core frequency—2.66 GHz to around 55% and the validation and write phase covers
• Number of cores sharing L3 cache— 4 around 52% of CPI. This is due to more number of threads
• Data access time by L3 cache – 30 cycles and hence more works done in validation and write phase.
• Network memory model --- bus The total time taken by the algorithm with 40 threads is 922.8
• Bus bandwidth – 25.6 GB/s (12.8 GB/s per direction and microseconds.
per connected chip pair)
• Local traffic has been ignored because the memory
controllers are on chip.

Fig. 4. Average CPI graph for the algorithm running 50

threads on 64 simulated cores

Fig. 1. Average CPI graph for the algorithm running 16

Fig. 4 shows the result of running the algorithm using 50
threads on 64 simulated cores
threads on 64 cores. With 50
In Fig. 1-4, the average Cycles per Instructions (CPI) graph
threads, the read phase spikes up
is plotted for time in microseconds on the X-axis versus
to around 62% and the validation
percentage CPI on Y-axis.

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DOI: 10.35940/ijeat.A9525.109119 1970 & Sciences Publication
 Pulsating STM – The in-memory Optimistic Concurrency Control Technique for Multi Core Systems

and write phase covers around 78% of CPI. The total time concurrency control technique based on timestamping. It
taken by this algorithm with 50 threads is 1.095 milliseconds. employs lazy conflict detection among the threads. The
algorithm is better than lock based protocols and other STM
VI. EVALUATION protocols as it is free from locks. The algorithm is built on
We have closely observed the results obtained on Sniper by multiple threads doing the same job of reading and writing. It
comparing the values obtained by running PulsatingSTM with is optimistic as all the threads are allowed to read a copy of
16, 32, 40 and 50 threads on 64 cores employing the data from the shared memory in their private read/write sets
gainestown configuration. The results suggest that on and perform write operation in their private set. Only when
increasing the number of threads, the throughput is the writing is complete, the validation phase begins. In the
increasing. This is attributable to the fact that as the thread validation phase, transaction’s timestamp is validated and its
count increases, the branch misses, L1, L2 cache misses and commit timestamp is calculated just before the write phase.
DRAM access reduces, thus, giving a better performance. The The algorithm is run on 64 cores using 16, 32, 40 and 50
results obtained on running the PulsatingSTM on sniper are threads on sniper, the multi-core simulator. The results
tabulated in Table 2. obtained show that the throughput obtained on running this
algorithm increases with increase in the number of threads.
Table-II: Parametric values from sniper for running
VIII. FUTURE WORK
PulsatingSTM employing different number of threads on
64 cores The authors next will implement the algorithm with
different number threads doing different jobs of reading and
Threads
writing. The authors have proposed a multi-version flavor of
16 32 40 50
this algorithm in the upcoming work wherein each element of
Instructions 5.580 19.35 29.25 44.25
the shared data structure will have multiple versions and
m m m m
threads writing to it will be writing new versions on the data
IPC 0.064 0.145 0.186 0.237
structure. Also, the authors propose employing this algorithm
Cycles 1.352 2.093 2.455 2.913
m m m m to techniques like parallel sorting of enormous arrays and
Time 508.3 786.7 922.8 1.095 come up with the results.
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DOI: 10.35940/ijeat.A9525.109119 Blue Eyes Intelligence Engineering
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 International Journal of Engineering and Advanced Technology (IJEAT)
ISSN: 2249 – 8958, Volume-9 Issue-1, October 2019

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11. X. Yu, A. Pavlo, D. Sanchez, and S. Devadas, ―TicToc: Time travelling
Optimistic Concurrency Control‖, In Proceedings of the 2016
International Conference on Management of Data SIGMOD, San
Francisco, California, USA, June 26 - July 01, 2016, pp. 1629-1642. Dr. Ranjana Rajnish is an Assistant
12. Mohamed Mohamedin, Sebastiano Peluso, Masoomeh Javidi Kishi, Professor at Amity Institute of Information
Ahmed Hassan, Roberto Palmieri ― Nemo: NUMA-aware Concurrency Technology at Amity University,
Control for Scalable Transactional Memory‖, In Proceedings of 47th Lucknow. Dr. Ranjana possesses
International Conference on Parallel Processing, Eugene, OR, USA, approximately 25 years of experience in
August 13–16, 2018, Article No. 38. academics/research. She has been engaged
13. Dave Dice, Ori Shalev, and Nir Shavit, ―Transactional Locking II.‖, In with institutions like U.P. Technical
Proceedings of the 20th international conference on Distributed University and Amity University in roles
Computing, Stockholm, Sweden, September 18 - 20, 2006 , pp. ranging from a faculty in computer science to Academic Head. Her area of
194–208. interest includes Software Engineering, Opinion Mining/Sentiment Analysis
14. Aleksandar Dragojević, Rachid Guerraoui, and Michal Kapalka, ― and Healthcare.
Stretching Transactional Memory‖, In Proceedings of the 30th ACM She has several publications in national and international journals and
SIGPLAN Conference on Programming Language Design and conference proceedings of National and International Conferences of repute.
Implementation, Dublin, Ireland, June 15 - 21, 2009, pp. 155-165. She is also member of various professional bodies like Computer Society of
15. Pascal Felber, Christof Fetzer, and Torvald Riegel, ―Dynamic India (CSI), Association of Computing Machinery(ACM), International
Performance Tuning of Word-based Software Transactional Memory‖, Association of Engineers (IAENG), Internet Society and Computer Science
In Proceedings of the 13th ACM SIGPLAN Symposium on Principles Teaching Association (CSTA).
and practice of parallel programming, Salt Lake City, UT, USA, Along with being a committed teacher and a passionate researcher, Dr.
February 20 - 23, 2008, pp. 237–246. Ranjana is reviewer for various International Journal and member of
16. Michael F. Spear, Maged M. Michael, and Christoph von Praun, editorial board for different International Journals. She is also reviewer,
―RingSTM: Scalable Transactions with a Single Atomic Instruction‖, member of technical programme committee in various conferences of repute
In Proceedings of the twentieth annual symposium on Parallelism in in and outside India. She has many Ph.D. scholars pursuing Ph.D. under her.
algorithms and architectures, Munich, Germany, June 14 - 16, 2008,
pp. 275–284.
17. Luke Dalessandro, Michael F. Spear, and Michael L. Scott, ―NOrec: Dr. Pankaj Kumar is currently working as
Streamlining STM by Abolishing Ownership Records‖. In Proceedings Assistant Professor (Reader) in Department
of the 15th ACM SIGPLAN Symposium on Principles and Practice of of Computer Science & Engineering in Sri
Parallel Programming. Bangalore, India, January 09 - 14, 2010, pp. Ramswaroop Group of Professional College,
67–78. Lucknow. He has more than 18 years of
18. [18] T. E. Carlson, W. Heirman, and L. Eeckhout., ―Sniper: Exploring teaching experiences. He received his MCA
the level of abstraction for scalable and accurate parallel multi-core degree in 2001, M.Tech in 2010 and PhD
simulations‖, In Proceedings of International Conference on High degree in Computer Application in 2011. His
Performance Analysis, Networking, Storage and Analysis, Seatle, WA, Area of Expertise is Parallel Computing/
USA, Nov. 12-18, 2011, pp. 1-12. Mining/Security. More than 50 research papers of Dr. Pankaj Kumar have
been published in various national/international journals and IEEE
proceeding publication. He is Senior Member of IEEE, Professional Member
AUTHORS PROFILE
of ACM and Life member of CSI, IETE, ISTE, IAENG, ISOC and IACSIT.
He is member of Management Committee of CSI and IETE Lucknow
Sana Jafar is currently working as an IT Chapter. He is reviewer for various International Journal and member of
consultant with Argus Technology LLC. She editorial board for different International Journals. He also participated in
is a research scholar in the faculty of various conferences as reviewer, member technical committee, and co-chair.
Information Technology from Amity One PhD thesis is awarded and eight students are enrolled as PhD scholar
University Uttar Pradesh Lucknow Campus, under his guidance. More than 10 students are guided by him in M.Tech
enrolled since January 2015. She has worked Thesis.
as an Assistant Professor (Computer Science
& IT) in the Department of Amity School of
o Engineering and Technology, Amity
University Uttar Pradesh Lucknow Campus from 2009 till 2018. She
completed her MCA with silver medal and received her degree with honors
in 2009. Her area of research is Parallel Computing and High Performance
Computing. She is a student member of IEEE. She has 4 papers published
and presented in IEEE sponsored International and National conferences and
one book chapter published in Scopus Indexed Ebook series titled
―Advances in Parallel Computing‖, IOS Press, Netherlands. Sana Jafar has
Participated in the Short Term Course (under QIP IIT Delhi) on many core
parallel Programming at IIT Delhi from 4th June -15th June 2018., learning
hands on Nvidia CUDA: API for parallel programming in GPU based
architecture and accessed the HPC clusters at IIT Delhi (PADUM). She has
also worked as an intern under Prof Subodh Kumar (Dept. CSE at IIT Delhi)
under the Summer Faculty Research Fellow Program from 4th June -13th
July 2018 at IIT Delhi. She has published a useful workbook on Object
oriented programming using C++ as main author(publishers: Alok
Prakashan) for the B.Tech students of Amity University and is in the process
of generalizing it for the B.Tech pursuing students of all the engineering
colleges in Uttar Pradesh. She has successfully attended various faculty
development programs and workshops in Amity University Lucknow
campus and outside. As well has played an important part in conducting
such programs within the Amity University Lucknow campus. She has
attended the five days military training camp organized by Amity University
Manesar in 2016 as faculty guide with post graduate students. She has also

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Retrieval Number: A9525109119/2019©BEIESP Blue Eyes Intelligence Engineering
DOI: 10.35940/ijeat.A9525.109119 1972 & Sciences Publication