Thanks to visit codestin.com
Credit goes to www.scribd.com

Scribd
Upload
18 views22 pages

Asic Lab6

The document outlines the ECO flow and physical verification process for ASIC design in LAB 6 of the MVLD505P course. It details two iterations of generating netlists, performing static timing analysis, inserting ECO cells, and conducting legality checks, followed by physical verification steps including filler cell insertion and DRC/LVS checks. The appendix includes commands and scripts used for various tasks in the design process.

Uploaded by

Satyadeep K
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
18 views22 pages

Asic Lab6

The document outlines the ECO flow and physical verification process for ASIC design in LAB 6 of the MVLD505P course. It details two iterations of generating netlists, performing static timing analysis, inserting ECO cells, and conducting legality checks, followed by physical verification steps including filler cell insertion and DRC/LVS checks. The appendix includes commands and scripts used for various tasks in the design process.

Uploaded by

Satyadeep K
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 22

ASIC Design

ECO Flow and Physical Verification – LAB 6

Course Code: MVLD505P


Slot: L45 + L46

Submitted By:
Shreyas Joshi - 24MVD0097
Satya Deep K - 24MVD0093
Shubham Gupta - 24MVD0066

Submitted To
Dr. Jagannadha Naidu K
ECO Flow
I) Iteration 1:
i. Generating netlist, SDC and SPEF files:

ii. Using PrimeTime for Post Route STA:


iii. Initial Analysis Coverage:

iv. Annotated Parasitics:


v. Changes suggested by PrimeTime:

vi. Analysis based on suggested changes:


vii. Implementing and Placing ECO cells in ICC2:
viii. Legality check:

ix. Routing ECO Cells:


x. Buffer Insertion Done:

II) Iteration 2:
i. Generating netlist, SDC and SPEF files:
ii. Using PrimeTime for Post Route STA:

iii. Initial Analysis Coverage:


iv. Annotated Parasitics:

v. Analysis based on suggested changes:


vi. Visualizing Clock Gate hold violation:

vii. Fixing Hold Voiolation:

viii. Implementing and Placing ECO cells in ICC2:


ix. Legality check:
x. Routing ECO Cells done:
Physical Verification
Initial Design after ECO Flow done:

Inserting Filler cells:

Routing Filler Cells:


Design with Filler Cells:

Signoff DRC check:


LVS check:

Signoff Create Metal Filling:


Final Design Block after Metal Filling:

Utilization Report:
Appendix
I) ECO Flow:
- Commands to generate:
1. Netlist: write_verilog DG_netlist_r.v
2. SDC File: write_sdc -output DG_netlist_r.sdc
3. SPEF File: write_parasitics -output DG -formt spef

- Primetime of Best timing ff0p95v125c (pt_cbest.tcl)


#set std_cell_delay_corner "ff0p95v125c"
#set macro_cell_delay_corner "ff1p16v125c"
#provide path for routed netlist
#this should be dumped from the icc2 session and used as input here.
set input_verilog "./DG_netlist_r.v "
#provide path for sdc
set input_sdc "./DG_netlist_r.sdc "
#provide path for spef
set input_spef "./DG.worst_para_-40.spef "
set my_design "Dice_Game"
set DESIGN_REF_PATH "/home/synopsys/installs/LIBRARIES/SAED14nm_EDK_08_2024/"
set search_path " ./ \
${DESIGN_REF_PATH} "
set link_path "* \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_RVT/liberty/nldm/base/saed14rvt_base_tt0p8v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_RVT/liberty/nldm/base/saed14rvt_base_ss0p72v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_RVT/liberty/nldm/base/saed14rvt_base_ff0p88v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_HVT/liberty/nldm/base/saed14hvt_base_tt0p8v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_HVT/liberty/nldm/base/saed14hvt_base_ss0p72v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_HVT/liberty/nldm/base/saed14hvt_base_ff0p88v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_LVT/liberty/nldm/base/saed14lvt_base_tt0p8v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_LVT/liberty/nldm/base/saed14lvt_base_ss0p72v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_LVT/liberty/nldm/base/saed14lvt_base_ff0p88v25c.db \
${DESIGN_REF_PATH}//SAED14nm_EDK_SRAM/liberty/nldm/saed14sram_tt0p8v25c.db \
${DESIGN_REF_PATH}//SAED14nm_EDK_SRAM/liberty/nldm/saed14sram_ss0p72v25c.db \
${DESIGN_REF_PATH}//SAED14nm_EDK_SRAM/liberty/nldm/saed14sram_ff0p88v25c.db"
set target_library " \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_RVT/liberty/nldm/base/saed14rvt_base_tt0p8v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_RVT/liberty/nldm/base/saed14rvt_base_ss0p72v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_RVT/liberty/nldm/base/saed14rvt_base_ff0p88v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_HVT/liberty/nldm/base/saed14hvt_base_tt0p8v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_HVT/liberty/nldm/base/saed14hvt_base_ss0p72v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_HVT/liberty/nldm/base/saed14hvt_base_ff0p88v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_LVT/liberty/nldm/base/saed14lvt_base_tt0p8v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_LVT/liberty/nldm/base/saed14lvt_base_ss0p72v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_LVT/liberty/nldm/base/saed14lvt_base_ff0p88v25c.db \
${DESIGN_REF_PATH}//SAED14nm_EDK_SRAM/liberty/nldm/saed14sram_tt0p8v25c.db \
${DESIGN_REF_PATH}//SAED14nm_EDK_SRAM/liberty/nldm/saed14sram_ss0p72v25c.db \
${DESIGN_REF_PATH}//SAED14nm_EDK_SRAM/liberty/nldm/saed14sram_ff0p88v25c.db"
catch {sh mkdir db rpts}
read_verilog "${input_verilog}"
#read_verilog "./${input_verilog}"
#set link_create_black_boxes false
current_design $my_design
link_design $my_design
read_sdc "${input_sdc}"
#read_sdc "./${input_sdc}"
read_parasitics "${input_spef}" -keep_capacitive_coupling -format SPEF
#read_parasitics "./${input_spef}" -keep_capacitive_coupling -format SPEF
update_timing -full
save_session ./db/${my_design}_w.session

- Primetime of worst timing ff0p95v125c, ff1p16v125c (pt_cworst.tcl):


#set std_cell_delay_corner "ff0p95v125c"
#set macro_cell_delay_corner "ff1p16v125c"
#provide path for routed netlist
#this should be dumped from the icc2 session and used as input here.
set input_verilog "./it2_DG_netlist_r.v "
#provide path for sdc
set input_sdc "./it2_DG_netlist_r.sdc "
#provide path for spef
set input_spef "./it2_DG.tlup_max_125.spef "
set my_design "Dice_Game"
set DESIGN_REF_PATH "/home/synopsys/installs/LIBRARIES/SAED14nm_EDK_08_2024/"
set search_path " ./ \
${DESIGN_REF_PATH} "
set link_path "* \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_RVT/liberty/nldm/base/saed14rvt_base_tt0p8v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_RVT/liberty/nldm/base/saed14rvt_base_ss0p72v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_RVT/liberty/nldm/base/saed14rvt_base_ff0p88v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_HVT/liberty/nldm/base/saed14hvt_base_tt0p8v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_HVT/liberty/nldm/base/saed14hvt_base_ss0p72v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_HVT/liberty/nldm/base/saed14hvt_base_ff0p88v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_LVT/liberty/nldm/base/saed14lvt_base_tt0p8v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_LVT/liberty/nldm/base/saed14lvt_base_ss0p72v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_LVT/liberty/nldm/base/saed14lvt_base_ff0p88v25c.db \
${DESIGN_REF_PATH}//SAED14nm_EDK_SRAM/liberty/nldm/saed14sram_tt0p8v25c.db \
${DESIGN_REF_PATH}//SAED14nm_EDK_SRAM/liberty/nldm/saed14sram_ss0p72v25c.db \
${DESIGN_REF_PATH}//SAED14nm_EDK_SRAM/liberty/nldm/saed14sram_ff0p88v25c.db"
set target_library " \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_RVT/liberty/nldm/base/saed14rvt_base_tt0p8v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_RVT/liberty/nldm/base/saed14rvt_base_ss0p72v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_RVT/liberty/nldm/base/saed14rvt_base_ff0p88v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_HVT/liberty/nldm/base/saed14hvt_base_tt0p8v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_HVT/liberty/nldm/base/saed14hvt_base_ss0p72v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_HVT/liberty/nldm/base/saed14hvt_base_ff0p88v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_LVT/liberty/nldm/base/saed14lvt_base_tt0p8v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_LVT/liberty/nldm/base/saed14lvt_base_ss0p72v25c.db \
${DESIGN_REF_PATH}/SAED14nm_EDK_STD_LVT/liberty/nldm/base/saed14lvt_base_ff0p88v25c.db \
${DESIGN_REF_PATH}//SAED14nm_EDK_SRAM/liberty/nldm/saed14sram_tt0p8v25c.db \
${DESIGN_REF_PATH}//SAED14nm_EDK_SRAM/liberty/nldm/saed14sram_ss0p72v25c.db \
${DESIGN_REF_PATH}//SAED14nm_EDK_SRAM/liberty/nldm/saed14sram_ff0p88v25c.db"

catch {sh mkdir db rpts}

read_verilog "${input_verilog}"
#read_verilog "./${input_verilog}"
#set link_create_black_boxes false
current_design $my_design
link_design $my_design
read_sdc "${input_sdc}"
#read_sdc "./${input_sdc}"
read_parasitics "${input_spef}" -keep_capacitive_coupling -format SPEF
#read_parasitics "./${input_spef}" -keep_capacitive_coupling -format SPEF
update_timing -full
save_session ./db/${my_design}_w.session

- ECO Cell Insertion and Sizing in PrimeTime:


fix_eco_drc -type max_transition -verbose -methods size_cell

fix_eco_drc -type max_capacitance -verbose -methods size_cell

fix_eco_drc -type max_transition -verbose -buffer_list {SAEDLVT14_BUF_ECO_1 SAEDLVT14_BUF_ECO_2


SAEDLVT14_BUF_ECO_3 SAEDLVT14_BUF_ECO_4 SAEDLVT14_BUF_ECO_6 SAEDLVT14_BUF_ECO_7
SAEDLVT14_BUF_ECO_8}

fix_eco_drc -type max_capacitance -verbose -buffer_list {SAEDLVT14_BUF_ECO_1 SAEDLVT14_BUF_ECO_2


SAEDLVT14_BUF_ECO_3 SAEDLVT14_BUF_ECO_4 SAEDLVT14_BUF_ECO_6 SAEDLVT14_BUF_ECO_7
SAEDLVT14_BUF_ECO_8}

fix_eco_timing -type setup -slack_lesser_than 0 -methods size_cell

fix_eco_timing -type setup -slack_lesser_than 0 -buffer_list {SAEDLVT14_BUF_ECO_1 SAEDLVT14_BUF_ECO_2


SAEDLVT14_BUF_ECO_3 SAEDLVT14_BUF_ECO_4 SAEDLVT14_BUF_ECO_6 SAEDLVT14_BUF_ECO_7
SAEDLVT14_BUF_ECO_8}

fix_eco_timing -type hold -slack_lesser_than 0 -methods size_cell

fix_eco_timing -type hold -slack_lesser_than 0 -buffer_list {SAEDHVT14_BUF_ECO_1 SAEDHVT14_BUF_ECO_2


SAEDHVT14_BUF_ECO_3 SAEDHVT14_BUF_ECO_4 SAEDHVT14_BUF_ECO_6 SAEDHVT14_BUF_ECO_7
SAEDHVT14_BUF_ECO_8}

#write_changes -format icc2tcl -output pt_changes_1.tcl

- Changes in PrimeTime and Buffer insertion (Iteration 1):


###############################################################################

# Change list, formatted for IC Compiler

###############################################################################

current_instance
current_instance {C1}
size_cell {U_PTECO_HOLD_BUF37} {SAEDHVT14_DEL_R2V3_1}
size_cell {U_PTECO_HOLD_BUF70} {SAEDHVT14_DEL_R2V3_1}
size_cell {U_PTECO_HOLD_BUF73} {SAEDHVT14_DEL_R2V3_1}
current_instance
current_instance {clk_gate_point_reg}
size_cell {U_PTECO_HOLD_BUF349} {SAEDHVT14_DEL_R2V3_1}
current_instance
current_instance {C1/clk_gate_count_reg}
size_cell {U_PTECO_HOLD_BUF348} {SAEDHVT14_DEL_R2V3_1}
current_instance
current_instance {C1}
size_cell {U_PTECO_HOLD_BUF28} {SAEDHVT14_DEL_R2V3_1}
size_cell {U_PTECO_HOLD_BUF131} {SAEDHVT14_DEL_R2V3_1}
size_cell {U_PTECO_HOLD_BUF121} {SAEDHVT14_DEL_R2V3_2}
current_instance
current_instance {clk_gate_point_reg}
size_cell {U_PTECO_HOLD_BUF307} {SAEDHVT14_DEL_R2V3_1}
current_instance
current_instance {C1/clk_gate_count_reg}
size_cell {U_PTECO_HOLD_BUF41} {SAEDHVT14_BUF_ECO_8}
current_instance
current_instance {C1}
size_cell {U_PTECO_HOLD_BUF99} {SAEDHVT14_DEL_R2V3_1}
size_cell {U_PTECO_HOLD_BUF98} {SAEDHVT14_DEL_R2V3_2}
size_cell {U_PTECO_HOLD_BUF49} {SAEDHVT14_BUF_ECO_8}
current_instance
current_instance {C1/clk_gate_count_reg}
size_cell {U_PTECO_HOLD_BUF306} {SAEDRVT14_DEL_R2V3_1}
current_instance
current_instance {C1}
size_cell {U_PTECO_HOLD_BUF1} {SAEDHVT14_DEL_R2V3_1}
size_cell {U_PTECO_HOLD_BUF12} {SAEDHVT14_DEL_R2V3_1}
size_cell {U_PTECO_HOLD_BUF3} {SAEDHVT14_BUF_ECO_8}
size_cell {U_PTECO_HOLD_BUF24} {SAEDHVT14_BUF_ECO_8}
size_cell {U_PTECO_HOLD_BUF144} {SAEDHVT14_DEL_R2V3_2}
insert_buffer [get_pins {U11/A1}] SAEDHVT14_BUF_ECO_8 -new_net_names {net_PTECO_HOLD_NET2} -
new_cell_names {U_PTECO_HOLD_BUF2}
insert_buffer [get_pins {U9/A2}] SAEDHVT14_BUF_S_20 -new_net_names {net_PTECO_HOLD_NET4} -
new_cell_names {U_PTECO_HOLD_BUF4}
insert_buffer [get_pins {count_reg_1_/D}] SAEDHVT14_BUF_S_20 -new_net_names {net_PTECO_HOLD_NET5} -
new_cell_names {U_PTECO_HOLD_BUF5}
insert_buffer [get_pins {count_reg_0_/D}] SAEDHVT14_BUF_S_20 -new_net_names {net_PTECO_HOLD_NET6} -
new_cell_names {U_PTECO_HOLD_BUF6}
insert_buffer [get_pins {count_reg_1_/Q}] SAEDHVT14_DEL_R2V3_1 -new_net_names {net_PTECO_HOLD_NET7} -
new_cell_names {U_PTECO_HOLD_BUF7}
current_instance
current_instance {C1/clk_gate_count_reg}
insert_buffer [get_pins {latch/D}] SAEDHVT14_BUF_S_20 -new_net_names {net_PTECO_HOLD_NET8} -
new_cell_names {U_PTECO_HOLD_BUF8}
current_instance
current_instance {C1}
insert_buffer [get_pins {U_PTECO_HOLD_BUF99/A}] SAEDHVT14_BUF_ECO_8 -new_net_names
{net_PTECO_HOLD_NET9} -new_cell_names {U_PTECO_HOLD_BUF9}
insert_buffer [get_pins {count_reg_2_/D}] SAEDHVT14_BUF_ECO_8 -new_net_names {net_PTECO_HOLD_NET10} -
new_cell_names {U_PTECO_HOLD_BUF10}
insert_buffer [get_pins {U6/B2}] SAEDHVT14_BUF_S_20 -new_net_names {net_PTECO_HOLD_NET11} -
new_cell_names {U_PTECO_HOLD_BUF11}
insert_buffer [get_pins {U_PTECO_HOLD_BUF9/A}] SAEDHVT14_BUF_ECO_8 -new_net_names
{net_PTECO_HOLD_NET13} -new_cell_names {U_PTECO_HOLD_BUF13}
insert_buffer [get_pins {U_PTECO_HOLD_BUF10/A}] SAEDHVT14_BUF_S_20 -new_net_names
{net_PTECO_HOLD_NET14} -new_cell_names {U_PTECO_HOLD_BUF14}
insert_buffer [get_pins {count_reg_2_/D}] SAEDHVT14_BUF_ECO_8 -new_net_names {net_PTECO_HOLD_NET15} -
new_cell_names {U_PTECO_HOLD_BUF15}
insert_buffer [get_pins {U11/A2}] SAEDHVT14_BUF_ECO_8 -new_net_names {net_PTECO_HOLD_NET16} -
new_cell_names {U_PTECO_HOLD_BUF16}
insert_buffer [get_pins {U12/A1}] SAEDHVT14_DEL_R2V1_1 -new_net_names {net_PTECO_HOLD_NET17} -
new_cell_names {U_PTECO_HOLD_BUF17}
insert_buffer [get_pins {U6/X}] SAEDHVT14_DEL_R2V2_1 -new_net_names {net_PTECO_HOLD_NET18} -
new_cell_names {U_PTECO_HOLD_BUF18}
insert_buffer [get_pins {U6/B1}] SAEDHVT14_BUF_S_20 -new_net_names {net_PTECO_HOLD_NET19} -
new_cell_names {U_PTECO_HOLD_BUF19}
insert_buffer [get_pins {U_PTECO_HOLD_BUF10/A}] SAEDHVT14_BUF_ECO_8 -new_net_names
{net_PTECO_HOLD_NET20} -new_cell_names {U_PTECO_HOLD_BUF20}
insert_buffer [get_pins {U_PTECO_HOLD_BUF16/A}] SAEDHVT14_BUF_S_20 -new_net_names
{net_PTECO_HOLD_NET21} -new_cell_names {U_PTECO_HOLD_BUF21}
insert_buffer [get_pins {U_PTECO_HOLD_BUF18/A}] SAEDHVT14_BUF_S_20 -new_net_names
{net_PTECO_HOLD_NET22} -new_cell_names {U_PTECO_HOLD_BUF22}
insert_buffer [get_pins {U10/A2}] SAEDHVT14_BUF_ECO_8 -new_net_names {net_PTECO_HOLD_NET23} -
new_cell_names {U_PTECO_HOLD_BUF23}
insert_buffer [get_pins {U_PTECO_HOLD_BUF19/A}] SAEDHVT14_BUF_ECO_1 -new_net_names
{net_PTECO_HOLD_NET25} -new_cell_names {U_PTECO_HOLD_BUF25}
insert_buffer [get_pins {U_PTECO_HOLD_BUF21/X}] SAEDHVT14_BUF_1P5 -new_net_names
{net_PTECO_HOLD_NET26} -new_cell_names {U_PTECO_HOLD_BUF26}
current_instance

- Changes in PrimeTime and Buffer insertion (Iteration 2):


###############################################################################

# Change list, formatted for IC Compiler


#
#
#
###############################################################################

current_instance
current_instance {C1}
size_cell {U_PTECO_HOLD_BUF25} {SAEDRVT14_BUF_U_0P5}
size_cell {U_PTECO_HOLD_BUF26} {SAEDRVT14_DEL_R2V2_2}
current_instance
current_instance {C2/clk_gate_fpulse_reg}
insert_buffer [get_pins {main_gate/A1}] SAEDHVT14_BUF_20 -new_net_names {net1} -new_cell_names {U1}
insert_buffer [get_pins {main_gate/A1}] SAEDHVT14_BUF_20 -new_net_names {net2} -new_cell_names {U2}
insert_buffer [get_pins {main_gate/A1}] SAEDHVT14_BUF_1 -new_net_names {net3} -new_cell_names {U3}
insert_buffer [get_pins {main_gate/A1}] SAEDHVT14_BUF_1 -new_net_names {net4} -new_cell_names {U4}
insert_buffer [get_pins {main_gate/A1}] SAEDHVT14_BUF_1 -new_net_names {net5} -new_cell_names {U5}
insert_buffer [get_pins {main_gate/A1}] SAEDHVT14_BUF_1 -new_net_names {net6} -new_cell_names {U6}
insert_buffer [get_pins {main_gate/A1}] SAEDHVT14_BUF_1 -new_net_names {net7} -new_cell_names {U7}
insert_buffer [get_pins {main_gate/A1}] SAEDHVT14_BUF_1 -new_net_names {net8} -new_cell_names {U8}
insert_buffer [get_pins {main_gate/A1}] SAEDHVT14_BUF_1 -new_net_names {net9} -new_cell_names {U9}
insert_buffer [get_pins {main_gate/A1}] SAEDHVT14_BUF_1 -new_net_names {net10} -new_cell_names {U10}
insert_buffer [get_pins {main_gate/A1}] SAEDHVT14_BUF_1 -new_net_names {net11} -new_cell_names {U11}
insert_buffer [get_pins {main_gate/A1}] SAEDHVT14_BUF_1 -new_net_names {net12} -new_cell_names {U12}
insert_buffer [get_pins {main_gate/A1}] SAEDHVT14_BUF_1 -new_net_names {net13} -new_cell_names {U13}
current_instance
- ECO Flow run:
source ./pt_changes_1.tcl
connect_pg_net -net VDD [get_pins -hier * -filter "name==VDD"]
connect_pg_net -net VSS [get_pins -hier * -filter "name==VSS"]
check_legality
#place_eco_cells -eco_changed_cells -displacement_threshold 5 -max_displacement_threshold 10
place_eco_cells -eco_changed_cells
check_legality
route_eco -utilize_dangling_wires true -reroute modified_nets_first_then_others -reuse_existing_global_route true
save_block -as DG_eco_done
report_timing
report_timing -delay_type min
report_constraints -all_violators
current_scenario func_slow
report_constraints -all_violators
#get_flat_cells *ropt*

II) Physical Verification TCL script run in icc2 (IC Compiler):


#Now Lets insert the filler cells
create_stdcell_fillers -lib_cells { */SAEDLVT14_FILL1 */SAEDLVT14_FILL2 */SAEDLVT14_FILL3
*/SAEDLVT14_FILL16 */SAEDLVT14_FILL32 */SAEDLVT14_FILL64 }
#Perform Logical Connections
connect_pg_net -net VSS [get_pins */VSS]
connect_pg_net -net VDD [get_pins */VDD]
# Delete the filler cells that have routing DRC violations
remove_stdcell_fillers_with_violation
#Let us verify and report routing design rule checking (DRC) violations, by using "check_routes" command
check_routes
# Set the DRC runset file.
set_app_options -name signoff.check_drc.runset -value ./icv_drc/saed14nm_1p9m_drc_rules.rs
set_app_options -name signoff.check_drc.max_errors_per_rule -value 1000
set_app_options -name signoff.check_drc.run_dir -value "icvDRC_run"
setenv _ICV_RSH_COMMAND ssh
signoff_check_drc
#set_app_options -list {signoff.fix_drc.init_drc_error_db "./icvDRC_run"}
#signoff_fix_drc

#Run the command to check the LVS,by using "check_lvs" command


check_lvs
#Metal fill
set_app_options -name signoff.create_metal_fill.runset -value ./icv_drc/saed14nm_1p9m_mfill_rules.rs
signoff_create_metal_fill
create_utilization_configuration -scope block core_utilization -include {all}
report_utilization -config core_utilization
save_block -as final
#close_block -f
#close_lib

You might also like