Computer Architecture
Lecture 4.
. Internal Memory.
Instructors
Elena Boldyreva, Associate Professor [email protected]
GOALS OF THIS LECTURE: PLAN:
1. get terminology about 1. How internal memory works
internal memory 2. Why internal memory works
2. more details about internal 3. Internal design basics
memory structure and
implementation
©. Stallings, William. Computer organization and architecture : designing for performance 2
Introduction
• It refers to the physical devices used to store programs (sequences of instructions) or data
(e.g. program state information) on a temporary or permanent basis for use in a computer
or other digital electronic devices.
• It is required for storage and subsequent retrieval of the instructions and data.
• It exhibits a wide range of technology and types.
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Memory hierarchy
• Internal Memory: This is where actual
processing is done which constitutes of small Internal Memory
set of high speed registers.
• Primary Memory (Main Memory): It is a large
memory which is accessed directly by a Cache Memory
processor. It is mainly based on integrated
circuits. Main Memory
• Secondary Memory: It is a large memory
which is slower than primary memory. It can Secondary Memory
be used as overflow memory incase the main
memory capacity has exceeded.
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Memory Classification
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Memory Types
• Memories are classified on the basis of several attributes, but in general they are
classified on the basis of their access time.
• They are as follows:
– Random Access Memory (RAM)
– Sequential Access Memory (SAM)
• Based on their read and write time, RAMs are further classified as,
– Read Only Memories (ROMs)
– Read Mostly Memories (RMMs)
– Read Write Memories (RWMs)
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Semiconductor Memory Types
Write
Memory Type Category Erasure Volatility
Mechanism
Random-access Read-write Electrically,
Electrically Volatile
memory (RAM) memory byte-level
Read-only
Masks
memory (ROM) Read-only
Not possible
Programmable memory
ROM (PROM)
Erasable PROM UV light, chip-
(EPROM) level Nonvolatile
Electrically Electrically
Read-mostly Electrically,
Erasable PROM memory
byte-level
(EEPROM)
Electrically,
Flash memory
block-level 7
Semiconductor Memory
• It is also called as read write memory.
• Today, random-access memory takes the
form of integrated circuits. RAM is
normally associated with volatile types
of memory (such as DRAM memory
modules), where stored information is
lost if the power is removed, although
many efforts have been made to
develop non-volatile RAM chips.
• Semiconductor RAMs are of two types.
– Static
– Dynamic
Memory Cell Operation
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Static RAM
▪ Static random-access memory (SRAM or static RAM)
is a type of semiconductor memory that uses bistable
latching circuitry to store each bit. The term static
differentiates it from dynamic RAM (DRAM) which
must be periodically refreshed. SRAM exhibits data
remanence, but it is still volatile in the conventional
sense that data is eventually lost when the memory is
not powered.
▪ They have memory cells that are similar to common
flip-flop and it stores bit as voltage.
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Static RAM Operation
Transistor arrangement gives stable logic state
▪ State 1
▪ C1 high, C2 low
▪ T1 T4 off, T2 T3 on
▪ State 0
▪ C2 high, C1 low
▪ T2 T3 off, T1 T4 on
▪ Address line transistors T5 T6 is switch
▪ Write – apply value to B & compliment to B
▪ Read – value is on line B
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Dynamic RAM
• Dynamic random-access memory (DRAM) is a type
of random-access memory that stores each bit of
data in a separate capacitor within an integrated
circuit.
• The capacitor can be either charged or discharged;
these two states are taken to represent the two
values of a bit, conventionally called 0 and 1.
• The advantage of DRAM is its structural simplicity:
only one transistor and a capacitor are required
per bit, compared to four or six transistors in
SRAM. This allows DRAM to reach very high
densities.
• The transistors and capacitors used are extremely
small; billions can fit on a single memory chip.
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Dynamic RAM
• Address line active when bit read or written
– Transistor switch closed (current flows)
• Write
– Voltage to bit line
• High for 1 low for 0
– Then signal address line
• Transfers charge to capacitor
• Read
– Address line selected
• transistor turns on
– Charge from capacitor fed via bit line to
sense amplifier
• Compares with reference value to
determine 0 or 1
– Capacitor charge must be restored
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SRAM v DRAM
• Both volatile
– Power needed to preserve data
• Dynamic cell
– Simpler to build, smaller
– More dense
– Less expensive
– Needs refresh
– Larger memory units
• Static
– Faster
– Cache
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Read Only Memory (ROM)
• Permanent storage
– Nonvolatile
• Microprogramming (see later)
• Library subroutines
• Systems programs (BIOS) • It is a non-volatile memory. It retains the stored
information even if the power is turned off. It is
• Function tables
equivalent to a group of registers each permanently
storing a word.
• Four Types of ROMs are presently available:
1. Masked ROM
2. Programmable ROM
3. Erasable Programmable ROM
4. Electrically erasable programmable ROMs
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Types of ROM
• Written during manufacture
– Very expensive for small runs
• Programmable (once)
– PROM
– Needs special equipment to program
• Read “mostly”
– Erasable Programmable (EPROM)
• Erased by UV
– Electrically Erasable (EEPROM)
• Takes much longer to write than read
– Flash memory
• Erase whole memory electrically
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Organization in detail
• A 16Mbit chip can be organised as 1M of
16 bit words
• A bit per chip system has 16 lots of
1Mbit chip with bit 1 of each word in
chip 1 and so on
• A 16Mbit chip can be organised as a
2048 x 2048 x 4bit array
– Reduces number of address pins
• Multiplex row address and
column address
• 11 pins to address (211=2048)
• Adding one more pin doubles
range of values so x4 capacity
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Refreshing
• Refresh circuit included on chip
• Disable chip
• Count through rows
• Read & Write back
• Takes time
• Slows down apparent performance
The refresh cycle is similar to the read cycle, but executes faster for two reasons:
1. For a refresh, only the row address is needed, so a column address doesn't have to be applied to the
chip address circuits.
2. Data read from the cells does not need to be fed into the output buffers or the data bus to send to
the CPU.
The refresh circuitry must perform a refresh cycle on each of the rows on the chip within the refresh
time interval, to make sure that each cell gets refreshed.
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Types of refresh circuits
Two scheduling strategies have been used:
1. Burst refresh - a series of refresh cycles are performed one after another
until all the rows have been refreshed, after which normal memory accesses
occur until the next refresh is required
2. Distributed refresh - refresh cycles are performed at regular intervals,
interspersed with memory accesses.
Burst refresh results in long periods when the memory is unavailable, so distributed
refresh has been used in most modern systems, particularly in real-time systems. In
distributed refresh, the interval between refresh cycles is
For example, DDR SDRAM has a refresh time of 64 ms and 8,192 rows, so the refresh cycle interval is 7.8 μs.
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Typical 16 Mb DRAM (4M x 4)
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Packaging
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256kByte Module Organization
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1MByte Module Organization
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Interleaved Memory
• Collection of DRAM chips
• Grouped into memory bank
• Banks independently service read or
write requests
• K banks can service k requests
simultaneously
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Error Correction
• Hard Failure
– Permanent defect
• Soft Error
– Random, non-destructive
– No permanent damage to
memory
• Detected using Hamming error
correcting code
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Synchronous DRAM (SDRAM)
• Access is synchronized with an
external clock
• Address is presented to RAM
• RAM finds data (CPU waits in
conventional DRAM)
• Since SDRAM moves data in time with
system clock, CPU knows when data
will be ready
• CPU does not have to wait, it can do
something else
• Burst mode allows SDRAM to set up
stream of data and fire it out in block
• DDR-SDRAM sends data twice per
clock cycle (leading & trailing edge)
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SDRAM Read Timing
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RAMBUS
• Adopted by Intel for Pentium &
Itanium
• Main competitor to SDRAM
• Vertical package – all pins on one side
• Data exchange over 28 wires < cm
long
• Bus addresses up to 320 RDRAM chips
at 1.6Gbps
• Asynchronous block protocol
– 480ns access time
– Then 1.6 Gbps
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DDR SDRAM
• SDRAM can only send data once
per clock
• Double-data-rate SDRAM can send
data twice per clock cycle
– Rising edge and falling edge
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