College of Engineering

Electrical Department of Engineering

COMBINATIONAL CIRCUIT DESIGN USING VHDL

Msc . Riham ali zubaid

Digital electronic library
Fourth stage
Introduction to VHDL

VHDL or HDL is a hardware description language. It describes the behavior of an electronic circuit
or system, from which the physical circuit or system can then be attained (implemented). The two
main immediate applications of VHDL are in the field of Programmable Logic Devices (including
CPLDs (Complex Programmable Logic Devices ) and FPGAs (Field Programmable Gate Arrays)
and in the field of ASICs (Application Specific Integrated Circuits).

Design Flow

As mentioned above, one of the major utilities of VHDL for programmable device (PLD or FPGA) or
in an ASIC. The design start, by writing the VHDL code, which is saved in a file with the extension
.vhdl and the same name as its ENTITY’s name.
The first step in the synthesis process is compilation. Compilation is the conversion of the high-level VHDL
language, which describes the circuit at the Register Transfer Level (RTL), into a netlist at the gate level.
The second step is optimization, which is performed on the gate-level netlist for speed or for area. At this
stage, the design can be simulated.
Finally, a place and route (fitter) software will generate the physical layout for a PLD/FPGA chip or will
generate the masks for an ASIC.
Figure : Summary of VHDL design flow
VHDL Code Structure

A standalone piece of VHDL code is composed of at least three fundamentalsections:

1. LIBRARY declarations: Contains a list of all libraries to be used in thedesign.

For example: ieee, std, work, etc.

2. ENTITY: Specifies the I/O pins of the circuit.

3. ARCHITECTURE: Contains the VHDL code proper, which describes howthe circuit should behave
(function).

Figure : Fundamental sections of a basic VHDL code.

A LIBRARY is a collection of commonly used pieces of code. Placing such pieces inside a library allows
them to be reused or shared by other designs. The typical structure of a library is illustrated in figure 42.
The code is usually written in the form of FUNCTIONS, PROCEDURES, or COMPONENTS, which are
placed inside PACKAGES, and then compiled intothe destination library.

Figure: Fundamental parts of a LIBRARY.

Library Declarations

To declare a LIBRARY (that is, to make it visible to the design) two lines of code are needed, one
containing the name of the library, and the other a use clause, as shown in the syntax below.

LIBRARY library_name;

USE library_name.package_name.package_parts;
At least three packages, from three different libraries, are usuallyneeded in a design:

- ieee.std_logic_1164 (from the ieee library),

- standard (from the std library), and

- work (work library).
Their declarations at the VHDL code must be written as follows:

LIBRARY ieee; -- A semi-colon (;) indicates USE

ieee.std_logic_1164.all; -- the end of a statement or LIBRARY std; -- declaration,
while a double
USE std.standard.all; -- dash (--) indicates a comment.
LIBRARY work;
USE work.all;
The libraries std and work shown above are made visible by default, so there is no need to declare them;
only the ieee library must be explicitly written. However, the latter is only necessary when the STD_LOGIC
(or STD_ULOGIC) data type is employed in the design .
The purpose of the three packages/libraries mentioned above is the
following:
1. The std_logic_1164 package of the ieee library specifies a multi-levellogic system .
2. std is a resource library (data types, text i/o, etc.) for the VHDL designenvironment .
3. work library is where we save our design (the .vhd file, plus all filescreated by the compiler,
simulator, etc.).

ENTITY
An ENTITY is a list with specifications of all input and output pins (PORTS)of the circuit. Its syntax is
shown below
The mode of the signal can be IN, OUT, INOUT, or BUFFER. As illustrated in figure, IN and OUT are
truly unidirectional pins, while INOUT is bidirectional. BUFFER, on the other hand, is employed when
the output signal must be used (read) internally.

The type of the signal can be BIT, STD_LOGIC, INTEGER, etc.

The name of the entity can be basically any name, except VHDL reserved words

Example: Let us consider the NAND gate of figure below. Its ENTITY can be specified as:

ENTITY nand_gate IS

PORT (a, b:IN BIT;

x : OUT BIT);

END nand_gate;

Figure : Signal modes. Figure : NAND gate.

ARCHITECTURE

The ARCHITECTURE is a description of how the circuit should behave (function). Its syntax is the
following:

As shown above, an architecture has two parts: a declarative part (optional), where signals and
constants (among others) are declared, and the code part (from BEGIN down). Like in the case of an
entity, the name of an architecture can be basically any name (except VHDL reserved words),
including the same name as the entity’s.
 Example: Write the architecture of NAND gate of figure below :
.

Solution:

ARCHITECTURE myarch OF nand_gate ISBEGIN

x <= a NAND b;
END myarch;

The meaning of the ARCHITECTURE above is the following:

The circuit must perform the NAND operation between the two input signals (a, b) and assign ( <= )
the result to the output pin (x). The name chosen for this architecture was myarch. In this example,
there is no declarative part, and the code contains just a single assignment.
 Complete VHDL code

Example: Write the VHDL code for the NAND circuit shown below?

Solution
H.W: Write the VHDL code for the logic circuit below?

By the classic (data flow) method without define internal signals

102
Solution 2: By describing the internal signals

103
Example: Draw the equivalent logic circuit for the VHDL code shown below?

entity log_cct is
port ( a,b,c,d,e : in bit;
y : out bit);
end log_cct;
architecture test1 of log_cct is
signal s1,s2,s3,s4 :bit;
begin
s1<= a or b;
s2 <= b nand c;
s3 <= d and e;
s4 <= s1 xor s2;
y <= s4 nor ( not s3);
end test1;

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Solution:

105
 Dealing with bus in VHDL code

Single Bit Versus Bit Vector

This section illustrates the difference between a single bit assignment and a bit vector assignment (that
is, BIT versus BIT_VECTOR, STD_LOGIC versus STD_LOGIC_VECTOR, or STD_ULOGIC
versus STD_ULOGIC_VECTOR).

Two VHDL codes are presented below. Both perform the AND operation between the input signals
and assign the result to the output signal. The only difference between them is the number of bits in
the input and output ports (one bit in the first, four bits in the second). The circuits inferred from these
codes are shown in figure..

106
109
Example: write the VHDL code for the circuit below?

110
First solution

111
Second solution
HW
Third solution

a(0:3)
c(0:3)
b(0:3)
Operators and Attributes

VHDL provides several kinds of pre-defined operators:

1. Assignment operators.
2. Logical operators.
3. Arithmetic operators.
4. Relational operators.
5. Shift operators.
6. Concatenation operators.

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1. Assignment Operators
Are used to assign values to signals, variables, and constants. They are:

<= Used to assign a value to a SIGNAL.

:= Used to assign a value to a VARIABLE, CONSTANT, or GENERIC. Usedalso for
establishing initial values.
=> Used to assign values to individual vector elements or with OTHERS.

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 2.Logical operators
Used to perform logical operations. The data must be of type BIT, STD_LOGIC, or STD_ULOGIC (or,
obviously, their respective extensions, BIT_VECTOR, STD_LOGIC_VECTOR, or
STD_ULOGIC_VECTOR). The logical
operators are:

(NOT ,AND , OR , NAND , NOR , XOR , XNOR)

Examples:

y <= NOT a AND b; -- (a'.b)

y <= NOT (a AND b); -- (a.b)'

y <= a NAND b; -- (a.b)'

Y <= a OR b; -- (a+b)
3. Arithmetic Operators

Arithmetic Operators Used to perform arithmetic operations. The data can be of type INTEGER,
SIGNED, UNSIGNED, or REAL Also, if the std_logic_signed or the std_logic_unsigned package
of the ieee library is used, then STD_LOGIC_VECTOR can also be employed directly in addition
and subtraction operations .

Addition

Subtraction
y mod x returns the remainder of y/x with
Multiplication the signal of x, while y rem x returns the
Division remainder of y/x with the signal of y.
Exponentiation

MOD Modulus

REM Remainder

ABS Absolute value

Example : Adder

Figure below. shows the top-level diagram of a 4-bit adder. The circuit has two inputs (a, b) and one output
(sum). Two solutions are presented. In the first, all signals are of type SIGNED, while in the second the
output is of type INTEGER. Notice the inclusion of the std_logic_arith package (line 4) which specifies the
SIGNED data type. Recall that a SIGNED value is represented like a vector; that is, similar to
STD_LOGIC_VECTOR, not like an INTEGER.

4-bit adder
 Concurrent Code

VHDL code can be concurrent (parallel) or sequential. The concurrent statements in VHDL are WHEN and
GENERATE. Besides them, assignments using only operators (AND, NOT, +, *, sll, etc.) can also be used
to construct concurrent code.

Concurrent versus Sequential

the fundamental differences between combinational logic and sequential logic, and by contrasting them
with thedifferences between concurrent code and sequential code.
Combinational versus Sequential Logic
By definition, combinational logic is that in which the output of the circuit depends solely on the
current inputs (figure (a)). It is then clear that, in principle, the system requires no memory and can
be implemented using conventional logic gates. In contrast, sequential logic is defined as that in which
the output does depend on previous inputs (figure (b)). Therefore, storage elements are required, which
are connected to the combinational logic block through a feedback loop, such that now the stored states
(created by previous inputs) will also affect the output of the circuit. A common mistake is to think that
any circuit that possesses storage elements (flip-flops) is sequential. A RAM (Random Access Memory)
is an example.

(a) (b)

Figure. Combinational (a)versus sequential (b) logic.

 Concurrent versus Sequential Code
VHDL code is inherently concurrent (parallel). Only statements placed inside a PROCESS, FUNCTION,
or PROCEDURE are sequential. Still, though within these blocks the execution is sequential, the block,
as a whole, is concurrent with any other (external) statements. Concurrent code is also called dataflow code.

In concurrent code the following can be used:

1. Operators.
2. The WHEN statement (WHEN/ELSE or WITH/SELECT/WHEN).
3. The GENERATE statement.

1. Using Operators
This is the most basic way of creating concurrent code. Operators (AND, OR, +, -, *, sll, sra, etc.) are
repeated in table 1 below. Operators can be used to implement any combinational circuit.
Table 1: Operators.
Example : Write the vhdl code using operator for the Multiplexer circuit shown on the figure below?

Figure below shows a 4-input, one bit per input multiplexer. The output must be equal to the input selected by
the selection bits, s1-s0. Its implementation,using only logical operators(data flow), can be done as follows:

4 inputs
Multiplexer
Example : Using suitable VHDL instructions, design 4-bits Binary To GRAYConverter as shown in figure ?

Solution:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

Entity TEST1 is
Port (bin : in std_logic_vector(3 downto 0);

G : out std_logic_vector(3 downto 0));

End TEST1;
Architecture TEST2 of TEST1 is
begin
G(3) <= bin(3);
G(2) <= bin(3) xor bin(2);
G(1) <= bin(2) xor bin(1);
G(0) <= bin(1) xor bin(0);TEST2 ;
Example : Draw the equivalent logic circuit for the VHDL code shown below.

Entity TEST1 is
port ( a,b,c,d,e : in bit;
y : out bit);
End TEST1;
Architecture TEST2 of TEST1 is
signal s1,s2,s3,s4 :bit;
begin
s1<= a or b;
s2 <= b nand c;
s3 <= d and e;
s4 <= s1 xor s2; s1
y <= s4 nor ( not s3);
end test2;

Solution: The equivalent logic circuit of the above VHDL code asshown in figure above .

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Example : Draw the equivalent logic circuit for the VHDL code shown below:

Entity test1 is
port ( a,b,c: IN bit; d: OUT bit);
end test1;
Architecture test2 OF test1 ISsignal x1,x2:bit;
begin

x1<= a and b;

x2<= x1 AND not c;

d<= a nand x2;

end test2;

Solution:

The equivalent circuit as shown in figure above .

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HW:
Draw the equivalent logic circuit for the VHDL code shown below:

entity TEST1 is
port (in1,in2,in3,in4,in5 : in bit;
final : out bit);
end TEST1;
architecture TEST2 of TEST1 issignal
w1,w2,w3 : bit;
begin
w1 <= in1 and in2;
w2 <= in3 or in4;
w3 <= in4 and (not in5);
final <= w1 or w2 or w3;
end TEST2;

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HW :Draw the equivalent logic circuit for the VHDL code shown below

entity cct1 is
port (x1,x2,x3,x4 : in bit;
f,g : out bit);
end cct1;
architecture cct2 of cct1 is
signal sig1,sig2,sig3 , sig4: bit;
begin
sig1 <= x1 and x3;
sig2 <= x2 and x4 ;
sig3 <= x1 or (not x3);
sig4 <= x4 or ( not x2);
f <= sig1 or sig2;
g <= sig3 and sig4;
end cct2;

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2. WHEN (Simple and Selected)
WHEN is one of the fundamental concurrent statements (along with operators and GENERATE). It
appears in two forms: WHEN / ELSE (simple WHEN) and WITH / SELECT / WHEN (selected WHEN).
Its syntax is shown below.

WHEN / ELSE:

assignment WHEN condition ELSEassignment

WHEN condition ELSE
...;

WITH / SELECT / WHEN:

WITH identifier SELECT

assignment WHEN value,
assignment WHEN value,
...;
Whenever WITH / SELECT / WHEN is used, all permutations must be tested, so the keyword OTHERS
is often useful. Another important keyword is UNAFFECTED, which should be used when no action is
to take place.

Example : Multiplexer #2

This example shows the implementation of multiplexer, but with a slightly different representation for
the sel input (figure below). However, in it WHEN was employed instead of logical operators. Two
solutions are presented: one using WHEN/ELSE (simple WHEN) and the other with
WITH/SELECT/WHEN (selected WHEN).

Multiplexer #2.
Example : Tri-state Buffer Write the vhdl code for the circuit shown in figure below.

This is another example that illustrates the use of WHEN. The 3-state buffer of figure 56 must provide
output = input when ena (enable) is low, or output =‘‘ZZZZZZZZ’’ (high impedance) otherwise.

Solution:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY tri_state IS
PORT ( ena: IN STD_LOGIC;

input: IN STD_LOGIC_VECTOR (7 DOWNTO 0); Tri-state buffer

output: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END tri_state;
ARCHITECTURE tri_state OF tri_state ISBEGIN
output <= input WHEN (ena='0') ELSE(OTHERS
=> 'Z');
END tri_state;
Example : Encoder
The top-level diagram of 8 X 3 encoder is shown in figure below. Two solutions are presented, one using
WHEN / ELSE, and the other with
WITH / SELECT / WHEN (HW)

8 x 3 Encoder
Example : ALU

Q//Write the vhdl code for the ALU shown in figure below?

An ALU (Arithmetic Logic Unit) is shown in figure. As the name says, it is a circuit capable of executing
both kinds of operations, arithmetic as well as logical. Its operation is described in the truth table of figure
58. The output (arithmetic or logical) is selected by the MSB of sel, while the specific operation is selected
by sel’s other three bits.
ALU operations
Solution:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ALU is
port (a, b: in std_logic_vector (7 downto 0);
sel: in std_logic_vector (3 downto 0); cin: in std_logic;
y: out std_logic_vector (7 downto 0));
end ALU;
ARCHITECTURE dataflow OF ALU IS
signal arith, logic: std_logic_vector (7 downto 0);BEGIN
----- Arithmetic unit: ------
WITH sel(2 DOWNTO 0) SELECT
arith <= a WHEN "000",
a+1 WHEN "001",
a-1 WHEN "010",

b WHEN "011",
 b+1 WHEN "100",

b-1 WHEN "101",

a+b WHEN "110",
a+b+cin WHEN OTHERS;
Logic unit:
WITH sel(2 DOWNTO 0) SELECT
logic <= NOT a WHEN "000",
NOT b WHEN "001",
a AND b WHEN "010",
a OR b WHEN "011",
a NAND b WHEN "100",
a NOR b WHEN "101",
a XOR b WHEN "110",
NOT (a XOR b) WHEN OTHERS;
 Mux:
WITH sel(3) SELECT
y <= arith WHEN '0',
logic WHEN OTHERS;
END dataflow;
3. GENERATE

GENERATE is another concurrent statement (along with operators and WHEN). It is equivalent to the
sequential statement LOOP in the sense that it allows a section of code to be repeated a number of times,
thus creating several instances of the same assignments. Its regular form is the FOR / GENERATE
construct, with the syntax shown below. Notice that GENERATE must be labeled.

FOR / GENERATE:
Example : Carry Ripple Adder

Figure below, shows an 8-bit unsigned carry ripple adder. Each section of the latter diagram is a full-
adder unit. Thus, its outputs can becomputed by means of:

2- bit carry ripple adder.

Full adder logic circuit diagram
Solution:
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY TEST1 IS
PORT ( a, b: IN STD_LOGIC_VECTOR (7 DOWNTO 0);cin: IN
STD_LOGIC;
S: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);cout:
OUT STD_LOGIC);
END TEST1;

ARCHITECTURE adder OF TEST1 IS

SIGNAL C: STD_LOGIC_VECTOR (8 DOWNTO 0);BEGIN
c(0) <= cin;
FOR i IN 0 TO 7 GENERATE
s(i) <= a(i) XOR b(i) XOR c(i);
c(i+1) <= (a(i) AND b(i)) OR (a(i) AND c(i)) OR (b(i) AND c(i));
END GENERATE;
cout <= c(8);
END adder;