Principle of Microcomputer
Based on ARM Technology
STM32 Interrupts
CONTENTS
• Objectives
• Overview of STM32 interrupts
• Priority of STM32 interrupts
• External interrupt/event controller (EXTI)
• Using external interrupts
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Bridge-in
Review the conception of exception and interrupt in Cortex M3.
Review the characteristics of exceptions in Cortex M3.
How many exceptions and interrupts are there in Cortex M3?
256 exceptions: 16 core exceptions + 240 external interrupts.
256 priority levels.
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★Objectives:
▪ know the structure of interrupts module in
STM32
▪ Know the registers related to interrupts module
in STM32
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Overview of STM32 interrupts(1/2)
As the Cortex M3 core is adopted, the mechanism of exception is
kept in STM32. The NVIC of STM32 is a subset of Cortex M3 NVIC.
When an exception takes place, the registers PC, PSR, R0–R3,
R12, and LR are pushed to the stack.
While the data bus (Dbus) is busy stacking the registers, the
instruction bus (Ibus) carries out another important task of the
interrupt sequence: It fetches the exception vector (the starting
address of the exception handler) from the vector table. Since the
stacking and vector fetch are performed on separate bus interfaces,
they can be carried out at the same time.
After the stacking and vector fetch are completed, the exception
will start to execute.
At the end of the exception handler, an exception exit (known
as an interrupt return in some processors) is required to restore
the system status so that the interrupted program can resume
normal execution.
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Overview of STM32 interrupts(2/2)
Features of Nested vectored interrupt controller (NVIC)
All interrupts including the core exceptions are managed by the
NVIC.
● up to 81 interrupts (depends on the STM32 device type)
● A programmable priority level of 0-15 for each interrupt. A
higher number corresponds to a lower priority, so level 0 is the
highest interrupt priority
● Low-latency exception and interrupt handling
● Preempt priority and subpriority
● An external Non-maskable interrupt (NMI)
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Priority of STM32 interrupts(1/6)
Preempt priority and subpriority
Using a configuration register in the NVIC called Priority Group,
the priority-level configuration registers for each exception with
programmable priority levels is divided into two halves. The upper half
(left bits) is the preempt priority, and the lower half (right bits) is the
subpriority.
◆ Preempt priority
An interrupt with higher preempt priority level can interrupt
main program or another interrupt with lower preempt priority.
----- Interrupt Nested
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Priority of STM32 interrupts(2/6)
◆ Subpriority
The subpriority level value is used only when two exceptions with
same preempt priority level occur at the same time. In this case, the
exception with higher subpriority (lower value) will be handled first.
When an exception is handling, another exception with same
preempt priority level can not interrupt it.
Exceptions with same preempt priority level can NOT be nested.
◆ Sequence of exceptions response
Consider the preemption firstly, and then the subpriority.
Nested character is dominated by preempt priority.
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Priority of STM32 interrupts(3/6)
◆ How to deal with the confliction of priority?
As we know, an interrupt with higher preempt priority level can
interrupt main program or another interrupt with lower preempt priority.
It is called Interrupt Nested.
Two exceptions with same preempt priority level can not be nested
with each other.
When two exceptions with same preempt priority level occur at the
same time, the exception with higher subpriority (lower value) will be
handled first.
When two exceptions with same preempt priority level and same
subpriority occur at the same time, they will be handled by the order of
the position listed in the vector table.
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Priority of STM32 interrupts(4/6)
◆ Definition of priority in STM32
4 bits of priority level is implemented in STM32, which exists in
Interrupt priority registers (NVIC_IPRx).
The base address of NVIC is 0xE000E000.
Interrupt priority registers (NVIC_IPRx):
Address offset: 0x00- 0x0B
Reset value: 0x0000 0000
Required privilege: Privileged
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Priority of STM32 interrupts(4/6)
◆ Definition of priority in STM32
4 bits of priority level is implemented in STM32, which exists in
Interrupt priority registers (NVIC_IPRx).
IPR bit assignments
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Priority of STM32 interrupts(5/6)
◆ Definition of priority in STM32
Bits[7:4] in each field of IPR are used to specify the two priority types.
Preemption Priority and Subpriority in STM32.
There are 5 groups described by 4 bits of priority register.
Preemption Priority
Priority Group Preemption Priority Level Subpriority Level
4 4 bits/16 levels 0 bit/ 0 level
3 3 bits/8 levels 1 bit/2 levels
2 2 bits/4 levels 2 bits/4 levels Subpriority
1 1 bit/2 levels 3 bits/8 levels
0 0 bit/ 0 level 4 bits/16 levels
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CONTENTS
• Objectives
• Overview of STM32 interrupts
• Priority of STM32 interrupts
• External interrupt/event controller (EXTI)
• Using external interrupts
13
★Objectives:
▪ Know the structure of EXTI
▪ Grasp how to use the external interrupts
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External interrupt/event controller (EXTI)
Overview
The external interrupt/event controller consists of up to 20
edge detectors in connectivity line devices, or 19 edge
detectors in other devices for generating event/interrupt
requests.
Each input line can be independently configured to select
the type (pulse or pending) and the corresponding trigger event
(rising or falling or both).
Each line can also masked independently.
A pending register maintains the status line of the interrupt
requests.
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External interrupt/event controller (EXTI)
Main features
The EXTI controller main features are the following:
● Independent trigger and mask on each
interrupt/event line
● Dedicated status bit for each interrupt line
● Generation of up to 20 software event/interrupt
requests
● Detection of external signal with pulse width lower
than APB2 clock period.
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External interrupt/event controller (EXTI)
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Block diagram
External interrupt/event controller (EXTI)
External interrupt/event line mapping
To configure the AFIO_EXTICRx for the mapping
of external interrupt/event lines onto GPIOs, the
AFIO clock should first be enabled.
In firmware library reference manual,
Value of EXTI_Line：P99
Value of NVIC_IRQChannel：P166
Other four EXTI lines are connected as follows:
● EXTI line 16 is connected to the PVD output
● EXTI line 17 is connected to the RTC Alarm event
● EXTI line 18 is connected to the USB Wakeup
event
● EXTI line 19 is connected to the Ethernet Wakeup
event (available only in connectivity line devices)
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External interrupt/event controller (EXTI)
EXTI registers
P211 of reference manual of STM32F10x
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Using external interrupt/event
Event and interrupt
Event: A trigger event occurs.
Interrupt: An event occurs and interrupt takes place, then
corresponding handling program is executed.
Event can trigger an interrupt, and maybe not.
Interrupts can be masked by other interrupts with higher priority,
whereas events can not be masked.
An event is a trigger signal in fact, and is used to trigger specified
peripherals or CM3 core (Wake up).
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Using external interrupt/event
To use external interrupt
EXTI lines should be configured and enabled firstly to
produce an interrupt.
Configure the two trigger selection registers according to
the edge detection requirement.
Write ‘1’ to corresponding bit of Interrupt mask register to
enable the interrupt request.
When the edge occurs on EXTI line, interrupt request will
be produced, and the corresponding pending bit is set to ‘1’.
If write ‘1’ to the pending bit, the interrupt request will be
cleared. This is often done in interrupt handling function to
clear the interrupt request.
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Using external interrupt/event
To use event
Event lines should be configured and enabled firstly to
produce an event.
Configure the two trigger selection registers according to
the edge detection requirement.
Write ‘1’ to corresponding bit of Event mask register to
enable the event request.
When an edge occures on event line, an event request
pulse will be produced, and the corresponding pending bit is
NOT set to ‘1’.
Writing a 1 to corresponding bit in Software interrupt
event register when it is at 0 sets the corresponding pending
bit in EXTI_PR. If the interrupt is enabled on this line on the
EXTI_IMR and EXTI_EMR, an interrupt request is generated.
This bit is cleared by clearing the corresponding bit of
EXTI_PR (by writing a 1 into the bit).
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Using external interrupt/event
Interrupt selection
● Configure Interrupt mask register (EXTI_IMR).
● Configure trigger selection registers(EXTI_RTSR
and EXTI_FTSR) .
● Configure NVIC Interrupt Set Enable Registers and
Interrupt Clear Enable Registers to enable interrupt
channel.(SETENA0, SETENA1…CLRENA0, CLRENA1…)
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Using external interrupt/event
Event selection
● Configure Event mask register (EXTI_EMR).
● Configure trigger selection registers(EXTI_RTSR
and EXTI_FTSR) .
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Using external interrupt/event
Software interrupt/Event selection
● Configure Interrupt or Event mask register
(EXTI_IMR, EXTI_EMR).
● Configure Software interrupt event register
(EXTI_SWIER) .
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Using external interrupt/event
Steps of programming:
*1. System initialization.
For example, clock configuration can be performed.
SystemInit() function can be called in firmware.
2. Configure GPIO.
Enable GPIO clock and AFIO clock.
3. Configure EXTI.
Select a pin as interrupt input.
4. Configure NVIC.
Enable the interrupt channel in NVIC and configure the
priority.
5. Wait for the interrupt.
Wait for the interrupt in the main program. And write the
handling code in interrupt service routine.
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Using external interrupt/event
void GPIO_Configuration(void) //Configure GPIO
{
GPIO_InitTypeDef GPIO_InitStructure;
//Configure PE8
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_Init(GPIOE, &GPIO_InitStructure);
//Configure PA0
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOA, &GPIO_InitStructure);
}
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Using external interrupt/event
void NVIC_Configuration(void) //Configure NVIC
{
NVIC_InitTypeDef NVIC_InitStructure;
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
//Select the priority group
NVIC_InitStructure.NVIC_IRQChannel = EXTI0_IRQn;
//Select interrupt channel:EXTI Line 0,as PA0 pin is select for input
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
//preemption is set to 0
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
//subpriority is set to 0
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
//enable pin as interrupt input
NVIC_Init(&NVIC_InitStructure); //call NVIC_Init()
}
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Using external interrupt/event
void EXTI_Configuration(void)
{
//call GPIO_EXTILineConfig function
GPIO_EXTILineConfig(GPIO_PortSourceGPIOB,
GPIO_PinSource0);
EXTI_InitStructure.EXTI_Line = EXTI_Line0;
//map the interrupt to Line0
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
//interrupt mode
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling
//set to the falling trigger
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
//eanble interrupt
EXTI_Init(&EXTI_InitStructure);
//call EXTI_Init firmware library funtion
//to write the parameters to registers.
}
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Using external interrupt/event
void EXTI0_IRQHandler(void)
{
if(EXTI_GetITStatus(EXTI_Line0) != RESET)
{/* interrupt occurs */
GPIO_WriteBit(GPIOD, GPIO_Pin_8, (BitAction)((1-
GPIO_ReadOutputDataBit(GPIOD, GPIO_Pin_8))));
//clear interrupt to avoid getin the IRQHandler wrong.
EXTI_ClearITPendingBit(EXTI_Line0);
}
}
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Summary
● Definition of priority in STM32
● External interrupt/event controller
● Difference between interrupt and event.
● How to select interrupt or event.
● Using external interrupt with FWLIB.
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