WORK IS WORSHIP

Digital VLSI Design – S6ECI01

Raveesh S.
Assistant Professor
Department of Electronics and Communication Engineering
Siddaganga Institute of Technology
Tumakuru – 572 103

Slides adopted from

1. Neil H.E. Weste, David Harris, Ayan Banerjee, CMOS VLSI Design, Pearson Education, 3rd Edition, 2006
2. Introduction to VLSI Circuits and Systems - John P Uyemura, John Wiley 2002
Unit -1 MOS Transistor and Combinational Circuit Design
• VLSI design flow
– Design Specification, Design Entry, Functional Simulation,
Planning Placement and Routing
• Ideal switches
• CMOS Logic circuits
– Inverter
– NAND and NOR Gates
– Compound Gates
– Pass transistors, Transmission gates and circuits
– Tristate buffer and Multiplexers
• Adders
• CMOS Inverter DC Characteristics
• Beta Ratio Effect
• Noise Margin
General naming convention

AOI22 AOI321 AOI221

• XOR and XNOR Gates

a b  a b  a b

 a  b  (a  b)  a  b  a  b

a b  a b  a b

 a  b  a b  a b
XOR and XNOR gates

Exclusive-OR Exclusive-NOR
Pass transistor logic
a
a
• AND b f
b f= a.b ?

a b f a b f
0 0 0 1 0 0
1 1 1
0 1 0
0 0 ?
1 0 0
0 1 ?
1 1 1

y=X if A =1
y=X.A
Pass transistor logic (contd.)
• Dual-rail tech. that is based on nFET logic
equations

 a  ab
 a  a.b  ab
f  a b

 ab aa 
 a.b
NAND/AND
Pass transistor logic (contd.)
• Several 2-input gates that can be created by using the
same transistor topology with different input
sequences
OR/NOR

a b f
0 0 0
0 1 1
1 0 1
 a  ab  a a  ab 1 1 1
 a  ab  ab ab
 a  b( a  a )
 ab
Pass transistor logic (contd.)

XOR/XNOR

 ab  ba  ab  ab

• Less layout area

• However, threshold will be loss
Tri-State circuits
• A tri-state circuit produces the usual 0
and 1 voltages, but also has a third high
impedance Z (or Hi-Z)
– Useful for isolating circuits from common bus lines

• A non-inverting circuit ( a buffer) can

be obtained by adding a regular static
inverter to the input
Transmission gate
• A CMOS transmission gate
– created by connecting an nFET and pFET in parallel
• Bi-directional
• Transmit the entire voltage range [0, VDD] (nMOS /pMOS problem)

y  x  s iff s  1
Transmission gate (contd.)
• Four representations of CMOS transmission
gate (TG)
A : Input
B : Output
C : Control Signal
0, Z (high impedance )
C
1, B  A
Transmission gate (contd.)
• Equivalent resistance Req
is Parallel Combination
of Req, n and Req, p

• Req constant
Transmission gate based 2:1 mux

Only 4 transistors

S TG0 TG1 Y D0
0 ON OFF D0 S Y
1 OFF ON D1 D1

S
Transmission gate based 4:1 mux
Transmission gate based 4:1 mux (contd.)
Transmission gate (contd.)
• TG based XOR/XNOR

a b  a b  a b

a b  a b  a b  a b
Transmission gate circuits
• Alternate XOR/XNOR • TG based OR gate
• Mixing TGs and FETs which
are designed for exclusive-OR
and equivalence (XNOR)
functions
• It’s important in adders and
error detection/correction
algorithms

f  a  (a)  a  b
 a  a b
 a  ab  a  b

 ab aa 
 ab
Single-Bit Addition
Half Adder Full Adder
A B
A B
Sum  A  B  C Cout C
Cout Cout  AB  BC  CA
Sum  A  B  C S

C out  A  B S
A B C Cout S
0 0 0 0 0
A B Cout S 0 0 1 0 1
0 0 0 0 0 1 0 0 1
0 1 0 1 0 1 1 1 0
1 0 0 1 1 0 0 0 1
1 1 1 0 1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Full Adder Design I

A B C Cout S
0 0 0 0 0
Sum  ABC  ABC  ABC  ABC
0 0 1 0 1
0 1 0 0 1 Sum(transistor)=6+24
0 1 1 1 0
1 0 0 0 1 Cout  ABC  ABC  ABC  ABC
1 0 1 1 0
1 1 0 1 0  AB  BC  CA
1 1 1 1 1
 AB   A  B C
Sum(transistor)=10
Full Adder Design II
• Implement sum as function of A, B, Cin, and Cout

A B C Cout S

0 0 0 1 0 Sum  CCout  BCout  ACout  ABC

0 0 1 1 1
0 1 0 1 1  Cout A  B  C   ABC
0 1 1 0 0
1 0 0 1 1 Cout  AB   A  B C
1 0 1 0 0
1 1 0 0 0
1 1 1 0 1
Full Adder Design II
• Critical path is usually C to Cout in ripple adder

MINORITY
A
B
C
Cout S
S

Cout
Four bit parallel adder

B[3] A[3] B[2] A[2] B[1] A[1] B[0] A[0]

Full Full Full Full

Ci
adder C3 adder C2 adder C1 adder

Co S[3] S[2] S[1] S[0]

DC transfer characteristics
• CMOS Inverter DC Characteristics
VDD

Vin Vout

• CMOS NAND and NOR DC Characteristics

• Beta Ratio Effect
• Noise Margin
DC transfer characteristics (contd.)

In1
PMOS only
VDD In2 PUN

InN
F(In1,In2,…InN)
Vin Vout
In1
In2 PDN
NMOS only
InN

PUN and PDN are dual logic networks

DC transfer characteristics (contd.)
• DC Response: Vout vs. Vin for a gate
• Ex: Inverter
– When Vin = 0 -> Vout = VDD
– When Vin = VDD -> Vout = 0
– In between, Vout depends on VDD
transistor size and current Idsp
Vin Vout
– By KCL, must settle such that Idsn
Idsn = |Idsp|
– We could solve equations
– But graphical solution gives more insight
DC transfer characteristics (contd.)
• Transistor Operation VDD
• Current depends on region of transistor
behavior Vin
Idsp
Vout
• For what Vin and Vout are nMOS and pMOS in Idsn
– Cutoff?
– Linear?
– Saturation?

VM  VDD
VDD 2

Logic ‘1’
Vout output
Logic ‘0’
output

0 VDD
Vin
DC transfer characteristics (contd.)
• nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn
Vin < Vtn Vin > Vtn Vin > Vtn
Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn
Vout < Vin - Vtn Vout > Vin - Vtn

VDD
Vgsn = Vin
Idsp
Vdsn = Vout Vin Vout
Idsn
DC transfer characteristics (contd.)
• pMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp
Vin > VDD + Vtp Vin < VDD + Vtp Vin < VDD + Vtp
Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp
Vout > Vin - Vtp Vout < Vin - Vtp

VDD
Vgsp = Vin - VDD Vtp < 0 Idsp
Vin Vout
Vdsp = Vout - VDD Idsn
DC transfer characteristics (Contd.)
• I-V Characteristics
– Make pMOS is wider than nMOS such that bn = bp
Vgsn5

Idsn Vgsn4

-Vdsp Vgsn3
-VDD Vgsn2
Vgsp1 Vgsn1
Vgsp2 0 VDD
Vgsp3 Vdsn

Vgsp4 -Idsp

Vgsp5
DC transfer characteristics (Contd.)
• Current vs. Vout, Vin

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout
DC transfer characteristics (Contd.)
• Load Line Analysis
 Vin = 00.2V
0.4V
0.6V
0.8V
V DD DD
DD

Vin0 Vin5
in5

Vin1 Vin4
Idsn
dsn, |Idsp
dsp
|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
in0
VDD
Vout
out
DD
DC transfer characteristics (Contd.)
• DC Transfer Curve
– Transcribe points onto Vin vs. Vout plot
Vin0 Vin5

Vin1 Vin4

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout
DC transfer characteristics (Contd.)
• Operating Regions
VDD
– Revisit transistor operating regions
Vin Vout

Region nMOS pMOS VDD

A B
A Cutoff Linear
B Saturation Linear Vout
C
C Saturation Saturation
D Linear Saturation
D
E Linear Cutoff 0 Vtn VDD/2
E
VDD+Vtp
VDD
Vin
Midpoint Voltage VM

(Let Vin = Vout = VM)

bn
(VM  VTn )  VDD  VM  VTp
I Dn  I Dp bp

bn bn bn
I Dn  (VM VTn ) 2 VM  VTn  VDD  VM  VTp
2 bp bp
bp
I Dp  (VDD  VM  VTp ) 2  bn  bn
2  1VM  VDD  VTp  VTn
 bp  bp
 
bn bp
(VM VTn ) 
2
(VDD  VM  VTp ) 2
2 2 bn
VDD  VTp  VTn
Divide above equation by b p bp
VM 
and take square root bn
1
bp
Midpoint Voltage VM (Contd.)
Symmetrical inverter principle
W 
 'n  
bn L n 1
 VM  VDD
bp W  2
 'p  
L p
2
1 
b n  2 VDD  VTp 
 'n  n  
  bp  1V V
 
 'p  p  2
DD Tn


 'n
 2 to 3 bn  b p
 'p
Beta ratio effect
• If bp / bn  1, switching point will move from VDD/2
• Called skewed gate
• Other gates: collapse into equivalent inverter
VDD
VDD bp
 10
bn
Vout 2
1
Vin Vout 0.5
bp
 0.1
bn

0
VDD
Vin
NAND analysis
1 1 1 Rp
  R p ,eq 
R p ,eq Rp Rp 2

Rn ,eq  Rn  Rn Rn ,eq  2 Rn
 NAND analysis (Contd.)
• Find VM for the case of simultaneous switching, where the
nFET and pFET transconductance are 2βn and (βp/2)

b n / 2 2b 
2
VM  VTn  
2

2
p
V DD  VM  VTp 
2

1 bn
VDD  VTp  VTn
2 bp
VM 
1 bn
1
2 bp
1 bn
VDD  VTp  VTn
N bp
VM 
1 bn
1
N bp
NOR analysis

R p ,eq  2 R p

Rn
Rn ,eq 
2
NOR analysis
• Find VM for the case of simultaneous switching, where the
nFET and pFET transconductance are (βn/2) and 2βp

2b n  b / 2
2
VM  VTn  
2 p

2
V DD  VM  VTp 
2

bn
VDD  VTp  2 VTn
bp
VM 
bn
1 2
bp
bn
VDD  VTp N VTn
bp
VM 
bn
1 N
bp
Noise margin
2 input XOR gate

Output ?
Noise margin
• How much noise can a gate input see before it does
not recognize the input?

VDD
VM  VDD
2

Logic ‘1’
output
Vout
Logic ‘0’
output

0 VDD
Vin

Input Input
low high
Noise margin ( Contd.)

where VNM H  VOH  VIH

VIH = minimum HIGH input voltage
VIL = maximum LOW input voltage
V0H = minimum HIGH output voltage
VNM L  VIL  VOL
V0L = maximum LOW output voltage.
Beta ratio effect
 End of
Unit-1, Part-2