SCHOOL OF ELECTRICAL & ELECTRONICS ENGINEERING
THANJAVUR - 610401, TAMILNADU, INDIA
COURSE CODE : ECE317
COURSE NAME : FPGA LABORATORY
SEMESTER : VI SEMESTER
B Tech – ECE
EVEN SEMESTER - 2024-25
1
LABORATORY RECORD NOTEBOOK
BONAFIDE CERTIFICATE
Certified that this is the bonafide record of work done by
Mr. / Ms. __________________________________________
with Register Number. _________________ during his / her
VI Semester in ECE317 – FPGA Laboratory during the
Academic year 2024 – 2025.
Date: ____________
Staff In-charge
Submitted for the University Examination held on _______________
Examiner – I Examiner – II
2
TABLE OF CONTENTS
S. Page
Date Title of the Experiment Marks Signature
No. No.
3
EXP NO:1 Combinational Circuits- Logic Gates
DATE:
AIM
To write a VerilogHDL code to implement all basic logic gates
APPARATUS REQUIRED
ModelSim
ALGORITHM
1. Declare the module with input and output ports.
2. Use Boolean expressions continuous assignment statements with for designing the all basic
logic gates
3. End the module.
VERILOG CODE:
ANDGATE
moduleand_gate(
input a,
input b, outputy);
assigny=a&b; endmodule
OR GATE
moduleor_gate(
input a,
input b, outputy);
assigny=a|b; endmodule
NOT GATE
modulenot_gate(
input a,
output y );
assign y = ~a; endmodule
NANDGATE
modulenand_gate(
input a,input b,outputy);
assigny=~(a&b);
endmodule
NOR GATE
modulenor_gate(
input a,
input b, output y);
assigny=~(a|b);
4
endmodule
XOR GATE
modulexor_gate(
input a,
input b, output y
);
assigny=a^b; endmodule
XNORGATE
modulexnor_gate(
input a,
input b, output y
);
assigny=~(a^b);
endmodule
RESULT
Thus the all basic logic gates were implemented.
5
EXP NO:2 a. HALF ADDER, HALF SUBTRACTOR
DATE:
AIM
To write a VerilogHDL code to implement half adder and full adder
APPARATUS REQUIRED
ModelSim
ALGORITHM
1. Declare the module with input and output ports.
2. Declare the required wires and registers.
3. Use boolean expressions with continuous assignment statements for designing half adder and half
subtractor using dataflow model.
4. End the module.
VERILOG CODE
HALF ADDER
module haa(s,c,a,b);
input a,b;
output s,c;
assign s=a^b;
assign c=a&b;
endmodule
HALF SUBTRACTOR
module fullsub(d,b,x,y,z);
output d,b;
input x,y,z;
assign diff = a ^ b ^ c;
assign borrow = ((~a) & b) | (b & c) | (c & (~a));
endmodule
6
RESULT
Thus the half adder and half subtractor were implemented.
7
EXP NO:2 b. FULL ADDER AND FULL SUBTRACTOR
DATE:
AIM
To write a VerilogHDL code to implement full adder and full subtractor
APPARATUS REQUIRED
ModelSim
ALGORITHM
1. Declare the module with input and output ports.
2. Declare the required wires and registers.
3. Use boolean expressions with continuous assignment statements for designing half
adder and full adder
using dataflow model.
4. End the module.
VERILOG CODE
Full Adder
module full_adder( s,cout,a,b,cin );
output s,cout;
input a,b,cin;
assign s = a ^ b ^ cin;
assign cout = (a&b) | (b&cin) | (cin&a);
endmodule
Full adder using only NAND
module fulladd(a,b,Cin,S,Cout);
input Cin,a,b;
output S;
output Cout;
wire w1,w2,w3,w4,w5,w6,w7;
nand n1(w1,a,b);
nand n2(w3,a,w1);
nand n3(w2,w1,b);
nand n4(w4,w3,w2);
nand n5(w5,w4,Cin);
nand n6(w6,w4,w5);
nand n7(w7,w5,Cin);
nand n8(Cout,w5,w1);
nand n9(S,w6,w7);
endmodule
8
Four bit adder using full adder as a component
module fulladd4(a, b, c_in,sum, c_out);
input [3:0] a, b;
input c_in;
output [3:0] sum;
output c_out;
wire c1, c2, c3;
fulladd fa0(a[0], b[0], c_in, sum[0], c1);
fulladd fa1(a[1], b[1], c1, sum[1], c2);
fulladd fa2(a[2], b[2], c2, sum[2], c3);
fulladd fa3(a[3], b[3], c3, sum[3], c_out);
endmodule
Full Subtractor
module full_subtractor(input a, b, Bin, output D, Bout);
assign D = a ^ b ^ Bin;
assign Bout = (~a & b) | (~(a ^ b) & Bin);
endmodule
RESULT
Thus the full adder and full subtractor were implemented
9
EXP NO:3 4 BIT RIPPLER CARRY ADDER
DATE:
AIM
To write a VerilogHDL code to implement 4 bit rippler carry adder
APPARATUS REQUIRED
ModelSim
ALGORITHM
1. Declare the module with input and output ports.
2. Declare the required wires and registers.
3. Use boolean expressions with continuous assignment statements for designing the 4-bit
rippler carry adder
4. End the module.
VERILOG CODE
4 bit rippler carry adder
module fulladd4(a, b, c_in,sum, c_out);
input [3:0] a, b;
input c_in;
output [3:0] sum;
output c_out;
wire c1, c2, c3;
fulladd fa0(a[0], b[0], c_in, sum[0], c1);
fulladd fa1(a[1], b[1], c1, sum[1], c2);
fulladd fa2(a[2], b[2], c2, sum[2], c3);
fulladd fa3(a[3], b[3], c3, sum[3], c_out);
endmodule
10
RESULT
Thus the 4 bit rippler carry adder was implemented
11
EXP NO:4 BCD ADDER , ADDER CUM SUBTRACTOR
DATE
AIM
To write a VerilogHDL code to implement BCD Adder,Adder cum Subtractor
APPARATUS REQUIRED
ModelSim
ALGORITHM
1. Declare the module with input and output ports.
2. Declare the required wires and registers.
3. Use logical condition with continuous assignment statements for designing the BCD
Adder,Adder cum Subtractor
4. End the module.
VERILOG CODE
BCD ADDER
module bcdadder4(sum,carryout,a,b,cin);
input[3:0]a,b;
input cin;
output reg [3:0]sum;
output reg carryout;
reg[4:0]temp;
//reg[3:0]sum,reg carryout;
always@(*)
begin
temp=a+b+cin;
if(temp>9)
begin
temp=temp+6;
carryout=1;
sum=temp;
end
else
begin
carryout=0;
sum=temp;
12
end
end
endmodule
Four bit Adder / Subtractor:
module fourbitaddsub (a, b, mode, res, cout);
input [3:0] A, B;
input mode; // (0- Add, 1- Sub)
output [3:0] result;
output Cout;
wire [3:0] Bmod;
wire C1, C2, C3;
assign Bmod[0] = B[0] ^ mode;
assign Bmod[1] = B[1] ^ mode;
assign Bmod[2] = B[2] ^ mode;
assign Bmod[3] = B[3] ^ mode;
fulladder fa1 (.A(A[1]), .B(Bmod[1]), .CIN(C1), .SUM(res[1]), .COUT(C2));
fulladder fa2 (.A(A[3]), .B(Bmod[3]), .CIN(C3), .SUM(res[3]), .COUT(Cout));
endmodule
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RESULT
Thus the BCD adder, adder cum subtractor were implemented
14
EXP NO:5 MULTPLEXER
DATE:
AIM
To write a VerilogHDL code to implement multiplexer.
APPARATUS REQUIRED
ModelSim
ALGORITHM
1. Create a module declaring input and output variables.
2. Assign inputs as per the block diagram and generate the output accordingly.
3. Use case statements to design the data selector logic.
4. End the module.
VERILOG CODE
MULTIPLEXER (2:1)
modulemux2_1(y,sel,a,b); input
a, b;
input sel;
outputregy;
always@(*)begin case
(sel)
1'b0: y = a;
1'b1:y=b;
endcase
end endmodule
MULTIPLEXER(4:1)
module mux41(y,s,a,en);
input [1:0]s;
input [3:0]a;
input en;
output y;
reg y;
always@(s,a)
begin
15
if(en)
begin
case(s)
2'b00:y<=a[3];
2'b01:y<=a[2];
2'b10:y<=a[1];
2'b11:y<=a[0];
Endcase
End
else
y<=1'bx;
end
endmodule
MULTIPLEXER( 4:1)
modulemux4(y,sel,a,b,c,d);
input a, b, c, d;
input[1:0]sel;
output reg y;
always@(*)
begin
case(sel)
2'b00: y <=a;
2'b01: y <=b;
2'b10: y <=c;
2'b11: y <=d;
endcase
end
endmodule
MULTIPLEXER (16:1)
modulemux(y,sel,a);
input [15:0]a;input
[3:0]sel; output y;
wire z1,z2,z3,z4;
mux4 x1(z1,sel[3:2],a[3],a[2],a[1],a[0]);
mux4 x2(z2,sel[3:2],a[7],a[6],a[5],a[4]);
mux4 x3(z3,sel[3:2],a[11],a[10],a[9],a[8]);
mux4 x4(z4,sel[3:2],a[15],a[14],a[13],a[12]);
mux4x5(y,sel[1:0],z4,z3,z2,z1);
endmodule
16
MUX(32X1)
modulemux32(y,sel,a);
input[31:0]a;
input[4:0]sel;
output y;
wirez1, z2;
mux16ux1(z1, sel[3:0], a[15:0]);
mux16ux2(z2, sel[3:0], a[31:16]);
mux2ux3(y,sel[4],z2,z1);
endmodule
RESULT
Thus a Verilog HDL code was implemented for Multiplexer
17
EXP NO:6 DEMULTIPLEXER
DATE:
AIM
To write a Verilog HDL code to implement Demultiplexer
APPARATUS REQUIRED
ModelSim
ALGORITHM
1. Create a module, declaring input and output variables.
2. Use AND gates along with select lines to construct the DEMUX.
3. Assign the single input and direct it to one of the four outputs based on select lines.
4. Use case statements to implement the demultiplexing logic.
5. End the module.
VERILOG CODE
1:4 DEMUX
module demux14(y, s, a, en);
input [1:0] s;
input a;
input en;
output reg [3:0] y;
always @(s, a, en) begin
if (en) begin
case (s)
2'b00: y = {3'b000, a};
2'b01: y = {2'b00, a, 1'b0};
2'b10: y = {1'b0, a, 2'b00};
2'b11: y = {a, 3'b000};
default: y = 4'b0000;
endcase
end else begin
y = 4'bxxxx;
end
end
endmodule
16:1 multiplexer using 4:1
module mux16_1(y,s0,s1,s2,s3,i0,i1,i2,i3,i4,i5,i6,i7,i8,i9,10,i11,i12,i13,i14,i15);
input s0,s1,s2,s3;
input i0,i1,i2,i3,i4,i5,i6,i7,i8,i9,i10,i11,i12,i13,i14,i15;
18
output y;
wire x1,x2,x3,x4;
mux m1(x1,s0,s1,i0,i1,i2,i3);
mux m2(x2,s0,s1,i4,i5,i6,i8);
mux m3(x3,s0,s1,i9,i10,i11,i12);
mux m4(x4,s0,s1,i12,i13,i14,i15);
mux m5(y,s2,s3,x1,x2,x3,x4);
endmodule
RESULT
Thus a Verilog HDL program was implemented for Demultiplexer
19
EXP NO:7 PRIORITY ENCODER &DECODER
DATE:
AIM
To write a Verilog HDL code to implement priority Encoder &Decoder
APPARATUS REQUIRED
ModelSim
ALGORITHM
1. Create a module, declaring input and output variables.
2. Use if,else statements to implement the priority Encoder , case statements to implement
the decoder
3. End the module.
VERILOG CODE:
PRIORITY ENCODER:
module encoder (y, a);
input [3:0] a;
output [1:0] y;
reg [1:0] y;
always @(*) begin
if (a[3] == 1)
y = 2'b11;
else if (a[2] == 1)
y = 2'b10;
else if (a[1] == 1)
y = 2'b01;
else
y = 2'b00;
end
endmodule
SEVEN SEGMENT DECODER
modulesevseg(
inputeg[3:0]bcd,
output reg [6:0] seg
);
always@(*)begin case(bcd)
4'b0000: seg = 7'b1111110;
4'b0001: seg = 7'b0110000;
20
4'b0010: seg = 7'b1101101;
4'b0011: seg = 7'b1111001;
4'b0100: seg = 7'b0110011;
4'b0101: seg = 7'b1011011;
4'b0110: seg = 7'b1011111;
4'b0111: seg = 7'b1110000;
4'b1000: seg = 7'b1111111;
4'b1001: seg = 7'b1111011;
Endcase
end
endmodule
Result
Thus a Verilog HDL program was implemented for Priority Encoder & Decoder
21
EXP NO:8 COMPARATOR
DATE:
AIM
To write a Verilog HDL code to implement Comparator
APPARATUS REQUIRED
Quartus prime 18.0
ALGORITHM
1. Create a module, declaring input and output variables.
2. Use if,else statements to implement the Comparator
3. End the module.
VERILOG CODE
1-BIT COMPARATOR
module comp(eq,gr,lr,a,b,eq1,gr1,lr1);
input a,b,eq1,gr1,lr1;
output reg eq,gr,lr;
always@(*)
begin
if(a==b)
begin
eq<=1'b 1;lr<=1'b 0;gr<=1'b 0;
end
else if(a<b)
begin
lr<=1'b 1;gr<=1'b 0;eq<=1'b 0;
end
else
begin
gr<=1'b 1;lr<=1'b 0;eq<=1'b 0;
end
end
endmodule
22
4-BIT COMPARATOR
module fourcomp(grr,lrr,eqr,a1,b1,lr1,gr1,eq1);
input [3:0]a1,b1;
input eq1,lr1,gr1;
output grr,lrr,eqr;
wire w1,w2,w3,w4,w5,w6,w7,w8,w9;
comp x1(w1,w2,w3,a1[0],b1[0],lr1,gr1,eq1);
comp x2(w4,w5,w6,a1[1],b1[1],w1,w2,w3);
comp x3(w7,w8,w9,a1[2],b1[2],w4,w5,w6);
comp x4(grr,lrr,eqr,a1[3],b1[3],w7,w8,w9);
endmodule
RESULT
Thus a Verilog HDL program was implemented for comparator
23
EXP NO:9 ARITHMETIC LOGIC UNIT
DATE:
AIM
To write a Verilog HDL code to implement Arithmetic Logic Unit
APPARATUS REQUIRED
Quartus prime 18.0
ALGORITHM
1. Create a module, declaring input and output variables.
2. Use if, else statements to implement the Arithmetic Logic Unit
3. End the module.
VERILOG CODE
ALU
module ALU(c,sel,a,b);
input [2:0]sel;
input a,b;
output reg[7:0]c;
always@(*)
begin
if(sel==3'b 000)
c<=a^b;
else if(sel==3'b 001)
c<=a+b;
else if(sel==3'b 010)
c<=a&b;
else if(sel==3'b 011)
c<=a-b;
else if(sel==3'b 100)
c<=a/b;
else if(sel==3'b 110)
c<=a|b;
else
c<=~(a&b);
end
endmodule
24
RESULT
Arithmetic and Logic Unit was implemented on Quartus prime 18.0
25
EXP NO:10 SEQUENTIAL CIRCUITS- FLIPFLOPS
DATE:
AIM
To write a Verilog HDL code to implement FLIPFLOPS
APPARATUS REQUIRED
Quartus prime 18.0
ALGORITHM
1. Create a module, declaring input and output variables.
2. Use if,else condition to implement the D flipflop
3. Use Case to implement the JK flipflop
4. End the module.
VERILOG CODE
D FLIPFLOP:
module dff(y,clk,a);
input a,clk;
output reg y;
always@(posedge clk)
begin
if(a==0)
y<=1'b0;
else
y<=1'b1;
end
endmodule
JK FLIPFLOP
module JKFlipflop(input clk,j,k,output q,qbar);
reg q1;
always @ (posedge clk)
case ({j,k})
2'b00 : q1 <= q1;
2'b01 : q1 <= 0;
2'b10 : q1 <= 1;
2'b11 : q1 <= ~q1;
endcase
assign q = q1;
assign qbar = ~q;
endmodule
26
RESULT
JK ,DFlipflop was implemented on Quartus prime 18.0
27
EXP NO:11 SEQUENTIAL CIRCUITS- SHIFT REGISTER
DATE:
AIM
To write a Verilog HDL code to implement Shift Register
APPARATUS REQUIRED
Quartus prime 18.0
ALGORITHM
1. Create a module, declaring input and output variables.
2. Declare wire and reg & implement the PIPO& SISO Shift registers
3. End the module.
VERILOG CODE
PIPO:
module pipo(y2,clk2,a2);
input[3:0]a2,clk2;
output reg [3:0]y2;
always @(posedge clk2)
begin
y2<=a2;
end
endmodule
SISO:
module siso(y,clk,d);
input d,clk;
output y;
wire w1,w2,w3;
dff x1(w1,clk,d);
dff x2(w2,clk,w1);
dff x3(w3,clk,w2);
dff x4(y,clk,w3);
endmodule
28
RESULT
Shiftregisters was implemented on Quartus prime 18.0
29
EXP NO:12 SEQUENTIAL CIRCUITS- UNIVERSAL SHIFT REGISTER
DATE:
AIM
To write a Verilog HDL code to implement Universal Shift Register
APPARATUS REQUIRED
Quartus prime 18.0
ALGORITHM
1. Create a module, declaring input and output variables.
2. Declare wire & implement the Universal Shift registers using D flipflop and mux
3. End the module.
VERILOG CODE
Universal Shift Register:
module usr(y,a,sr,sl,clk,s);
input sl,sr,clk;
input [3:0]a;
input [1:0]s;
output [3:0]y;
wire w1,w2,w3,w4;wire [3:0]z;
dff x1(z[3],clk,w4);
dff x2(z[2],clk,w3);
dff x3(z[1],clk,w2);
dff x4(z[0],clk,w1);
mux x5(w4,s,z[3],sr,z[2],a[3]);
mux x6(w3,s,z[2],z[3],z[1],a[2]);
mux x7(w2,s,z[1],z[2],z[0],a[1]);
mux x8(w1,s,z[0],z[1],sl,a[0]);
assign y=z;
endmodule
30
RESULT
Universal Shift register was implemented on Quartus prime 18.0
31
EXP NO:13 COUNTER
DATE:
AIM
To write a Verilog HDL code to implement Counter
APPARATUS REQUIRED
Quartus prime 18.0
ALGORITHM
1. Create a module, declaring input and output variables.
2. Use if,else condition to implement the counter
3. End the module.
VERILOG CODE
UP COUNTER (4-BIT)
module up_counter (
input clk, // Clock input
input reset, // Reset input (active high)
output reg [3:0] count // 4-bit counter output
);
always @(posedge clk or posedge reset) begin
if (reset)
count <= 4'b0000; // Reset the counter to 0
else
count <= count + 1; // Increment the counter by 1
end
endmodule
DOWN COUNTER (4-BIT)
module down_counter (input clk, // Clock input
input reset, // Reset input (active high)
output reg [3:0] count // 4-bit counter output
);
always @(posedge clk or posedge reset) begin
if (reset)
count <= 4'b1111; // Reset the counter to 15 (1111 in binary)
else
count <= count - 1; // Decrement the counter by 1
end
endmodule
32
UPDOWN COUNTER
module udc(count,ud,clk,rst);
output reg[3:0]count=4'b0;
input clk,rst,ud;
always@(posedgeclk)
begin
if(rst==0)
begin
if(ud==1&&count<4'hf)count=count+1;
else if (ud==1&&count=4'hf)count=4'h0;
else if(ud==0&&count>4'h0)count=count-1;
else count=4'hf;
end
end
endmodule
RESULT
Counter was implemented on Quartus prime 18.0
33
EXP NO:14 BCD COUNTER
DATE:
AIM
To write a Verilog HDL code to implement BCD Counter
APPARATUS REQUIRED
Quartus prime 18.0
ALGORITHM
1. Create a module, declaring input and output variables.
2. Use if,else condition to implement the counter
3. End the module.
VERILOG CODE
BCD COUNTER
module bcdcounter( clk, rst, bcd_out);
input clk, rst;
output [3:0] bcd_out;
reg [3:0] bcd_out;
initial
begin
bcd_out=4'd0;
end
always @ (posedge clk)
begin
if (rst==0)
bcd_out=4'd0;
else if(bcd_out<4'd9)
bcd_out=bcd_out+4'd1;
else
bcd_out=4'd0;
end
endmodule
34
RESULT
BCD Counter was implemented on Quartus prime 18.0
35
EXP NO:15 REAL TIME CLOCK
DATE:
AIM
To write a Verilog HDL code to implement Real time clock
APPARATUS REQUIRED
Quartus prime 18.0
ALGORITHM
1. Create a module, declaring input and output variables for bcd counter frequency divider
2. Use case statement to implement the seven segment display
3. End the module.
VERILOG CODE
REAL TIME CLOCK
module bcdcounter(
input clk,
input reset,
output [6:0] display1, // Units place
output [6:0] display2, // Tens place
output clk0
);
reg [3:0] unit_count;
reg [2:0] tens_count;
reg [6:0] y1, y2;
reg [24:0] count1 = 0;
always @(posedge clk) begin
if (count1 > 48000000)
count1 <= 0;
else
count1 <= count1 + 1;
end
assign clk0 = (count1 < 24000000) ? 1 : 0;
always @(posedge clk0 or posedge reset) begin
if (reset) begin
unit_count <= 4'b0000;
tens_count <= 3'b000;
end else if (unit_count == 4'b1001) begin // If units place reaches 9
unit_count <= 4'b0000;
36
if (tens_count == 3'b101) // If tens place reaches 5
tens_count <= 3'b000;
else
tens_count <= tens_count + 1;
end else begin
unit_count <= unit_count + 1;
end
end
always @(unit_count) begin
case (unit_count)
4'b0000: y1 <= 7'b1000000;
4'b0001: y1 <= 7'b1111001;
4'b0010: y1 <= 7'b0100100;
4'b0011: y1 <= 7'b0110000;
4'b0100: y1 <= 7'b0011001;
4'b0101: y1 <= 7'b0010010;
4'b0110: y1 <= 7'b0000010;
4'b0111: y1 <= 7'b1111000;
4'b1000: y1 <= 7'b0000000;
4'b1001: y1 <= 7'b0011000;
default: y1 <= 7'b1111111;
endcase
end
always @(tens_count) begin
case (tens_count)
3'b000: y2 <= 7'b1000000;
3'b001: y2 <= 7'b1111001;
3'b010: y2 <= 7'b0100100;
3'b011: y2 <= 7'b0110000;
3'b100: y2 <= 7'b0011001;
3'b101: y2 <= 7'b0010010;
default: y2 <= 7'b1111111;
endcase
end
assign display1 = y1;
assign display2 = y2;
RESULT
Real time clock was implemented on Quartus prime 18.0
37
EXP NO:16 ON CHIP IP CORE LPM COUNTER
DATE:
AIM
To implement IP CORE LPM Counter using block diagram method
APPARATUS REQUIRED
Quartus prime 18.0
STEPS FOR IP CORE LPM COUNTER
STEP 1:
Select new project wizard→give projet name in Directory, Name ,Toplevel entity→Project type
( Next)→Add files (NEXT) →family device board made the changes
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STEP 1 A:
SELECT NEXT →EDA Tool settings(next) →summary (finish)
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STEP 2:
file→new→block diagram/schematic file→OK IP Catalog→arithmetic→ select
LPM_COUNTER →give file name(test) →OK
STEP 3: Select q output bus 26 bits
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STEP 4:next→next→ next → next
STEP 5:select(.bsf,.v and other check box)
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STEP 6:
STEP 7:
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STEP 8: select lpm counter (file name test) from project
STEP 8: (I)select input ,output (search the block)
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(II)
(III)
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STEP 9:save and compile connect DE10 LITE KIT
STEP 10: Assign pin in Pinplanner (clock p11,led a8) and compile
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STEP 11: Tools→programmer
STEP 12: select USB BLASTER in hardware setup
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STEP 13: select .sof file start download
RESULT
IP CORE LPM Counter using block diagram method was implemented on Quartus prime 18.0
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EXP NO:17 ON CHIP IP CORE MULTIPLIER
DATE:
AIM
To write a Verilog HDL code to implement IP CORE LPM multiplier
APPARATUS REQUIRED
Quartus prime 18.0
STEPS FOR IP CORE LPM MULTIPLIER
1. Create a module, declaring input and output variables
2. Call the LPM MULTIPLIER from the ip catalog (lpm counter block’s verilog code)
3. Set top level entity compilation
4. Connect FPGA KIT with system
5. Assign pin using pin planner
6. Compile the program after pin planning
7. Download the program using USB BLASTER and START running
8. Based on pin assign the input and verify the output using LED
VERILOG CODE
LPM MULTIPLIER
module mult(dataa,datab,result);
input[1:0]dataa,datab;
output[3:0]result;
mull x1 (
dataa,
datab,
result);
endmodule
RESULT
IP CORE LPM Multiplier was implemented on Quartus prime 18.0
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EXP NO:18 MEMORY ACCESS
DATE:
AIM
To write a Verilog HDL code to implement MEMORY ACCESS
APPARATUS REQUIRED
Quartus prime 18.0
STEPS FOR MEMORY ACCESS
STEP 1:
Select new project wizard→give projet name in Directory, Name ,Toplevel entity→Project type
( Next)→Add files (NEXT) →family device board made the changes
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STEP 1 A:
SELECT NEXT →EDA Tool settings(next) →summary (finish)
STEP 2
file→new→verilogHDL→OKwrite the verilog program→save the program→verilog file(.v)created
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STEP 3: IPCATALOG select RAM 1 PORT
STEP 4:
1.
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2.
Select next
3.
NO CHANGES → Select NEXT→NEXT
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4.
Select allow insystem memory give name within 4 letters give next→next→select .bsf,.v file
5.
Finish….> .qip file open select yes
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6.Select another memory from ip catalog
7.
Right click main file and select → set the top level entity
STEP 5:
1.Start compilation→connect DE 10 KIT
2.Assignments→ select pin planner→assign pin number for clk→p11,wren1→pin c10,wren
2→pin c11
3. After pinplanner ….>compile the program
4.Tools→programmer
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STEP 6: TOOLS→IN system memory content editor
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STEP 7:
IN system memory content editor →BROWSE the (.sof) file → Download
STEP 8:
1.SELECT M1 & WRITE →M1 value updated automaticaly
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2. SELECT M2 & WRITE →M2 value updated automaticaly
VERILOG CODE
MEMORY ACCESS
module memaccess (clk,wren1,wren2,fout);
input clk,wren1,wren2;
output [9:0]fout;
wire [4:0]addr;
wire [7:0]dout;
wire [7:0]mem1out;
wire [9:0]mulout;
addr (clk,addr,dout);
jk(addr,clk,dout,wren1,mem1out);
mul(mem1out,mulout);
jk2(addr,clk,mulout,wren2,fout);
endmodule
module addr(clk,addr,dout);
input clk;
output reg [4:0] addr;
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output reg [7:0] dout;
always @(posedge clk)
begin
addr=addr+1'b1;
dout=dout+1'b1;if(dout>6'd31) dout=0;
end
endmodule
module mul(in,out);
input[7:0] in;
output [9:0] out;
assign out= in*2'b10;
endmodule
RESULT
MEMORY ACCESS was implemented on Quartus prime 18.0
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EXP NO:19 APPLICATION DEVELOPMENT USING SOFT COREPROCESSOR
DATE:
AIM
To write Verilog program to access the soft-core processor (NIOS II) to display “hello
world”in console window.
APPARATUS REQUIRED
Quartus prime 18.0
ALGORITHM
1. For a minimum configuration NIOS II Processor, we need Nios II Core, onchip
memory and JTAG Communication module
2. Add one by one using the following procedure.
3. Then add the software component to the same.
4. Run the code on the Nios II processor and observe the result
PROCEDURE
Part I: NIOS II Processor Creation through PLATFORM DESIGNER
Step 1: Create a project
Step 2: Open Tools->Platform Designer
Step 3: Add Embedded Processor NIOS II processor select NIOS II e
Step 4: Add Memories and Memory controller On chip On-chip memory
Step 5: Add Interface Protocols Serial JTAG UART
Step 6: Connect the clk signal with NIOS clk, On-chip memory clk1 and JTAG UART
clk
Step 7: Connect the clk_reset signal with NIOS reset, On-chip memory reset and JTAG
UART reset
Step 8: Connect data master and instruction masters of NIOS with on-chip memory S1
i.e.Avlonmemory mapped slave
Step 9: Connect data master of NIOS to Avalon_jtag_slave of jtag_uart
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Step10: Open NIOS processor connection and assign Reset vector memory and
Exceptionvector memory to onchip_memory2 option
Step11: In Platform Designer, go to system tab and select Assign Base Addresses
Step12: Connect clk_in_reset signal to jtag_debug_module reset signal of NIOS
processor
Step13: Save the file with .qsys [.sopcinfo] extension and click generate option
Step14: Go to Quartus II and select the .qip [.sopcinfo] file from the current project
location
Step15: Go to Assignments->Device->Device and Pin Options. In that window, under
configuration select single compressed image with memory initialization option and click
OK.
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Step16: Compile the .qip [.sopcinfo] file and upon successful compilation, goto pin
planner and assign
The clock signal pin number P11 (50 MHz clock pin in MAX10 board)
For reset assign one push button switch B8.
Part II: Eclipse IDE – writing a Hello World Program
Step 1: In Quartus II, Go to Tools and open NIOS II Software Build Tools for Eclipse
Step 2: After opening Eclipse, select the current folder as workspace
Step 3: Right click on the project explorer and open New → NIOS II Application and
BSPfrom template
Step 4: In the Target Hardware information, choose the .sopcinfo file from the current
projectlocation
Step 5: Type the project name
Step 6: Click Next and press finish button
Step 7: Open hello_world.c SMALL file and edit the word to be printed and save it
Step 8: Right click on the project file in Eclipse and choose Build Project
Step 9: Once Build Project is successful, Go to Quartus II project and program the .sof
file
Step10: Right click project and Run as NIOS II hardware
Step11: Output can be seen in NIOS II console
RESULT:
Hello World was displayed by accessing soft core processor (NIOS II) and output was
verified.
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EXP-20 IMPLEMENTATION OF VGA CONTROLLER ON FPGA
DATE:
AIM:
To implement VGA Controller using Quartus prime 18.0 on FPGA board.
APPARATUS REQUIRED
Quartus prime 18.0
ALGORITHM
1. Create a module, declaring input and output variables.
2. Use if,else condition to implement the vga controller
3. End the module.
VERILOG CODE FOR VGA CONTROLLER
module vga14 (
input clk, // 50 MHz clock input
input rst, // Reset signal
output reg hsync, // Horizontal Sync
output reg vsync, // Vertical Sync
output reg [3:0] vga_r, // 4-bit Red
output reg [3:0] vga_g, // 4-bit Green
output reg [3:0] vga_b // 4-bit Blue
);
// VGA 640x480 @ 60 Hz Timing Parameters
localparam H_ACTIVE = 640; // Active Video
localparam H_FRONT = 16; // Front Porch
localparam H_SYNC = 96; // Sync Pulse
localparam H_BACK = 48; // Back Porch
localparam H_TOTAL = 800; // Total Pixels Per Line
localparam V_ACTIVE = 480; // Active Video
localparam V_FRONT = 10; // Front Porch
localparam V_SYNC = 2; // Sync Pulse
localparam V_BACK = 33; // Back Porch
localparam V_TOTAL = 525; // Total Lines Per Frame
reg clk_25MHz;
reg [1:0] clk_div;
// Clock divider to generate 25 MHz clock
always @(posedge clk or posedge rst) begin
if (rst)
clk_div <= 2'b0; // Reset clock divider
else
clk_div <= clk_div + 1; // Increment counter
end
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// Generate 25 MHz clock from 50 MHz input clock
assign clk_25MHz = clk_div[0]; // Divide clock by 2 (50MHz ➝ 25MHz)
reg [9:0] h_count, v_count;
// Generate horizontal and vertical counters
always @(posedge clk_25MHz or posedge rst) begin
if (rst) begin
h_count <= 10'd0;
v_count <= 10'd0;
end else begin
if (h_count == H_TOTAL - 1) begin
h_count <= 10'd0;
if (v_count == V_TOTAL - 1)
v_count <= 10'd0;
else
v_count <= v_count + 1;
end else begin
h_count <= h_count + 1;
end
end
end
// Horizontal sync signal generation
always @(posedge clk_25MHz) begin
hsync <= (h_count >= (H_ACTIVE + H_FRONT)) &&
(h_count < (H_ACTIVE + H_FRONT + H_SYNC));
end
// Vertical sync signal generation
always @(posedge clk_25MHz) begin
vsync <= (v_count >= (V_ACTIVE + V_FRONT)) &&
(v_count < (V_ACTIVE + V_FRONT + V_SYNC));
end
// VGA Color Bar Logic
always @(posedge clk_25MHz or posedge rst) begin
if (rst) begin
vga_r <= 4'b0000;
vga_g <= 4'b0000;
vga_b <= 4'b0000;
end else begin
if ((h_count < H_ACTIVE) && (v_count < V_ACTIVE)) begin
if (v_count < 160) begin
// Red bar
if ((v_count % 2 == 0) || (v_count % 3 == 0))
vga_r <= 4'b1111;
else
vga_r <= 4'b0000;
vga_g <= 4'b0000;
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vga_b <= 4'b0000;
end else if (v_count < 320) begin
// Green bar
if ((v_count % 2 == 0) || (v_count % 3 == 0))
vga_r <= 4'b1111; // Mixed color (red + green)
else
vga_r <= 4'b0000;
vga_g <= 4'b1111;
vga_b <= 4'b0000;
end else if (v_count < 480) begin
// Blue bar
vga_r <= 4'b0000;
vga_g <= 4'b0000;
vga_b <= 4'b1111;
end else begin
// Outside active video → Black screen
vga_r <= 4'b0000;
vga_g <= 4'b0000;
vga_b <= 4'b0000;
end
end else begin
// Outside active video → Black screen
vga_r <= 4'b0000;
vga_g <= 4'b0000;
vga_b <= 4'b0000;
end
end
end
endmodule
RESULT
VGA Controller was implemented on Quartus prime 18.0 on FPGA and output is
verified.
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