PROCEDURE HOW TO DESIGN

SYNCHRONOUS COUNTERS
• Step 1: Based on the description of the problem,
determine the required number n of the FFs- the
smallest value of n is such that the number of states
N < 2n- and the desired counting sequence
• Step 2: Draw the state diagram showing all the
possible states
• Step 3: Write the excitation table that lists the
present state (PS), the next state (NT) and the
required excitation.
• Step 4: Obtain the minimal expressions for the
excitations of the FFs using K-maps.
• Step 5: Implement the minimal expressions to get
the logic circuit.
 Important Points to be remembered
# If the synchronous counter is a shortened-modulus counter it
may suffer from problem of lock-out. That is, the counter may
not self-start.
# A self-starting counter is the one that will eventually enter its
proper sequence of states regardless of its initial stat.
# The counter can be made self-starting by so designing it that it
goes to particular states whenever it enters an invalid state.
# The same procedure can be used for counters of any number
bits and any arbitrary sequence.
# The only restriction on the sequence is that, it can not contain
the same state more than once within one complete cycle
before repeating itself.
 Example #1
‰ Design and implement a synchronous 3-bit up/down counter using
J-K FFs.
‰ Solution
‰ STEP 1:
‰ A 3-bit counter requires three FFs
‰ Mode selector signal is required to select Up/Down mode
. Hence , M=0 for down counter and
M=1 for up counter

‰ The clock signal is applied to all FFs simultaneously.

‰ The J and K inputs of the FFs are expressed in terms of the present
state outputs of the FFs and the control signal.
 STEP 2: State diagram of 3-bit Up/Down Counter

M=1 UP M=0 DOWN

1 1 1

000 001 010 011

0 0 0
1 0 0 1
0 0 0

111 110 101 100

1 1 1
 3-bit Up-Counter
M=1 UP
 3-bit Down-Counter
M=1 DOWN
 3-bit Up/Down-Counter
M=1 UP M=0 DOWN
 How to determine the J-K inputs during the transition
of the output from present state to next state
Transition at Output OPERATION J-K Excitation
PS NS J K
0 0 NC 0 0 0 X
RESET 0 1
0 1 SET 1 0
TOGGLE
1 1 1 X

1 0 RESET 0 1
X 1
TOGGLE 1 1

1 1 NC 0 0
X 0
SET 1 0
How to determine the J-K inputs during the transition of the
output from present state to next state
Transition at Output OPERATION J-K Excitation
PS NS J K
NC
0 0 0 X
RESET

0 1 SET 1 X
TOGGLE

1 0 RESET X 1
TOGGLE

NC
1 1 X 0
SET
 Excitation Tables
Present State Mode Next State Required Excitations
(PS) (NS)
Q3 Q2 Q1 M Q3 Q2 Q1 J3 K3 J2 K2 J1 K1
0 0 0 0 1 1 1 1 X 1 X 1 X
0 0 0 1 0 0 1 0 X 0 X 1 X
0 0 1 0 0 0 0 0 X 0 X X 1
0 0 1 1 0 1 0 0 X 1 X X 1
0 1 0 0 0 0 1 0 X X 1 1 X
0 1 0 1 0 1 1 0 X X 0 1 X
0 1 1 0 0 1 0 0 X X 0 X 1
0 1 1 1 1 0 0 1 X X 1 X 1
1 0 0 0 0 1 1 X 1 1 X 1 X
1 0 0 1 1 0 1 X 0 0 X 1 X
1 0 1 0 1 0 0 X 0 0 X X 1
1 0 1 1 1 1 0 X 0 1 X X 1
1 1 0 0 1 0 1 X 0 X 1 1 X
1 1 0 1 1 1 1 X 0 X 0 1 X
1 1 1 0 1 1 0 X 0 X 0 X 1
1 1 1 1 0 0 0 X 1 X 1 X 1
 K-Mapping

Q1 M Q1 M Q1 M Q1 M Q1 M Q1 M Q1 M Q1 M
Q3 Q2 1 1 X X
Q3 Q2 X X 1 1
Q 3Q 2 1 1 X X X X 1 1
Q 3Q 2
Q 3Q 2 1 1 X X X X 1 1
Q 3Q 2
Q3 Q2 1 1 X X
Q3 Q2 X X 1 1
(a)
(b)
J1 = 1 K1 = 1
 Q1 M Q1 M Q1 M Q1 M Q1 M Q1 M Q1 M Q1 M
Q3 Q2 1 0 1 0 Q3 Q2 X X X X

Q 3Q 2 X X X X 1 0 1 0
Q 3Q 2
Q 3Q 2 X X X X 1 0 1 0
Q 3Q 2
Q3 Q2 1 0 1 0 Q3 Q2 X X X X

(c)
(d)
J 2 = Q1 M + Q1M K 2 = Q1 M + Q1 M
 Q1 M Q1 M Q1 M Q1 M Q1 M Q1 M Q1 M Q1 M
Q3 Q2 1 0 0 0 Q3 Q2 X X X X

Q 3Q 2 0 0 1 0 Q 3Q 2 X X X X

Q 3Q 2 X X X X Q 3Q 2 0 0 1 0

Q3 Q2 X X X X Q3 Q2 1 0 0 0

(e) (f)

J 3 = Q 2 Q1 M + Q 2 Q1 M K 3 = Q 2 Q1 M + Q 2 Q1 M
Implementation

Q 1
Q 2
Q 3
 Examples#2

‰Design a mod-6 counter using J-K FFs with separate logic circuitry for each J
and K input. Construct a state diagram to determine whether the counter is
self-starting or not.
‰ with the following counting states: 0,3,5,2,1,4,0
‰When the counter to invalid states it goes to 0
J1=Q3’ ; K1=Q2’+Q3; J2=Q3’Q1’+Q3Q1; K2=1
J3=Q1; K3=1
 State Diagram

Invalid States

101
111

100 000 110

011 001

010
 Excitation Table

Present State Next State Required Excitations

(PS) (NS)
Q3 Q2 Q1 Q3 Q2 Q1 J3 K3 J2 K2 J1 K1
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 0 0 0 X 1 0 X X 1
1 1 1 0 0 0 X 1 X 1 X 1
1 1 0 1 1 1 X 0 X 0 1 X
 K-Mapping

Present Next Required

Q3 Q3 Q3 Q3 State State Excitations
(PS) (NS)
Q1 Q 2 1 1
Q1 Q 2 X X Q3 Q2 Q1 Q3 Q2 Q1 J K J K J K
3 3 2 2 1 1

0 0 0 0 0 1 0 X 0 X 1 X
Q1Q 2 1 1 Q1Q 2 X X 0 0 1 0 1 0 0 X 1 X X 1

0 1 0 0 1 1 0 X X 0 1 X
Q 1Q 2 X X Q 1Q 2 1 1 0 1 1 1 0 0 1 X X 1 X 1

1 0 0 1 0 1 X 0 0 X 1 X
Q1 Q 2 X X Q1 Q 2 1 1 1 0 1 0 0 0 X 1 0 X X 1

1 1 1 0 0 0 X 1 X 1 X 1
(a)
(a) 1 1 0 1 1 1 X 0 X 0 1 X

J1 = 1 K1 = 1
 Q3 Q3 Q3 Q3
Q1 Q 2 0 0 Q1 Q 2 X X Present Next Required
State State Excitations
Q1Q 2 X X 0 0 (PS) (NS)
Q1Q 2 Q3 Q2 Q1 Q3 Q2 Q1 J K J K J K

Q 1Q 2 X X 3 3 2 2 1 1

Q 1Q 2 1 1 0 0 0 0 0 1 0 X 0 X 1 X

0 0 1 0 1 0 0 X 1 X X 1
Q1 Q 2 1 0 Q1 Q 2 X X 0 1 0 0 1 1 0 X X 0 1 X

0 1 1 1 0 0 1 X X 1 X 1
(c) (d) 1 0 0 1 0 1 X 0 0 X 1 X

1 0 1 0 0 0 X 1 0 X X 1
J 2 = Q1 Q 3 K 2 = Q1 1 1 1 0 0 0 X 1 X 1 X 1

1 1 0 1 1 1 X 0 X 0 1 X
 Present Next Required
Q3 Q3 Q3 State State Excitations
Q3 (PS) (NS)
Q1 Q 2 0 X
Q1 Q 2 X 0 Q3 Q2 Q1 Q3 Q2 Q1 J K J K J K
3 3 2 2 1 1

0 0 0 0 0 1 0 X 0 X 1 X
Q1Q 2 0 X X 0 0 0 1 0 1 0 0 X 1 X X 1
Q1Q 2
0 1 0 0 1 1 0 X X 0 1 X
Q 1Q 2 1 X
Q 1Q 2 X 1 0 1 1 1 0 0 1 X X 1 X 1

1 0 0 1 0 1 X 0 0 X X 1
Q1 Q 2 0 X
Q1 Q 2 X 1 1 0 1 0 0 0 X 1 0 X X 1

1 1 1 0 0 0 X 1 X 1 X 1
(e) 1 1 0 1 1 1 X 0 X 0 1 X
(f)
J 3 = Q 2 Q1 K 3 = Q1
Mod-6 Synchronous Counter

Q 1
Q 2
Q 3
 Table How to check for lock-out

PS Present inputs NS

Q3 Q2 Q1 J3 K3 J2 K2 J1 K1 Q3 Q2 Q1

1 1 0 0 0 0 0 1 1 1 1 1

1 1 1 1 1 0 1 1 1 0 0 0
 Excitation Table

Present State Next State Required Excitations

(PS) (NS)
Q3 Q2 Q1 Q3 Q2 Q1 J3 K3 J2 K2 J1 K1
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1 X 0 0 X X 1
1 0 1 0 0 0 X 1 0 X X 1
1 1 0 1 1 1 0 0 0 0 1 1
1 1 1 0 0 0 1 1 0 1 1 1
Present State (PS) Next State Required Excitations
(NS)

Q3 Q2 Q1 Q3 Q2 Q1 J3 K3 J2 K2 J1 K1

0 0 0 0 1 0 0 X 1 X 0 X

0 1 0 1 0 0 1 X X 1 0 X

1 0 0 0 0 1 X 1 0 X 1 X

0 0 1 0 1 1 0 X 1 X X 0

0 1 1 1 0 1 1 X X 1 X 0

1 0 1 0 0 0 X 1 O X X 1

1 1 1 0 0 0 X 1 X 1 X 1

1 1 0 1 1 1 X 0 X 0 1 X