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AXI SystemVerilog Report

This report details the design and simulation of an AXI protocol-based communication system using SystemVerilog, highlighting advancements over traditional Verilog designs. The project aims to implement an AXI master-slave system with modular verification and ensure protocol compliance. Results indicate successful read and write operations, demonstrating improved modularity and reusability in the SystemVerilog version.

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n15shrinidhilbijapur
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44 views3 pages

AXI SystemVerilog Report

This report details the design and simulation of an AXI protocol-based communication system using SystemVerilog, highlighting advancements over traditional Verilog designs. The project aims to implement an AXI master-slave system with modular verification and ensure protocol compliance. Results indicate successful read and write operations, demonstrating improved modularity and reusability in the SystemVerilog version.

Uploaded by

n15shrinidhilbijapur
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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A Report on

AXI - PROTOCOL (SystemVerilog-based Design)


Submitted by

SHASHWAT DINESH NAIK 1DS22EC206


SHRINIDHI L BHIJAPUR 1DS22EC211
RAHUL K 1DS23EC423
SATISH K GOWDA 1DS22EC199

1. Abstract
This project presents the design and simulation of an AXI (Advanced eXtensible Interface)
protocol-based communication system using SystemVerilog. Unlike the earlier Verilog-
based design, this version leverages SystemVerilog interfaces, modports, and class-based
testbench architecture. ...

2. Introduction
AXI, part of ARM’s AMBA family, is essential in modern SoC designs, offering high-speed
communication with independent read/write channels. SystemVerilog adds advanced
features to hardware description ...

3. Problem Definition
Design an AXI master-slave communication system using SystemVerilog interfaces and
class-based verification ...

4. Objectives
• Implement AXI master and slave using SystemVerilog interfaces
• Modularize verification using classes: driver, monitor, scoreboard
• Ensure protocol compliance with handshake signaling
• Validate data integrity during write and read operations

5. Block Diagram (SystemVerilog Version)


+--------------------+ +---------------------+
| AXI Master | | AXI Slave |
| (axi_master_slave)| | (axi_slave module) |
| Uses axi_if.master |<--axi_if--->| Uses axi_if.slave |
+--------------------+ +---------------------+
^ ^
| |
+---------+ +------------+
| Driver | | Monitor |
+---------+ +------------+
\ /
+---------------+
| Scoreboard |
+---------------+

6. SystemVerilog Code Snippets


### AXI Interface (axi_if.sv)

interface axi_if (input logic clk, input logic reset); ... endinterface

### Master Module (axi_master_slave.sv)

module axi_master_slave (input logic clk, reset, axi_if.master axi); ...


endmodule

### AXI Slave Module (axi_slave.sv)

module axi_slave(axi_if axi); ... endmodule

7. Testbench with Classes (axi_master_slave_tb.sv)


### AXI Driver Class

class axi_driver; virtual axi_if vif; ... endclass

### AXI Monitor Class

class axi_monitor; virtual axi_if vif; ... endclass

### AXI Scoreboard Class

class axi_scoreboard; mailbox mon2scb; ... endclass

8. Results
The SystemVerilog-based AXI master successfully initiates read and write operations ...

[SCOREBOARD] Data Matched: cafebabe


Read data = cafebabe

9. Comparison Table
| Metric | Verilog Version | SystemVerilog Version |
|--------------|----------------------|---------------------------|
| Modularity | Single module | Interface + modports + classes |
| Reusability | Limited | High (interface, classes) |
| Verification | Basic TB | Structured TB (driver, monitor)
|
| Compliance | Basic AXI | Supports burst, handshake,
pipelining |
10. Conclusion
The SystemVerilog version of the AXI protocol design improves upon the earlier Verilog
model by introducing interfaces, modularity, and structured verification ...

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