SYLLABUS

CS3352 DIGITAL PRINCIPLES AND COMPUTER

ORGANIZATION L T PC
3 0 2 4
COURSE OBJECTIVES:
• To analyze and design combinational circuits.
• To analyze and design sequential circuits
• To understand the basic structure and operation of a digital computer.
• To study the design of data path unit, control unit for processor and to familiarize
with thehazards.
• To understand the concept of various memories and I/O interfacing.

UNIT I COMBINATIONAL LOGIC 9

Combinational Circuits – Karnaugh Map - Analysis and Design Procedures – Binary
Adder – Subtractor – Decimal Adder - Magnitude Comparator – Decoder – Encoder –
Multiplexers – Demultiplexers.

UNIT II SYNCHRONOUS SEQUENTIAL LOGIC 9

Introduction to Sequential Circuits – Flip-Flops – operation and excitation tables,
Triggering of FF, Analysis and design of clocked sequential circuits – Design –
Moore/Mealy models, state minimization, state assignment, circuit implementation -
Registers – Counters.

UNIT III COMPUTER FUNDAMENTALS 9

Functional Units of a Digital Computer: Von Neumann Architecture – Operation and
Operands of Computer Hardware Instruction – Instruction Set Architecture (ISA):
Memory Location, Address and Operation – Instruction and Instruction Sequencing –
Addressing Modes, Encoding of Machine Instruction – Interaction between
Assembly and High Level Language.
UNIT IV PROCESSOR 9
Instruction Execution – Building a Data Path – Designing a Control Unit –
Hardwired Control, Microprogrammed Control – Pipelining – Data Hazard –
Control Hazards.

UNIT V MEMORY AND I/O 9

Memory Concepts and Hierarchy – Memory Management – Cache Memories:
Mapping andReplacement Techniques – Virtual Memory – DMA – I/O – Accessing
I/O: Parallel and Serial Interface – Interrupt I/O – Interconnection Standards: USB,
SATA
45 PERIODS
PRACTICAL EXERCISES: 30 PERIODS
1. Verification of Boolean theorems using logic gates.
2. Design and implementation of combinational circuits using gates for arbitrary
functions.
3. Implementation of 4-bit binary adder/subtractor circuits.
4. Implementation of code converters.
5. Implementation of BCD adder, encoder and decoder circuits
6. Implementation of functions using Multiplexers.
7. Implementation of the synchronous counters
8. Implementation of a Universal Shift register.
9. Simulator based study of Computer Architecture

COURSE OUTCOMES:
At the end of this course, the students will be able to:
CO1 : Design various combinational digital circuits using logic gates
CO2 : Design sequential circuits and analyze the design procedures
CO3 : State the fundamentals of computer systems and analyze the execution of an
instruction
CO4 : Analyze different types of control design and identify hazards
CO5 : Identify the characteristics of various memory systems and I/O communication
TOTAL: 75 PERIODS
TEXT BOOKS:
1. M. Morris Mano, Michael D. Ciletti, “Digital Design : With an Introduction to the
Verilog HDL, VHDL, and System Verilog”, Sixth Edition, Pearson Education,
2018.
2. David A. Patterson, John L. Hennessy, “Computer Organization and Design, The
Hardware/Software Interface”, Sixth Edition, Morgan Kaufmann/Elsevier, 2020.

REFERENCES:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Naraig Manjikian, “Computer
Organization andEmbedded Systems”, Sixth Edition, Tata McGraw-Hill, 2012.
2. William Stallings, “Computer Organization and Architecture – Designing for
Performance”, TenthEdition, Pearson Education, 2016.
3. M. Morris Mano, “Digital Logic and Computer Design”, Pearson Education, 2016.
 CONTENTS
UNIT-I
COMBINATIONAL LOGIC
1.1 Introduction 1.1
1.2 Analogue Versus Digital 1.2
1.3 Combinational Circuits 1.4
1.4 Implementing Combinational Logic 1.4
1.5 Simplification Techniques 1.5
1.6 Sum-of-Products 1.6
1.7 Products -Of-Sum 1.7
1.8 Karnaugh Map 1.9
1.9 Don’t Care Combinations 1.19
1.10 Analysis and Design Procedures 1.21
1.11 Binary Adder 1.22
1.11.1 Half Adder 1.23
1.11.2 Full-Adder 1.24
1.11.3 Parallel Binary Adder 1.26
1.11.4 Half Subtractor 1.28
1.11.5 Full- Subtractor 1.30
1.12 BCD Adder 1.32
1.13 Magnitude Comparator 1.35
1.13.1 Single-Bit Magnitude Comparator 1.36
1.13.2 4-Bit Magnitude Comparator 1.36
1.14 Multiplexers (Data Selectors) 1.39
1.14.1 Basic Four-Input Multiplexer 1.40
1.14.2 Implementation of Boolean Expression Using Multiplexers 1.43
1.14.3 Applications of Multiplexers 1.44
1.15 Demultiplexers (Data Distributors) 1.45
1.15.1 1 To 4 Demultiplexer 1.45
1.16 Decoders 1.46
1.16.1 Basic Binary Decoder 1.47
1.16.2 3-To-8 Decoder 1.47
 1.16.3 BCD-To-Seven-Segment Decoder/Driver 1.50
1.16.3.1 Design of BCD-To-Seven –Segment Decoder 1.50
1.16.3.2 Applications of Decoders 1.55
1.17 Encoders 1.56
1.17.1 Octal-To-Binary Encoder 1.56
1.17.2 Decimal-To-BCD Encoder 1.57

UNIT-II
SYNCHRONOUS SEQUENTIAL LOGIC
2.1 Introduction 2.1
2.2 Latches and Flip-Flops 2.4
2.2.1 S-R Latch 2.5
2.2.2 Flip-Flops 2.7
2.2.2.1 sr Flip-Flop - (Set / Reset) 2.8
2.2.2.2 D Flip-Flop - (Delay) 2.13
2.2.2.3 J-K Flip-Flop 2.15
2.2.2.4 Master-Slave J-K Flip-Flop 2.18
2.2.2.5 T Flip- Flop 2.19
2.3 Triggering of Flip – Flops 2.22
2.3.1 Level Triggering in Flip - Flops 2.22
2.3.2 Edge Triggering in Flip – Flops 2.23
2.4 Realisation of One Flip-Flop Using Other Flip- Flops 2.23
2.4.1 Realization of Delay Flip-Flop Using S-R Flip – Flop 2.24
2.5 Counters 2.26
2.5.1 Synchronous Counters 2.26
2.5.1.1 Binary 4-Bit Synchronous Up Counter 2.27
2.5.1.2 Binary 4-Bit Synchronous Down Counter 2.28
2.5.1.3 Ripple (Asynchronous) Counter 2.29
2.5.1.4 Binary Ripple Counter 2.31
2.5.1.5 Up/Down Counters 2.32
2.5.1.6 Modulus of a Counter 2.34
2.6 Designing Counters with Arbitrary Sequences 2.35
2.6.1 Excitation Table of a Flip-Flop 2.36
 2.6.2 State Transition Diagram 2.36
2.6.3 Design Procedure 2.37
2.7 Shift Register 2.41
2.7.1 Serial-In Serial-Out Shift Register 2.41
2.7.2 Serial-In Parallel-Out Shift Register 2.42
2.7.3 Parallel-In Serial-Out Shift Register 2.43
2.7.4 Parallel-In Parallel-Out Shift Register 2.43
2.8 Shift Register Counters 2.44
2.8.1 Ring Counter 2.44
2.8.2 Shift Counter 2.45
2.9 Asynchronous Sequential Circuits 2.47
2.9.1 Clocked Sequential Circuits 2.48
2.9.1.1 Moore Model 2.48
2.9.1.2 Mealy Model 2.49

UNIT- III
COMPUTER FUNDAMENTALS
3.1 Functional Units of a Digital Computer: Von Neumann Architecture 3.2
3.2 Operation and Operands of Computer Hardware Instruction 3.5
3.2.1 Basic Operational Concepts 3.5
3.2.2 Basic Operands Concepts 3.7
3.3 Instruction Set Architecture (Isa): Memory Location, Address and 3.9
Operation
3.3.1 Memory Locations and Addresses 3.10
3.4 Instruction and Instruction Sequencing 3.13
3.5 Addressing Modes 3.16
3.6 Encoding of Machine Instruction 3.25
3.7 Interaction Between Assembly and High Level Language 3.29

UNIT-IV
PROCESSOR
4.1 Instruction Execution 4.1
4.1.1 Mipsarchitecture 4.2
4.2 Building a Data Path 4.6
4.3 Designing a Control Unit 4.11
4.3.1 Hardwired Control 4.11
4.3.2 Micro-Programmed Control 4.13
4.4 Pipelining 4.13
4.5 Data Hazards 4.21
4.6 Control Hazards 4.25

UNIT - V
MEMORY AND I/O
5.1 Memory Concepts and Hierarchy 5.1
5.1.2 Memory Hierarchy 5.3
5.2 Memory Management 5.7
5.3 Cache Memories 5.10
5.4 Mapping and Replacement Techniques 5.16
5.5 Virtual Memory 5.20
5.6 DMA 5.23
5.7 I/O 5.25
5.8 Accessing I/O 5.26
5.9 Parallel and Serial Interface 5.27
5.9.1 Serial Interface 5.28
5.9.2 Parallel Interface 5.30
5.9.3 Difference Between Serial and Parallel Communication 5.31
5.9.4 Advantages of Serial Communication Over Parallel 5.33
Communication
5.10 Interrupt I/O 5.33
5.10.1 Interrupt Hardware 5.34
5.10.2 Handling Multiple Devices 5.34
5.10.3 Vectored Interrupts 5.35
5.10.4 Interrupt Nesting 5.35
5.10.5 Exceptions 5.35
5.11 Interconnection Standards: USB, SATA 5.36
5.11.1 USB 5.36
5.11.2 SATA 5.39
 1
COMBINATIONAL LOGIC

1.1 INTRODUCTION
❖ Digital electronics is the branch of electronics that deals with the study of digital
signals, and the components that use or create them.
❖ Digital electronics or the digital circuit comprises various components that
perform specific functions.
❖ These components are divided into two categories:
Active components
Passive components
❖ The active components are the transistors and diodes while the passive
components are the capacitors, resistors, inductors, etc.
➢ Logic Gates
❖ Logic gates are the basic components of the digital circuit with one output and
more than one input.
❖ AND, OR and NOT gates are the basic gates while NAND and NOR the universal
gates.
❖ EX-OR and EX-NOR are the special gates.
➢ Advantages of Digital System vs Analog System
❖ The transmission of data in digital systems takes place without degradation due to
noise when compared to an analog system.
1.2 Combinational Logic

❖ The digital system comes with noise-immunity, which makes the storage of data
easier.
❖ Whereas the analog system undergoes wear and tear, which degrades the
information in storage.
❖ The digital system comes with an interface with computers which makes it easy
to control the data.
❖ The system can be kept bug free by updating the software. This feature is not
available in the analog system.
➢ Disadvantages of Digital System
Though the digital system has noise-immunity and better storage it does have
disadvantages too:
❖ The energy consumed by the digital system is more compared to the analog
system. This energy is consumed in calculations and signal processing which
results in the generation of heat.
❖ These systems are expensive.
❖ The digital systems are fragile, that is if one of the digital data is misinterpreted,
the final data will change completely.
❖ Taking care of analog issues in digital systems could be demanding as analog
components are used in designing the digital system.
➢ Applications of Digital Circuits
Digital electronics or digital circuits are an integral part of electronic devices and
here are the uses of digital circuits:
❖ The display of digital watches is designed based on digital circuits.
❖ Rocket science and quantum computing use digital electronics.
❖ The automatic doors work on the principle of digital electronics.
❖ Everyday encounters with traffic lights are based on digital circuits.

1.2 ANALOGUE VERSUS DIGITAL

❖ There are two basic ways of representing the numerical values of the various
physical quantities with which we constantly deal in our day-to-day lives.
❖ One of the ways, referred to as analogue, is to express the numerical value of the
quantity as a continuous range of values between the two expected extreme values.
 Digital Principles and System Design 1.3

❖ For example, the temperature of an oven settable anywhere from 0 to 100 °C may
be measured to be 65 °C or 64.96 °C or 64.958 °C or even 64.9579 °C and so on,
depending upon the accuracy of the measuring instrument.
❖ Similarly, voltage across a certain component in an electronic circuit may be
measured as 6.5 V or 6.49 V or 6.487 V or 6.4869 V.
❖ The underlying concept in this mode of representation is that variation in the
numerical value of the quantity is continuous and could have any of the infinite
theoretically possible values between the two extremes.
❖ The other possible way, referred to as digital, represents the numerical value of
the quantity in steps of discrete values. The numerical values are mostly
represented using binary numbers.
❖ For example, the temperature of the oven may be represented in steps of 1 °C as
64 °C, 65 °C, 66°C and so on. To summarize, while an analogue representation
gives a continuous output, a digital representation produces a discrete output.
❖ Analogue systems contain devices that process or work on various physical
quantities represented in analogue form.
❖ Digital systems contain devices that process the physical quantities represented in
digital form.
❖ Digital techniques and systems have the advantages of being relatively much
easier to design and having higher accuracy, programmability, and noise
immunity, easier storage of data and ease of fabrication in integrated circuit form,
leading to availability of more complex functions in a smaller size.
❖ There all world, however, is analogue. Most physical quantities – position,
velocity, acceleration, force, pressure, temperature and flow rate, for example –
are analogue in nature.
❖ That is why analogue variables representing these quantities need to be digitized
or discretized at the input if we want to benefit from the features and facilities that
come with the use of digital techniques.
❖ In a typical system dealing with analogue inputs and outputs, analogue variables
are digitized at the input with the help of an analogue-to-digital converter block
and reconverted back to analogue form at the output using a digital-to-analogue
converter block.
1.4 Combinational Logic

1.3 COMBINATIONAL CIRCUITS

❖ A combinational circuit is one where the output depends only on the present
combination of inputs at that point of time with total disregard to the past state of
the inputs.
❖ The logic gate is the most basic building block of combinational logic. Figure
shows the block schematic representation of a generalized combinational circuit
having n input variables and m output variables. Since the number of input
variables is n, there are 2n possible combinations of bits at the input.

Fig 1.1 Generalized combinational circuit.

1.4 IMPLEMENTING COMBINATIONAL LOGIC

❖ The different steps involved in the design of a combinational logic circuit are as
follows:
• Statement of the problem.
• Identification of input and output variables.
• Expressing the relationship between the input and output variables.
• Construction of a truth table to meet input–output requirements.
• Writing Boolean expressions for various output variables in terms of input
variables.
• Minimization of Boolean expressions.
• Implementation of minimized Boolean expressions.
❖ There are various simplification techniques available for minimizing Boolean
expressions. These include the use of theorems and identities, Karnaugh mapping,
the Quinne–McCluskey tabulation method and so on. Also, there are various
possible minimized forms of Boolean expressions.
❖ The following guidelines should be followed while choosing the preferred form
 Digital Principles and System Design 1.5

for hardware implementation:

❖ The implementation should have the minimum number of gates, with the gates
used having the minimum number of inputs.
❖ There should be a minimum number of interconnections, and the propagation time
should be the shortest.
❖ Limitation on the driving capability of the gates should not be ignored.
❖ It is difficult to generalize as to what constitutes an acceptable simplified Boolean
expression. The importance of each of the above-mentioned aspects is governed
by the nature of application.

1.5 SIMPLIFICATION TECHNIQUES

❖ The primary objective of all simplification procedures is to obtain an expression
that has the minimum number of terms.
❖ Obtaining an expression with the minimum number of literals is usually the
secondary objective.
❖ If there is more than one possible solution with the same number of terms, the one
having the minimum number of literals is the choice.
❖ The techniques to be discussed include the Karnaugh map method. Before we
move on to discuss these techniques in detail, it would be relevant briefly to
describe
o Sum-of-Products (SOP) and
o Product-of-Sums (POS)
❖ The given Boolean expression will be in either of the two forms, and the objective
will be to find a minimized expression in the same or the other form.
❖ Product term
✓ The AND function is referred to as a product. The variable in a product term
can appear either in complemented or uncomplemented form. For example
𝐴𝐵̅ 𝐶
❖ Sum term
✓ An OR function is generally used to refer a sum. The logical sum of several
variables on which a function depends is considered to be a Sum term.
Variables in a sum term can appear either in complemented or
1.6 Combinational Logic

uncomplemented form. For example 𝐴 + 𝐵̅ + 𝐶

❖ Sum Of Products (SOP)
✓ The logical sum of two or more logical product terms is called a Sum of
Products expression. It is basically an OR operation of AND operated
variables such as
(i) 𝑌 = 𝐴𝐵 + 𝐵𝐶 + 𝐴𝐶
(ii) 𝑌 = 𝐴𝐵 + 𝐵̅ 𝐶 + 𝐴̅𝐶
❖ Product Of Sums (POS)
✓ A product of sums expression is a logical product of two or more logical sum
terms. It is basically an AND operation of OR operated variables such as
(i) 𝑌 = (𝐴 + 𝐵)(𝐵 + 𝐶)(𝐴 + 𝐶̅ )
(ii) 𝑌 = (𝐴 + 𝐵̅ + 𝐶)(𝐴 + 𝐶)

1.6 SUM-OF-PRODUCTS
❖ A sum-of-products expression contains the sum of different terms, with each term
being either a single literal or a product of more than one literal.
❖ It can be obtained from the truth table directly by considering those input
combinations that produce a logic ‘1‘at the output.
❖ Each such input combination produces a term. Different terms are given by the
product of the corresponding literals.
❖ The sum of all terms gives the expression. For example, the truth table in Table
can be represented by the Boolean expression
𝑌 = 𝐴̅. ̅
𝐵 . 𝐶̅ + 𝐴̅. 𝐵. 𝐶 + 𝐴. 𝐵. ̅𝐶 + 𝐴. ̅
𝐵. 𝐶
❖ A Product term containing all the K variables of the function in either
complemented or uncomplemented form is called a Minterm in other words a
sum-of-products expression is also known as a minterm expression. The Minterms
of a 3-variable function can be represented by m0, m1, m2, m3, m4, m5, m6 and m7
❖ Table truth table of Boolean expression of equation
A B C Y Minterm
0 0 0 1 𝐴̅𝐵̅ 𝐶̅
0 0 1 0 𝐴̅𝐵̅ 𝐶
 Digital Principles and System Design 1.7

0 1 0 0 𝐴̅𝐵 𝐶̅
0 1 1 1 𝐴̅𝐵𝐶
1 0 0 0 𝐴𝐵̅ 𝐶̅
1 0 1 1 𝐴𝐵̅ 𝐶
1 1 0 1 𝐴𝐵𝐶̅
1 1 1 0 𝐴𝐵𝐶

Canonical Sum of product expression

Using the following procedure, the canonical sum of product form of a logic
function can be obtained.
1. Examine each term in the given logic function
2. Check for the variable that are missing in each product
3. Multiply the product using (𝑋 + ̅̅̅
𝑋), for each variable X that is missing
4. Multiply and omit the redundant terms
Example 1.1 Obtain the canonical sum of product form of the function
Y (A, B) = A+ B
Solution:
A + B = A.1 + B.1
= 𝐴(𝐵 + 𝐵̅ ) + 𝐵. (𝐴 + 𝐴̅)
= 𝐴𝐵 + 𝐴𝐵̅ + 𝐵𝐴 + 𝐵𝐴̅
̅ +𝑨
Y (A, B) = 𝑨𝑩 + 𝑨𝑩 ̅𝑩

1.7 PRODUCTS -OF-SUM

❖ A products -of- sum expression contains the product of different terms, with each
term being either a single literal or a product of more than one literal.
❖ It can be obtained from the truth table directly by considering those input
combinations that produce a logic ‘0‘at the output.
❖ Each such input combination gives the expression. Different terms are obtained
by taking the sum of the corresponding literals.
❖ Here, ‘0’ and ‘1’ respectively the uncomplemented and Complemented.
❖ This can be implemented by using OR operation.
1.8 Combinational Logic

❖ The product of all terms gives the expression. For example, the truth table in Table
can be represented by the Boolean expression
𝑌 = ( ̅𝐴 + ̅
𝐵 + 𝐶̅ )(𝐴̅ + 𝐵 + 𝐶)(𝐴 + 𝐵 + ̅𝐶 ) (𝐴 + ̅
𝐵 + 𝐶)
❖ A sum term containing all the K variables of the function in either complemented
or uncomplemented form is called a Maxterm in other words a product of sum
expression is also known as a maxterm expression. The Maxterms of a 3-variable
function can be represented by M0, M1, M 2, M 3, M 4, M 5, M 6 and M 7
❖ Table truth table of Boolean expression of equation
A B C Y Maxterm
0 0 0 1 𝐴+𝐵+𝐶
0 0 1 0 𝐴 + 𝐵 + 𝐶̅
0 1 0 0 𝐴 + 𝐵̅ + 𝐶
0 1 1 1 𝐴 + 𝐵̅ + 𝐶̅
1 0 0 0 𝐴̅ + 𝐵 + 𝐶
1 0 1 1 𝐴̅ + 𝐵 + 𝐶̅
1 1 0 1 𝐴̅ + 𝐵̅ + 𝐶
1 1 1 0 𝐴̅ + 𝐵̅ + 𝐶̅

Canonical product of sum expression

Using the following procedure, the canonical product of sum form of a logic
function can be obtained.
1. Examine each term in the given logic function
2. Check for the variable that are missing in each sum
3. Add the sum using (𝑋𝑋)̅̅̅, for each variable X that is missing
4. Expand the expression using distributive property and omit the redundant terms
Example 1.2 Obtain the canonical product of sum form of the function
Solution:
Y (ABC) = (𝐴 + 𝐵̅ )(𝐵 + 𝐶)(𝐴 + 𝐶̅ )
= (𝐴 + 𝐵̅ + 0)(𝐵 + 𝐶 + 0)(𝐴 + 𝐶̅ + 0)
= (𝐴 + 𝐵̅ + 𝐶𝐶̅ )(𝐵 + 𝐶 + 𝐴𝐴̅)(𝐴 + 𝐶̅ + 𝐵𝐵̅ )
 Digital Principles and System Design 1.9

Using the distributive property, each sum term can be explained as

Y = (𝐴 + 𝐵̅ + 𝐶) (𝐴 + 𝐵̅ + 𝐶̅ ) (𝐵 + 𝐶 + 𝐴)(𝐵 + 𝐶 + 𝐴̅) (𝐴 + 𝐶̅ + 𝐵)(𝐴 + 𝐶̅ + 𝐵̅ )
Y = (𝐴 + 𝐵̅ + 𝐶) (𝐴 + 𝐵̅ + 𝐶̅ ) (𝐴 + 𝐵 + 𝐶)(𝐴̅ + 𝐵 + 𝐶) (𝐴 + 𝐵 + 𝐶̅ )
This is called the maxterm canonical form

1.8 KARNAUGH MAP

❖ A Karnaugh map is graphical representation of the logic systems.
❖ It can be drawn directly from either minterm (Sum-of-products) or max term
(product- of -sums)
❖ Using the map method to optimize Boolean functions is practical only for
functions of two, three, or four variables. With care, you can use it for functions
of five or six variables, but the map method is cumbersome to use at that point.
❖ The Karnaugh map provides a simple and straight-forward method of minimizing
Boolean expressions.
❖ With the Karnaugh map Boolean expressions having up to four and even six
variables can be simplified.
❖ Diagram below illustrates the correspondence between the Karnaugh map and the
truth table for the general case of a two variable problem.

A B F 0 1
A
0 0 a B
0 1 b 0 a b
1 0 C 1 c d
1 1 d
Fig 1.2 K-Map
❖ In an n-variable K-map, there are 2n cells. Each cell corresponds to one
combination of n variables.
❖ The variables have been marked as A, B, C, D and the binary numbers formed by
them are taken as AB, ABC and ABCD for 2, 3 and 4 variables respectively.
1.10 Combinational Logic

A 0 1 AB 00 01 11 10
B C
0 0 2 0 0 2 6 4

1 1 3 1 1 3 7 5

(a) 2- variables (b) 3 – variables

AB 00 01 11 10
CD
00 0 4 12 8

01 1 5 13 9

11 3 7 15 11

10 2 6 14 10

(c) 4 – variables
Fig 1.3 Karnaugh maps
❖ The 3 and 4 variable K-maps shows that the column and row headings, used in
representing the cells, are cyclic or unit distance code which results in adjacent
cells, differing in just one variable.
❖ The left and right most cells of the 3 variable K-map are adjacent, for example the
cells 0 and 4 are adjacent, and the cells 1 and 5 are adjacent.
Example 1.3:
Consider the following map. The function plotted is: Z = f (A,B) = A + AB
Solution:
 Digital Principles and System Design 1.11

Example 1.4:
Consider the expression Z = f(A,B) = + A + B plotted on the K- map
Solution:

❖ The Karnaugh map uses the following rules for the simplification of
expressions by grouping together adjacent cells containing ones
❖ Groups may not include any cell containing a zero
A A
0 1 0 1
B B
0 0
0

1 1 1 1 1

❖ Groups may be horizontal or vertical, but not diagonal.

❖ Groups must contain 1, 2, 4, 8, or in general 2n cells. That is if n = 1, a

group will contain two 1's since 21 = 2.
❖ If n=2, a group will contain four 1's since 22 = 4.
1.12 Combinational Logic

❖ Each group should be as large as possible

❖ Groups may wrap around the table. The leftmost cell in a row may be grouped with
the rightmost cell and the top cell in a column may be grouped with the bottom
cell.

❖ There should be as few groups as possible, as long as this does not contradict any
of the previous rules.
 Digital Principles and System Design 1.13

Example 1.5: Plot the logical expression 𝑨𝑩𝑪𝑫 + 𝑨𝑩 ̅𝑪

̅𝑫̅ + 𝑨𝑩
̅ 𝑪 + 𝑨𝑩 on a 4 – variable
K-map; obtain the simplified expression from the map.
Solution:
To enter into a K-map, a logic expression must be either in the canonical SOP
from or in the canonical POS form.
The canonical SOP form of the given expression can be obtained as follows:
Y= ABCD=A𝐵̅ 𝐶̅ 𝐷
̅ +A𝐵̅C=AB

= ABCD+A𝐵̅ 𝐶̅ 𝐷
̅ +A𝐵̅C (D=𝐷
̅ ) + AB(C+𝐶̅ ) (D+𝐷
̅)

= ABCD+ A𝐵̅ 𝐶̅ 𝐷
̅ +A𝐵̅ 𝐶𝐷+A𝐵̅ 𝐶𝐷
̅ + (ABC+AB𝐶̅ ) (D+𝐷
̅)

= ABCD+ A𝐵̅ 𝐶̅ 𝐷
̅ +A𝐵̅ 𝐶𝐷+A𝐵̅ 𝐶𝐷
̅ +ABCD+ABC𝐷
̅ +AB𝐶̅ D+AB𝐶̅ 𝐷
̅

= ABCD+ A𝐵̅ 𝐶̅ 𝐷
̅ +A𝐵̅ 𝐶𝐷+A𝐵̅ 𝐶𝐷
̅ + ABC𝐷
̅ + AB𝐶̅ D+AB𝐶̅ 𝐷
̅

= 𝑚15+ 𝑚8+ 𝑚11+ 𝑚10 + 𝑚14 + 𝑚13+ 𝑚12

= ∑ (8,10,11,12,13,14,15)
𝑚

The K-map for the above expression is shown in Fig.1.4.

1.14 Combinational Logic

AB 00 01 11 10
CD
00 0 0 1 1

01 0 0 1 0

11 0 0 1 1

10 0 0 1 1

Fig. 1.4
In the K-map in Fig.1.4, there are three quads; the minimized terms for them are
AB, AC and 𝐴𝐷 ̅ and the simplified expression is;
̅
Y= AB+AC+A𝐷
Example 1.6: Simplify the expression Y=∑𝒎(𝟑, 𝟒, 𝟓, 𝟕, 𝟗, 𝟏𝟑, 𝟏𝟒, 𝟏𝟓), using the K-map
method.
Solution:
The K-map foe above function is shown in Fig. 1.5.
AB 00 01 11 10
CD

00 0 1 0 0

01 0 1 1 1

11 1 1 1 0

10 0 0 1 0

Fig. 1.5
In the above K-map, the cells5, 7, 13 and 15 can be grouped to form a quad as
indicated by the dotted lines, In order to group the remaining 1s, four pairs have to be
formed as shown in Fig.1.5.
 Digital Principles and System Design 1.15

However, all the four 1s covered by the quad are also covered by the pairs. So,
the quad in the above K-map is redundant. Therefore, the simplified expression will be,
Y= 𝐴̅CD+ABC+A𝐶̅ D+𝐴̅𝐵 𝐶̅
Example 1.7 Simply the expression Y=∑𝑚(7,9,10,11,12,13,14,15), using the K – map
method.
Solution:
The K – map for the above function is shown in Fig.1.6.
AB 00 01 11 10
CD
00 1
0 0 0

01 1
0 0 1

11
0 1 1 1

10
0 0 1 1

Fig. 1.6
In the given K-map, there are three quads and one pair, the corresponding
simplified terms are AB, AD, AC and BCD. Now, the simplified expression is
Y=AB+AD+AC+BCD
Since the quads and pair formed in the above K –map overlap, the expression can
be further simplified using the Boolean algebra as follows:
Y = AB+AD+AC+BCD
= A (B+D+C) + BCD

Example 1.8 Simplify the expression Y=𝑚1 + 𝑚5 + 𝑚10 + 𝑚11 + 𝑚12 + 𝑚13 + 𝑚15
using the K-map method.
Solution:
The K- map for the above expression is shown in fig.1.7.
1.16 Combinational Logic

AB 00 01 11 10
CD
00 0 0 1 0

01 1 1 1 0

11 0 0 1 1

10 0 0 0 1
Fig.1.7
As shown in fig.1.7, the K- map contains four pairs but no quads or octets; the
corresponding simplified expression is given by
Y = 𝐴̅𝐶̅ 𝐷 + 𝐴𝐵𝐶̅ + 𝐴𝐵𝐷 + 𝐴𝐵̅ 𝐶 (1)
It is important to note that the simplified expression obtained from the K-map is
not unique. This can be explained by grouping the pairs in a different manner as shown
in fig.1.8.
From the K-map shown in fig.1.8, the simplified expression can be written as,
Y = 𝐴̅𝐶̅ 𝐷 + 𝐴𝐵𝐶̅ + 𝐴𝐶𝐷 + 𝐴𝐵̅ 𝐶 (2)
In equation (1) and (2), the third term is different due to the different groupings done
in fig.1.8.
Though the simplified expression for any given function is not unique, both the
above expression are logically equivalent.
Two expressions are said to be logically equivalent if and only if both the
expression have the same value for every combination of input variables.
AB 00 01 11 10
CD
00 0 0 1 0
01 1 1 1 0

11 0 0 1 1
10 0 0 0 1

Fig.1.8
 Digital Principles and System Design 1.17

Example 1.9 Simplify the expression Y =∏(0,1,4,5,6,8,9,12,13,14), using the K-map

method.
Solution:
The given function is the POS form. This can also be written as
̅ )(𝐴 + 𝐵̅ + 𝐶 + 𝐷)
Y = (𝐴 + 𝐵 + 𝐶 + 𝐷)(𝐴 + 𝐵 + 𝐶 + 𝐷
(A+ ̅
𝐵 + 𝐶̅ + 𝐷)(A+𝐵̅ + 𝐶̅ + 𝐷) ( 𝐴̅ + 𝐵 + 𝐶 + 𝐷)
( 𝐴̅+B+C+𝐷
̅ )( 𝐴̅+𝐵̅+C+D)( 𝐴̅+𝐵̅+C+𝐷
̅ )( 𝐴̅ + 𝐵̅+𝐶̅ + 𝐷)
To simplify a POS expression, for each maxterm in the expression, a 0 has to be
entered in the corresponding cells and groups must be formed with 0 cells instead of 1
cells to get the minimal expression.
The simplified term corresponding to each group can be obtained by the OR
operation of the variables that are same for all cells of that group.
Here, a variable corresponding to 0 has to be represented in an uncomplemented
form and that corresponding to 1in the complemented form.
The K-map for the function is shown in Fig. 1.9

AB 00 01 11 10
CD
00 0 0 0 0

01 0 0 0 0

11 1 1
1 1

10 1 0 0 1

Fig. 1.9
In the above K-map, one octet and one quad are produced by combining 0 cells.
The simplified sum term corresponding to the octet is C where as for the quad is
(𝐵̅+D).
Hence, the simplified POS expression for the given function is
Y= C (𝐵̅+D)
1.18 Combinational Logic

Example 1.10 Obtain (a) minimal sum of product and (b) minimal product of sum
expressions for the function given below:
F (A, B, C, D) = ∑𝒎(𝟎, 𝟏, 𝟐, 𝟓, 𝟖, 𝟗, 𝟏𝟎)
Solution:
Cells with 1 are grouped to obtain the minimal sum of products; cells with 0 are
grouped to obtain minimal product of sum as shown in fig. 1.10.

AB 00 01 11
CD
00 1 0 0 1

01 1 1 0 1

11 0 0 0 0

10 1 0 0 1

̅+𝑩
Fig. 1.10 (a) Y = (𝑨 ̅ )(𝑪
̅+𝑫
̅ )(𝑩
̅+𝑫
̅)

AB 00 01 11 10
CD

00 1 0 0 1

01 1 1 0 1

11 0 0 0 0

10 1 0 0 1

̅𝑫
Fig. 1.10 (b) Y = 𝑩 ̅ +𝑨
̅𝑪̅ 𝑫 + 𝑨𝑩
̅𝑪̅
 Digital Principles and System Design 1.19

a) To obtain minimal product of sum: Three quads can be formed as shown in Fig.
1.10 (a) with the corresponding sum terms (𝐴̅ + ̅𝐵)
̅̅̅, (𝐶̅ + 𝐷
̅ )𝑎𝑛𝑑 (𝐵̅ + 𝐷). Thus
the minimal product of sum expression for the given function is:
Y = (𝐴̅ + 𝐵̅ )(𝐶̅ + 𝐷
̅ )(𝐵̅ + 𝐷
̅)
b) To obtain minimal sum of products. A quad with four corner 1s and two pairs can
be formed as shown in Fig.1.10.(b) Hence, the minimal SOP expression is:
Y = 𝐵̅ 𝐷
̅ + 𝐴̅𝐶̅ 𝐷 + 𝐴𝐵̅ 𝐶̅

1.9 DON’T CARE COMBINATIONS

❖ In certain digital systems, some input combinations never occur during the process
of a normal operation because those input conditions are guaranteed never to
occur. Such input combinations are don’t care combinations.
❖ We don’t care what the function output is for such combinations. These
combinations can be plotted on a map to provide further simplification of the
function.
❖ The functions considered so far in the various examples, for simplification using
the K-map method, are completely specified, i.e, it assumes the value 1 for some
input combinations and the value 0 for others.
❖ Also, there are functions which as assume the value 1 for some combinations, the
value 0 for some other, and either 0 or 1 for the remaining combinations. Such
functions are called incompletely specified functions, and the combinations for
which the value of the function is not specified are called don’t care combination.
❖ The don’t care combinations are represented by d or x or∅.
Example 1.11 Simplify the Boolean function F (A, B, C, D) = ∑𝒎(𝟏, 𝟑, 𝟕, 𝟏𝟏, 𝟏𝟓) +
∑𝒅(𝟎, 𝟐, 𝟓)
Solution:
The K-map for the given function is shown in fig 1.11 with entries d in cells
corresponding to combination 0, 2 and 5.
The 1s and d s are combined in order to enclose the maximum number of adjacent
cells with 1.
As shown in the K- map in Fig 1.11, by combining the 1s and d s, two equal’s
quads can be obtained.
1.20 Combinational Logic

The d in cell 5 is left free since it does not combining the 1s and d s, two equals
can be obtained.
The d in cell 5 is left free since it does not contribute in increasing the size of any
group. Now, the simplified expression in SOP form is
Y = 𝐴̅𝐵̅ +CD
AB 00 01 11 10
CD

00 d 0 0 0

1
01 d 0 0

11 1 1 1 1

10 d 0 0 0

Fig .1.11
Example 1.12 Obtain the minimal SOP expression for the function
Y=∑𝒎(𝟏, 𝟓, 𝟕, 𝟏𝟑, 𝟏𝟒, 𝟏𝟓, 𝟏𝟕, 𝟏𝟖, 𝟐𝟏, 𝟐𝟐, 𝟐𝟓, 𝟐𝟗) + ∑𝒅(𝟔, 𝟗, 𝟏𝟗, 𝟐𝟑, 𝟑𝟎)
Solution
The K-map for the given function is shown in Fig.1.12.
ABC
000 001 011 010 110 111 101 100
DE

00 0 0 0 0 0 0 0 0

01 1 1 1 d 1 1 1 1

11 0 1 1 0 0 0 d d

10 0 d 1 0 0 d 1 1

Fig .1.12
 Digital Principles and System Design 1.21

By combining the 1s and d s, one octet and two quads can be obtained as shown
in Fig.1.12. The simplified expression is
̅ 𝐸 + 𝐴̅CD+A𝐵̅ 𝐷
Y=𝐷

1.10 ANALYSIS AND DESIGN PROCEDURES:

❖ The design of combinational circuits starts from the outline of the problem
statement and ends in a logic circuit diagram or a set of Boolean functions from
which the logic diagram can be easily obtained.
❖ The design procedure of the combinational circuit involves following steps
1. The problem definition.
2. The determination of number of available input variables and required
output variables.
3. Assigning letter symbols to input and output variables.
4. The derivation of truth table indicating the relationships between input
and output variables.
5. Obtain simplified Boolean expression for each output.
6. Obtain the logic diagram.
Example 1.13:
Design a combination logic circuit with three input variables that will produce logic
1 output when more than one input variables are logic 1.
Solution:
Given problem specifies that there are three input variables and one output variable.
We assign A, B and C letter symbols to three input variables and assign Y letter
symbol to one output variable. The relationship between input variables and output
variable can be tabulated as shown in truth table below.
A B C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1.22 Combinational Logic

1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

Now we obtain the simplified Boolean expression for output variable Y using K-
map simplification.
BC
00 01 11 10
A

0 0 0 1 0

0
1 1 1 1

Y = AC + BC + AB

B
Y
C

A
B

1.11 BINARY ADDER

❖ Digital computers perform various arithmetic operations.
❖ The most basic operation, no doubt, is the addition of two binary digits.
❖ This simple addition consists of four possible elementary operations
❖ The first three operations produce a sum whose length is one digit, but when the
 Digital Principles and System Design 1.23

last operation is performed sum is two digits.

❖ The higher significant bit of this result is called a carry, and lower significant bit
is called sum.
❖ The logic circuit which performs this operation is called a half-adder.
❖ The circuit which performs addition of three bits (two significant bits and a
previous carry) is a full-adder.
❖ Let us see the logic circuits to perform half-adder and full-adder operations.

1.11.1 Half Adder

o The half-adder operation needs two binary inputs augends and addend bits; and
two binary outputs sum and carry.
o The truth table shown below gives the relation between input and output variables
for half-adder operation.
Block Diagram:

A Sum
Inputs Half Adder Output
B Carry s

Fig 1.4 Logic Symbol of Half adder

Truth Table:

Inputs Outputs
A B Carry Sum
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
1.24 Combinational Logic

Kmap Simplification:For carry For Sum

B B
0 1 0 1
A A
0 0 0 0 0 1

1 0 1 1 1 0

Carry = AB 𝑆𝑢𝑚 = 𝐴𝐵̅ + 𝐴̅𝐵

=𝑨⊕𝑩
Logic Diagram:

Sum
B

Carry

Fig. 1.5: Logic diagram for half- adder

Limitations of Half-Adder
o In multi digit addition we have to add two bits along with the carry of previous
digit addition.
o Effectively such addition requires addition of three bits.
o This is not possible with half adder. Hence half-adders are not used in practice.

1.11.2 Full-Adder:
o A full-adder is a combinational circuit that forms the arithmetic sum of three input
bits.
o It consists of three inputs and two outputs.
o Two of the input variables, denoted by A and B, represent the two significant bits
to be added.
 Digital Principles and System Design 1.25

o The third input represents the carry from the previous lower significant position.
o The Block diagram and truth table for full-adder is
Block Diagram:

A Sum
Inputs Outputs
B Full Adder
Carry
Cin

Fig: 1.6 Logic Symbol of Full adder

Truth Table:
Inputs Outputs
A B Cin Carry Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

Kmap Simplification:
For sum
AB
00 01 11 10
cin
0 1 1

1 1 1

𝑆 = 𝐴̅𝐵̅ 𝐶𝑖𝑛 + 𝐴̅𝐵 𝐶̅ 𝑖𝑛 + 𝐴𝐵̅ 𝐶̅ 𝑖𝑛 + 𝐴𝐵𝐶𝑖𝑛

1.26 Combinational Logic

For carry
AB
00 01 11 10
cin
0 1

1 1 1 1

𝐶𝑜𝑢𝑡 = 𝐴𝐵 + 𝐵𝐶𝑖𝑛 + 𝐶𝑖𝑛 𝐴

Logic Diagram:

Fig: 1.7 Logic diagram of Full adder

1.11.3 Parallel Binary Adder:
o In most logic circuits, addition of more than 1-bit carried out.
o The addition of multi bit numbers can be accomplished using several full-adders.
o The 4-bit adder using full-adder circuits is capable of adding two 4-bit numbers
resulting in a 4-bit sum and a carry output as shown in Fig. 1.8.
o Since all the bits of the augend and addend are fed into the adder circuits
simultaneously and the additions in each position are taking place at the same
time, this circuit is known as parallel adder.
 Digital Principles and System Design 1.27

o The addition operation is illustrated in the following example: the 4-bit words to
be added be represented by A3A2A1A0 = 1111 and B3B2B1B0 = 0011.
Significant place 4 3 2 1
Input carry 1 1 1 0
Augend word A: 1 1 1 1
Addend word B: 0 0 1 1
1 0 0 1 0 Sum

Output carry

A3 B3 A2 B2 A1 B1 A0 B0

C4 C3 C3 C2 C2 C1 C1 C0

Cout Gnd

S3 S2 S1 S0
Fig: 1.8 4- bit binary parallel adder
o In a 4-bit parallel binary adder circuit, the input to each full-adder will be A1, B1
and C1, and the outputs will be Si and Ci+1, where i’ varies from 0 to 3.
o Also, the carry output of the lower order stage is connected to the input of the
carry output of the next higher order stage.
o Hence, this type of adder is called ripple carry adder.
o In the least significant stage, A0, B0 and C0 (which is 0) are added resulting in Sum
S0 and carry C1.
o This carry C1 becomes the carry input to the second stage.
o Similarly, in the second stage, A1, B1 and C1 are added resulting in S1 and C2; in
the third stage, A3, B3 and C3 are added resulting in S3 and C4 which is the output
carry.
o Thus, the circuit resulting a sum (S3, S2, S1, S0) and a carry output (Cout).
1.28 Combinational Logic

o Through the parallel binary adder is said to generate output immediately after the
inputs are applied, its speed of operation is limited by the carry propagation delay
through all stages.
o In each full-adder, the carry input has to be generated from the previous full-adder
which has an inherent propagation delay.
o The propagation delay (tp) of a full-adder is the time difference between the
instant at which the inputs (Ai, Bi and Ci ) are applied and the instant at which its
outputs (Si and Ci+1 ) are generated.
o Suppose, in a 4-bit binary adder, the output in LSB stage is generated only after
tp seconds.
o For a 4-bit binary adder, where each full adder has a propagation delay of 50ns,
the output in the fourth stage will be generated only after 4tp=4×50ns=200ns.
o The magnitude of such delay is prohibitive for high-speed computers.
o One of the methods of speeding up this process is look-ahead carry addition which
elimination the ripple-carry delay.
o This method is based on the carry generate and the carry propagate functions of
the full-adder.
1.11.4 Half Subtractor:
o The half-subtractor is a combinational circuit which is used to perform subtraction
of two bits.
o It has two inputs, X (minuend) and Y (Subtrahend) two outputs D (difference) and
Bout (borrow out).
o The truth table shown below gives the relation between input and output variables
for half-subtractor operation.
Block Diagram:

X
D
Inputs Half Outputs
Subtractor
Y Bout

Fig 1.9 Logic Symbol of Half Subtractor

 Digital Principles and System Design 1.29

Truth Table:
Inputs Outputs
Minuend X Subtrahend Y Difference D Borrow Bout

0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Kmap Simplification:
For Difference,
X
Y 0 1
0 1

1 1
̅ 𝒀 + 𝑿𝒀
𝑫=𝑿 ̅ =𝑿⊕ 𝒀
For Borrow,
X
Y 0 1
0

1 1
̅𝒀
𝑩𝒐𝒖𝒕 = 𝑿
Logic Diagram:

Fig. 1.10 Logic diagram for half- Subtractor

1.30 Combinational Logic

1.11.5 Full- Subtractor:

o The full-subtractor is a combinational circuit which is used to perform subtraction
of three bits.
o It has two inputs, X (minuend), Y (Subtrahend) and Bin (borrow from previous
stage) two outputs D (difference) and Bout (borrow out).
o The truth table shown below gives the relation between input and output variables
for full-subtractor operation.
Block Diagram:

X D
Full
Inputs Y Outputs
Subtractor
Bin Bout

Fig 1.11 Logic Symbol of Full Subtractor

Truth Table:
Inputs Outputs

Minuend X Subtrahend Y Borrow in Difference D Borrow Bout

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1
 Digital Principles and System Design 1.31

Kmap Simplification:
For Difference,

XY
Bin 00 01 11 10
0 1 1

1 1 1

̅𝒀
𝑫=𝑿 ̅ 𝑩𝒊𝒏 + 𝑿
̅ 𝒀𝑩𝒊𝒏
̅̅̅̅̅ + 𝑿𝒀
̅ 𝑩𝒊𝒏
̅̅̅̅̅ + 𝑿𝒀𝑩𝒊𝒏
For Borrow,
XY
Bin 00 01 11 10

0 1

1 1 1 1

̅𝒀 + 𝑿
𝑩𝒐𝒖𝒕 = 𝑿 ̅ 𝑩𝒊𝒏 + 𝒀𝑩𝒊𝒏
Logic Diagram:

Fig. 1.12 Logic diagram for full-subtractor

1.32 Combinational Logic

1.12 BCD ADDER

❖ A BCD adder is used to perform the addition of BCD numbers.
❖ A BCD digit can have any of the ten possible four-bit binary representations, that
is, 0000, 0001… 1001, the equivalent of decimal numbers 0, 1… 9.
❖ When we set out to add two BCD digits and we assume that there is an input carry
too, the highest binary number that we can get is the equivalent of decimal number
19 (9 + 9 + 1).
❖ The binary sum and the BCD sum in this case are the same.
❖ It is only when the sum is greater than 9 that the two results are different.
❖ It can also be seen from the table that, for a decimal sum greater than 9 (or the
equivalent binary sum greater than 1001), if we add 0110 to the binary sum, we
can get the correct BCD sum and the desired carry output too.
Decimal Uncorrected BCD Sum Corrected BCD Sum
digit C3 S3 S2 S1 S0 Cout S3 S2 S1 S0

0 0 0 0 0 0 0 0 0 No
Correction
1 0 0 0 1 0 0 0 1
required
2 0 0 1 0 0 0 1 0
3 0 0 1 1 0 0 1 1
4 0 1 0 0 0 1 0 0
5 0 1 0 1 0 1 0 1
6 0 1 1 0 0 1 1 0
7 0 1 1 1 0 1 1 1
8 1 0 0 0 1 0 0 0
9 1 0 0 1 1 0 0 1
10 1 0 1 0 1 0 0 0 0 Correction
required
11 1 0 1 1 1 0 0 0 1
12 1 1 0 0 1 0 0 1 0
 Digital Principles and System Design 1.33

13 1 1 0 1 1 0 0 1 1
14 1 1 1 0 1 0 1 0 0
15 1 1 1 1 1 0 1 0 1
16 1 0 0 0 0 1 0 1 1 0
17 1 0 0 0 1 1 0 1 1 1
18 1 0 0 1 0 1 1 0 0 0
19 1 0 0 1 1 1 1 0 0 1

Z3Z2
Z1Z0 00 01 11 10
00 12
01 13
11 15 11
10 14 10

❖ The Boolean expression that can apply the necessary correction is written as
C = K + Z3Z2 + Z3Z1
❖ A correction needs to be applied whenever K = 1.
❖ This takes care of the last four entries.
❖ Also, a correction needs to be applied whenever both Z3 and Z2 are ‘1‘.
❖ This takes care of the next four entries from the bottom, corresponding to a
decimal sum
❖ From the above tabular form 12, 13, 14 and 15. For the remaining two entries
corresponding to a decimal sum equal to 10 and11, a correction is applied for both
Z3 and Z1, being ‘1‘.
❖ While hardware-implementing, 0110 can be added to the binary sum output with
the help of a second four-bit binary adder.
❖ The correction logic as dictated by the Boolean expression should ensure that
(0110) gets added only when the above expression is satisfied.
1.34 Combinational Logic

❖ Otherwise, the sum output of the first binary adder should be passed on as such to
the final output, which can be accomplished by adding (0000) in the second adder.
❖ Figure shows the logic arrangement of a BCD adder capable of adding two BCD
digits with the help of two four-bit binary adders and some additional
combinational logic.

Fig. 1.13 BCD Adder

❖ For example, an n-digit BCD adder would require n such stages in cascade. As
an illustration,
❖ Fig. shows the block diagram of a circuit for the addition of two three-digit BCD
numbers.
❖ The first BCD adder, labelled LSD (Least Significant Digit), handles the least
significant BCD digits.
❖ It produces the sum output (S3 S2 S1 S0), which is the BCD code for the least
significant digit of the sum.
❖ It also produces an output carry that is fed as an input carry to the next higher
 Digital Principles and System Design 1.35

adjacent BCD adder. This BCD adder produces the sum output (S7 S6 S5 S4),
which is the BCD code for the second digit of the sum, and a carry output.
❖ This output carry serves as an input carry for the BCD adder representing the most
significant digits.
❖ The sum outputs (S11 S10 S9 S8) represent the BCD code for the MSD of the
sum.

1.13 MAGNITUDE COMPARATOR

❖ A Magnitude Comparator is a combinational circuit that compares the magnitude
of two number (A and B) and generates one of the following outputs: A = B, A<B
and A>B.
❖ The block diagram of a single-bit magnitude comparator is shown in Fig.1.14.

A0˃B0
A0 Single - bit
magnitude A0=B0
B0 comparator
A0˂B0

Fig. 1.14 Block diagram of single - bit magnitude comparator

❖ To implement the magnitude comparator, the EX-NOR gates and AND
gates are used.
❖ The property of the EX-NOR gate can be used to find whether the two
binary digits are equal or not,
❖ AND gates are used to find whether a binary digits less than or greater than another
bit.

A0 𝐴̅0
𝐵̅0 B0

Fig. 1.15
1.36 Combinational Logic

❖ Fig. 1.15 shows an EX-NOR gate with two input 𝐴0 and 𝐵0 .

❖ If 𝐴0 =𝐵0, then the output of EX-NOR gate will be 1.
❖ If 𝐴0 ≠ 𝐵0 , the output will be 0.

1.13.1 Single-bit Magnitude Comparator

❖ If the above EX-NOR gate and two AND gate are combined as shown in Fig. 1.16,
the circuit will function as a single bit magnitude comparator.
❖ The same principle can be extended to an n-bit magnitude comparator. The design
of a 4-bit magnitude comparator is discussed in the next section.

Fig.1.16 Single- bit magnitude comparator

1.13.2 4-bit Magnitude Comparator
❖ A 4-bit magnitude comparator two 4-bit number A and B and gives one of the
following outputs: A = B, A < B and A > B.
❖ Let A = 𝐴3 𝐴2 𝐴1 𝐴0 and B = 𝐵3 𝐵2 𝐵1 𝐵0 be the two 4-bit numbers to be compared.
❖ The following steps involved in comparing two such numbers can be used as the
basis for a hardware implementation.
❖ The steps involved in comparing two 4-bit numbers are:
(a) Examine the two most significant bits (𝐴3 and𝐵3). If 𝐴3 >𝐵3, then A >B; if
𝐴3 <𝐵3, then A < B. If 𝐴3 = 𝐵3, no decision can be made regarding the relative
 Digital Principles and System Design 1.37

magnitude of two numbers and the next pair of bits (𝐴2 and 𝐵2) must be
examined
(b) If 𝐴3 = 𝐵3 and 𝐴2 >𝐵2, then A > B; if 𝐴3 = 𝐵3 and 𝐴2 <𝐵2, then A < B.
However, if 𝐴3 = 𝐵3 and 𝐴2 =𝐵2, no conclusion can be drawn regarding the
relative magnitudes of the two numbers and the next pair of bits (𝐴1 and𝐵1)
must be examined.
(c) If 𝐴3 = 𝐵3, 𝐴2 = 𝐵2 and 𝐴1 > 𝐵1; then A > B; if 𝐴3 = 𝐵3 , 𝐴2 = 𝐵2 and 𝐴1 <
𝐵1 , then A < B. However, if 𝐴3 = 𝐵3 , 𝐴2 = 𝐵2 and 𝐴1 =𝐵1, no conclusion can
be yet be drawn regarding the relative magnitudes of the two numbers and the
LSBs (𝐴0 and𝐵0) must be examined.
(d) If 𝐴3 = 𝐵3, 𝐴2 = 𝐵2, 𝐴1 = 𝐵1 and 𝐴0 > 𝐵0, then A > B; if 𝐴3 = 𝐵3, 𝐴2 = 𝐵2, 𝐴1
= 𝐵1
And 𝐴0 <𝐵0, then A < B. However, if 𝐴3 =𝐵3 , 𝐴2 =𝐵2, 𝐴1 = 𝐵1 and 𝐴0 =𝐵0,
then A = B.
If the most significant bits are equal (i.e. 𝐴3 = 𝐵3 =0 OR 𝐴3 = 𝐵3 =1), then
𝐸3 = ̅̅̅ 𝐵3+ 𝐴3 𝐵3 = ̅̅̅̅̅̅̅̅̅̅̅
𝐴3 ̅̅̅ 𝐴3 ⊕ 𝐵3
If the next two most significant bits are equal, then
𝐸2 = ̅̅̅
𝐴2 ̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅
𝐵2+ 𝐴2 𝐵2 = 𝐴 2 ⊕ 𝐵2

If the next two most significant bits are equal, then

𝐸1 = ̅̅̅
𝐴1 ̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅
𝐵1+ 𝐴1 𝐵1 = 𝐴 1 ⊕ 𝐵1

If the two least significant bits are equal, then

𝐸0 = ̅̅̅ 𝐵0+ 𝐴0 𝐵0 = ̅̅̅̅̅̅̅̅̅̅̅
𝐴0 ̅̅̅ 𝐴0 ⊕ 𝐵0
Hence, if A = B, then
̅̅̅̅̅̅̅̅̅̅̅̅
E= 𝐸3 𝐸2 𝐸1 𝐸0 = (𝐴 ̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅
3 ⊕ 𝐵3) (𝐴2 ⊕ 𝐵2) ·(𝐴1 ⊕ 𝐵1 ) ·(𝐴0 ⊕ 𝐵0 ) =1

The expression for determining whether A > B is

A > B = 𝐴3 ̅̅̅
𝐵3 + 𝐸3 𝐴2 ̅̅̅
𝐵2+ 𝐸3 𝐸2 𝐴1 ̅̅̅
𝐵1+𝐸3 𝐸2 𝐸1 𝐸0 𝐴0 ̅̅̅
𝐵0
❖ The first term in this equation 𝐴3 ̅̅̅
𝐵3 =1 if 𝐴3 >𝐵3, and if that is the case, then A >
B.
❖ The second term in this equation 𝐸3 𝐴2 ̅̅̅
𝐵2 =1 if 𝐴3 = 𝐵3 and 𝐴2 > 𝐵2 and, if that
is the case, then A > B.
1.38 Combinational Logic

❖ The third term 𝐸3 𝐸2 𝐴1 ̅̅̅

𝐵1 =1 if 𝐴3 = 𝐵3 , 𝐴2 = 𝐵2 and 𝐴1 =𝐵1; if these three
condition are satisfied, then A > B.
❖ Finally, the fourth term 𝐸3 𝐸2 𝐸1 𝐸0 𝐴0 ̅̅̅
𝐵0 =1 if 𝐴3 =𝐵3, 𝐴2 =𝐵2, 𝐴1 = 𝐵1 and 𝐴0
=𝐵0; if these four conditions are satisfied, then A > B.
The expression for determining whether A < B is
̅̅̅3 𝐵3 + 𝐸3 ̅̅̅
A < B =𝐴 𝐴2 𝐵2 +𝐸3 𝐸2 ̅̅̅
𝐴1 𝐵1+𝐸3 𝐸2 𝐸1 ̅̅̅
𝐴0 𝐵0
❖ This has the same form as the A > B expression and can be analyzed in a similar
manner.
❖ Its truth table is given in the following table
Comparing Inputs Cascading Inputs Outputs
A3, B3 A2, B2 A1, B1 A0, B0 A>B A<B A=B A>B A<B A=B
A3>B3 X X X X X X 1 0 0
A3 < B3 X X X X X X 0 1 0
A3 = B3 A2 > B2 X X X X X 1 0 0
A3 = B3 A2 < B2 X X X X X 0 1 0
A3 = B3 A2 = B2 A1 > B1 X X X X 1 0 0
A3 = B3 A2 = B2 A1< B1 X X X X 0 1 0
A3 = B3 A2 = B2 A1 = B1 A0 > B0 X X X 1 0 0
A3 = B3 A2 = B2 A1 = B1 A0< B0 X X X 0 1 0
A3 = B3 A2 = B2 A1 = B1 A0= B0 1 0 0 1 0 0
A3 = B3 A2 = B2 A1 = B1 A0= B0 0 1 0 0 1 0
A3 = B3 A2 = B2 A1 = B1 A0= B0 0 0 1 0 0 1

❖ The implementation of a 4-bit magnitude comparator using EX-NOR and AND

gates using the above expression is shown Fig. 1.17.
 Digital Principles and System Design 1.39

Fig.1.17 4 - bit magnitude comparator

Applications of Comparators:
1. These are used in control applications in which the binary numbers representing
physical variables such as temperature, position, etc. are compared with a
reference value.
2. Comparators are also used as process controllers and for Servo motor control.
3. Used in password verification and biometric applications.

1.14 MULTIPLEXERS (DATA SELECTORS)

❖ The term ‘multiplex’ means “many into one”.
❖ Multiplexing is the process of transmitting a large number of information over a
single line.
❖ A digital multiplexer (MUX) is a combinational circuit that selects one digital
1.40 Combinational Logic

information from several sources and transmits the selected information on a

single output line.
❖ A multiplexer is also called a data selector since it selects one of many inputs and
directs the information to the output.
❖ The multiplexer has several data-input lines and a single output line.
❖ The selection of a particular input line is controlled by a set of selection lines.
❖ The block diagram of a multiplexer with ‘n’ input lines, ‘m’ select signals and one
output line is show in Fig.1.18.
❖ The selection lines decide the number of input lines is equal to 2m, then m select
lines are required to select one of the n input lines.
❖ For example, to select 1 out of an input lines, two select lines are required; to
select 1 of 8 input lines, 3 select lines are required and so on.

Multiplexer

n input 1 Output
Signals Signals
m select
Signals

Fig: 1.18 Block diagram of multiplexer

1.14.1 Basic Four-Input Multiplexer

❖ The logic symbol of a 4-to-1 multiplexer is shown in Fig 1.19.
❖ It has four data input line (D0-D3), a single output line (Y) and two select lines
(S0 and S1) to select one of the four input lines.
❖ The truth table for a 4-to-1 multiplexer is shown in Table
 Digital Principles and System Design 1.41

Data Select Inputs Output

S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3

Logic Symbol

D0
Data D1 4 – to – 1 Y Data
Inputs D2 MUX Output
D3
S1 S0

Fig. 1.19 Logic Symbol

❖ From the truth table, a logical expression for the output in terms of the data input
and the select inputs can be derived as follows:
The data output Y=data input D0, if and only if S1=0 and S0=0.
Therefore, Y=D0 ̅𝑆1 𝑆0̅ = D00.
̅ 0̅=D01.1=D0
The data output Y=D1, if and only if S1=0 and S2=1.
Therefore, Y= D1𝑆1̅ 𝑆0=D1, when S1S0=01
Similarly, Y=D2S1𝑆0̅ =D2, when S1S0=10 and
Y=D3S1S0=D3, when S1S0=11
❖ If the above terms are OR ed, then the final expression for the data output is given
by,
Y=D0𝑆1̅ 𝑆0̅ +D1𝑆1̅ 𝑆0 + 𝐷2 𝑆1 𝑆0̅ + 𝐷3 𝑆1 𝑆0
❖ Using the above expression, the 4-to-1 multiplexer can be implemented using two
NOT gates, four 3-input AND gates and one 4-input OR gate as shown in Fig.1.20.
❖ Here, each of the four data input lines is applied to any one input of an AND gate
1.42 Combinational Logic

and the AND gate outputs are connected with the inputs of OR gate to generate
the output Y.

Fig.1.20 4- to- 1 multiplexer

❖ Consider the case when S1S0=00.
❖ If S1S0=00 is applied to the select lines, the AND gate associated with D0 will have
two of the inputs equal to 1 and the third input connected to D0.
❖ The other three AND gates have 0 in atleast one of their inputs, which makes their
output equal to 0.Hence, the OR output Y is equal to the value of D0.
❖ Thus, it provides a path from the selected input (i.e. D0 and the data on the input
D0 appears on the data-output line.
❖ If S1S0=01 (binary 1) is applied to the select lines, the data on the input D1 appears
on the output line.
❖ Similarly, if S1S0=11 is applied, the data on D3 is switched to the output line.
 Digital Principles and System Design 1.43

1.14.2 Implementation of Boolean Expression using Multiplexers

❖ Any Boolean or logical expression can be easily implemented using a multiplexer.
❖ For example, if A is the single variable, then the inputs of the multiplexer are A, ̅𝐴,
1 AND 0.
❖ By this method, any logical expression can be implemented.
❖ In general, a Boolean expression of (n+1) variables can be implanted using a
multiplexer with 2n inputs.
❖ The given function is implemented by circling the min terms of the function and
applying the following rules to find the values for the input of the multiplexer.
1. If both the min term in a column are not circled, apply 0 to the corresponding
input.
2. If both the min term in a column are circled, apply 1 to the corresponding
input.
3. If the bottom min term is circled and the top is not circled, apply A to the
input
4. If the top min term is circled and the bottom is not circled, apply 𝐴̅ to the
input.
❖ To demonstrate this product consider the function
F(A,B,C,D)=∑(0,1,3,4,8,9,15)
❖ As the given function is a four-variable function, we need a multiplexer with 3
select lines and eight inputs.
❖ Apply variables B, C and D to the select lines. The procedure for implementing
the function are:
o (𝑖). list the input of the multiplexer and
o (ii) List under them all the min terms in two rows as shown in Table.
D0 D1 D2 D3 D4 D5 D6 D7
𝐴̅ (0) (1) 2 (3) (4) 5 6 7
A (8) (9) 10 11 12 13 14 (15)
1 1 0 𝐴̅ 𝐴̅ 0 0 A
1.44 Combinational Logic

o The first half of the min terms are associated with 𝐴̅ and the second half with
A.
❖ Now, using the procedure and the table, the given function can be implemented
using an 8-to-1 multiplexer as shown in Fig.1.21.

1 D0

D1
0 D2

D3 8 × 1 MUX
Y=F
D4

D5

D6

A D7

S2 S1 S0

B
C
D

Fig. 1.21 Implementation using 8- to – 1 MUX

1.14.3 Applications of Multiplexers
❖ Multiplexer’s circuits find the numerous applications in digital systems. Some of
the fields where multiplexing finds immense use are data selection, data routing,
operation sequencing, parallel-to-serial conversion, waveform generation and
logic function generation.
▪ Data routing
▪ Logic function generator
▪ Control Sequencer
▪ Parallel-to-serial converter
 Digital Principles and System Design 1.45

1.15 DEMULTIPLEXERS (DATA DISTRIBUTORS)

❖ The term ‘demultiplex’ means “one into many”.
❖ Demultiplexing is the process of taking information from one input and
transmitting the same over one of several outputs.
❖ A multiplexer is also called a data distributor

Demultiple
xer n output
1 Input signal signals
DMUX

Fig.1.22. Block diagram of demultiplexer

1.15.1 1 to 4 Demultiplexer
❖ A 1-to-4 demultiplexer has a single input (D), four outputs (Y0 to Y3) and two
select inputs (S1 and S0)
❖ The truth table of the 1- to-4 demultiplexer is shown
Data Select Inputs Output
D S1 S0 Y3 Y2 Y1 Y0
D 0 0 0 0 0 D
D 0 1 0 0 D 0
D 1 0 0 D 0 0
D 1 1 D 0 0 0

❖ From the above truth table , the expression for outputs can be written as
𝑌0 = 𝑆̅1 𝑆̅0 𝐷
𝑌1 = 𝑆̅1 𝑆0 𝐷
𝑌2 = 𝑆1 𝑆̅0 𝐷
𝑌3 = 𝑆1 𝑆0 𝐷
1.46 Combinational Logic

❖ Now, using the above expression a 1-to-4 demultiplexer can be implemented using
four 3- input AND gates and two NOT gates

Fig.1.23 Logic diagram of 1-to-4 demultiplexer

❖ Here the input data line is connected to all the AND gates.
❖ The two select lines S1S0 enable only one gate at a time and the data that appears
on the input line.

1.16 DECODERS
❖ A decoder is similar to de-multiplexer but without any data input.
❖ Most digital systems require the decoding of data. Decoding is necessary in
application such as data de-multiplexing, digital display, digital-to-analog
converters and memory addressing.
 Digital Principles and System Design 1.47

❖ A decoder is a logic circuit that converts an n-bit binary input code(data) into 2nd
output lines, such that each output line will be activated for one of the possible
combinations of inputs.
❖ In a decoder, the number of output is greater than the number of inputs.
❖ Here, it is important to note that if the number of inputs and outputs are equal in a
digital system then it can be called converters, e.g. BCD to Excess-3 code, Binary
to Gray and Gray to Binary code converters.

1.16.1 Basic Binary Decoder

❖ An AND gate can be used as the basic decoding element because its output is
HIGH only when all the inputs are HIGH.
❖ For example, if the input binary number is 1001, then, to make all the inputs to
the AND gate HIGH, the two middle bits(0s) must be inverted by using two NOT
gates as shown in fig 1.24

Fig.1.24 decoding logic

1.16.2 3-to-8 Decoder
❖ A 3-to-8 decoder has three inputs (A, B, C) and eight outputs (D0 to D7).
❖ Based on the 3 inputs, one of the eight outputs is selected.
❖ The truth table for 3-to-8 decoder is shown in Table.
❖ From the below truth table, it is clear that only one of eight outputs (D0 to D7) is
selected based on the three select inputs.
❖ Also, from the truth table, the logic expressions for the outputs can be written as
follows:
1.48 Combinational Logic

Input Outputs
A B C D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

𝐷0=𝐴̅𝐵̅𝐶̅ ; 𝐷1 = 𝐴̅𝐵̅ 𝐶 ; 𝐷2 = 𝐴̅𝐶̅ 𝐵 ; 𝐷3 = 𝐴̅𝐵𝐶

𝐷4 = 𝐴𝐵̅𝐶̅ ; 𝐷5 = 𝐴𝐵̅𝐶 ; 𝐷6 = 𝐴𝐵𝐶̅ ; 𝐷7 = 𝐴𝐵𝐶

❖ Using the above expressions, the circuit of a 3-to-8 decoder can be implemented
using three NOT gates and eight 3-input AND gates as shown in Fig.1.24.
❖ The three inputs, A, B and C are decoded into eight outputs, each output
representing one of the minterms of the 3-input variables.
❖ The three inverters provide the complement of the inputs and each one of the eight
AND gates generate one of the minterms.
❖ The decoder can be used for decoding any 3-bit code to provide eight outputs,
corresponding to eight different combinations of the input code.
❖ This is also called a 1-of-8 decoder, since only one of eight output lines is HIGH
for a particular input combination.
❖ For example, when ABC=010, only the AND gate-2 has HIGH at all its inputs,
and therefore D2 = HIGH.
❖ Similarly, if ABC=110, the AND gate 6 has all its inputs in HIGH state and
thereby D6 =HIGH.
❖ It is also called a binary-to-octal decoder since the inputs represent three-bit binary
numbers and the outputs represent the eight digits in the octal number system.
 Digital Principles and System Design 1.49

NOTE: Enable inputs

❖ Some decoders have one or more enable inputs which are used to control the
operation of the decoder.
❖ With the enable line held HIGH, the decoder functions normally and the input
code, A, B and C will determine which output is HIGH.
❖ Hence, the decoder is enabled only if the enable line is HIGH.

Fig.1.24 Logic diagram of 3-to-8 decoder

1.50 Combinational Logic

1.16.3 BCD-to-Seven-segment Decoder/Driver

❖ A seven-segment display is normally used for displaying any one of the decimal
digits, 0 through 9.
❖ A BCD-to-seven segment decoder accepts a decimal digit in BCD and generates
the corresponding seven-segment code.
❖ Figure 1.25 shows a seven-segment display composed of seven elements or
segments.
❖ Each segment is made up of a material that emits light when current is passed
through it.
❖ Most commonly used displays are LEDs and incandescent filaments. Note that
letters a, b, c, d, e, f and g run clockwise from the top of each segment.
❖ For instance, to display a 1, the segments b and c have to be illuminated; to display
a 0, the segments a, b, c, d, e and f have to be illuminated by properly forward
biasing the LEDs in the selected segments.

Fig.1.25 Seven segment digits display

1.16.3.1 Design of BCD-to-seven –segment decoder

❖ A BCD-to-seven-segment decoder can be designed using logic gates.
❖ A block diagram of BCD-to-seven-segment decoder with four BCD inputs (A, B,
C and D) and seven outputs (a, b, c, d, e, f and g) corresponding to seven segments
of a display, is shown in Fig.1.26.
 Digital Principles and System Design 1.51

A BCD to a
b
B 7- Segment c
d
C decoder e
f
D
g

Fig 1.26 Block diagram of BCD to 7 segment decoder

❖ The truth table of the BCD-to-7-segment decoder is shown in Table.
BCD Inputs Seven segment outputs
A B C D a b c d e f g
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 1

❖ Since the BCD inputs are valid combinations, the other input combination of four
variables corresponding to 10, 11, 12, 13, 14 and 15 can be termed as don’t care
combinations to aid the simplification of logic expressions.
❖ Now, the logic expressions, corresponding to seven-segment can be written from
the truth table shown in Table as follows:

𝑎 = ∑ (0, 2, 3, 5, 6, 7, 8, 9) + ∑ (10, 11, 12, 13, 14,15)

𝑚 𝑑

𝑏 = ∑ (0, 1, 2, 3, 4, 7, 8, 9) + ∑ (10, 11, 12, 13, 14, 15)

𝑚 𝑑
1.52 Combinational Logic

𝑐 = ∑ (0, 1, 3, 4, 5, 6, 7, 8, 9) + ∑ (10, 11, 12, 13, 14, 15)

𝑚 𝑑

𝑑 = ∑ (0, 2, 3, 5, 6, 8, 9) + ∑ (10, 11, 12, 13, 14, 15)

𝑚 𝑑

𝑒 = ∑ (0, 2, 6, 8) + ∑ (10, 11, 12, 13, 14, 15)

𝑚 𝑑

𝑓 = ∑ (0, 4, 5, 6, 8, 9) + ∑ (10, 11, 12, 13, 14, 15)

𝑚 𝑑

𝑔 = ∑ (2, 3, 4, 5, 6, 8, 9) + ∑ (10, 11, 12, 13, 14, 15)

𝑚 𝑑

❖ The above expressions can be simplified using K-map method as shown

̅ = 𝐴 + 𝐶 + ̅̅̅̅̅̅̅̅̅
From the above K-map, 𝑎 = 𝐴 + 𝐶 + 𝐵𝐷 + 𝐵̅ 𝐷 𝐵⊕𝐷

̅ = 𝐵̅ + ̅̅̅̅̅̅̅̅̅
𝑏 = 𝐵̅ + 𝐶𝐷 + 𝐶̅ 𝐷 𝐶 ⊕𝐷
 Digital Principles and System Design 1.53

𝑐 = 𝐵 + 𝐶̅ + 𝐷

𝑑 = 𝐴 + 𝐵̅ 𝐷
̅ + 𝐶𝐷
̅ + 𝐵̅ 𝐶 + 𝐵𝐶̅ 𝐷
̅ + 𝐵̅ (𝐶 + 𝐷
= 𝐴 + 𝐶𝐷 ̅ ) + 𝐵𝐶̅ 𝐷
̅ + 𝐵 ⊕ (𝐶 + 𝐷
= 𝐴 + 𝐶𝐷 ̅)
1.54 Combinational Logic

𝑒 = 𝐵̅ 𝐷
̅ + 𝐶𝐷
̅=𝐷
̅ (𝐵̅ + 𝐶)

𝑓 = 𝐴 + 𝐶̅ 𝐷
̅ + 𝐵𝐶̅ + 𝐵𝐷
̅ = 𝐴 + 𝐶̅ 𝐷
̅ + 𝐵(𝐶̅ + 𝐷
̅)

̅ + 𝐵𝐶̅ + 𝐵̅ 𝐶 = 𝐴 + 𝐶𝐷
𝑔 = 𝐴 + 𝐶𝐷 ̅ + (𝐵 ⊕ 𝐶)
 Digital Principles and System Design 1.55

Fig. 1.27 Logic diagram of BCD–to–7 segment decoder

1.16.3.2 Applications of decoders:
❖ Decoders are used in counter system.
❖ They are used in digital-to-analog converters.
❖ Decoder outputs can be used to drive a display system.
1.56 Combinational Logic

1.17 ENCODERS
❖ An encoder is a digital circuit that performs the inverse operation of a decoder.
❖ Here the opposite of the decoding is called encoding.
❖ An encoder is a combinational logic circuit that converts an active input signal
into a coded output signal.
❖ It has n input only one of which is active at any time and m output lines.
❖ It encodes one of the active input to a binary output with m bits.
❖ In an encoder, the number of outputs is less than the number of inputs.
❖ The blocks diagram of an encoder is shown in Fig.1.28.

m outputs
Encoder
n inputs

Fig.1.28 Block diagram of an encoder

1.17.1 Octal-to-Binary Encoder

❖ Binary-to octal-decoder (3-to-8 decoder) accepts a 3-bit input code and activates
one of eight output lines corresponding to that code.
❖ An octal-to-binary encoder performs the opposite function; it accepts eight inputs
and produces a 3-bit output code corresponding to the activated input.
❖ The truth table for the octal-to-binary encoder is shown below
Inputs Outputs
D0 D1 D2 D3 D4 D5 D6 D7 Y2 Y1 Y0
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
 Digital Principles and System Design 1.57

❖ The above truth table shows that Y0 (LSB of output code) must be 1 whenever the
input D1 OR D3 OR D5 OR D7 is HIGH. Thus,
𝑌0 = 𝐷1+ 𝐷3 + 𝐷5 + 𝐷7
Similarly, 𝑌1 = 𝐷2 + 𝐷3 + 𝐷6 + 𝐷7
𝑌2 = 𝐷4 + 𝐷5 + 𝐷6 + 𝐷7
❖ Using the above expressions, the octal-to-binary encoder can be implemented
using three 4-input OR gates as shown in Fig. 1.29.
❖ The circuit is designed in such a way that, when D0 is HIGH, the binary code 000
is generated; when D1 is HIGH.
❖ The binary code 001 is generated, and soon.

Fig. 1.29 Octal to binary encoder

Note:
The design is made simply by the fact that only eight one of the total of 28 possible
input conditions are used.

1.17.2 Decimal-to-BCD Encoder

❖ A decimal-to-BCD encoder is one with ten inputs corresponding to ten decimal
digits (0 to 9) and four outputs (A, B, C, D) representing the BCD value if input
decimal digit.
❖ The truth table for a decimal-to-BCD encoder is shown in the following table.
1.58 Combinational Logic

Decimal Inputs BCD outputs

0 1 2 3 4 5 6 7 8 9 A B C D
1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 0 0 0 1 0 0
0 0 0 0 0 1 0 0 0 0 0 1 0 1
0 0 0 0 0 0 1 0 0 0 0 1 1 0
0 0 0 0 0 0 0 1 0 0 0 1 1 1
0 0 0 0 0 0 0 0 1 0 1 0 0 0
0 0 0 0 0 0 0 0 0 1 1 0 0 1

❖ From the above truth table, it is clear that the output A is HIGH whenever the
input 8 OR 9 is HIGH.
Therefore, A=8+9
❖ The output B is HIGH whenever the input 4 Or 5 OR 6 OR 7 is HIGH.
Therefore, B=4+5+6+7
❖ Similarly, C=2+3+6+7 and D=1+3+5+7+9
❖ Now, the above expression for BCD outputs can be implemented as shown in
Fig.1.30 using four OR gates.

Fig.1.30 Decimal to BCD encoder

 2
SYNCHRONOUS SEQUENTIAL
LOGIC

2.1 INTRODUCTION
❖ The analysis and design of combinational digital circuits. It constitutes only a part
of digital systems. The other major aspect of digital system is analysis and design
of sequential circuits
❖ There are many applications in which digital outputs are required to be generated
in accordance with the sequence in which the input signals are received.
❖ This requirement cannot be satisfied using a combinational logic system. These
applications require outputs to be generated that are not only dependent on the
present input conditions but they also depend upon the past history of these inputs.
❖ The past history is provided by feedback from the output back to the input. Fig.2.1
shows the block diagram of sequential circuit.
❖ As shown in the Fig.2.1 memory elements are connected to the combinational
circuit as a feedback path.
❖ The information stored in the memory elements at any given time defines
the present state of the sequential circuit.
❖ The present state and the external inputs determine the outputs and the next state
of the sequential circuit.
❖ Thus we can specify the sequential circuit by a lime sequence of external
inputs, internal states (Present states and next states) and outputs.
2.2 Synchronous Sequential Logic

Fig 2.1 Generalized sequential circuit.

S.No Combinational Circuit Sequential Circuit
1 In this output depends only upon In this output depends upon present as
present input. well as past input.
2 Speed is fast Speed is slow.

3 It is designed easy. It is designed tough as compared to

combinational circuits.
4 There is no feedback between input There exists a feedback path between
and output. input and output.
5 This is time independent. This is time dependent.

6 Elementary building blocks: Logic Elementary building blocks: Flip-flops

gates
7 Used for arithmetic as well as boolean Mainly used for storing data.
operations.
8 Combinational circuits don’t have Sequential circuits have capability to
capability to store any state. store any state or to retain earlier state.
9 As combinational circuits don’t have As sequential circuits are clock
clock, they don’t require triggering. dependent they need triggering.
 Digital Principles and System Design 2.3

10 These circuits do not have any These circuits have memory element.
memory element.
11 It is easy to use and handle. It is not easy to use and handle.

12 Examples – Encoder, Decoder, Examples – Encoder, Decoder,

Multiplexer, Demultiplexer Multiplexer, Demultiplexer

❖ The sequential circuits can be classified depending on the timing of their signals:
o Synchronous sequential circuits and Asynchronous sequential circuits.
o In synchronous sequential circuits, signals can affect the memory elements
only at discrete.
o Instants of time. In asynchronous sequential circuits change in input
signals can affect memory element at any instant of time.
o The memory elements used in both circuits are flip-flops which are capable
of storing 1-bit binary information.
Sl. Key Synchronous Sequential Asynchronous Sequential
No. Circuits Circuits
1 Definition Synchronous sequential On other hand Asynchronous
circuits are digital sequential sequential circuits are digital
circuits in which the feedback sequential circuits in which
to the input for next output the feedback to the input for
generation is governed by next output generation is not
clock signals. governed by clock signals.
2 Memory Unit In Synchronous sequential On other hand unclocked flip
circuits, the memory unit flop or time delay is used as
which is being get used for memory element in case of
governance is clocked flip Asynchronous sequential
flop. circuits.
3 State The states of Synchronous On other hand there are
sequential circuits are always chances for the Asynchronous
predictable and thus reliable. circuits to enter into a wrong
state because of the time
difference between the
2.4 Synchronous Sequential Logic

arrivals of inputs. This is

called as race condition.
4 Complexity It is easy to design However on other hand the
Synchronous sequential presence of feedback among
circuits logic gates causes instability
issues making the design of
Asynchronous sequential
circuits difficult.
5 Performance Due to the propagation delay Since there is no clock signal
of clock signal in reaching all delay, these are fast compared
elements of the circuit the to the Synchronous Sequential
Synchronous sequential Circuits
circuits are slower in its
operation speed
6 Example Synchronous circuits are used On other hand Asynchronous
in counters, shift registers, circuits are used in low power
memory units. and high speed operations
such as simple
microprocessors, digital
signal processing units and in
communication systems for
email applications, internet
access and networking.

2.2 LATCHES AND FLIP-FLOPS

❖ Latches and flip-flops both are bistable elements. These are the basic building
blocks of most sequential circuits.
❖ The main difference between latches and flip-flops is in the method used for
changing their state.
❖ We use the name flip-flop for a sequential device that normally samples its inputs
and changes its outputs only at times determined by clocking signal.
❖ On the other hand, we use the name latch for a sequential device that checks all
of its inputs continuously and changes its outputs accordingly at any time
 Digital Principles and System Design 2.5

independent of a clocking signal.

❖ Many times enable signal is provided with the latch.
❖ When enable signal is active output changes occur as input changes. But when
enable signal is not activated input changes do not affect output.

2.2.1 S-R Latch

❖ The simplest type of latch is the set-reset (SR) latch. It cannot be constructed from
either two NAND gates or two NOR gates.

Fig. 2.2 SR latch using NOR gates

❖ The SR latch using two NOR gates. As shown in the Fig. 2.2, the two NOR gates
are cross coupled so that the output of NOR gate I is connected to one of the inputs
of NOR gate 2 and vice versa.
❖ The latch has two outputs Q and Q and two inputs, set and reset. Before going to
analyze the SR latch, we recall that a logic 1 at any input of a NOR gate forces its
output to a logic 0.
❖ Let us understand the operation of this circuit for various input/output
possibilities.

CASE 1: S=1and R=0

❖ In this case, S input of the NOR gate 2 at logic 1, hence its output, Q is at logic
Both inputs to NOR gate 1 are now at logic So that its output, Q is at logic 1.
2.6 Synchronous Sequential Logic

CASE 2: S = 0 and R = 1
❖ In this case, R input of the NOR gate I is at logic 1, hence its output, Q is at logic
0.Both inputs to or gate 2 are now at logic.0. So that its output, Q is at logic 1.

CASE 3: S = 0 and R = 0
❖ Assume, Q = 1 and Q = 0
❖ Let us assume that initially Q = 1 and Q = 0. With Q = 0, neither inputs to NOR
gate I are at logic 0.
❖ So its output, Q is at logic 1, With Q = 1, one did not input of NOR gate 2 is at
logic 1, hence its output, Q is at logic 0.
❖ This shows that when S and R both are low (at logic 0) the output state does not
change.
❖ Assume, Q = 0 and = 1
❖ Let us make opposite assumption that Q= 0 and Q =1. With Q = 1, one input of
NOR gate 1 is at logic I hence its output Q is at logic 0. With Q = 0, both inputs
to NOR gate 2 are at logic 0.
❖ So its output Q is at logic 1.
❖ In this case also there is no change in the output state
CASE 4: S = 1 and R = 1
❖ When R and S both are at logic 1, they force the outputs of both NOR gates to the
low state
 Digital Principles and System Design 2.7

(Q= 0 and Q = 0).

❖ So we call this an indeterminate or prohibited state, and represent this condition
in the truth table as (×).
❖ This condition also violates the basic definition of a latch that requires Q to be the
complement of Q.
❖ Thus in normal operation this condition must be avoided by making sure that l are
not applied to both the inputs simultaneously.
S R Qn Qn+1 State
0 0 0 0 No change (NC)
0 0 1 1
S Q 0 1 0 0 Reset
0 1 1 0
R 𝑄ത
1 0 0 1 Set
1 0 1 1
1 1 0 × Indeterminate
1 1 1 ×
Fig. 2.3 (a) Symbol (b) Truth table
❖ Fig. 2.3 shows the symbol and truth table for SR latch.
❖ Summarize the operation of SR latch as follows
❖ With both inputs low, the output does not change and latch remains latched in its
last state. This condition is called inactive state because nothing changes.
❖ When R input is low and S input is high, the Q output of latch is set (at logic 1).
When R input is high and S input is low, the Q output. Of latch is reset (at logic
0). When R and S inputs both are high, output is unpredictable. This is called
indeterminate condition.
❖ An Application of the SR Latch a Switch Debouncer

2.2.2 Flip-Flops
❖ Flip-flops are the first stage in sequential logic design which incorporates memory
(storage of previous states).
❖ Flip-flops that we will look at include the following:
2.8 Synchronous Sequential Logic

❖ SR type Flip-flop or Set / Reset

❖ D type Flip-flop or Data / Delay
❖ JK type Flip-flop
❖ T type Flip-flop or Triggered /Toggle

2.2.2.1SR Flip-flop - (Set / Reset)

❖ This type of flip-flop has two inputs: Set and Reset. Two outputs: Q and Q' (Q'
being the inverse of Q).
❖ The SR flip-flop can also have a clock input for a level driven circuit as opposed
to a pulse driven circuit.

Fig. 2.4 Block diagram of SR Flip flop

❖ The operation of an SR flip-flop is as follows: The Set input will make Q go to 1
i.e. will 'set' the output.
❖ The Reset input will make the output Q go to 0 i.e. Reset the output.
❖ The scenario of having both Set and Reset at logic 1 is not allowed as this is not a
logical pair of inputs.
❖ Knowing the above, we can layout the operating characteristics and the state
change table
❖ The S-R flip-flop consists of two additional AND gates at the S and R inputs of
S-R latch as shown in fig 2.5
❖ In this circuit, when the clock input is LOW, the output of both the AND gates are
LOW and the changes in S and R inputs will not affect the output (Q) of the flip-
flop.
❖ When the clock input becomes HIGH, the value at S and R inputs will be passed
to the output of the AND gates and the output (Q) of the flip-flop will change
according to the changes in S and R inputs as long as the clock input is HIGH .
 Digital Principles and System Design 2.9

S Q

S-R flip flop

R 𝑄ത

Fig. 2.5 Block Diagram of SR Flip flop

❖ In the manner, one can strobe or clock the flip-flop so as to store either a 1 by
applying S=1, R=0 (i.e, set) or 0 by applying S=0, R=1 (i.e, reset) at any time and
then hold that bit of information for any desired period of time by applying a LOW
at the clock input.
❖ This flip-flop is called clocked S-R flip-flop.
❖ The S-R flip-flop which consists of the basic NAND latch and two other NAND
gates is shown in fig.2.6

Fig. 2.6 NAND based SR Flip flop

❖ The S and R inputs control the state of the flip-flop in the same manner as
described earlier for the basic (unlocked) S-R latch.
❖ However, the flip-flop does not respond to these inputs until the rising edge of the
clock signal occurs.
❖ The clock pulse input acts as an enable signal for the other two inputs.
❖ The outputs of NAND gates 1 and 2 stay at the logic 1 level as long as the clock
input remains at 0.
❖ This 1 level at the inputs of NAND based basic S-R latch retains the present state,
2.10 Synchronous Sequential Logic

i.e, no change occurs.

❖ The characteristic table of the S-R flip-flop is shown in truth table.
❖ This table shows the operation of the flip-flop in tabular form.

Present Clock pulse Data inputs Next state Action

state Qn CLK S R Qn+1
0 0 0 0 0 No change
1 0 0 0 1 No change
0 1 0 0 0 No change
1 1 0 0 1 No change
0 0 0 1 0 No change
1 0 0 1 1 No change
0 1 0 1 0 Reset
1 1 0 1 0 Reset
0 0 1 0 0 No change
1 0 1 0 1 No change
0 1 1 0 1 Set
1 1 1 0 1 Set
0 0 1 1 0 No change
1 0 1 1 1 No change
0 1 1 1 ? Forbidden
1 1 1 1 ? Forbidden

Case 1
❖ For S=0, R=0 and CLK=0, the flip-flop simply remains in its present state.
❖ That is, Q remains unchanged. Even for S=0, R=0 and CLK=1, the flip-flop
remains in its present state. This condition will not affect the outputs of flip-flop.
❖ The first four rows of the truth table clearly indicate that the state of the flip-flop
remains unchanged, i.e., 𝑄𝑛 + 1 = 𝑄𝑛.
 Digital Principles and System Design 2.11

Case 2
❖ For S=0, R=1 and CLK=0, the flip-flop remains in its present state.
❖ When CLK=1,the NAND gate 1 output will go to 1 and the NAND gate 2 output
will go to 0.
❖ Now, a 0 at NAND gate-4 inputs forces 𝑄ത = 1
❖ Which in turn results in NAND gate-3 output Q=0.
❖ Thus, for S=0, R=1 and CLK=1, the flip-flop RESETS to the 0 state.
Case 3
❖ For S=1, R=0 and CLK=0, the flip-flop remains in its present state.
❖ But for S=1, R=0 and CLK=1 the set state of the flip-flop is reached.
❖ This causes the NAND gate-1 output to go to 0 and the NAND gate-2 output to 1.
❖ Now a 0 at NAND gate-3 input forces Q to 1 which in turn forces NAND gate-4
output 𝑄ത to 0.
Case 4
❖ An inderminate condition occurs when all the inputs, namely CLK, S and R, are
equal to 1.
❖ This condition results in 0’s in the output of gate-1 and 2 and 1’s in both outputs
Q and 𝑄ത .
❖ When the CLK input goes back to 0 (while S and R remains at 1), it is not possible
to determine the next state, as it depends on wheather the output of gate-1 or gate-
2 goes to 1 first.
State diagram and Characteristics equations:
Set

Reset
0 1 Set

Reset

Fig. 2.7 State diagram of S-R Flip flop

❖ From the above state diagram the present and next state table and application or
excitation table for S-R flip-flop can be written as
2.12 Synchronous Sequential Logic

Present State SET input RESET input Next state

Qn S R Qn+1

0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 d
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 d

❖ Application or excitation table for S-R flip-flop

Qn Qn+1 Excitation Inputs
S R
0 0 0 D
0 1 1 0
1 0 0 1
1 1 d 0

❖ Using the above present state- next state table of S-R flip-flop, a k map for the
next state transition (Qn+1)

SR 00 01 11 10
Qn
0 0 0 d 1

1 1 0 d 1

From the above k-map, Qn+1 = S𝑅ത + 𝑅ത Qn

̅
Qn+1 = (S+ Qn)𝑹
 Digital Principles and System Design 2.13

2.2.2.2 D Flip-flop - (Delay)

❖ The D (delay) flip-flop has only one input called the delay (D) input and two
outputs Q and 𝑄ത .
❖ It can be constructed from an S-R flip-flop by insterting an inverter between S and
R and assigning the symbol D to the S input.
❖ The structure of D flip-flop is shown in fig. 2.8

Fig. 2.8 D Flip flop

❖ Basically, it consist of a NAND flip-flop with a gating arrangement on its inputs.it
operates as follows:
❖ When the CLK input is LOW, the D input has no effect, since the set and reset
inputs of the NAND flip-flop are kept HIGH.
❖ When the CLK goes HIGH, the Q output will take on the value of the D input,
❖ If CLK=1 and D=1,the NAND gate-1 output goes 0 which is the 𝑠̅ input of the
basic NAND based S-R flip-flop and NAND gate-2 output goes 1 which is the
𝑅ത input of the basic NAND based S-R flip-flop.
❖ Therefore, for 𝑆̅=0 and 𝑅ത =1, THE FLIP-FLOP output will be 1, i.e, it follows D
input.
❖ Similarly, for CLK=1and D=0, the flip-flop output will be 0.If D changes while
the CLK is HIGH,Q will follow and change quickly.
CLK Input Output
D Qn+1
0 d No Change
1 0 0
1 1 1
2.14 Synchronous Sequential Logic

State diagram and Characteristics equations:

D

̅
𝐷 0 1 D

̅
𝐷

❖ From the above state diagram the present and next state table and application or
excitation table for D flip-flop can be written as
Present State Delay input Next state
Qn D Qn+1

0 0 0
0 1 1
1 0 0
1 1 1

❖ Application or excitation table for D flip-flop

Qn Qn+1 Excitation
Inputs D
0 0 0
0 1 1
1 0 0
1 1 1

❖ Using the above present state- next state table of D flip-flop, a k map for the next
state transition (Qn+1)
D 0 1
Qn
0 0 1
1 0 1
From the above k-map, Qn+1 = D
 Digital Principles and System Design 2.15

2.2.2.3 J-K Flip-flop

❖ The SR Flip Flop or Set-Reset flip flop has lots of advantages. But, it has the
following switching problems:
❖ When Set 'S' and Reset 'R' inputs are set to 0, this condition is always avoided.
❖ When the Set or Reset input changes their state while the enable input is 1, the
incorrect latching action occurs.
❖ The JK Flip Flop removes these two drawbacks of SR Flip Flop.
❖ The JK flip flop is one of the most used flip flops in digital circuits.
❖ The JK flip flop is a universal flip flop having two inputs 'J' and 'K'.
❖ In SR flip flop, the 'S' and 'R' are the shortened abbreviated letters for Set and
Reset, but J and K are not.
❖ The J and K are themselves autonomous letters which are chosen to distinguish
the flip flop design from other types.
❖ The JK flip flop work in the same way as the SR flip flop work.
❖ The JK flip flop has 'J' and 'K' flip flop instead of 'S' and 'R'.
❖ The only difference between JK flip flop and SR flip flop is that when both inputs
of SR flip flop is set to 1, the circuit produces the invalid states as outputs, but in
case of JK flip flop, there are no invalid states even if both 'J' and 'K' flip flops are
set to 1.

Fig. 2.9 JK flip flop Using SR Flip flop

❖ The graphical symbol is shown in fig 2.9 and the truth table is shown below
2.16 Synchronous Sequential Logic

Inputs Output Action

CLK J K
x 0 0 Qn No
Change
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 𝑄ത 𝑛 Toggle

❖ The design of the JK flip – flop is such that the three inputs to one NAND gate
are J,
❖ Clock signal along with a feedback signal from Q’ and the three inputs to the other
NAND are K, clock signal along with a feedback signal from Q.
❖ This arrangement eliminates the indeterminate state in SR flip – flop.

Fig. 2.10 JK flip flop Using NAND gate

Case 1
❖ When both the inputs J and K are LOW, then Q returns its previous state value i.e.
it holds the previous data.
❖ When we apply a clock pulse to the J K flip flop and the J input is low then
irrespective of the other NAND gates, the NAND gate-1 output becomes HIGH.
❖ In the same manner, if the K input is low then output of NAND gate-2 is also
HIGH.
❖ So thus the output remains in the same state i.e. no change in the state of flip flop.
 Digital Principles and System Design 2.17

Case 2
❖ When J is LOW and K is HIGH, then flip flop will be in Reset state i.e. Q = 0, Q’
= 1.
❖ When we apply a clock pulse to the J K flip flop and the inputs are J is low and K
is high the output of the NAND gate connected to J input becomes 1.
❖ Then Q becomes 0. This will reset the flip flop again to its previous state.
❖ So the Flip flop will be in RESET state.
Case 3
❖ When J is HIGH and K is LOW, then flip – flop will be in Set state i.e. Q = 1, Q’
=0
❖ When we apply a clock pulse to the J K flip flop and the inputs are J is high and
K is low the output of the NAND gate connected to K input becomes 1.
❖ Then Q’ becomes 0. This will set the flip flop with the high clock input. So the
Flip flop will be in SET state.
Case 4
❖ When both the inputs J and K are HIGH, then flip – flop is in Toggle state.
❖ This means that the output will complement of the previous state.
Race around condition of JK Flip Flop
❖ For high inputs of J K flip flop, only the lower NAND gates are triggered by the
outputs that are compliment to each other i.e Q and Q’.
❖ So while high inputs are connected to flip – flop, at any instant, one gate is enabled
and other gate will be disabled.
❖ If the upper gate is in disabled state, it will drive the flip flop to SET state, later
when the lower gate is enabled, it will drive the flip flop to RESET state which
causes the toggling of output.
❖ This will cause the Race around condition in J K flip – flop.
Steps to avoid racing condition
❖ We can avoid the Race around condition by setting up the clock-on time less than
the propagation delay of the flip flop. It can be achieved by edge triggering.
❖ By making the flip flop to toggle over one clock period. This concept is introduced
in Master Slave J K flip flop.
2.18 Synchronous Sequential Logic

2.2.2.4 Master-Slave J-K Flip-flop

❖ A Master- Slave flip-flop can be constructed using two J-K flip-flops.
❖ The first flip-flop, called the master, is driven by the positive edge of the clock
pulse, the second flip-flop, called the Slave, is driven by the negative edge of the
clock pulse.
❖ Therefore, when the clock input has a positive edge, the master acts according to
its J-K inputs, but the slave does not respond since it requires a negative edge at
the clock input.
❖ When the clock input has a negative edge, the slave flip-flop copies the master
outputs.
❖ But the master does not respond to the feedback from Q and 𝑄ത .
❖ Since it requires a positive edge at its clock input. Thus, the master- slave flip-flop
does not have race-around problem.

Fig.2.11 Master – slave J-K flip-flop

❖ A master-slave J-K flip-flop constructed using NAND gates.
❖ It consists of two flip-flops connected in series. NAND gate-1 through 4 from the
master flip-flop and NAND gate 5 through 8 from the slave flip-flop.
❖ When the clock is positive, a charge in J and K inputs cause a change of state in
the master flip-flop.
❖ During this period, the slave retains its previous state and serves as a buffer
between the master and the output.
❖ When the clock goes negative, the master flip-flop does not respond. I.e. it
maintains its previous state, While the Slave flip-flop is enabled and changes its
state to that of the, master flip-flop.
 Digital Principles and System Design 2.19

❖ The new state of the slave then becomes the state of the entire master slave flip-
flop.
❖ The operation of master-slave J-K flip- flop for different J-K input combinations
can be explained as follows.

Fig.2.12 NAND gate using Clocked Master – slave J-K flip-flop

❖ Case 1: If J=1 and K=0 the master flip-flop sets on the positive clock edge. The
HIGH Q(1) output of the master drives the input (J) of the Slave . So, when the
negative clock edge hits, the slave also sets. The slave flip-flop copies the action
of the master flip-flop.
❖ Case 2: If J=0 and K=1, the master resets on the leading edge of the CLK pulse.
The HIGH 𝑄ത output of the master drives the input (K) of the slave flip-flop. Then
the above flip-flop resets at the arrival of the trailing edge of the CLK pulse. Once
again the slave flip-flop copies the action of the master flip-flop.
❖ Case 3: If J=K=1, the master flip-flop toggles on the positive clock edge and the
slave toggles on the negative clock edge. The condition J=K=0 input does not
produce any change.
❖ Master –Slave flip-flop operate from a complete clock pulse, and the outputs
change on the negative transition.

2.2.2.5 T Flip- Flop

❖ Another basic flip-flop, called the T or trigger or toggle flip-flop, has only a single
data (T) input, a clock input and two outputs Q and ̅ 𝑄.
❖ The T-type flip-flop is obtained from a J-K flip-flop by connecting its J and K
inputs together.
❖ The designation T comes from the ability of the flip-flop to ”toggle” or
2.20 Synchronous Sequential Logic

complement its state.

❖ The block diagram of a T flip-flop and its circuit implementation using a J-K flip-
flop are shown in Fig. 2.13.

Fig.2.13 T flip-flop using a J-K flip flop

❖ The J and K inputs are wired together. The truth table for T flip-flop is shown
below.
Qn T Qn+1
0 0 0
0 1 1
1 0 1
1 1 0

❖ When the T input is in the 0 state (i.e. J=K=0) prior to a clock pulse, the Q output
will not change with clocking.
❖ When the T inputs is at a 1 (i.e. J=K=1) level prior to clocking, the output will be
in the 𝑄ത state after clocking.
❖ In other words, if the T input is a logical 1 and the device is clocked, the output
will change state regardless of what output was prior to clocking.
❖ This is called toggling hence the name T flip-flop.
❖ The truth table shown that when T=0, then𝑄𝑛+1 = 𝑄𝑛 , i.e., the next state is the
same as the present state and no change occurs.
❖ When T=1, then 𝑄𝑛+1 = 𝑄ത𝑛 , i.e. the state of the flip-flop is complemented.
State Diagram and Characteristic Equation of T Flip-flop
❖ The state transition diagram for the Trigger flip-flop is shown in fig. 2.14
❖ It is clear that when T=1, the flip-flop changes or toggles its state irrespective of
its previous state; when T=1 and 𝑄𝑛 =0, the next state will be 1; when T=1 and
 Digital Principles and System Design 2.21

𝑄𝑛 =1, the next state will be 0.

𝑇ത 0 1 T

𝑇ത

Fig2.14 State diagram of trigger flip-flop

❖ Similarly, one can under-stand that when T=0, the flip-flop retains its previous
state.
❖ From the above state diagram, one can draw the present state-next state table and
application or excitation table for the Trigger flip-flop as shown below.
Present State input Next state
Qn T Qn+1

0 0 0
0 1 1
1 0 1
1 1 0

Qn Qn+1 Excitation
Inputs T
0 0 0
0 1 1
1 0 1
1 1 0

❖ The K-map for the next state (𝑄𝑛+1) of trigger flip-flop can be drawn as shown
below and the simplified expression for 𝑄𝑛+1 can be found as follows.
❖ The characteristic equation for trigger flip-flop is 𝑄𝑛+1 = 𝑇𝑄ത𝑛 + 𝑇ത𝑄𝑛
❖ So, in a trigger flip-flop, the next state will be the complement of the previous
state when T=1.
2.22 Synchronous Sequential Logic

T 0 1
Qn
0 0 1
1 1 0

2.3 TRIGGERING OF FLIP – FLOPS

❖ Flip-flops are synchronous bistable devices.
❖ The term synchronous means that the changes in the output occur at a specified
point on a triggering input called the clock.
❖ That is, changes in the output occur in synchronization (in time) with the clock.
❖ Based on the specific interval or point in the clock during or at which triggering
of flip –flop takes place, it can be classified into two different types.
I. Level Triggering
II. Edge Triggering
❖ A clock pulse starts from an initial value of 0, goes momentarily to 1, and after a
short time, returns to its initial 0 value.
2.3.1 Level Triggering in Flip - Flops
❖ During clocked S – R flip – flop, it was shown that the clock input triggers the flip
– flop, i.e. enables the flip – flop, when the clock pulse goes HIGH, and the flip
– flop is said to be level triggered flip – flop.
❖ Since the flip – flop changes its state when the clock is positive, it is termed as
positive level triggered flip – flop.
❖ If NOT gate is introduced in between the clock input and the input of AND gate,
then the flip – flop changes its state only when the clock is negative (i.e, when
clock = LOW), and it is called negative level triggered flip – flop.
❖ The main drawback of level triggering is that, as long as the clock is positive or
negative, the flip – flop changes its state more than once or many times for the
change in inputs.
❖ If the inputs are made stable for the entire clock duration, then the output changes
only once.
❖ When the clock becomes unasserted (i.e. clock = 0) the output of flip – flop reflects
 Digital Principles and System Design 2.23

the last change in its input.

❖ This can be overcome in Master - Slave flip – flops where the flip – flops changes
state only once for a clock.

2.3.2 Edge Triggering In Flip – Flops

❖ A clock pulse goes through two signal transitions from 0 to 1 and returns from 1
to 0.
❖ As shown in Fig. 2.15, as positive transition is defined as the positive edge and
the negative transition as the negative edge.
❖ This definition applies also to negative pulses.
❖ The term edge – triggered means that the flip – flop changes its state either at the
positive edge (rising or leading ) or at the negative edge (falling or trailing edge)
of the clock pulse and is sensitive to its inputs only at this transition of the Clock.

Fig2.15 Transition of Clock pulse

2.4 REALISATION OF ONE FLIP-FLOP USING OTHER FLIP-

FLOPS
❖ It is possible to implement a flip- flop circuit using any other flip-flop.
❖ To realize a flip-flop (X) using flip-flop(Y), the flip-flop (Y) along with a
combinational circuit, called NEXT state decoder, used which functions like flip-
flop (X).
❖ For this to be realized, for each set o inputs of flip-flop (X) .i.e. A&B and present
state (𝑄𝑛 ), we have to find the inputs to the flip-flop (Y) i.e. C & D, that will cause
the flip-flop (Y) to make transition into the proper next state(𝑄𝑛+1)of the flip-flop
(X) .
❖ These inputs to flip-flop (Y) are called the next state code.
❖ The design procedure for such realization can be summarized in the following
steps:
2.24 Synchronous Sequential Logic

i. Obtain a clear word description of the desired flip-flop(X).

ii. Obtain a Present State-Next State (PS-NS) table for the desired flip-flop(X).
iii. Using the excitation table or application table of the chosen flip-flop(Y)
append the next state code or the excitation input values to the above present
state-next table.
iv. Using K-maps, simplify the logic expressions for excitation inputs of flip-flop
(Y) and design the next state decoder logic.
v. Draw a circular for the desired flip-flop (X) using next state decoder logic and
the chosen flip-flop (Y).

2.4.1 Realization of Delay Flip-Flop using S-R Flip – flop

❖ Consider the realization of Delay flip-flop using S-R flip-flop.
❖ Here, the desired flip-flop (X) is delay flip-flop and the chosen flip-flop(Y) is S-
R flip-flop. The basic block diagram is shown in fig.2.16.

Fig2.16 Block diagram of D Flip flop using S-R flip flop

Step- 1 The operation of Delay flip-flop is well known and hence there is no need for
word description.
Step 2 The Present State-Next state table for D flip-flop can be drawn as shown in
Table.
Present State Delay input Next state
Qn D Qn+1

0 0 0
0 1 1
1 0 0
1 1 1
 Digital Principles and System Design 2.25

Step 3 Using the application table of S-R flip-flop is given in Table, the next state
codes i.e. S & R values can be augmented in the above PS-Ns table as shown in Table.
Step 4 In this step, one can design the next state decoder, i.e. the simplified expressions
for S and R, from the excitation map as shown in figure.
D 0 1
D 0 1
Qn
Qn
0 0 1
0 d 0

1 0 1
1 1 0

S=D ̅
𝑅=𝐷

Step 5 From the above step, S=D and R=𝐷 ̅ .Now the circuit for delay flip-flop using S-
R flip-flop can be drawn as shown in figure. 2.17, with a single NOT gate in the next state
decoder logic. Note that the designed circuit confirms with the earlier connection of the
delay flip-flop using S-R flip-flop.
Qn D Qn+1 Excitation
Inputs
S R
0 0 0 0 d
0 1 1 1 0
1 0 0 0 1
1 1 1 d 0

Fig2.17 D flip-flop using S-R flip-flop

2.26 Synchronous Sequential Logic

2.5 COUNTERS
❖ A counter is a register capable of counting the number of clock pulses arriving at
its clock input.
❖ Specified sequence of states appears as the counter output.
❖ This is the main difference between a register and a counter.
❖ A specified sequence of states is different for different types of counters.
❖ There are two types of counters, synchronous and asynchronous.
❖ In synchronous counter, the common clock input is connected to all of the flip-
flops and thus they are clocked simultaneously.
❖ In asynchronous counter, commonly called, ripple counters, the first flip- flop is
clocked by the external clock pulse and then each successive flip-flop is clocked
by the 0 or Q output of the previous flip-flop.
❖ Therefore in an asynchronous counter, the flip-flops are not clocked
simultaneously.

2.5.1 Synchronous Counters

❖ Synchronous counters are simple state machines made out of flip flops and logic
gates.
❖ They have two parts, a register made out of flip flops and a decoder made out of
logic gates.
❖ A register is a simple group of flip flops that are all clocked at the same time.
❖ In this way they can hold the counters output value until the next clock cycle.
❖ The decoder, decodes the current count and generates the correct value for the
next count to the flop flops.
❖ For example in a simple up counter the decoder would always output the current
count plus one.
❖ The major advantage of Synchronous Counters is that all the bits of their output
change at the same time.
❖ In a synchronous counter, also known as a parallel counter, all the flip-flops in the
counter change state at the same time in synchronism with the input clock signal.
❖ The clock signal in this case is simultaneously applied to the clock inputs of all
the flip-flops.
 Digital Principles and System Design 2.27

❖ The delay involved in this case is equal to the propagation delay of one flip-flop
only, irrespective of the number of flip-flops used to construct the counter.
❖ In other words, the delay is independent of the size of the counter.

2.5.1.1 Binary 4-bit Synchronous Up Counter

Figure 2.18 3-bit Synchronous Up Counter

❖ It can be seen above, that the external clock pulses (pulses to be counted) are fed
directly to each of the J-K flip-flops in the counter chain and that both the J and K
inputs are all tied together in toggle mode, but only in the first flip-flop, flip-flop
FFA (LSB) are they connected HIGH, logic ―1 allowing the flip-flop to toggle
on every clock pulse.
❖ Then the synchronous counter follows a predetermined sequence of states in
response to the common clock signal, advancing one state for each pulse.
❖ The J and K inputs of flip-flop FFB are connected directly to the output QA of flip-
flop FFA, but the J and K inputs of flip-flops FFC and FFD are driven from
separate AND gates which are also supplied with signals from the input and
output of the previous stage.
❖ These additional AND gates generate the required logic for the JK inputs of the
next stage.
❖ If we enable each JK flip-flop to toggle based on whether or not all preceding flip-
flop outputs (Q) are ―HIGH we can obtain the same counting sequence as with
the asynchronous circuit but without the ripple effect, since each flip-flop in this
circuit will be clocked at exactly the same time.
2.28 Synchronous Sequential Logic

❖ Then as there is no inherent propagation delay in synchronous counters, because

all the counter stages are triggered in parallel at the same time, the maximum
operating frequency of this type of frequency counter is much higher than that for
a similar asynchronous counter circuit.

Fig. 2.19 4-bit Synchronous Counter Waveform Timing Diagram.

❖ Because this 4-bit synchronous counter counts sequentially on every clock pulse
the resulting outputs count upwards from 0 ( 0000 ) to 15 ( 1111 ).
❖ Therefore, this type of counter is also known as a4-bit Synchronous Up Counter.
❖ However, we can easily construct a 4-bit Synchronous Down Counter by
connecting the AND gates to the Q output of the flip-flops as shown to produce a
waveform timing diagram the reverse of the above.
❖ Here the counter starts with all of its outputs HIGH ( 1111 ) and it counts down
on the application of each clock pulse to zero, ( 0000 ) before repeating again.

2.5.1.2 Binary 4-bit Synchronous Down Counter

❖ As synchronous counters are formed by connecting flip-flops together and any
number of flip- flops can be connected or cascaded together to form a divide-
by-n binary counter, the modulo‘s or MOD number still applies as it does
for asynchronous counters so a Decade counter or BCD counter with counts
from 0 to 2n-1 can be built along with truncated sequences.
 Digital Principles and System Design 2.29

Figure 2.20 4-bit Synchronous Down Counter

❖ All we need to increase the MOD count of an up or down synchronous counter is
an additional flip-flop and AND gate across it.

2.5.1.3 Ripple (Asynchronous) Counter

❖ Ripple counters are the simplest type of counters.
❖ They are nothing more than toggle flip flops connected in a chain to divide each
other’s output frequency by two. The result is a binary count.
❖ They are called ripple counters because the new count ripples through them.
❖ The major disadvantage of ripple counters is that because of new count "rippling"
through the flip flops all the bits of the count arrive at different times.
❖ A ripple counter is a cascaded arrangement of flip- flops where the output of one
flip-flop drives the clock input of the following flip-flop.
❖ The number of flip-flops in the cascaded arrangement depends upon the number
of different logic states that it goes through before it repeats the sequence, a
parameter known as the modulus of the counter.
❖ In a ripple counter, also called an asynchronous counter or a serial counter, the
clock input is applied only to the first flip-flop, also called the input flip-flop, in
the cascaded arrangement.
❖ The clock input to any subsequent flip-flop comes from the output of its
immediately preceding flip-flop.
❖ For instance, the output of the first flip-flop acts as the clock input to the second
flip-flop, the output of the second flip-flop feeds the clock input of the third flip-
flop and so on.
2.30 Synchronous Sequential Logic

❖ In general, in an arrangement of n flip-flops, the clock input to the nth flip-flop

comes from the output of the (n−1) th flip-flop for n>1.

Figure 2.21 Generalized block schematic of n-bit binary ripple counter

❖ Figure 2.21 shows the generalized block schematic arrangement of an n-bit binary
ripple counter.
❖ As a natural consequence of this, not all flip-flops change state at the same time.
❖ The second flip-flop can change state only after the output of the first flip-flop has
changed its state.
❖ That is, the second flip-flop would change state a certain time delay after the
occurrence of the input clock pulse owing to the fact that it gets its own clock
input from the output of the first flip-flop and not from the input clock.
❖ This time delay here equals the sum of propagation delays of two flip-flops, the
first and the second flip-flops.
❖ In general, the nth flip-flop will change state only after a delay equal ton times the
propagation delay of one flip-flop.
❖ The term ‘ripple counter’ comes from the mode in which the clock information
ripples through the counter.
❖ It is also called an ‘asynchronous counter’ as different flip-flops comprising the
counter do not change state in synchronization with the input clock.
❖ In a counter like this, after the occurrence of each clock input pulse, the counter
has to wait for a time period equal to the sum of propagation delays of all flip-
flops before the next clock pulse can be applied.
❖ The propagation delay of each flip-flop, of course, will depend upon the logic
family to which it belongs.
 Digital Principles and System Design 2.31

2.5.1.4 Binary Ripple Counter

❖ The operation of a binary ripple counter can be best explained with the help of a
typical counter of this type.
❖ Figure 2.22 (a) shows a four-bit ripple counter implemented with negative edge-
triggered J-K flip-flops wired as toggle flip-flops.
❖ The output of the first flip-flop feeds the clock input of the second, and the output
of the second flip-flop feeds the clock input of the third, the output of which in
turn feeds the clock input of the fourth flip-flop.
❖ The outputs of the four flip-flops are designated asQ0 (LSB flip-flop), Q1, Q2 and
Q3 (MSB flip-flop).
❖ Figure 2.22(b) shows the waveforms appearing atQ0, Q1, Q2 and Q3 outputs as the
clock signal goes through successive cycles of trigger pulses.
❖ The counter functions as follows.
❖ Let us assume that all the flip-flops are initially cleared to the ‘0’ state.

Figure 2.22 (a), (b) four-bit binary ripple counter.

2.32 Synchronous Sequential Logic

❖ On HIGH-to-LOW transition of the first clock pulse, Q0 goes from ‘0’ to ‘1’ owing
to the toggling action.
❖ As the flip-flops use dare negative edge-triggered ones, the ‘0’ to ‘1’ transition of
Q0 does not trigger flip-flop FF1. FF1, along with FF2 and FF3, remains in its ‘0’
state.
❖ So, on the occurrence of the first negative-going clock transition, Q0= 1, Q1= 0,
Q2= 0 and Q3= 0.
❖ On the HIGH-to-LOW transition of the second clock pulse, Q0 toggles again.
❖ That is, it goes from ‘1’ to ‘0’.
❖ This ‘1’ to ‘0’ transition at the Q0 output triggers FF1, the output Q1 of which
goes from ‘0’ to ‘1’.
❖ The Q2 and Q3 outputs remain unaffected.
❖ Therefore, immediately after the occurrence of these condition HIGH-to-LOW
transition of the clock signal, Q0= 0, Q1= 1, Q2= 0 and Q3= 0.
❖ On similar lines, we can explain the logic status of Q0, Q1, Q2 and Q3 outputs
immediately after subsequent clock transitions.
❖ Thus, we see that the counter goes through 16 distinct states from 0000 to 1111
and then, on the occurrence of the desired transition of the sixteenth clock pulse,
it resets to the original state of 0000from where it had started.

2.5.1.5 UP/DOWN Counters

❖ Counters are also available in integrated circuit form as UP/DOWN counters,
which can be made to operate as either UP or DOWN counters.
❖ An UP counter is one that counts upwards or in the forward direction by one LSB
every time it is clocked.
❖ A four-bit binary UP counter will count as 0000, 0001, 0010, 0011, 0100, 0101,
0110, 0111, 1000, 1001, 1010, 1011,1100, 1101, 1110, 1111, 0000, 0001, _ _ _
and so on.
❖ A DOWN counter counts in the reverse direction or downwards by one LSB every
time it is clocked.
❖ The four-bit binary DOWN counter will count as 0000, 1111, 1110, 1101, 1100,
1011, 1010, 1001, 1000, 0111, 0110, 0101, 0100, 0011, 0010, 0001, 0000, 1111,
_ _ _ and so on.
 Digital Principles and System Design 2.33

❖ Some counter ICs have separate clock inputs for UP and DOWN counts, while
others have a single clock input and an UP/DOWN control pin.
❖ The logic status of this control pin decides the counting mode.
❖ As an example, ICs 74190 and 74191 are four-bit UP/DOWN counters in the TTL
family with a single clock input and an UP/DOWN control pin.
❖ While IC 74190 is a BCD decade counter, IC74191 is a binary counter.
❖ Also, ICs 74192 and 74193 are four-bit UP/DOWN counters in the TTL family,
with separate clock input terminals for UP and DOWN counts.
❖ While IC 74192 is a BCD decade counter, IC 74193 is a binary counter.

Figure 2.23 3 bit UP/DOWN Counter

Figure2.24 3 bit UP/DOWN counter with a common clock input

❖ Figure 2.23 shows a three-bit binary UP/DOWN counter. This is only one possible
logic arrangement.
❖ As we can see, the counter counts upwards when UP control is logic ‘1’ and
DOWN control is logic ‘0’.
2.34 Synchronous Sequential Logic

❖ In this case the clock input of each flip-flop other than the LSB flip-flop is fed
from the normal output of the immediately preceding flip-flop.
❖ The counter counts downwards when the UP control input is logic ‘0’ and DOWN
control is logic ‘1’.
❖ In this case, the clock input of each flip-flop other than the LSB flip-flop is fed
from the complemented output of the immediately preceding flip-flop.
❖ Figure 2.24 shows another possible configuration for a three-bit binary ripple
UP/DOWN counter.
❖ It has a common control input. When this input is in logic ‘1’ state the counter
counts downwards, and when it is in logic ‘0’ state it counts upwards.

2.5.1.6 Modulus of a Counter

❖ The modulus (MOD number) of a counter is the number of different logic states
it goes through before it comes back to the initial state to repeat the count
sequence.
❖ An n-bit counter that counts through all its natural states and does not skip any of
the states has a modulus of 2n.
❖ We can see that such counters have a modulus that is an integral power of 2, that
is, 2, 4, 8, 16 and so on.
❖ These can be modified with the help of additional combinational logic to get a
modulus of less than 2n.
❖ To determine the number of flip-flops required to build a counter having a given
modulus, identify the smallest integer m that is either equal to or greater than the
desired modulus and is also equal to an integral power of 2.
❖ For instance, if the desired modulus is 10, which is the case in a decade counter,
the smallest integer greater than or equal to 10 and which is also an integral power
of 2 is16.
❖ The number of flip-flops in this case would be 4, as 16 = 24. On the same lines,
the number of flip-flops required to construct counters with MOD numbers of 3,
6, 14, 28 and 63 would be 2, 3, 4, 5and 6 respectively.
❖ In general, the arrangement of a minimum number of N flip-flops can be used to
construct any counter with a modulus given by the equation
2𝑛 ≥ N ≥2𝑛−1
 Digital Principles and System Design 2.35

2.6 DESIGNING COUNTERS WITH ARBITRARY SEQUENCES

❖ A large variety of synchronous and asynchronous counters are available in IC
form, and some of these have been mentioned and discussed in the previous
sections.
❖ The counters discussed previously count in either the normal binary sequence with
a modulus of 2N or with slightly altered binary sequences where one or more of
the states are skipped.
❖ The latter type of counter has a modulus of less than 2N, N being the number of
flip-flops used.
❖ Nevertheless, even these counters have a sequence that is either upwards or
downwards and not arbitrary.
❖ There are applications where a counter is required to follow a sequence that is
arbitrary and not binary.
❖ As an example, an MOD-10 counter may be required to follow the sequence 0000,
0010, 0101, 0001, 0111, 0011, 0100, 1010, 1000, 1111, 0000, 0010 and so on.
❖ In such cases, the simple and seemingly obvious feedback arrangement with a
single NAND gate discussed in the earlier sections of this chapter for designing
counters with a modulus of less than 2N cannot be used.
❖ There are several techniques for designing counters that follow a given arbitrary
sequence.
❖ In the present section, we will discuss in detail a commonly used technique for
designing synchronous counters using J-K flip-flops or D flip-flops.
❖ The design of the counters basically involves designing a suitable combinational
logic circuit that takes its inputs from the normal and complemented outputs of
the flip-flops used and decodes the different states of the counter to generate the
correct logic states for the inputs of the flip-flops such as J, K, D, etc.
❖ But before we illustrate the design procedure with the help of an example, we will
explain what we mean by the excitation table of a flip-flop and the state transition
diagram of a counter.
❖ An excitation table in fact can be drawn for any sequential logic circuit, but, once
we understand what it is in the case of a flip-flop, which is the basic building block
of sequential logic, it would be much easier for us to draw the same for more
complex sequential circuits such as counters, etc.
2.36 Synchronous Sequential Logic

2.6.1 Excitation Table of a Flip-Flop

❖ The excitation table is similar to the characteristic table that we discussed in the
previous chapter on flip-flops.
❖ The excitation table lists the present state, the desired next state and the flip-flop
inputs (J, K, D, etc.) required to achieve that.
❖ if the output is in the logic ‘0’ state and it is desired that it goes to the logic ‘1’
state on occurrence of the clock pulse, the J input must be in the logic ‘1’ state and
the K input can be either in the logic ‘0’ or logic ‘1’ state.
❖ This is true as, for a ‘0’ to ‘1’ transition, there are two possible input conditions
that can achieve this.
❖ These are J = 1, K = 0 (SET mode) and J = K = 1 (toggle mode), which further
leads to J = 1, K = X (either 0or 1).
❖ The other entries of the excitation table can be explained on similar lines.
❖ In the case of a D flip-flop, the D input is the same as the logic status of the desired
next state.
❖ This is true as, in the case of a D flip-flop, the D input is transferred to the output
on the occurrence of the clock pulse, irrespective of the present logic status of the
Q output.

2.6.2 State Transition Diagram

❖ The state transition diagram is a graphical representation of different states of a
given sequential circuit and the sequence in which these states occur in response
to a clock input.
❖ Different states are represented by circles, and the arrows joining them indicate
the sequence in which different states occur.

Figure 2.25 State transition diagram for an MOD 8 binary counter

 Digital Principles and System Design 2.37

❖ As an example, Fig. 2.25 shows the state transition diagram of an MOD-8 binary
counter.

2.6.3 Design Procedure

❖ We will illustrate the design procedure with the help of an example.
❖ We will do this for an MOD-6synchronous counter design, which follows the
count sequence 000, 010, 011, 001, 100, 110, 000,010, _ _ _ :
❖ Determine the number of flip-flops required for the purpose.
❖ Identify the undesired states. In the present case, the number of flip-flops required
is 3 and the undesired states are 101 and 111
❖ Draw the state transition diagram showing all possible states including the ones
that are not desired.
❖ The undesired states should be depicted to be transiting to any of the desired states.
❖ We have chosen the 000 state for this purpose.
❖ It is important to include the undesired states to ensure that, if the counter
accidentally gets into any of these undesired states owing to noise or power-up,
the counter will go to a desired state to resume the correct sequence on application
of the next clock pulse.
STEP1 State diagram
❖ Now, the state diagram for the MOD-6 counter can be drawn as shown in fig.2.26.
❖ Here, it is assumed that the state transition from one state to another takes place
when the clock pulse is asserted; when the clock is unasserted, the counter remains
in the present state.

f b

e
c
d
Figure 2.26 shows the state transition diagram
2.38 Synchronous Sequential Logic

STEP2 State table

❖ From the above state diagram, one can draw PS-NS table
Present State (PS) Next State (NS)
a b
b c
c d
d e
e f
f a

❖ The state table given in above Table has no redundant state because no two states
are equivalent.
❖ Hence, there is no modification required in the given state table.
STEP 3 State assignment
❖ Let us assign two state variables to states a, b, c, d, e, and f as follows:
a=000, b=001, c=010, d=011, e=100 and f=101. Then, the PS-NS table
gets modified as shown in Table.

Present State (PS) Next State (NS)

q2 q1 q0 Q2 Q1 Q0
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 0 0 0
1 1 0 d d d
1 1 1 d d d
 Digital Principles and System Design 2.39

STEP4 Excitation table

❖ Although any one of the four flip-flops, i.e. SR, JK, T and D can be used,
❖ The selection of J-K flip-flop will result in a simplified circuit for synchronous
counters.
❖ The excitation table having entries for flip-flop inputs (𝐽1 ,𝐾1 and𝐽0 ,𝐾0 ) can be
drawn from the above PS-NS table (and using the application table of JK Flip-
flop given in Table) as shown below gives the excitation values of MOD-6
counter.
Present State (PS) Next State (NS) Excitation Inputs
q2 q1 q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
0 0 0 0 0 1 0 d 0 d 1 d
0 0 1 0 1 0 0 d 1 d d 1
0 1 0 0 1 1 0 d d 0 1 d
0 1 1 1 0 0 1 d d 1 d 1
1 0 0 1 0 1 d 0 0 d 1 d
1 0 1 0 0 0 d 1 0 d d 1
1 1 0 d d d d d d d d d
1 1 1 d d d d d d d d d

STEP 5 Excitation maps

❖ The excitation maps for J2, K2, 𝐽1 ,𝐾1, 𝐽0 AND 𝐾0 inputs of the counter can be
drawn as shown in Fig. 2.27 from the excitation table.

q2q1 00 01 11 10 q2q1 00 01 11 10
q0 q0
0 0 0 d d 0 d d d 0

1 0 1 d d 1 d d d 1

For J2 For K2
J2 = q1q0 K2 = q0
2.40 Synchronous Sequential Logic

q2q1 00 01 11 10 q2q1 00 01 11 10
q0 q0
0 0 d d 0 0 d 0 d d

1 1 d d 0 1 d 1 d d

For J1 For K1
J1 = 𝑞ത 2q0 K1 = q0

SR 00 01 11 10 SR 00 01 11 10
Qn Qn
0 1 1 d 1 0 d d d d

1 d d d d 1 1 1 d 1

For J0 For K0
J0 = 1 K1 = 1

STEP 6 Schematic diagram

❖ Using the above excitation equations, the circuit diagram for the MOD 6 counter
can be drawn as below Fig. 2.27

Figure 2.27 Circuit diagram for MOD-6 Synchronous counter

 Digital Principles and System Design 2.41

2.7 SHIFT REGISTER

❖ A shift register is a digital device used for storage and transfer of data.
❖ The data to be stored could be the data appearing at the output of an encoding
matrix before they are fed to the main digital system for processing or they might
be the data present at the output of a microprocessor before they are fed to the
driver circuitry of the output devices.
❖ The shift register thus forms an important link between the main digital system
and the input/output channels.
❖ The shift registers can also be configured to construct some special types of
counter that can be used to perform a number of arithmetic operations such as
subtraction, multiplication, division, complementation, etc.
❖ The basic building block in all shift registers is the flip-flop, mainly a D- type flip-
flop.
❖ Although in many of the commercial shift register ICs their internal circuit
diagram might indicate the use of R-S flip-flops, a careful examination will reveal
that these R- S flip-flop shave been wired as D flip-flops only.
❖ The storage capacity of a shift register equals the total number of bits of digital
data it can store, which in turn depends upon the number of flip-flops used to
construct the shift register.
❖ Since each flip-flop can store one bit of data, the storage capacity of the shift
register equals the number of flip-flops used.
❖ As an example, the internal architecture of an eight-bit shift register will have a
cascade arrangement of eight flip- flops.
❖ Based on the method used to load data onto and read data from shift registers, they
are classified as serial-in serial-out (SISO) shift registers, serial-in parallel-out
(SIPO) shift registers, parallel-in serial-out (PISO) shift registers and parallel-in
parallel-out (PIPO) shift registers.

2.7.1 Serial-In Serial-Out Shift Register

❖ The following fig. 2.28 shows the basic four-bit serial-in serial-out shift register
implemented using D flip- flops.
❖ The circuit functions as follows. A reset applied to the CLEAR input of all the
flip-flops resets their Q outputs to 0s. Refer to the timing waveforms of Fig. 2.29.
2.42 Synchronous Sequential Logic

Figure 2.28 SISO shift register

Figure 2.29 Timing waveforms for the shift register

❖ The waveforms shown include the clock pulse train, the waveform representing
the data to be loaded onto the shift register and the Q outputs of different flip-
flops.
❖ The flip-flops shown respond to the LOW-to-HIGH transition of the clock pulses
as indicated by their logic symbols. During the first clock transition, the QA output
goes from logic ‘0’ to logic ‘1’.

2.7.2 Serial-In Parallel-Out Shift Register

❖ A serial-in parallel-out shift register is architecturally identical to a serial-in serial-
out shift register except that in the case of the former all flip-flop outputs are also
brought out on the IC terminals.
❖ The gated serial inputs A and B control the incoming serial data, as a logic LOW
 Digital Principles and System Design 2.43

at either of the inputs inhibits entry of new data and also resets the first flip-flop
to the logic LOW level at the next clock pulse.
❖ Logic HIGH at either of the inputs enables the other input, which then determines
the state of the first flip-flop.
❖ Data at the serial inputs may be changed while the clock input is HIGH or LOW,
and the register responds to LOW-to-HIGH transition of the clock.

2.7.3 Parallel-In Serial-Out Shift Register

❖ We will explain the operation of a parallel-in serial-out shift register with the help
of the logic diagram of a practical device available in IC form.
❖ The parallel-in or serial-in modes are controlled by a SHIFT/LOAD input.
❖ When the SHIFT/LOAD input is held in the logic HIGH state, the serial data input
AND gates are enabled and the circuit behaves like a serial-in serial- out shift
register.
❖ When the SHIFT/LOAD input is held in the logic LOW state, parallel data input
AND gates are enabled and data are loaded in parallel, in synchronism with the
next clock pulse. Clocking is accomplished on the LOW-to-HIGH transition of
the clock pulse via a two- input NOR gate.
❖ Holding one of the inputs of the NOR gate in the logic HIGH state inhibits the
clock applied to the other input.
❖ Holding an input in the logic LOW state enables the clock to be applied to the
other input. An active LOW CLEAR input overrides all the inputs, including the
clock, and resets all flip-flops to the logic ‘0’ state.

2.7.4 Parallel-In Parallel-Out Shift Register

❖ The hardware of a parallel-in parallel-out shift register is similar to that of a
parallel-in serial- out shift register.
❖ If in a parallel-in serial-out shift register the outputs of different flip-flops are
brought out, it becomes a parallel-in parallel-out shift register.
❖ In fact, the logic diagram of a parallel-in parallel-out shift register is similar to that
of a parallel-in serial-out shift register.
❖ As an example, IC74199 is an eight-bit parallel-in parallel-out shift register.
2.44 Synchronous Sequential Logic

2.8 SHIFT REGISTER COUNTERS

❖ We have seen that both counters and shift registers are some kinds of cascade
arrangement of flip-flops.
❖ A shift register, unlike a counter, has no specified sequence of states. However, if
the serial output of the shift register is fed back to the serial input, we do get a
circuit that exhibits a specified sequence of states.
❖ The resulting circuits are known as shift register counters. Depending upon the
nature of the feedback, we have two types of shift register counter, namely the
ring counter and the shift counter, also called the Johnson counter.

2.8.1 Ring Counter

❖ A ring counter is obtained from a shift register by directly feeding back the true
output of the output flip-flop to the data input terminal of the input flip-flop.
❖ If D flip-flops are being used to construct the shift register, the ring counter, also
called a circulating register, can be constructed by feeding back the Q output of
the output flip-flop back to the D input of the input flip-flop.
❖ If J-K flip-flops are being used, the Q and Q outputs of the output flip-flop are
respectively fed back to the J and K inputs of the input flip-flop.
❖ Figure 2.30 shows the logic diagram of a four- bit ring counter.
❖ Let us assume that flip-flop FF0 is initially set to the logic ‘1’ state and all other
flip-flops are reset to the logic ‘0’ state.
❖ The counter output is therefore 1000.
❖ With the first clock pulse, this ‘1’ gets shifted to the second flip-flop output and
the counter output becomes 0100.

Figure 2.30 Four bit ring counter

 Digital Principles and System Design 2.45

❖ Similarly, with the second and third clock pulses, the counter output will become
0010 and 0001.
❖ With the fourth clock pulse, the counter output will again become 1000.
❖ The count cycle repeats in the subsequent clock pulses.
❖ Circulating registers of this type find wide application in the control section of
microprocessor-based systems where one event should follow the other.
❖ The timing waveforms for the circulating register of Figure 2.30, as shown in Fig.
2.31, further illustrate their utility as a control element in a digital system to
generate control pulses that must occur one after the other sequentially.

Figure 2.31 Timing waveforms of the four bit ring counter

2.8.2 Shift Counter
❖ A shift counter on the other hand is constructed by having an inverse feedback in
a shift register.
❖ For instance, if we connect the Q output of the output flip-flop back to the K input
of the input flip-flop and the Q output of the output flip-flop to the J input of the
input flip-flop in a serial shift register, the result is a shift counter, also called a
Johnson counter.
❖ If the shift register employs D flip-flops, the Q output of the output flip-flop is fed
back to the D input of the input flip-flop.
2.46 Synchronous Sequential Logic

❖ If R-S flip-flops are used, the Q output goes to the R input and the Q output is
connected to the S input.
❖ Figure 2.32 shows the logic diagram of a basic four-bit shift counter.

Figure 2.32 Four bit shift counter

❖ Let us assume that the counter is initially reset to all 0s. With the first clock cycle,
the outputs will become 1000.
❖ With the second, third and fourth clock cycles, the outputs will respectively be
1100,1110 and 1111.
❖ The fifth clock cycle will change the counter output to 0111.
❖ The sixth, seventh and eighth clock pulses successively change the outputs to
0011, 0001 and 0000.
❖ Thus, one count cycle is completed in eight cycles.
❖ Figure 2.33 shows the timing waveforms.
❖ Different output waveforms are identical except for the fact that they are shifted
from the immediately preceding one by one clock cycle.
❖ Also, the time period of each of these waveforms is 8 times the period of the clock
waveform. That is, this shift counter behaves as a divide-by-8 circuit.
❖ In general, a shift counter comprising n flip-flops acts as a divide-by-2n circuit.
❖ Shift counters can be used very conveniently to construct counters having a
modulus other than the integral power of 2.
 Digital Principles and System Design 2.47

Figure 2.33 Timing waveforms of the shift counter

2.9 ASYNCHRONOUS SEQUENTIAL CIRCUITS

❖ Synchronous sequential circuits are further classified depending on the timing of
their signals
❖ Synchronous sequential circuits and Asynchronous Sequential Circuits.
❖ In synchronous sequential circuits signals can affect the memory elements only at
discrete instants of time.
❖ In asynchronous sequential circuits change in input signals can affect memory
element at any instant of time.
❖ The following table shows the Comparison between synchronous sequential
circuits and asynchronous sequential circuits.
Sl.No Synchronous sequential circuits Asynchronous sequential circuits
1. In synchronous circuits memory In asynchronous circuits memory
elements are clocked flip-flops Elements are either unclocked flip-flops
or time delay elements.
2. The change in input signals can The change in input signals can affect
affect memory element upon memory element at any instant of time
activation of clock signal
3. The maximum operating speed of Because of absence of clock
clock depends on time delays asynchronous circuits can operate faster
2.48 Synchronous Sequential Logic

involved than synchronous circuits

4. Easier to design More difficult to design

2.9.1 Clocked sequential circuits

❖ In synchronous or clocked sequential circuits clocked flipflops are used as
memory elements which change their individual states in synchronism with the
periodic clock signal.
❖ The change in states of flipflop and change in state of the entire circuit occur at
the transition of the clock signal.
❖ The states of the output of the flipflop in the sequential circuit give the state of the
sequential circuit.
Present state
❖ The status of all state variables at some time t, before the next clock edge represent
condition called present state.
Next state
❖ The status of all state variables at some time t+1 represent a condition called next
state.
❖ The synchronous or clocked sequential circuits are represented by two models.
o Moore model: The output depends only on the present state of the flip-flops.
o Mealy model: The outputs depends on both the present state of the flip-flops
and on the inputs

2.9.1.1 Moore model

Figure: 2.34 Moore circuit model with an output decoder

 Digital Principles and System Design 2.49

❖ When the output of the sequential circuit depends only on the present state of the
flip-flop the sequential circuit is referred to as Moore model. Let us see one
example of Moore model.
2.9.1.2 Mealy model
❖ When the output of the sequential circuit depends on both the present state of the
flip-flops and on the inputs, the sequential circuit is referred to as mealy model.
❖ Figure 2.35.shows the sample mealy model.

Figure 2.35 Example of mealy model

❖ Looking at Figure: 2.35 we can easily realize that, changes in the input within the
clock pluses cannot affect the state of the flip-flop.
❖ However, they can affect the output of the circuit. Due to this, if the input
variations are not synchronized with the clock, the derived output also not be
synchronized with the clock and we get false output (as it is a synchronous
sequential network).
❖ The false outputs can be eliminated by allowing input to change only at the active
transition of the clock (in our example HIGH –to-LOW).
❖ In general form the Mealy model can be represented with in its block schematic
as shown as in figure. 2.35

Figure 2.35 Mealy circuit model

 3
COMPUTER FUNDAMENTALS

INTRODUCTION
Computer Organization: It refers to the operational units and their interconnections that
realize the architectural specifications. It describes the function of and design of the
various units of digital computer that store and process information. The attributes in
computer organization refers to:
• Control signals
• Computer/peripheral interface
• Memory technology
Computer hardware: Consists of electronic circuits, displays, magnetic and optical
storage media, electromechanical equipment and communication facilities.
Computer Architecture: It is concerned with the structure and behavior of the
computer. It includes the information formats, the instruction set and techniques for
addressing memory. The attributes in computer architecture refers to the:
• Instruction set
• Data representation
• I/O mechanisms
• Addressing techniques
The basic distinction between architecture and organization is: the attributes of the
former are visible to programmers whereas the attributes of the later describes how
features are implemented in the system.
3.2 Computer Fundamentals

3.1 FUNCTIONAL UNITS OF A DIGITAL COMPUTER: VON

NEUMANN ARCHITECTURE
The modern day computer system’s functional unit is given by Von Neumann
Architecture

Fig 3.1: Von Neumann Architecture

A computer consists of five functionally independent main parts:
Input, Memory, Arithmetic and logic, Output, and Control units, as shown in
Figure 3.1. The input unit accepts coded information from human operators using
devices such as keyboards or from other computers over digital communication lines.
➢ The information received is stored in the computer’s memory, either for later use
or to be processed immediately by the arithmetic and logic unit.
➢ The processing steps are specified by a program that is also stored in the
memory.
➢ Finally, the results are sent back to the outside world through the output unit.
All of these actions are coordinated by the control unit. An interconnection
network provides the means for the functional units to exchange information and
coordinate their actions.
Input unit
Computers accept the coded information through input unit. Computer must
receive both data and program statements to function properly and must be able to solve
problems. The method of feeding data and programs to a computer is accomplished by
an input device. Input devices read data from a source, such as magnetic disks, and
translate that data into electronic impulses for transfer into the CPU. Whenever a key is
pressed, the corresponding letter or digit is automatically translated into its
corresponding binary code and transmitted over a cable to either the memory or the
processor.
 Digital Principles and System Design 3.3

Central Processing Unit (CPU)

The CPU processes data transferred to it from one of the various input devices.
It then transfers either an intermediate or final result of the CPU to one or more output
devices. A central control section and work areas are required to perform calculations or
manipulate data. The CPU is the computing center of the system. It consists of a control
section, an arithmetic-logic section, and an internal storage section (memory unit). Each
section within the CPU serves a specific function and has a particular relationship with
the other sections within the CPU.
Memory Unit
It stores the programs and data. Memory unit is broadly classified into two types :
Primarymemory and Secondary memory.
1. Primary Memory:
It is a fast memory that operates at electronic speeds. Programs must be stored in
the memory while they are being executed. The memory contains large no of
semiconductor storage cells. Each cell carries 1 bit of information. The cells are
processed in a group of fixed size called Words. To provide easy access to any word in
a memory, a distinct address is associated with each word location. Addresses are
numbers that identify successive locations. The number of bits in each word is called
the word length. The word length ranges from 16 to 64 bits. There are 3 types of
primary memory:
I. RAM: Memory in which any location can be reached in short and fixed amount
of time after specifying its address is called RAM. Time required to access 1
word is called Memory Access Time.
II. Cache Memory: The small, fast, RAM units are called Cache. They are tightly
coupled with processor to achieve high performance.
III. Main Memory: The largest and the slowest unit is the main memory.
Arithmetic & Logic Unit
Most computer operations are executed in ALU. The arithmetic-logic section
performs arithmetic operations, such as addition, subtraction, multiplication, and division.
Through internal logic capability, it tests various conditions encountered during
processing and takes action based on the result. Data may be transferred back and forth
between these two sections several times before processing is completed. Access time to
registers is faster than access time to the fastest cache unit in memory.
3.4 Computer Fundamentals

Output Unit
The output unit is the counterpart of the input unit. Its function is to send
processed results to the outside world. A familiar example of such a device is a printer.
Most printers employ either photocopying techniques, as in laser printers, or ink jet
streams. Such printers may generate output at speeds of 20 or more pages per minute.
However, printers are mechanical devices, and as such are quite slow compared
to the electronic speed of a processor. Some units, such as graphic displays, provide
both an output function, showing text and graphics, and an input function, through
touch screen capability.
Control Unit
The operations of Input unit, output unit, ALU are co-ordinate by the control
unit. The control unit is the Nerve centre that sends control signals to other units and
senses their states. The control section directs the flow of traffic (operations) and data. It
also maintains order within the computer. The control section selects one program
statement at a time from the program storage area, interprets the statement, and sends
the appropriate electronic impulses to the arithmetic-logic and storage sections so they
can carry out the instructions. The control section does not perform actual processing
operations on the data.
The control section instructs the input device on when to start and stop
transferring data to the input storage area. It also tells the output device when to start
and stop receiving data from the output storage area. Data transfers between the
processor and the memory are controlled by the control unit through timing signals.
Information stored in the memory is fetched, under program control into an arithmetic
and logic unit, where it is processed.
The operation of a computer can be summarized as follows:
➢ The computer accepts information in the form of programs and data through an
input unit and stores it in the memory.
➢ Information stored in the memory is fetched under program control into an
arithmetic and logic unit, where it is processed.
➢ Processed information leaves the computer through an output unit.
➢ All activities in the computer are directed by the control unit
 Digital Principles and System Design 3.5

3.2 OPERATION AND OPERANDS OF COMPUTER HARDWARE

INSTRUCTION
3.2.1 Basic Operational Concepts
To perform a given task, an appropriate program consisting of a list of
instructions is stored in the memory. Individual instructions are brought from the
memory into the processor, which executes the specified operations. Data to be used as
instruction operands are also stored in the memory.
A typical instruction might be
Load R2, LOC
This instruction reads the contents of a memory location whose address is
represented symbolically by the label LOC and loads them into processor register R2.
Execution of this instruction requires several steps. First, the instruction is
fetched from the memory into the processor. Next, the operation to be performed is
determined by the control unit. The operand at LOC is then fetched from the memory
into the processor. Finally, the operand is stored in register R2.
After operands have been loaded from memory into processor registers,
arithmetic or logic operations can be performed on them. For example, the instruction
Add R4, R2, R3
adds the contents of registers R2 and R3, and then places their sum into register R4. The
operands in R2 and R3 are not altered, but the previous value in R4 is overwritten by
the sum. After completing the desired operations, the results are in processor registers.
They can be transferred to the memory using instructions such as
Store R4, LOC
This instruction copies the operand in register R4 to memory location LOC. The
original contents of location LOC are overwritten, but those of R4 are preserved.
For Load and Store instructions, transfers between the memory and the
processor are initiated by sending the address of the desired memory location to the
memory unit and asserting the appropriate control signals. The data are then transferred
to or from the memory.
Figure 1.2 shows how the memory and the processor can be connected. It also
shows some components of the processor that have not been discussed yet. The
interconnections between these components are not shown explicitly since we will only
3.6 Computer Fundamentals

discuss their functional characteristics here.

In addition to the ALU and the control circuitry, the processor contains a
number of registers used for several different purposes. The instruction register (IR)
holds the instruction that is currently being executed.
Its output is available to the control circuits, which generate the timing
signals that control the various processing elements involved in executing the
instruction. The program counter (PC) is another specialized register.

Figure 3.2: Connection between the processor and the main Memory.
It contains the memory address of the next instruction to be fetched and
executed. During the execution of an instruction, the contents of the PC are updated to
correspond to the address ofthe next instruction to be executed.
In addition to the IR and PC, Figure 3.2 shows general-purpose registers R0
through Rn−1, often called processor registers. They serve a variety of functions,
including holding operands that have been loaded from the memory for processing.
The processor-memory interface is a circuit which manages the transfer of data
between the main memory and the processor. If a word is to be read from the memory,
the interface sends the address of that word to the memory along with a Read control
signal. The interface waits for the word to be retrieved, then transfers it to the
appropriate processor register.
 Digital Principles and System Design 3.7

Let us now consider some typical operating steps.

✓ A program must be in the main memory in order for it to be executed.
✓ It is often transferred there from secondary storage through the input unit.
✓ Execution of the program begins when the PC is set to point to the first
instruction of theprogram.
✓ The contents of the PC are transferred to the memory along with a Read control
signal.
✓ When the addressed word (in this case, the first instruction of the program)
has beenfetched from the memory it is loaded into register IR.
✓ At this point, the instruction is ready to be interpreted and executed.
Category Instruction Operation
Arithmetic Add $s1, $s2, $s3 S1=s2+s3.
There are three operands in this instruction.
The data resides in the registers.
Sub $s1, $s2, $s3 S1=s2-s3.
There are three operands in this instruction.
The data resides in the registers.
Data Transfer Lw $s1, 50($s2 ) S1=memory [s2+50]
Data is transferred from memory to registers.
Memory[s2+50]=$s1
Sw $s1, 50($s2) Data is transferred from register to memory

3.2.2 Basic Operands Concepts

• The operands of arithmetic instruction must be from specially built memory
locations called registers.
• The registers are accessed as 32 bit groups termed as words.
• MIPS architecture supports 32 registers.
Memory Operands
• The operands are always stored in registers.
• Data transfer instruction is a command that moves data between memory and
registers.
3.8 Computer Fundamentals

• Address of an operand is a value used to delineate the location of a specific

data element within a memory array.
• The data transfer instruction that copies data from memory to a register is
traditionally called load (lw- load word).
• The format of the load instruction is the name of the operation followed by the
register to be loaded, then a constant and register used to access memory.
• The sum of the constant portion of the instruction and the contents of the second
register forms the memory address.
• Store (sw- store word) instruction copies data from a register to memory.
• The format of a store is the name of the operation, followed by the register
to be stored, then offset to select the array element, and finally the base register.
• The MIPS address is specified in part by a constant and in part by the contents of
a register.
• Many programs have more variables than computers have registers. The
compiler tries to keep the most frequently used variables in registers and places
the rest in memory, using loads and stores to move variables between registers
and memory.
• The process of putting less commonly used variables into memory is called
spilling registers.
Constant or Immediate Operands
• Sometimes it is necessary to load a constant from memory to use one. The
constants would have been placed in memory when the program was loaded.
Example: addi $s3,$s3,10
• This instruction is interpreted as addition of content of $s3 and the value
10. The sum is stored in $s3. Addi means add immediate, since one of the
operand is in immediate addressing mode.
• As per the design principle “Make common case faster”, the constant operands
must be loaded faster from the memory.
• Since constants occur more frequently in the instruction, they are mentioned in
the instruction itself rather than to load from registers.
 Digital Principles and System Design 3.9

Example
Given the following C statement:
f = (g + h) - (i + j);
Assume the compiler associates the variables f, g, h, i, and j to the registers $s0,
$s1, $s2, $s3, and $s4, respectively
What is the compiled MIPS assembly language code?
Answer
add $t0, $s1, $s2 # Register $t0 contains g+h
add $t1, $s3, $s4 # Register $t1 contains i+j
sub $s0, $t0, $t1 # f gets $t0-$t1, or (g+h) - (i+j)
What if we have a program that manipulates a large array of numbers - they
cannot all be stored in the registers of the MIPS processor.
➢ In this case, the elements of the array would be stored in the memory of the
MIPS computer.
➢ The memory is a large storage space that can store millions of data elements.
➢ When we need to perform an operation on certain elements of this array, we
transfer these elements from the memory to the registers -MIPS cannot perform
operations directly on data elements stored in memory (certain computers can).
➢ These instructions are called data transfer instructions.

3.3 INSTRUCTION SET ARCHITECTURE (ISA): MEMORY

LOCATION, ADDRESS AND OPERATION
INSTRUCTION
An instruction is a binary code, which specifies a basic operation for the
computer.
Instruction Set Architecture (ISA) describes the processor in terms of what the
assembly language programmer sees, i.e. the instructions and registers.
So the instruction set architecture is basically the interface between hardware
and the software. The only way that you can interact with the hardware is the instruction
set of the processor.
3.10 Computer Fundamentals

To command the computer, you need to speak its language and the instructions
are the words of a computer’s language and the instruction set is basically its
vocabulary. ISA is the portion of the machine which is visible to either the assembly
language programmer or a compiler writer or an application programmer.
A complete instruction set, including operand addressing methods, is often
referred to as the instruction set architecture (ISA) of a processor.
3.3.1 Memory Locations and Addresses
The memory consists of many millions of storage cells, each of which can store
a bit of information having the value 0 or 1. Because a single bit represents a very small
amount of information, bits are seldom handled individually.
Each group of n bits is referred to as a word of information, and n is called the
word length. The memory of a computer can be schematically represented as a
collection of words, as shown in Figure 3.3.

Figure. 3.3 Memory words

Modern computers have word lengths that typically range from 16 to 64 bits. If
the word length of a computer is 32bits, a single word can store a 32-bit signed number
or four ASCII-encoded characters, each occupying 8bits, as shown in Figure 3.4.
 Digital Principles and System Design 3.11

A unit of 8 bits is called a byte. Machine instructions may require one or more
words for their representation.

Figure 3.4 Examples of encoded information in a 32-bit word

Accessing the memory to store or retrieve a single item of information, either a
word or a byte, requires distinct names or addresses for each location.
It is customary to use numbers from 0 to 2k −1, for some suitable value of k, as
the addresses of successive locations in the memory.
Thus, the memory can have up to 2k addressable locations. The 2k addresses
constitute the address space of the computer.
For example, a 24-bit address generates an address space of 224 (16,777,216)
locations. This number is usually written as 16M (16 mega), where 1M is the number
220 (1,048,576).
A 32-bit address creates an addressspaceof232 or4G (4giga) locations, where 1G
is 230. Other notational conventions that are commonly used are K (kilo) for the number
210 (1,024), and T (tera) for thenumber 240.
Byte Addressability
We now have three basic information quantities to deal with: bit, byte, and word.
• A byte is always 8 bits
• but the word length typically ranges from 16 to 64 bits.
3.12 Computer Fundamentals

It is impractical to assign distinct addresses to individual bit locations in the

memory. The most practical assignment is to have successive addresses refer to
successive byte locations in the memory. This is the assignment used in most modern
computers.
The term byte-addressable memory is used for this assignment. Byte locations
have addresses 0,1,2,....Thus, if the word length of the machine is 32bits,successive
words are located at addresses 0,4,8,...,with each word consisting of four bytes.
Big-Endian and Little-Endian Assignments
There are two ways that byte addresses can be assigned across words, as shown
in Figure 3.5.
The name big-endian is used when lower byte addresses are used for the more
significant bytes (the leftmost bytes) of the word.

Figure 3.5 Byte and Word addressing

The name little-endian is used for the opposite ordering, where the lower
byte addresses areused for the less significant bytes (the rightmost bytes) of the word.
Memory Operations
The two basic operations involving the memory are needed, namely, Read and
Write.
The Read operation transfers a copy of the contents of a specific memory
location to the processor. The memory contents remain unchanged.
 Digital Principles and System Design 3.13

To start a Read operation, the processor sends the address of the desired location
to the memory and requests that its contents be read. The memory reads the data stored
at that address and sendsthem to the processor.
The Write operation transfers an item of information from the processor to a
specific memory location, overwriting the former contents of that location.
To initiate a Write operation, the processor sends the address of the desired
location to the memory, together with the data to be written into that location.

3.4 INSTRUCTION AND INSTRUCTION SEQUENCING

A computer must have instructions capable of performing four types of operations:
• Data transfers between the memory and the processor registers
• Arithmetic and logic operations on data
• Program sequencing and control
• I/O transfers
Register Transfer Notation (RTN)
To describe the transfer of information, the contents of any location are denoted
by placing square brackets around its name. Thus, the expression
R2←[LOC]
Means that the contents of memory location LOC are transferred into processor
registerR2.
As another example, consider the operation that adds the contents of registers R2
and R3, and places their sum into register R4. This action is indicated as
R4←[R2]+[R3]
This type of notation is known as Register Transfer Notation (RTN). Note that
the righthand side of an RTN expression always denotes a value, and the left-hand side
is the name of a location where the value is to be placed, overwriting the old contents of
that location.
Assembly-Language Notation
For example, a generic instruction that causes the transfer described above, from
memorylocation LOC to processor register R2, is specified by the statement
Load R2, LOC
3.14 Computer Fundamentals

The contents of LOC are unchanged by the execution of this instruction, but the
old contents of register R2 are overwritten.
The second example of adding two numbers contained in processor registers R2
and R3 and placing their sum in R4 can be specified by the assembly-language
statement
Add R4, R2, R3
In this case, registers R2 and R3 hold the source operands, while R4 is the
destination.
RISC and CISC Instruction Sets
The restriction that each instruction must fit into a single word reduces the
complexity and the number of different types of instructions that may be included in the
instruction set of a computer. Such computers are called Reduced Instruction Set
Computers (RISC).
Although the use of complex instructions was not originally identified by any
particular label, computers based on this idea have been subsequently called Complex
Instruction Set Computers (CISC).
Instruction Execution and Straight-Line Sequencing
In the preceding subsection, we used the task C =A+ B, implemented as C←[A]
+ [B], as an example. Figure 3.6 shows a possible program segment for this task as it
appears in the memory of a computer.
We assume that the word length is 32 bits and the memory is byte-addressable.
The four instructions of the program are in successive word locations, starting at location
i. Since each instruction is 4 bytes long, the second, third, and fourth instructions are at
addresses i+4, i+8, and i+12.
Let us consider how this program is executed. The processor contains a register
called the program counter (PC), which holds the address of the next instruction to be
executed.
To begin executing a program, the address of its first instruction (i in our
example) must be placed into the PC. Then, the process or control circuits use the
information in the PC to fetch and execute instructions, one at a time, in the order of
increasing addresses. This is called straight-line sequencing.
During the execution of each instruction, the PC is incremented by 4 to point to
the next instruction. Thus, after the Store instruction at location i + 12 is executed, the
 Digital Principles and System Design 3.15

PC contains the value i + 16, which is the address of the first instruction of the next
program segment.

Figure 3.6 A Program for C → [A] + [B]

Branching & Looping
Branching - This type of instruction loads a new address into the program counter. As a
result, the processor fetches and executes the instruction at this new address, called the
branch target, instead of the instruction at the location that follows the branch
instruction in sequential address order.
A conditional branch instruction causes a branch only if a specified condition is
satisfied. If the condition is not satisfied, the PC is incremented in the normal way, and
the next instruction in sequential address order is fetched and executed.
Looping
In the program in Figure 3.8, the instruction Branch_if_[R2]>0 LOOP is a
conditional branch instruction that causes a branch to location LOOP if the contents of
register R2 are greater than zero. This means that the loop is repeated as long as there
are entries in the list that are yet to be added to R3.
3.16 Computer Fundamentals

At the end of the nth pass through the loop, the Subtract instruction produces a
value of zero in R2, and, hence, branching does not occur. Instead, the Store instruction
is fetched and executed. It moves the final result from R3 into memory location SUM.

Figure 3.7 & 3.8 Branching and Looping Example

3.5 ADDRESSING MODES

The different ways in which the location of an operand is specified in an
instruction is called as Addressing mode.
Different operands will use different addressing modes. One or more bits in the
instruction format can be used as mode field. The value of the mode field determines
which addressing mode is to be used. The effective address will be either main
memory address of a register.
The most common addressing modes are:
1. Immediate addressing mode
2. Direct addressing mode
3. Indirect addressing mode
4. Register addressing mode
 Digital Principles and System Design 3.17

5. Register indirect addressing mode

6. Displacement addressing mode
7. Stack addressing mode
1. Immediate Addressing:
• This is the simplest form of addressing. Here, the operand is given in the
instruction.
• This mode is used to define constant or set initial values of variables.
• The advantage of this mode is that no memory reference other than
instruction fetchis required to obtain operand.
• The disadvantage is that the size of the number is limited to the size of the
addressfield because most instruction sets is small compared to word length.
Example: ADD 3
• Adds 3 to contents of accumulator and 3 is the operand.

Fig 3 .9: Immediate Mode

2. Direct Addressing:
• In direct addressing mode, effective address of the operand is given in the
addressfield of the instruction.
• It requires one memory reference to read the operand from the given location
andprovides only a limited address space.
• Length of the address field is usually less than the word length.

Fig 3 .10: Direct Addressing modes

3.18 Computer Fundamentals

• Example : Move P, Ro
Add Q, Ro
Where P and Q are the address of operand, Ro is any register. Sometimes
Accumulator (AC) is the default register. Then the instruction will look like:
Add A
3. Indirect or Pseudodirect Addressing:
• Indirect addressing mode, the address field of the instruction refers to the
address of a word in memory, which in turn contains the full length address of
the operand.
• The address field of instruction gives the memory address where on, the
operandis stored in memory.
• Control fetches the instruction from memory and then uses its address part to
accessmemory again to read Effective Address.
• The advantage of this mode is that for the word length of N, an address
space of2N can be addressed.
• The disadvantage is that instruction execution requires two memory references
tofetch the operand.
• Multilevel or cascaded indirect addressing can also be used.
Example: Effective Address (EA) = (A).
• The operand will be present in the memory location A.

Fig 3.11: Indirect Addressing Modes

 Digital Principles and System Design 3.19

4. Register Addressing:
• Register addressing mode is similar to direct addressing. The only difference
is that the address field of the instruction refers to a register rather than a
memory location.
• 3 or 4 bits are used as address field in the instruction to refer 8 to 16 generate
purposeregisters (GPR).
• The operands are in registers that reside within the CPU.
• The instruction specifies a register in CPU, which contain the operand.
• There is no need to compute the actual address as the operand is in a
register andto get operand there is no memory access involved.
• The advantages of register addressing are small address field is needed in the
instructionand faster instruction fetch.
• The disadvantages includes very limited address space and usage of multiple
registershelps in performance but it complicates the instructions.
• Example: MOV AX, BX

Fig 3 .12: Register Mode

5. Register Indirect Addressing:
• This mode is similar to indirect addressing. The address field of the instruction
refersto a register.
• The instruction specifies a register in CPU whose contents give the operand in
memory.
• The selected register contain the address of operand rather than the
operanditself.
• The register contains the effective address of the operand. This mode uses
onememory reference to obtain the operand.
3.20 Computer Fundamentals

• Control fetches instruction from memory and then uses its address to access
Register and looks in Register(R) for effective address of operand in
memory.
• The address space is limited to the width of the registers available to store
theeffective address.
• Example:MOV AL, [BX]
Code example in Register:
MOV BX, 1000H
MOV 1000H, operand
• The instruction MOV AL, [BX]) specifies a register[BX] which contain the
address of operand (1000H) rather than address itself.

Fig 3.13: Register Indirect Mode

6. Displacement Addressing:
• It is a combination of direct addressing or register indirect addressing
mode.

Fig 3 .14 a): Displacement Addressing Modes

• Displacement Addressing Modes requires that the instruction have two address
fields, at least one of which is explicit means, one is address field indicate direct
 Digital Principles and System Design 3.21

address and other indicate indirect address.

• Value contained in one addressing field is A, which is used directly and the
value in other address field is R, which refers to a register whose contents are
to be addedto produce effective address.
• Example: EA=A+(R)
• In displacement addressing mode there are 3 types of addressing mode.
• Relative addressing:
The contents of program counter is added to the address part of instruction to
obtain the Effective Address. The address field of the instruction is added to
implicitly reference register Program Counter to obtain effective address.
Example: EA=A+PC
Assume that PC contains the value 825 and the address part of instruction
contain the value 24, then the instruction at location 825 is read from memory during
fetch phase and the Program Counter is then incremented by one to 826. Here both
PC and instruction contains address. The effective address computation for relative
address mode is 826+24=850

Fig 3 .14 b): Relative addressing

Base register addressing
The content of the Base Register is added to the direct address part of the
instructionto obtain the effective address.
The address field point to the Base Register and to obtain EA, the contents of
Instruction Register, is added to direct address part of the instruction.
3.22 Computer Fundamentals

This is similar to indexed addressing mode except that the register is now called as
Base Register instead of Index Register.
Example: EA=A+Base

Fig 3.14 c): Base Register Addressing Mode

Indexed addressing:
The content of Index Register is added to direct address part of instruction to
obtain the effective address. The register indirect addressing field of instruction point to
Index Register, which is a special CPU register that contain an Indexed value, and
direct addressing field contain base address.
The data array is in memory and each operand in the array is stored in memory
relative to base address. The distance between the beginning address and the address
of operand is the indexed value stored in indexed register.
Any operand in the array can be accessed with the same instruction, which
provided that the index register contains the correct index value i.e., the index register
can be incremented to facilitate access to consecutive operands.
Example: EA=A+Index

Fig 3.14 d): Indexed Addressing

 Digital Principles and System Design 3.23

7. Stack Addressing:
• Stack is a linear array of locations referred to as last-in first out queue.
• The stack is a reserved block of location, appended or deleted only at the
top ofthe stack.
• Stack pointer is a register which stores the address of top of stack location.
• This mode of addressing is also known as implicit addressing.
• Example: Add
• This instruction pops two items from the stack and adds.
Additional Modes:
There are two additional modes. They are:
• Auto-increment mode
• Auto-decrement mode
These are similar to Register indirect Addressing Mode except that the register is
incremented or decremented after (or before) its value is used to access memory. These
modes are required because when the address stored in register refers to a table of data
in memory, then it is necessary to increment or decrement the register after every access
to table so that next value is accessed from memory.
Auto-increment mode:
• Auto-increment Addressing Mode are similar to Register Indirect Addressing
Mode except that the register is incremented after its value is loaded (or
accessed) at another location like accumulator(AC).
• The Effective Address of the operand is the contents of a register in the
instruction.
• After accessing the operand, the contents of this register is automatically
incrementedto point to the next item in the list.
• Example: (R) +.
• The contents in register R will be accessed and them it will be incremented to
point the next item in the list.
• The effective address is (R )=400 and operand in AC is 7. After loading R1 is
incremented by 1, it becomes 401.
3.24 Computer Fundamentals

Fig 3 .15: Auto-increment Mode

Auto-decrement mode:
• Auto-decrement Addressing Mode is reverse of auto-increment , as in it the
registeris decrement before the execution of the instruction.
• Effective address is equal to EA=(R) - 1
• The Effective Address of the operand is the contents of a register in the
instruction.
• After accessing the operand, the contents of this register is automatically
decrementedto point to the next item in the list.
• Example: - ( R)
• The contents in register R will be decremented and then it is accessed.

Fig 3 .16: Auto Decrement Addressing Mode

 Digital Principles and System Design 3.25

3.6 ENCODING OF MACHINE INSTRUCTION

• We have seen a variety of useful instructions and addressing modes. These
instructions specify the actions that must be performed by the processor circuitry
to carry out the desired tasks. We have often referred to them as machine
instructions.
• Actually, the form in which we have presented the instructions is indicative of
the form used in assembly languages, except that we tried to avoid using
acronyms for the various operations, which are awkward to memorize and are
likely to be specific to a particular commercial processor.
• To be executed in a processor, an instruction must be encoded in a compact
binary pattern. Such encoded instructions are properly referred to as machine
instructions.
• The instructions that use symbolic names and acronyms are called assembly
language instructions, which are converted into the machine instructions using
the assembler program.
• We have seen instructions that perform operations such as add, subtract, move,
shift, rotate, and branch. These instructions may use operands of different sizes,
such as 32-bit and 8-bit numbers or 8-bit ASCII-encoded characters.
• The type of operation that is to be performed and the type of operands used may
be specified using an encoded binary pattern referred to as the OP code for the
given instruction.
• Suppose that 8 bits are allocated for this purpose, giving 256 possibilities for
specifying different instructions. This leaves 24 bits to specify the rest of the
required information.
• Let us examine some typical cases.
Add R1, R2
• Has to specify the registers R1 and R2, in addition to the OP code. If the
processor has 16 registers, then four bits are needed to identify each register.
Additional bits are needed to indicate that the Register addressing mode is used
for each operand.
The instruction
Move 24(R0), R5
3.26 Computer Fundamentals

• Requires 16 bits to denote the OP code and the two registers, and some bits to
express that the source operand uses the Index addressing mode and that the
index value is 24.
The shift instruction
LShiftR #2, R0
And the move instruction
Move #$3A, R1
• Have to indicate the immediate values 2 and #$3A, respectively, in addition to
the 18bits used to specify the OP code, the addressing modes, and the register.
This limits the size of the immediate operand to what is expressible in 14 bits.
• Consider next the branch instruction
Branch >0 LOOP
• Again, 8 bits are used for the OP code, leaving 24 bits to specify the branch
offset. Since the offset is a 2’s-complement number, the branch target address
must be within 223 bytes of the location of the branch instruction. To branch to
an instruction outside this range, a different addressing mode has to be used,
such as Absolute or Register Indirect. Branch instructions that use these modes
are usually called Jump instructions.
• In all these examples, the instructions can be encoded in a 32-bit word. Depicts a
possible format. There is an 8-bit Op-code field and two 7-bit fields for
specifying the source and destination operands. The 7-bit field identifies the
addressing mode and the register involved (if any). The “Other info” field allows
us to specify the additional information that may be needed, such as an index
value or an immediate operand.
RISC AND CISC STYLES
RISC and CISC are two different styles of instruction sets. We introduced
RISC first because it is simpler and easier to understand. Having looked at some basic
features of both styles, we should summarize their main characteristics.
CISC :
• The CISC approach attempts to minimize the number of instructions per
program, sacrificing the number of cycles per instruction.
 Digital Principles and System Design 3.27

• Computers based on the CISC architecture are designed to decrease the memory
cost.
• Because, the large programs need more storage, thus increasing the memory cost
and large memory becomes more expensive.
• To solve these problems, the number of instructions per program can be reduced
by embedding the number of operations in a single instruction, thereby making
the instructions more complex.
RISC :
• RISC (Reduced Instruction Set Computer) is used in portable devices due to its
powerefficiency.
For Example, Apple iPod and Nintendo DS. RISC is a type of
microprocessorarchitecture that uses highly-optimized set of instructions.
• RISC does the opposite, reducing the cycles per instruction at the cost of the
number of instructions per program Pipelining is one of the unique feature of
RISC.
• It is performed by overlapping the execution of several instructions in a pipeline
fashion.It has a high performance advantage over CISC.
3.28 Computer Fundamentals

Figure 3.17 RISC & CISC Architecture

RISC style is characterized by:
• Simple addressing modes
• All instructions fitting in a single word
• Fewer instructions in the instruction set, as a consequence of simple addressing
modes
• Arithmetic and logic operations that can be performed only on operands in
processor registers
• Load/store architecture that does not allow direct transfers from one memory
location toanother; such transfers must take place via a processor register
• Simple instructions that are conducive to fast execution by the processing unit
using techniquessuch as pipelining
• Programs that tend to be larger in size, because more, but simpler instructions
are needed toperform complex tasks.
CISC style is characterized by:
• More complex addressing modes
• More complex instructions, where an instruction may span multiple words
 Digital Principles and System Design 3.29

• Many instructions that implement complex tasks

• Arithmetic and logic operations that can be performed on memory operands as
well asoperands in processor registers
• Transfers from one memory location to another by using a single Move
instruction
• Programs that tend to be smaller in size, because fewer, but more complex
instructions areneeded to perform complex tasks.

3.7 INTERACTION BETWEEN ASSEMBLY AND HIGH LEVEL

LANGUAGE.
Both of these are types of computer languages, but there is a significant
difference between assembly language and high-level language. In this article, we will
discuss the difference between them both. But let us first understand a bit more about
each of these individually.
What is an Assembly level language?
An assembly language is a type of low-level language of the computer that lets
users write various programs by making use of the alphanumeric codes for a set of
instructions instead of the numeric codes. IBM PC DOS is a commendable example of a
large assembly language of the present time.
What is a High-level language?
A high-level language is a machine-independent type of language. It lets users
write various programs in such a language that resembles the English words (and
alphabets) and all the familiar mathematical symbols. The very first high-level language
3.30 Computer Fundamentals

was the COBOL language. C#, Python, etc., are a few examples of high-level
languages.
Difference Between Assembly Language and High-Level Language
Here is a list of the differences present between Assembly Language and High-
Level Language.
Parameters Assembly Language High-Level Language
Conversion The assembly language A high-level language
requires an assembler for the requires an interpreter/
process of conversion. compiler for the process of
conversion.
Process of Conversion We perform the conversion We perform the
of an assembly language into conversion of a high-level
a machine language. language into an assembly
language and then into a
machine-level language
for the computer.
Machine Dependency The assembly language is a A high-level language is a
machine-dependent type of machine-independent type
language. of language.
Codes It makes use of the It makes use of the
mnemonic codes for English statements for
operation. operation.
Operation of Lower It provides support for It does not provide any
Level various low-level operations. support for low-level
languages.
Access to Hardware Accessing the hardware Accessing the hardware
Component component is very easy in component is very
this case. difficult in this case.
Compactness in Code The code is more compact in No code compactness is
this case. present in this case.
Type of Processor The program that we write This language is
for one processor in an processor-independent. It
 Digital Principles and System Design 3.31

assembly language will not means that the programs

run on any other processor that we write using high-
type. It means that it is level languages can easily
processor-dependent. run on any processor
independent of its type.
Accuracy It has better accuracy. Accuracy is much lesser in
this case.
Performance An assembly language The performance is
performs better than any comparatively not so
high-level language, in good.
general.
Length of Executable It is shorter in assembly It is larger in a high-level
Code language. language.
Time Taken in Code Execution of code takes less It takes up more time for
Execution time in this case because the execution because it needs
code is not very large. to execute a large code.
Efficiency It is way more efficient It is comparatively less
because of the shorter efficient because the
executable codes. executable codes are
comparatively longer in
length.
Reading of Pointers We can do that directly at a It is not possible to do so
physical address in the case in the case of a high-level
of an assembly language. language.
Extra Instructions We don’t need that in the This language must give
case of an assembly some extra instructions for
language. running any code on the
computer.
Ease of Understanding It is very difficult to debug It is very easy to debug
and understand the code of and understand the code of
an assembly language. an assembly language.
 4
PROCESSOR
4.1 INSTRUCTION EXECUTION
INTRODUCTION
The key performance metrics of the computer systems are;
i. Instruction count: This depends on the compiler used and instruction set
architecture.
ii. Clock cycle time: This depends on processor implementation.
iii. Clock cycles per instruction (CPI): This depends on processor implementation.
• Memory consists of a large array of words or bytes, each with its own
address. The CPU fetches instructions from memory according to the value
of the program counter.
• These instructions may cause additional loading from and storing to specific
memory addresses. A typical instruction-execution cycle, for example, first
fetches an instruction from memory
• The instruction is then decoded and may cause operands to be fetched from
memory.

Figure 4.1 Sequence of Instruction Execution

4.2 Processor

• After the instruction has been executed on the operands, results may be stored
back in memory.
• The memory unit see sortly a stream of memory addresses; it does not know
how they are generated (by the instruction counter, indexing, indirection, literal
addresses, and so on) or what they are for (instructions or data).
• Accordingly, we can ignore a program generates a memory address. We are
interested only in the sequence of memory addresses generated by the running
program.
• The following is a summary of the six steps used to execute a single instruction.
Step 1: Fetch instruction.
Step 2: Decode instruction and Fetch Operands.
Step 3: Perform ALU operation.
Step 4: Access memory.
Step 5: Write back result to register file.
Step 6: Update the PC.
• The objectives of this module are to discuss how an instruction gets executed in
a processor and the datapath implementation, using the MIPS architecture as a
case study.

4.1.1 MIPSARCHITECTURE
MIPS (Million Instructions per Second) is a simple, streamlined, highly scalable
RISC architecture with adopted by the industries.
The features that makes its widely useable are:
• Simple load and store with large number of register
• The number and the character of the instructions
• Better pipelining efficiency with visible pipeline delay slots
• Efficiency with compilers
These features make the MIPS architecture to deliver the highest performance
with high levels of power efficiency. It is important to learn the architecture of MIPS to
understand the detailed working of the processors.
 Digital Principles and System Design 4.3

Implementation of MIPS
MIPS have 32 General purpose registers (GPR) or integer registers (64 bit)
holding integer data. Floating point registers (FPR) are also available in MIPS capable
of holding both single precision (32 bit) and double precision data (64 bit). The
following are the data types available for MIPS:
Size Name Registers

8bits Byte Integerregister

16bits Halfword Integerregister
32bits Word Floatingpoint register
64bits Doubleword Floatingpoint register

Fig 4.2: Implementation of MIPS architecture with multiplexers and control lines
With these resources the MIPS performs the following operations:
• Memory referencing : load word(lw) and store word(sw)
• Arithmetic-logical instructions: add, sub, and, or, and slt
• Branch instructions: equal(beq) and jump (j)The common steps in load and store
instructions are:
4.4 Processor

i. Set the program counter (PC) to the address of the code and fetch the
instruction from that memory.
ii. Read one or two registers, using fields of the instruction to select the
registers to read. For the load word instruction, read only one register and
for store word the processor has to operate on two registers.
The ALU operations are done and the result of the operation is stored in the
destination register using store operation. When a branching operation is involved, then
next address to be fetched must be changes based on the branch target.
Sequence of operations
• Program Counter(PC):This register contains the address (location) of the
instruction
currently getting executed. The PC is incremented to read the next instruction to
beexecuted.
• The operands in the instruction are fetched from the registers.
• The ALU or branching operations are done. The results of the ALU operations
arestored in registers. If the result is given in load and store forms, then the
results are written to the memory address and from there they are transferred to
the registers.
• In case of branch instructions, the result of the branch operation is used to
determine the next instruction to be executed.
• The multiplexer (MUX1), selects one input control from multiple inputs. This
act s as a data selector.
• This helps to control several units depending on the type of instruction.
• The top multiplexor controls the target value of the PC. To execute next
instruction the PC is set as PC+4. To execute a branch instruction set the PC to
the branch target address.
• The multiplexor is controlled by the AND gate that operates on the zero output
of the ALU and a control signal that indicates that the instruction is a branch.
• The multiplexor (MUX2) returns the output to the register file for loading the
resultant data of ALU operation into the registers.
• MUX3 determines whether the second ALU input is from the registers or from
the offset field of the instruction.
 Digital Principles and System Design 4.5

• The control lines determine the operation performed at the ALU. The control
lines decide whether to read or write the data.
MIPS instruction format
There are only three instruction formats in MIPS. The instructions belong to any
one of the following type:
➢ Arithmetic/logical/shift/comparison
➢ Controlinstructions(branchandjump)
➢ Load/store
➢ Other(exception, register movement to/from GP registers, etc.)
The data and memory are well separated in MIPS implementation because:
• The instruction formats for the operations arenot unique; hence the memory
access will also be different.
• Maintaining separate memory area is less expensive.
• The operations of the processor are performed in single cycle. A single memory
(forboth data and memory access) will not allow for two different accesses
within onecycle.
LOGICDESIGNCONVENTIONS
The information in a computer system is encoded in binary form (0 or 1). The
highvoltage is encoded as 1 and low voltage as 0. The data is transmitted inside the
processorsthrough control wires / lines. These lines are capable of carrying only one bit
at a time. Sotransfer of multiple data can be done through deploying multiple control
lines or buses. The data should be synchronized with time by transferring it according to
the clock pulses. All the internal operations inside the processor are implemented
through logic elements. The logic elements are broadly classified into: Combinatorial
and Sequential elements.
DIFFERENCES BETWEEN COMBINATORIAL AND SEQUENTIAL
ELEMENTS
Combinatorial Elements Sequential Elements
The output of the combinatorial circuit Theoutputdependsonthepreviousstageoutput
depends only on the current input. s.
It has faster operation speed and easy It has comparatively low operation speed
4.6 Processor

implementation. and tough implementation.

No feedback connections. The output is connected with the input

through feedback connections.
For a given set of inputs, combinatorial Theoutputsvarybasedonpreviousoutputs.
elements give the same output since there
is no storage of past data.
The basic building blocks are gates, which The basic building blocks are flip flops,
are time independent. which are time dependent.
It is used for Arithmetic and Logic It is used for data storage.
operations.
No need for trigger. Triggering is needed to control the clock
cycles.
No memory element. Memory element is needed which is used to
store the states.
Ex: Encoder, full adder, Decoder, Ex: Counters
Multiplier

4.2 BUILDING A DATA PATH

A datapath is a representation of the flow of information (data and instructions)
through the CPU, implemented using combinatorial and sequential circuitry.

Fig: 4.3Components of Datapath

Datapath is a functional unit that operates or hold data. In the MIPS
implementation the data path elements includes instruction and data memories, the
register file, the arithmetic logic unit (ALU), and adders. The functionalities of basic
elements are listed below:
 Digital Principles and System Design 4.7

• Instruction Memory: It is a state element that provides read access because the
data path do not perform write operation. This combinatorial memory always
holds contents of location specified by the address.
• Program Counter (PC): This is a 32 bit state register containing the address of
the current instruction that is being executed. It is updated after every clock
cycle and do not require an explicit write signal.
• Adder: This is a combinatorial circuit that updates the value of PC after every
clock cycle to get that address of the next instruction to be executed.
Instruction Fetch:
The fundamental operation in Instruction Fetch is to send the address in the PC to
the instruction memory and obtain the specified instruction, and the increment the PC.

Fig:4.4: Instruction Fetch

R type instructions:
• They all read two registers, perform an ALU operation on the contents of the
registers, and write the result.
• This instruction class includes add, sub, and, or, and slt.
• The processor’s 32 general-purpose registers are stored in a structure called a
register file.
• A register file is a collection of registers in which any register can be read or
written by specifying the number of the register in the file. The register file
4.8 Processor

contains the register state of the machine.

• The R-format always performs ALU operation that has three register operands
(2-readand1-write).
• The register number must be specified in order to read the data from the register
file. Also the output from a register file will contain the data that is read from the
register.
• The write operation to a register has two inputs: the register number and the
value to be written. This operation is edge triggered.
Load and Store instructions:
• The load and store instructions compute a memory address by adding the base
register.
• If the instruction is a load, the value read from memory must be written into the
register file in the specified register.
• The memory is computed by adding the address of base register and the 16-bit
signed offset field (which is a part of the instruction).
• If the instruction is a store, the value to be stored must also be read from the
register.

Fig4.5: Data memory and sign extension unit

• The processor has a sign extension unit to sign-extend the 16-bit offset field in
the instruction to a 32-bit signed value.
• The data memory unit is necessary to perform write operation of store
instruction. So it has both read and write control signals, an address input and
data input.
 Digital Principles and System Design 4.9

Branch Instructions:
Branch Target is the address specified in a branch, which is used to update the
PC if the branch is taken. In the MIPS architecture the branch target is computed as
the sum of the offset field of the instruction and the address of the Instruction
following the branch.
The beq instruction (branch instruction) has three operands, two registers that
are compared for equality, anda16-bitoffsettocomputethebranchtargetaddress.
Beq t1, t2, offset
• Thus, the branch data path must do two operations: compute the branch target
address and compare the register contents.
• Branch Taken is where the branch condition is satisfied and the program
counter (PC) loads the branch target. All unconditional branches are taken
branches.
• Branch not Taken is where the branch condition is false and the program
counter (PC) loads the address of the instruction that sequentially follows the
branch.

Fig4.6: Data path of branch Instructions

4.10 Processor

• The branch target is calculated by taking the address of the net instruction after
thebranch instruction, since the PC value will be updated as PC+4 even before
the branchdecisionistaken
• The offset field is shifted left 2 bits to increase the effective range of the offset
field by a factor of four.
• The unit labelled Shift left 2 adds two zero’s to the low-order end of the sign-
extended off set field. This operation truncated the sign values.
• The control logic decides whether the incremented PC or branch target should
replace the PC, based on the Zero output of the ALU.
• The jump instruction operates by replacing the lower 28 bits of the PC with the
lower 26 bits of the instruction shifted left by 2 bits. This shift is done by
concatenating 00 to the jump offset.
• Delayed branch is where the instruction immediately following the branch is
always executed, independent of whether the branch condition is true or false.
• MIPS architecture implements delayed branch (i.e.) the instruction immediately
following the branch is always executed, independent of whether the branch
condition is true or false.
• When the condition is false, the execution looks like a normal branch.
• When the condition is true, a delayed branch first executes the instruction
immediately following the branch in sequential instruction order before jumping
to the specified branch target address.
• Delayed branches facilitate pipelining.
Creating a single Data path
• A simple implementation of a single data path is to execute all operations within
one clock cycle.
• The data path resources can be utilized only for one clock cycle. To facilitate
this, some resources must be duplicated for simultaneous access while other
resources will be shared.
• One example is having separate memory or instructions and memory.
• When a resource is used in shared mode, then multiple connections must be
made. The selection of which control will access the resource will be decided by
a multiplexer.
 Digital Principles and System Design 4.11

Fig: 4.7: Simple data path

• The data path illustrated in Fig4.7 shows the assembling of individual elements
into a simple data path.
• To implement branch instructions the data path must include an adder circuitry
to compute branch target (ReferFig: 4.6).
• The control unit for this data path must take inputs and generate a write signal
foreach state element. Apart from the inputs a selector control must be included
for each multiplexor and the ALU control.
• The operations of arithmetic-logical (or R-type) instructions and the memory
instructions data path are almost similar.
• The arithmetic-logical instructions use the ALU with the inputs coming from the
two registers. The memory instructions can also use the ALU to do the
addresscalculation, but the second input is the sign-extended 16-bit offset field
from theinstruction.

4.3 DESIGNING A CONTROL UNIT

The Control Unit is classified into two major categories:
1. Hardwired Control
2. Microprogrammed Control

4.3.1 Hardwired Control

The Hardwired Control organization involves the control logic to be
implemented with gates, flip-flops, decoders, and other digital circuits.
4.12 Processor

The following image shows the block diagram of a Hardwired Control organization.

Figure 4.8 Control Unit of a Basic Computer

o A Hard-wired Control consists of two decoders, a sequence counter, and a
number of logic gates.
o An instruction fetched from the memory unit is placed in the instruction register
(IR).
o The component of an instruction register includes; I bit, the operation code, and
bits 0 through 11.
o The operation code in bits 12 through 14 are coded with a 3 x 8 decoder.
o The outputs of the decoder are designated by the symbols D0 through D7.
o The operation code at bit 15 is transferred to a flip-flop designated by the
symbol I.
o The operation codes from Bits 0 through 11 are applied to the control logic
gates.
o The Sequence counter (SC) can count in binary from 0 through 15.
 Digital Principles and System Design 4.13

4.3.2 Micro-Programmed Control

The Microprogrammed Control organization is implemented by using the
programming approach.
In Microprogrammed Control, the micro-operations are performed by executing
a program consisting of micro-instructions.
The following image shows the block diagram of a Microprogrammed Control
organization.

o The Control memory address register specifies the address of the micro-
instruction.
o The Control memory is assumed to be a ROM, within which all control
information is permanently stored.
o The control register holds the microinstruction fetched from the memory.
o The micro-instruction contains a control word that specifies one or more micro-
operations for the data processor.
o While the micro-operations are being executed, the next address is computed in
the next address generator circuit and then transferred into the control address
register to read the next microinstruction.
o The next address generator is often referred to as a micro-program sequencer, as
it determines the address sequence that is read from control memory.

4.4 PIPELINING
As computer systems evolve, greater performance can be achieved by taking
advantage of improvements in technology, such as faster circuitry. In addition,
organizational enhancements to the processor can improveperformance.
Pipelining is an implementation technique in which multiple instructions are
overlapped in execution.
4.14 Processor

Pipelining is a process of arrangement of hardware elements of the CPU such

that its overall performance is increased. Simultaneous execution of more than one
instruction takes place in a pipelined processor. Let us see a real-life example that
works on the concept ofpipelined operation. Consider a water bottle packaging plant.
Let there be 3 stages that a bottle should pass through, Inserting the bottle (I), Filling
water in the bottle (F), and Sealing the bottle(S). Let us consider these stages as stage
1, stage 2 and stage 3 respectively. Let each stage take 1 minute to complete its
operation. Now, in a non-pipelined operation, a bottle is first inserted in the plant,
after 1 minute it is moved to stage 2 where water is filled. Now, in stage 1 nothing is
happening. Similarly, when the bottle moves to stage 3, both stage 1 and stage 2 are
idle. But in pipelined operation, when the bottle is in stage 2, another bottle can be
loaded at stage 1. Similarly, when the bottle is in stage 3, there can be one bottle each
in stage 1 and stage 2. So, after each minute, we get a new bottle at the end of stage 3.
Hence, the average time taken to manufacture 1 bottle is:
Without pipelining = 9/3 minutes = 3m
IFS||||||
|||IFS|||
| | | | | | I F S (9 minutes)
With pipelining = 5/3 minutes = 1.67m
IFS||
|IFS|
| | I F S (5 minutes)
Thus, pipelined operation increases the efficiency of a system.
Design of a basic pipeline
• In a pipelined processor, a pipeline has two ends, the input end and the output
end. Between these ends, there are multiple stages/segments such that the
output of one stage is connected to the input of the next stage and each stage
performs a specific operation.
• Interface registers are used to hold the intermediate output between two stages.
These interface registers are also called latch or buffer.
• All the stages in the pipeline along with the interface registers are controlled
by a common clock.
 Digital Principles and System Design 4.15

Execution in a pipelined processor Execution sequence of instructions in a

pipelined processor can be visualized using a space-time diagram. For example,
consider a processor having 4 stages and let there be 2 instructions to be executed. We
can visualize the execution sequence through the following space-time diagrams:

Figure 4.9 Space-Time diagrams

Total time = 5 Cycle
The pipeline has two independent stages. The first stage fetches an instruction
and buffers it. When the second stage is free, the first stage passes it the buffered
instruction. While the second stage is executing the instruction, the first stage takes
advantage of any unused memory cycles to fetch and buffer the next instruction. This is
called instruction prefetch or fetch overlap.
4.16 Processor

Figure 4.10 Two stage instruction pipeline

We can turn the pipelining speed-up discussion above into a formula. If the
stages are perfectly balanced, then the time between instructions on the pipelined
processor—assuming ideal conditions—is equal to

Under ideal conditions and with a large number of instructions, the speed-up
from pipelining is approximately equal to the number of pipe stages; a five-stage
pipeline is nearly five times faster.
It should be clear that this process will speed up instruction execution. If the
fetch and execute stages were of equal duration, the instruction cycle time would be
halved.
1. The execution time will generally be longer than the fetch time. Execution will
involve reading and storing operands and the performance of some operation.
Thus, the fetch stage may have to wait for some time before it can empty its
buffer.
2. A conditional branch instruction makes the address of the next instruction to be
fetched unknown. Thus, the fetch stage must wait until it receives the next
instruction address from the execute stage. The execute stage may then have to
wait while the next instruction is fetched.
 Digital Principles and System Design 4.17

When a conditional branch instruction is passed on from the fetch to the execute
stage, the fetch stage fetches the next instruction in memory after the branch instruction.
Then, if the branch is not taken, no time is lost. If the branch is taken, the fetched
instruction must be discarded and a new instruction fetched.
To increase speedup, the pipeline must have more stages.
Fetch instruction (FI): Read the next expected instruction into a buffer.
Decode instruction (DI): Determine the opcode and the operand specifiers.
Calculate operands (CO): Calculate the effective address of each source operand. This
may involve displacement, register indirect, indirect, or other forms of address
calculation.
Fetch operands (FO): Fetch each operand from memory. Operands in registers need
not be fetched.
Execute instruction (EI): Perform the indicated operation and store the result, if any,
in the specified destination operand location.
Write operand (WO): Store the result in memory.

4.11 Timing Diagram for Instruction pipeline operation

Factors serve to limit the performance enhancement.
• If the six stages are not of equal duration, there will be some waiting involved at
various pipeline stages, as discussed before for the two-stage pipeline.
4.18 Processor

• Another difficulty is the Conditional branch instruction, which can invalidate

several instruction fetches.
• A similar unpredictable event is an interrupt
Types of Pipelining
Pipelining is categorized into six types
1. Arithmetic Pipelining
It is designed to perform high-speed floating-point addition, multiplication and
division. Here, the multiple arithmetic logic units are built in the system to perform the
parallel arithmetic computation in various data format. Examples of the arithmetic
pipelined processor are Star-100, TI-ASC, Cray-1, Cyber-205.
2. Instruction Pipelining
Here, the number of instruction are pipelined and the execution of current
instruction is overlapped by the execution of the subsequent instruction. It is also
called instruction lookahead.
3. Processor Pipelining
Here, the processors are pipelined to process the same data stream. The data
stream is processed by the first processor and the result is stored in the memory block.
The result in the memory block is accessed by the second processor. The second
processor reprocesses the result obtained by the first processor and the passes the
refined result to the third processor and so on.
4. Unifunction Vs. Multifunction Pipelining
The pipeline performing the precise function every time is unifunctional
pipeline. On the other hand, the pipeline performing multiple functions at a different
time or multiple functions at the same time is multifunction pipeline.
5. Static vs Dynamic Pipelining
The static pipeline performs a fixed-function each time. The static pipeline is
unifunctional. The static pipeline executes the same type of instructions continuously.
Frequent change in the type of instruction may vary the performance of the pipelining.
Dynamic pipeline performs several functions simultaneously. It is a
multifunction pipelining.
 Digital Principles and System Design 4.19

6. Scalar vs Vector Pipelining

Scalar pipelining processes the instructions with scalar operands. The vector
pipeline processes the instruction with vector operands.
Pipelining Hazards
Whenever a pipeline has to stall due to some reason it is called pipeline hazards.
Below we have discussed four pipelining hazards.
1. Data Dependency
Consider the following two instructions and their pipeline execution:

In the figure above, you can see that result of the Add instruction is stored in the
register R2 and we know that the final result is stored at the end of the execution of the
instruction which will happen at the clock cycle t4.
But the Sub instruction need the value of the register R2 at the cycle t3. So the
Sub instruction has to stall two clock cycles. If it doesn’t stall it will generate an
incorrect result. Thus depending of one instruction on other instruction for data is data
dependency.
2. Memory Delay
When an instruction or data is required, it is first searched in the cache memory
if not found then it is a cache miss. The data is further searched in the memory which
may take ten or more cycles. So, for that number of cycle the pipeline has to stall and
this is a memory delay hazard. The cache miss, also results in the delay of all the
subsequent instructions.
3. Branch Delay
Suppose the four instructions are pipelined I1, I2, I3, I4 in a sequence. The
instruction I1 is a branch instruction and its target instruction is Ik. Now, processing
4.20 Processor

starts and instruction I1 is fetched, decoded and the target address is computed at the
4th stage in cycle t3.
But till then the instructions I2, I3, I4 are fetched in cycle 1, 2 & 3 before the
target branch address is computed. As I1 is found to be a branch instruction, the
instructions I2, I3, I4 has to be discarded because the instruction Ik has to be processed
next to I1. So, this delay of three cycles 1, 2, 3 is a branch delay.

Prefetching the target branch address will reduce the branch delay. Like if the
target branch is identified at the decode stage then the branch delay will reduce to 1
clock cycle.
 Digital Principles and System Design 4.21

4. Resource Limitation
If the two instructions request for accessing the same resource in the same clock
cycle, then one of the instruction has to stall and let the other instruction to use the
resource. This stalling is due to resource limitation. However, it can be prevented by
adding more hardware.

4.5 DATA HAZARDS

A data hazard occurs when there is a conflict in the access of an operand
location. In general terms, we can state the hazard in this form: Two instructions in a
program are to be executed in sequence and both access a particular memory or register
operand. If the two instructions are executed in strict sequence, no problem occurs.
However, if the instructions are executed in a pipeline, then it is possible for the
operand value to be updated in such a way as to produce a different result than would
occur with strict sequential execution. In other words, the program produces an
incorrect result because of the use of pipelining

In the above case, ADD instruction writes the result into the register R3 in t5. If
bubbles are not introduced to stall the next SUB instruction, all three instructions would
be using the wrong data from R3, which is earlier to ADD result. The program goes
wrong! The possible solutions before us are:
Solution 1: Introduce three bubbles at SUB instruction IF stage. This will facilitate
SUB – ID to function at t6. Subsequently, all the following instructions are also delayed
in the pipe.
4.22 Processor

Solution 2: Data forwarding - Forwarding is passing the result directly to the

functional unit that requires it: a result is forwarded from the output of one unit to the
input of another. The purpose is to make available the solution early to the next
instruction.
In this case, ADD result is available at the output of ALU in ADD –IE i.e t3 end.
If this can be controlled and forwarded by the control unit to SUB-IE stage at t4, before
writing on to output register R3, then the pipeline will go ahead without any stalling.
This requires extra logic to identify this data hazard and act upon it. It is to be noted that
although normally Operand Fetch happens in the ID stage, it is used only in IE stage.
Hence forwarding is given to IE stage as input. Similar forwarding can be done with OR
and AND instruction too.

Figure 4.12 Data forwarding solution for Data Hazard

Solution 3: Compiler can play a role in detecting the data dependency and reorder
(resequence) the instructions suitably while generating executable code. This way the
hardware can be eased.
Solution 4: In the event, the above reordering is infeasible, the compiler may detect and
introduce NOP (no operation) instruction(s). NOP is a dummy instruction equivalent
bubble, introduced by the software.
The compiler looks into data dependencies in code optimisation stage of the
compilation process.
Example :
Reordering Code to Avoid Pipeline Stalls
 Digital Principles and System Design 4.23

Consider the following code segment in C:

a = b + e;
c = b + f;
Here is the generated MIPS code for this segment, assuming all variables are in
memory and are addressable as off sets from $t0:
lw $t1, 0($t0)
lw $t2, 4($t0)
add $t3, $t1,$t2
sw $t3, 12($t0)
lw $t4, 8($t0)
add $t5, $t1,$t4
sw $t5, 16($t0)
Find the hazards in the preceding code segment and reorder the instructions to
avoid any pipeline stalls.
Both add instructions have a hazard because of their respective dependence on
the immediately preceding lw instruction. Notice that bypassing eliminates several other
potential hazards, including the dependence of the fi rstadd on the fi rstlw and any
hazards for store instructions. Moving up the third lw instruction to become the third
instruction eliminates both hazards:
lw $t1, 0($t0)
lw $t2, 4($t0)
lw $t4, 8($t0)
add $t3, $t1,$t2
sw $t3, 12($t0)
add $t5, $t1,$t4
sw $t5, 16($t0)
On a pipelined processor with forwarding, the reordered sequence will complete
in two fewer cycles than the original version.
Performance of Pipelines with Stalls
• A stall causes the pipeline performance to degrade from the ideal performance.
4.24 Processor

Speedup from pipelining = [ 1/ (1+ pipeline stall cycles per instruction) ] * Pipeline

Data Hazards classification

Data hazards are classified into three categories based on the order of READ or
WRITE operation on the register and as follows:
1. RAW (Read after Write) [Flow/True data dependency]
This is a case where an instruction uses data produced by a previous one.
Example
ADD R0, R1, R2
SUB R4, R3, R0
2. WAR (Write after Read) [Anti-Data dependency]
This is a case where the second instruction writes onto register before the first
instruction reads. This is rare in a simple pipeline structure. However, in some
machines with complex and special instructions case, WAR can happen.
ADD R2, R1, R0
SUB R0, R3, R4
3. WAW (Write after Write) [Output data dependency]
This is a case where two parallel instructions write the same register and must
do it in the order in which they were issued.
ADD R0, R1, R2
SUB R0, R4, R5
WAW and WAR hazards can only occur when instructions are executed in
parallel or out of order. These occur because the same register numbers have been
allotted by the compiler although avoidable. This situation is fixed by renaming one of
the registers by the compiler or by delaying the updating of a register until the
appropriate value has been produced. Modern CPUs not only have incorporated Parallel
execution with multiple ALUs but also Out of order issue and execution of instructions
along with many stages of pipelines. The example of Figure is a RAW hazard.
 Digital Principles and System Design 4.25

4.6 CONTROL HAZARDS

Control hazards A control hazard, also known as a branch hazard, occurs when
the pipeline makes the wrong decision on a branch prediction and therefore brings
instructions into the pipeline that must subsequently be discarded.
A Conditional hazard occurs when the decision to execute an instruction is
based on the result of another instruction like a conditional branch, which checks the
condition’s resultant value.
Dealing with Branches
One of the major problems in designing an instruction pipeline is assuring a
steady flow of instructions to the initial stages of the pipeline. The primary impediment,
as we have seen, is the conditional branch instruction. Until the instruction is actually
executed, it is impossible to determine whether the branch will be taken or not.
A variety of approaches have been taken for dealing with conditional branches:
• Multiple streams
• Prefetch branch target
• Loop buffer
• Branch prediction
• Delayed branch
Multiple Streams: A simple pipeline suffers a penalty for a branch instruction because
it must choose one of two instructions to fetch next and may make the wrong choice.
A brute-force approach is to replicate the initial portions of the pipeline and allow
the pipeline to fetch both instructions, making use of two streams. There are two
problems with this approach:
4.26 Processor

❖ With multiple pipelines there are contention delays for access to the registers
and to memory.
❖ Additional branch instructions may enter the pipeline (either stream) before the
original branch decision is resolved. Each such instruction needs an additional
stream.
Prefetch Branch Target When a conditional branch is recognized, the target of the
branch is prefetched, in addition to the instruction following the branch. This target is
then saved until the branch instruction is executed. If the branch is taken, the target has
already been prefetched.
Loop Buffer A loop buffer is a small, very-high-speed memory maintained by the
instruction fetch stage of the pipeline and containing the n most recently fetched
instructions, in sequence. If a branch is to be taken, the hardware first checks whether
the branch target is within the buffer.
Delayed Branch It is possible to improve pipeline performance by automatically
rearranging instructions within a program, so that branch instructions occur later than
actually desired.
The branch and jump instructions decide the program flow by loading the
appropriate location in the Program Counter (PC). The PC has the value of the next
instruction to be fetched and executed by CPU. Consider the following sequence of
instructions.

Figure 4.13 Control Hazard scenario

In this case, there is no point in fetching the I3. What happens to the pipeline?
While in I2, the I3 fetch needs to be stopped. This can be known only after I2 is
 Digital Principles and System Design 4.27

decoded as JMP and not until then. So the pipeline cannot proceed at its speed and
hence this is a Control Dependency (hazard). In case I3 is fetched in the meantime, it is
not only a redundant work but possibly some data in registers might have got altered
and needs to be undone.
Similar scenarios arise with conditional JMP or BRANCH.
Solutions for Conditional Hazards
1. Stall the Pipeline as soon as decoding any kind of branch instructions. Just not
allow anymore IF. As always, stalling reduces throughput. The statistics say that
in a program, at least 30% of the instructions are BRANCH. Essentially the
pipeline operates at 50% capacity with Stalling.
2. Prediction – Imagine a for or while loop getting executed for 100 times. We
know for sure 100 times the program flows without the branch condition being
met. Only in the 101st time, the program comes out of the loop. So, it is wiser to
allow the pipeline to proceed and undo/flush when the branch condition is met.
This does not affect the throttle of the pipeline as much stalling.
3. Dynamic Branch Prediction - A history record is maintained with the help of
Branch Table Buffer (BTB). The BTB is a kind of cache, which has a set of
entries, with the PC address of the Branch Instruction and the corresponding
effective branch address. This is maintained for every branch instruction
encountered. So, whenever a conditional branch instruction is encountered, a
lookup for the matching branch instruction address from the BTB is done. If hit,
then the corresponding target branch address is used for fetching the next
instruction. This is calleddynamic branch prediction. This method is successful
to the extent of the temporal locality of reference in the programs. When the
prediction fails flushing needs to take place.
4. Reordering instructions - Delayed branch i.e. reordering the instructions to
position the branch instruction later in the order, such that safe and useful
instructions which are not affected by the result of a branch are brought-in
earlier in the sequence thus delaying the branch instruction fetch. If no such
instructions are available then NOP is introduced. This delayed branch is applied
with the help of Compiler.
 5
MEMORY AND I/O

5.1 MEMORY CONCEPTS AND HIERARCHY

5.1.1 Memory Concepts
Memory unit enables us to store data inside the computer. The computer memory
alwaysadheres to principle of locality.
Principle of locality or locality of reference is the tendency of a processor to
access the same set of memory locations repetitively over a short period of time.

Two different types of locality are:

• Temporal locality: The principle stating that if a data location is
referencedthen it will tend to be referenced again soon.
• Spatial locality: The locality principle stating that if a data location is
referenced, data locations with nearby addresses will tend to be referenced
soon.
The locality of reference is useful in implementing the memory hierarchy.
Memory hierarchy is a structure that uses multiple levels of memories; as the
distance from the CPU increases, the size of the memories and the access time
both increase.

A memory hierarchy consists of multiple levels of memory with different speeds

and sizes. Thefaster memories are more expensive per bit than the slower memories
and thus smaller.
5.2 Memory and I/O

Fig 5.1 Memory Hierarchy

• Main memory is implemented from Dynamic Random Access Memory
(DRAM).
• The levels closer to the processor (caches) use Static Random Access Memory
(SRAM).
• DRAM is less costly per bit than SRAM, although it is substantially slower.
• For each k, the faster, smaller device at level k serves as a cache for the larger,
slower device at level k+1.
• The computer programs tend to access the data at level k more often that at level
k+1.
• The storage at level at k+1 can be slower.
• Cache memory (CPU memory) is high-speed SRAM that a computer
microprocessor can access more quickly than it can access regular RAM.
This memory is typically integrated directly into the CPU chip or placed
on aseparate chip that has a separate bus interconnect with the CPU.
The data transfer between various levels of memory is done through blocks. The
minimum unit of information is called a block. If the data requested by the processor
appears in some block in the upper level, this is called a hit. If the data is not found in
the upper level, the request is called a miss. The lower level in the hierarchy is then
accessed to retrieve the block containing the requested data.
 Digital Principles and System Design 5.3

Fig 5.2: Data access by processor

The fraction of memory accesses found in a cache is termed as hit rate or
hit ratio.
Miss rate is the fraction of memory accesses not found in a level of the
memory hierarchy. Hit time is the time required to access a level of the memory
hierarchy, including the time needed to determine whether the access is a hit or a
miss.
Miss penalty is the time required to fetch a block into a level of the memory
hierarchy from the lower level, including the time to access the block,
transmit it from one level to the other, and insert it in the level that
experienced the miss.

Because the upper level is smaller and built using faster memory parts, the
hit time will be much smaller than the time to access the next level in the hierarchy,
which is the major component of the miss penalty.

5.1.2 MEMORY HIERARCHY

A memory unit is a collection of semi-conductor storage cells with circuits to
access the data stored in them. The data storage in memory is done in words. The
number of bits in a word depends on the architecture of the computer. Generally a
word is always multiple of 8. Memory is accessed through unique system assigned
address. The accessing of data from memory is based on principle of locality.
5.4 Memory and I/O

Principle of Locality
The locality of reference or the principle of locality is the term applied to
situations where the same value or related storage locations are frequently accessed.
There are three basic types of locality of reference:
• Temporal locality: Here a resource that is referenced at one point in time is
referencedagain soon afterwards.
• Spatial locality: Here the likelihood of referencing a storage location is
greater if astorage location near it has been recently referenced.
• Sequential locality: Here storage is accessed sequentially, in descending or
ascendingorder.The locality or reference leads to memory hierarchy.
Need for memory hierarchy
Memory hierarchy is an approach for organizing memory and storage systems. It
consist of multiple levels of memory with different speeds and sizes. The following are
the reasons for such organization:
➢ Fast storage technologies cost more per byte and have less capacity
➢ Gap between CPU and main memory speed is widening
➢ Well-written programs tend to exhibit good locality.
The memory hierarchy is shown in Fig 5.1. The entire memory elements of
the computerfall under the following three categories:
• Processor Memory:
This is present inside the CPU for high-speed data access. This consists of
small set of registers that act as temporary storage. This is the costliest
memory component.
• Primary memory:
This memory is directly accessed by the CPU. All the data must be brought
inside main memory before accessing them. Semiconductor chips acts as main
memory.
• Secondary memory:
This is cheapest, large and relatively slow memory component. The data from
the secondary memory is accessed by the CPU only after it is loaded to main
memory.
 Digital Principles and System Design 5.5

There is a trade-off among the three key characteristics of memory namely-

• Cost
• Capacity
• Access time
Terminologies in memory access
• Block or line: The minimum unit of information that could be either present
or totallyabsent.
• Hit: If the requested data is found in the upper levels of memory hierarchy it
is calledhit.
• Miss: If the requested data is not found in the upper levels of memory
hierarchy it iscalled miss.
• Hit rate or Hit ratio: It is the fraction of memory access found in the upper
level .Itis a performance metric.
Hit Ratio = Hit/(Hit + Miss)
• Miss rate: It is the fraction of memory access not found in the upper level (1-
hit rate).
• Hit Time: The time required for accessing a level of memory hierarchy,
including the time needed for finding whether the memory access is a hit or
miss.
• Miss penalty: The time required for fetching a block into a level of the
memory hierarchy from the lower level, including the time to access, transmit,
insert it to new level and pass the block to the requestor.
• Bandwidth: The data transfer rate by the memory.
• Latency or access time: Memory latency is the length of time between the
memory’s receipt of a read request and its release of data corresponding
with the request.
• Cycle time: It is the minimum time between requests to memory.
The memory access time increases as the level increases. Since the CPU
registers are located in very close proximity to the CPU they can be accessed very
quickly and they are the more costly. As the level increases, the memory access time
also increases thereby decreasing the costs.
5.6 Memory and I/O

Fig 5.3: Memory level vs Access Time

Levels in Memory Hierarchy
The following are the levels in memory hierarchy:
• CPU Registers:
They are at the top most level of this hierarchy, they hold the most frequently used
data. They are very limited in number and are the fastest. They are often used
by the CPU and the ALU for performing arithmetic and logical operations, for
temporary storageof data.
• Static Random Access Memory (SRAM):
Static Random Access Memory (Static RAM or SRAM) is a type of RAM that
holds data in a static form, that is, as long as the memory has power. SRAM
stores a bit of data on four transistors using two cross-coupled inverters. The two
stable states characterize 0 and 1. During read and write operations another two
access transistors are used to manage the availability to a memory cell.
• Main memory or Dynamic Random Access Memory (DRAM):
Dynamic random access memory (DRAM) is a type of memory that is
typically used for data or program code that a computer processor needs to
function. In other words it is said to be the main memory of the computer.
Random access allows processor to access any part of the memory directly rather
than having to proceed sequentially from a starting place. The main advantages
 Digital Principles and System Design 5.7

of DRAM are its simple design, speed and low cost in comparison to alternative
types of memory. The main disadvantages of DRAM are volatility and high
power consumption relative to other options.
• Local Disks (Local Secondary Storage):
A local drive is a computer disk drive that is installed directly within the
host or the local computer. It is a computer’s native hard disk drive (HDD), which
is directly accessed by the computer for storing and retrieving data. It is a cheaper
memory with more memory access time.
• Remote Secondary Storage:
This includes Distributed file system (DFS) and online storage like cloud. The
storage area is vast with low cost but larger access time.
Distinction between Static RAM and Dynamic RAM
SRAM DRAM
Stores data till the power is supplied. Stored data only for few milliseconds
irrespective of the power supply.
Uses nearly 6 transistors for each Uses single transistor and capacitor
memory cell. for each memory cell.
Do not refresh the memory cell. Refreshing circuitry is needed.
Faster data access. Slower access.
Consumes more power. Low power consumption.
Cost pet bit is high. Comparatively lower costs.
They are made of more number of They are made of less number of
components per cells. components per cells.

5.2 MEMORY MANAGEMENT

• Memory Management is the process of controlling and coordinating computer
memory, assigning portions known as blocks to various running programs to
optimize the overall performance of the system.
• It is the most important function of an operating system that manages primary
memory. It helps processes to move back and forward between the main
memory and execution disk.
5.8 Memory and I/O

• It helps OS to keep track of every memory location, irrespective of whether it is

allocated to some process or it remains free.
Swapping:
• Swapping is a mechanism in which a process can be swapped temporarily out of
main memory (or move) to secondary storage (disk) and make that memory
available to other processes. At some later time, the system swaps back the
process from the secondary storage to main memory.
Benefits of Swapping
Here, are major benefits/pros of swapping:
• It offers a higher degree of multiprogramming.
• Allows dynamic relocation. For example, if address binding at execution time is
being used, then processes can be swap in different locations. Else in case of
compile and load time bindings, processes should be moved to the same
location.
• It helps to get better utilization of memory.
• Minimum wastage of CPU time on completion so it can easily be applied to a
priority-based scheduling method to improve its performance.
What is Memory allocation?
Memory allocation is a process by which computer programs are assigned
memory or space.
Here, main memory is divided into two types of partitions
1. Low Memory - Operating system resides in this type of memory.
2. High Memory- User processes are held in high memory.
Partition Allocation
Memory is divided into different blocks or partitions. Each process is allocated
according to the requirement. Partition allocation is an ideal method to avoid internal
fragmentation.
Below are the various partition allocation schemes:
First Fit: In this type fit, the partition is allocated, which is the first sufficient block
from the beginning of the main memory.
 Digital Principles and System Design 5.9

Best Fit: It allocates the process to the partition that is the first smallest partition among
the free partitions.
Worst Fit: It allocates the process to the partition, which is the largest sufficient freely
available partition in the main memory.
Next Fit: It is mostly similar to the first Fit, but this Fit, searches for the first sufficient
partition from the last allocation point.
What is Paging?
• Paging is a storage mechanism that allows OS to retrieve processes from the
secondary storage into the main memory in the form of pages.
• In the Paging method, the main memory is divided into small fixed-size blocks
of physical memory, which is called frames.
• The size of a frame should be kept the same as that of a page to have maximum
utilization of the main memory and to avoid external fragmentation. Paging is
used for faster access to data, and it is a logical concept.
What is Fragmentation?
Processes are stored and removed from memory, which creates free memory
space, which are too small to use by other processes.
After sometimes, that processes not able to allocate to memory blocks because
its small size and memory blocks always remain unused is called fragmentation. This
type of problem happens during a dynamic memory allocation system when free blocks
are quite small, so it is not able to fulfill any request.
Two types of Fragmentation methods are:
1. External fragmentation
2. Internal fragmentation
• External fragmentation can be reduced by rearranging memory contents to
place all free memory together in a single block.
• The internal fragmentation can be reduced by assigning the smallest
partition, which is still good enough to carry the entire process.
What is Segmentation?
• Segmentation method works almost similarly to paging.
• The only difference between the two is that segments are of variable-length,
5.10 Memory and I/O

whereas, in the paging method, pages are always of fixed size.

• A program segment includes the program's main function, data structures, utility
functions, etc. The OS maintains a segment map table for all the processes. It
also includes a list of free memory blocks along with its size, segment numbers,
and its memory locations in the main memory or virtual memory.
What is Dynamic Loading?
Dynamic loading is a routine of a program which is not loaded until the program
calls it. All routines should be contained on disk in a relocatable load format. The main
program will be loaded into memory and will be executed. Dynamic loading also
provides better memory space utilization.
What is Dynamic Linking?
Linking is a method that helps OS to collect and merge various modules of code
and data into a single executable file. The file can be loaded into memory and executed.
OS can link system-level libraries into a program that combines the libraries at load
time.
In Dynamic linking method, libraries are linked at execution time, so program
code size can remain small.

5.3 CACHE MEMORIES

Cache memory or CPU memory is high-speed SRAM that a processor can
access more quickly than a regular RAM. This memory is integrated directly into
the CPU chip or placed on a separate chip that has a separate bus interconnect
with the CPU.
The cache memory stores instructions and data that are more frequently used or
data that is likely to be used next. The processor looks first in the cache memory
for the data. If it finds the instructions or data then it does perform a more time-
consuming reading of data from larger main memory or other data storage devices.
The processor do not need to know the exact location of the cache. It can
simply issue read and write instructions. The cache control circuitry determines
whether the requested data resides in the cache.
• Cache and temporal reference: When data is requested by the processor, the
data should be loaded in the cache and should be retained till it is needed
again.
 Digital Principles and System Design 5.11

• Cache and spatial reference: Instead of fetching single data, a contiguous

block of data is loaded into the cache.
Terminologies in Cache
• Split cache: It has separate data cache and a separate instruction cache. The two
caches work in parallel, one transferring data and the other transferring
instructions.
• A dual or unified cache: The data and the instructions are stored in the
same cache. A combined cache with a total size equal to the sum of the two split
caches will usually have a better hit rate.
• Mapping Function: The correspondence between the main memory blocks
and those in the cache is specified by a mapping function.
• Cache Replacement: When the cache is full and a memory word that is not in
the cache is referenced, the cache control hardware must decide which block
should be removed to create space for the new block that contains the
referenced word. The collection of rules for making this decision is the
replacement algorithm.
Cache performance:
When the processor needs to read or write a location in main memory, it first
checks for a corresponding entry in the cache. If the processor finds that the
memory location is in the cache, a cache hit has said to be occurred. If the processor
does not find the memory location in the cache, a cache miss has occurred. When a
cache miss occurs, the cache replacement is made by allocating a new entry and copies
in data from main memory. The performance of cache memory is frequently measured
in terms of a quantity called Hit ratio.
Hit ratio = hit / (hit + miss) = Number of hits/ Total accesses to the cache
Miss penalty or cache penalty is the sum of time to place a bock in the
cache and time todeliver the block to CPU.
Miss Penalty= time for block replacement + time to deliver the block to CPU
Cache performance can be enhanced by using higher cache block size, higher
associativity, reducing miss rate, reducing miss penalty, and reducing the time to hit in
the cache. CPU execution Time of a given task is defined as the time spent by the
system executing that task, including the time spent executing run-time or system
services.
5.12 Memory and I/O

CPU execution time=(CPU clock cycles + memory stall cycles (if any))x
Clock cycle time
The memory stall cycles are a measure of count of the memory cycles during
which the CPU is waiting for memory accesses. This is dependent on caches misses
and cost per miss (cache penalty).
Memory stall cycles = number of cache misses x miss penalty
= Instruction Count x (misses/ instruction) x miss penalty
= Instruction Count (IC) x (memory access/ instruction) x miss
penalty
= IC x Reads per instruction x Read miss rate X Read miss
penalty
+ IC x Write per instruction x Write miss rate X Write
miss penalty
Misses / instruction = (miss rate x memory access)/ instruction
Issues in Cache memory:
• Cache placement: where to place a block in the cache?
• Cache identification: how to identify that the requested information is
available in thecache or not?
• Cache replacement: which block will be replaced in the cache, making
way for anincoming block?
Cache Mapping Policies:
These policies determine the way of loading the main memory to the cache
block. Main memory is divided into equal size partitions called as blocks or frames.
The cache memory is divided into fixed size partitions called as lines. During
cache mapping, block of main memory is copied to the cache and further access is
made from the cache not fromthe main memory.
Cache mapping is a technique by which the contents of main memory are
brought into the cache memory.
 Digital Principles and System Design 5.13

Fig 5.4: Cache mapping

Handling Cache misses:
When a program accesses a memory location that is not in the cache, it is called
a cache miss. The performance impact of a cache miss depends on the latency of
fetching the data from the next cache level or main memory. The cache miss handling is
done with the processor control unit and with a separate controller that initiates the
memory access and refills the cache. The following are the steps taken when a
cache miss occurs:
• Send the original PC value (PC - 4) to the memory.
• Instruct main memory to perform a read and wait for the memory to complete
its access.
• Write the cache entry, putting the data from memory in the data portion of the
entry, writing the upper bits of the address (from the ALU) into the tag field, and
turning the valid bit on.
• Restart the instruction execution at the first step, which will re fetch the
instruction, this time finding it in the cache.
Writing to a cache:
• Suppose on a store instruction, the data is written into only the data cache
(without changing main memory); then, after the write into the cache, memory
would have a different value from that in the cache. This leads to
inconsistency.
• The simplest way to keep the main memory and the cache consistent is to
always write the data into both the memory and the cache. This scheme is
called write-through.
5.14 Memory and I/O

Write through is a scheme in which writes always update both the cache
and thememory, ensuring that data is always consistent between the two.

• With a write-through scheme, every write causes the data to be written to main
memory.These writes will take a long time.
• A potential solution to this problem is deploying write buffer.
• A write buffer stores the data while it is waiting to be written to memory.
• After writing the data into the cache and into the write buffer, the processor
can continueexecution.
• When a write to main memory completes, the entry in the write buffer is
freed.
• If the write buffer is full when the processor reaches a write, the processor must
stall until there is an empty position in the write buffer.
• If the rate at which the memory can complete writes is less than the rate at which
the processor is generating writes, no amount of buffering can help because
writes are being generated faster than the memory system can accept them.
Write buffer is a queue that holds data while the data are waiting to be written
to memory.
• The rate at which writes are generated may also be less than the rate at which the
memory can accept them, and yet stalls may still occur. To reduce the
occurrence of such stalls, processors usually increase the depth of the write
buffer beyond a single entry.
• Another alternative to a write-through scheme is a scheme called write-back.
When a write occurs, the new value is written only to the block in the
cache.
• The modified block is written to the lower level of the hierarchy when it is
replaced.
• Write-back schemes can improve performance, especially when processors can
generate writes as fast or faster than the writes can be handled by main memory;
a write-back scheme is, however, more complex to implement than write-
through.
Write-back is a scheme that handles writes by updating values only to the
block in the cache, then writing the modified block to the lower level of the
hierarchy whenthe block is replaced.
 Digital Principles and System Design 5.15

Example 5.1: Program P runs on computer A in 10 seconds. Designer says clock

rate can be increased significantly, but total cycle count will also increase by 20%.
What clock rate do we need on computer B for P to run in 6 seconds? (Clock rate
on A is 100 MHz).
The new machine is B. We want CPU Time_B = 6 seconds.
We know that Cycles count_B = 1.2 Cycles count_A. Calculate Cycles
count_A.CPU Time_A = 10 sec. = ; Cycles count_A = 1000 x 106 cycles
Calculate Clock rate_B:
CPU Time_B = 6 sec. = ; Clock rate_B = = 200 MHz
Machine B must run at twice the clock rate of A to achieve the target
execution time.
Example 5.2: We have two machines with different implementations of the same ISA.
Machine A has a clock cycle time of 10 ns and a CPI of 2.0 for program P; machine
B has a clock cycle time of 20 ns and a CPI of 1.2 for the same program. Which
machine isfaster?Let IC be the number of instructions to be executed. Then
Cycles count_A = 2.0 IC Cycles count_B = 1.2 IC
calculate CPU Time for each machine:
CPU Time_A = 2.0 IC x 10 ns = 20.0 IC ns CPU Time_B = 1.2 IC x 20
ns = 24.0 IC ns
» Machine A is 20%faster.
Example 5.3: Consider an implementation of MIPS ISA with 500 MHz clock and
– each ALU instruction takes 3 clock cycles,
– each branch/jump instruction takes 2 clock cycles,
– each sw instruction takes 4 clock cycles,
– eachlw instruction takes 5 clock cycles.
Also, consider a program that during its execution executes:
– x=200 million ALU instructions
– y=55 million branch/jump instructions
– z=25 million sw instructions
– w=20 million lw instructions
5.16 Memory and I/O

Find CPU time. Assume sequentially executing CPU. Clock cycles for a
program = (3x + 2y + 4z + 5w)
= 910 x 106 clock cyclesCPU_time = Clock cycles for a program / Clock rate
= 910 x 106 / 500 x 106 = 1.82 sec
Example 5.4: Consider another implementation of MIPS ISA with 1 GHz clock
and
– each ALU instruction takes 4 clock cycles,
– each branch/jump instruction takes 3 clock cycles,
– each sw instruction takes 5 clock cycles,
– eachlw instruction takes 6 clock cycles.
Also, consider the same program as in Example 1.
Find CPI and CPU time. Assume sequentially executing CPU.CPI
= (4x + 3y + 5z + 6w) / (x + y + z + w)
= 4.03 clock cycles/ instruction
CPU time = Instruction count x CPI / Clock rate
= (x+y+z+w) x 4.03 / 1000 x 106
= 300 x106 x 4.03 /1000 x 106
= 1.21 sec

5.4 MAPPING AND REPLACEMENT TECHNIQUES

• The mapping functions are used to map a particular block of main memory to a
particular block of cache. This mapping function is used to transfer the block
from main memory to cache memory.
• Three different mapping functions are available:
i) Direct mapping
ii) Fully Associative mapping
iii) Set Associative mapping
Direct Mapping
• The simplest technique is direct mapping that maps each block of main
memory intoonly one possible cache line.
 Digital Principles and System Design 5.17

• Here, each memory block is assigned to a specific line in the cache.

• If a line is previously taken up by a memory block and when a new block
needs to beloaded, then the old block is replaced.
• Direct mapping‘s performance is directly proportional to the Hit ratio.

The direct mapping concept is if the ith block of main memory has to be
placed at the jth block of cache memory.j = i % (number of blocks in
cache memory)

• Consider a 128 block cache memory. Whenever the main memory blocks 0,
128, 256 are loaded in the cache, they will be allotted cache block 0, since j=
(0 or 128 or 256) % 128 is zero).
• Contention or collision is resolved by replacing the older contents with latest
contents.
• The placement of the block from main memory to the cache is determined
from the16 bit memory address.
• The lower order four bits are used to select one of the 16 words in the
block.
• The 7 bit block field indicates the cache position where the block has to
be stored.
• The 5 bit tag field represents which block of main memory resides inside
the cache.
• This method is easy to implement but is not flexible.
Drawback: The problem was that every block of main memory was directly
mapped to the cache memory. This resulted in high rate of conflict miss. Cache
memory has to be very frequently replaced even when other blocks in the cache memory
were present as empty.
5.18 Memory and I/O

Fig 5.5: Direct memory mapping

Associative Mapping:
• The associative memory is used to store content and addresses of the
memory word.
• Any block can go into any line of the cache. The 4 word id bits are used to
identify which word in the block is needed and the remaining 12 bits represents
the tag bit that identifies the main memory block inside the cache.
• This enables the placement of any word at any place in the cache memory. It is
considered to be the fastest and the most flexible mapping form.

Fig 5.6 : Associative Mapping

 Digital Principles and System Design 5.19

• The tag bits of an address received from the processor are compared to the
tag bits of each block of the cache to check, if the desired block is present.
Hence it is knownas Associative Mapping technique.
• Cost of an associated mapped cache is higher than the cost of direct-mapped
because of the need to search all 128 tag patterns to determine whether a
block is in cache.
Set associative mapping:
• It is the combination of direct and associative mapping technique.
• Cache blocks are grouped into sets and mapping allow block of main memory to
reside into any block of a specific set.
• This reduces contention problem (issue in direct mapping) with low hardware
cost (issue in associative mapping).
• Consider a cache with two blocks per set. In this case, memory block 0, 64,
128,…..,4032 map into cache set 0 and they can occupy any two block
within this set.
• It does this by saying that instead of having exactly one line that a block
can map to in the cache, we will group a few lines together creating a set. Then
a block in memory can map to any one of the lines of a specific set.
• The 6 bit set field of the address determines which set of the cache might contain
the desired block. The tag bits of address must be associatively compared to
the tags of the two blocks of the set to check if desired block is present.

Fig 5.7 : Set associative mapping

5.20 Memory and I/O

Replacement Algorithms
When a main memory block needs to be brought into the cache while all the
blocks are occupied, then one of them has to be replaced. This selection of the block to
be replaced is using cache replacement algorithms. Replacement algorithms are only
needed for associative and set associative techniques. The following are the common
replacementtechniques:
• Least Recently Used (LRU): This replaces the cache line that has been in
the cache the longest with no references to it.
• First-in First-out (FIFO): This replaces the cache line that has been in the
cache the longest.
• Least Frequently Used (LFU): This replaces the cache line that has
experienced the fewest references.
• Random: This picks a line at random from the candidate lines.

5.5 VIRTUAL MEMORY

Virtual memory is a memory management capability of an operating
system that uses hardware and software to allow a computer to compensate
for physical memory shortages by temporarily transferring data from RAM
to disk storage.

The concept of virtual memory in computer organisation is allocating memory

from the hard disk and making that part of the hard disk as a temporary RAM. In
other words, it is a technique that uses main memory as a cache for secondary storage.
The motivationsfor virtual memory are:
• To allow efficient and safe sharing of memory among multiple programs
• To remove the programming burdens of a small, limited amount of main
memory.
Virtual memory provides an illusion to the users that the PC has enough primary
memory left to run the programs.
Sometimes the size of programs to be executed may sometimes very bigger than
the size of primary memory left, the user never feels that the system needs a bigger
primary storage to run that program.
When the RAM is full, the operating system occupies a portion of the hard disk
 Digital Principles and System Design 5.21

and uses it as a RAM. In that part of the secondary storage, the part of the program
which not currently being executed is stored and all the parts of the program that are
executed are first brought into the main memory.
This is the theory behind virtual memory.
Terminologies:
• Physical address is an address in main memory.
• Protection is a set of mechanisms for ensuring that multiple processes sharing
the processor, memory, or I/O devices cannot interfere, with one another by
reading or writing each other’s data.
• Virtual memory breaks programs into fixed-size blocks called pages.
• Page fault is an event that occurs when an accessed page is not present in main
memory.
• Virtual address is an address that corresponds to a location in virtual space and
is translated by address mapping to a physical address when memory is
accessed.
• Address translation or address mapping is the process by which a virtual address
is mapped to an address used to access memory.
Working mechanism
• In virtual memory, blocks of memory are mapped from one set of
addresses (virtual addresses) to another set (physical addresses).
• The processor generates virtual addresses while the memory is accessed using
physical addresses.
• Both the virtual memory and the physical memory are broken into pages, so that
a virtual page is really mapped to a physical page.
• It is also possible for a virtual page to be absent from main memory and not be
mapped to a physical address, residing instead on disk.
• Physical pages can be shared by having two virtual addresses point to the same
physical address. This capability is used to allow two different programs to
share data or code.
• Virtual memory also simplifies loading the program for execution by providing
relocation. Relocation maps the virtual addresses used by a program to different
physical addresses before the addresses are used to access memory. This
5.22 Memory and I/O

relocation allows us to load the program anywhere in main memory.

Fig 5.8 : Mapping of virtual and physical memory

Addressing in virtual memory
• A virtual address is considered as a pair (p,d) where lower order bits give an
offset dwithin the page and high-order bits specify the page p.
• The job of the Memory Management Unit (MMU) is to translate the page
number pto a frame number f.
• The physical address is then (f,d), and this is what goes on the memory
bus.
• For every process, there is a page and page-number p is used as an index into
this arrayfor the translation.
• The following are the entries in page tables:
1. Validity bit: Set to 0 if the corresponding page is not in memory
2. Frame number: Number of bits required depends on size of physical
memory
3. Protection bits: Read, write, execute accesses
4. Referenced bit is set to 1 by hardware when the page is accessed: used
by pagereplacement policy
5. Modified bit (dirty bit) set to 1 by hardware on write-access: used to avoid
writingwhen swapped out.
 Digital Principles and System Design 5.23

Fig 5.9: Conversion of logical address to physical address

5.6 DMA
• Direct Memory Access (DMA) means CPU grants I/O module authority to
read fromor write to memory without involvement.
• DMA module controls exchange of data between main memory and the I/O
device.
• Because of DMA device can transfer data directly to and from memory, rather
than using the CPU as an intermediary, and can thus relieve congestion on
the bus.
• CPU is only involved at the beginning and end of the transfer and interrupted
only afterentire block has been transferred.
• The CPU programs the DMA controller by setting its registers so it knows
what totransfer where.
• It also issues a command to the disk controller telling it to read data from the
disk intoits internal buffer and verify the checksum.
• When valid data are in the disk controller’s buffer, DMA can begin. The DMA
controllerinitiates the transfer by issuing a read request over the bus to the
disk controller.
5.24 Memory and I/O

• This read request looks like any other read request, and the disk controller
does notknow whether it came from the CPU or from a DMA controller.

Fig 5.10 : CPU bus signals for DMA transfer

• The memory address to write to is on the bus address lines, so when the disk
controllerfetches the next word from its internal buffer, it knows where to
write it.
• The write to memory is another standard bus cycle.
• When the write is complete, the disk controller sends an acknowledgement
signal tothe DMA controller, also over the bus.

Fig 5.11 : Operations in DMA

• The DMA controller then increments the memory address to use and
decrements the byte count. If the byte count is still greater than 0, steps 2
through 4 are repeated untilthe count reaches 0.
 Digital Principles and System Design 5.25

• At that time, the DMA controller interrupts the CPU to let it know that the
transfer isnow complete.
• When the operating system starts up, it does not have to copy the disk block to
memory;it is already there.
• The DMA controller requests the disk controller to transfer data from the disk
controller’s buffer to the main memory. In the first step, the CPU issues a
command to the disk controller telling it to read data from the disk into its
internal buffer.

5.7 I/O
• The method that is used to transfer information between internal storage and
external I/O devices is known as I/O interface.
• The CPU is interfaced using special communication links by the peripherals
connected to any computer system. These communication links are used to
resolve the differences between CPU and peripheral.
• There exists special hardware components between CPU and peripherals to
supervise and synchronize all the input and output transfers that are called
interface units.
Mode of Transfer:
• The binary information that is received from an external device is usually
stored in the memory unit.
• The information that is transferred from the CPU to the external device is
originated from the memory unit. CPU merely processes the information but
the source and target is always the memory unit.
• Data transfer between CPU and the I/O devices may be done in different
modes.
• Data transfer to and from the peripherals may be done in any of the three
possible ways
➢ Programmed I/O.
➢ Interrupt- initiated I/O.
➢ Direct memory access ( DMA).
5.26 Memory and I/O

5.8 ACCESSING I/O

• A simple arrangement to connect I/O devices to a computer is to use a single bus
arrangement, as shown in figure 5.12.
• Each I/O device is assigned a unique set of address. When the processor places a
particular address on the address lines, the device that recognizes this address
responds to the commands issued on the control lines.
• The processor requests either a read or a write operation which is transferred
over the data lines. When I/O devices and the memory share the same address
space, the arrangement is called memory-mapped I/O.

Figure 5.12 A single-bus structure

• Consider, for instance, with memory-mapped I/O, if DATAIN is the address of
the input buffer of the keyboard
Move DATAIN, R0
And DATAOUT is the address of the output buffer of the display/printer Move
R0, DATAOUT
• This sends the contents of register R0 to location DATAOUT, which may be the
output databuffer of a display unit or a printer.
• Most computer systems use memory-mapped I/O. Some processors have special
I/O instructions to perform I/O transfers. The hardware required to connect an
I/O device to the bus is shown below:
• The address decoder enables the device to recognize its address when this
address appears on the address lines.
• The data register holds the data. The status register contains information. The
address decoder, data and status registers and controls required to coordinate I/O
transfers constitutes interface circuit
 Digital Principles and System Design 5.27

Figure 5.13 I/O interface for an input device

• For eg: Keyboard, an instruction that reads a character from the keyboard should
be executed only when a character is available in the input buffer of the
keyboard interface.
• The processor repeatedly checks a status flag to achieve the synchronization
between processor and I/O device, which is called as program-controlled I/O.
• Two commonly used mechanisms for implementing I/O operations are:
• Interrupts and
• Direct memory access
Interrupts: synchronization is achieved by having the I/O device send a special signal
overthe bus whenever it is ready for a data transfer operation.
Direct memory access: For high speed I/O devices. The device interface transfer data
directly to or from the memory without informing the processor.

5.9 PARALLEL AND SERIAL INTERFACE

• There are two ways of transmittinga byte between two digital devices.
• We can either transmit the byte in Parallel or we can transmit the byte in Serial
form.
• The Figure 5.14 illustrates the differences between these two types of
communication mechanisms.
5.28 Memory and I/O

Figure 5.14 Serial and Parallel Interface

5.9.1 Serial Interface
• Serial Interface is the process of sequentially transferring the information/bits
on the same channel. Due to this, the cost of wire will be reduced, but it slows
the transmission speed.
• Generally, communication can be described as the process of interchanging
information between individuals in the form of audio, video, verbal words, and
written documents.
• The serial protocol is run on every device that can be our mobile, personal
computers, and many more with the help of following some protocols.
 Digital Principles and System Design 5.29

• The protocol is a type of reliable and secure form of communication that

contains a set of rules addressed with the help of a source host and a destination
host. In serial communication, binary pulses are used to show the data.
• Binary contains the two numbers 0 and 1. 0 is used to show the LOW or 0
Volts, and 1 is used to show the HIGH or 5 Volts. The serial interface can
either be asynchronous or synchronous.
Synchronous Communication
• In synchronous communication, the frames or data will be constructed with the
help of combining the groups of bits. That frames will be continuously sent in
time with a master clock.
• It uses a synchronized clock frequency to operate the data of sender or receiver.
In synchronous communication, there is no need to use the gaps, start bits and
stop bits. The time taken by the sender and receiver is synced that's why the
frequency of timing error will be less, and the data will move faster.
• On the basis of the timing being synced correctly between the sender and
receiver devices, the data accuracy is totally dependent. The synchronous serial
transmission is more expensive as compared to asynchronous serial
transmission.

Figure 5.15 Synchronous Transmission

Asynchronous Communication
• In asynchronous communication, the groups of bits will be treated as an
independent unit, and these data bits will be sent at any point in time.
• In order to make synchronization between sender and receiver, the stop bits and
start bits are used between the data bytes. These bits are useful to ensure that the
data is correctly sent. The time taken by data bits of sender and receiver is not
constant, and the time between transmissions will be provided by the gaps.
5.30 Memory and I/O

• In asynchronous communication, we don't require synchronization between the

sender and receiver devices, which is the main advantage of asynchronous
communication. This method is also cost-effective.
• In this method, there can be a case when data transmission is slow, but it is not
compulsory, and it is the main disadvantage of the asynchronous method.

Figure 5.16 Asynchronous Transmission

• On the basis of the data transfer rate and the type of transmission mode, serial
communication will take many forms. The transmission mode can be classified
into simplex, half-duplex, and full-duplex.
• Each transmission mode contains the source, also known as sender or
transmitter, and destination, also known as the receiver.

5.9.2 Parallel Interface

• It is used to transmit a huge amount of data signals simultaneously on the
different channels within the same radio path or cable at a time. It is used to
comprise a huge amount of wired channels in parallel.
• In parallel interface, the data transfer between sender and receiver is done with
the help of multiple channels. The data bus in the parallel devices is wider as
compared to the serial devices. That's why it can transfer the data from source to
destination at a time.
• The parallel transmission bit rate is higher as compared to the serial transmission
bit rate.
• The costs of multiple wires are higher as compared to the single wire. The
parallel cable gets longer that's why it requires a high cost.
 Digital Principles and System Design 5.31

• If the distance is larger, synchronization timing between more than one channel
becomes more sensitive. A constant clocking signal is used to provide the timing
in parallel communication.
• The signal is sent with the help of a separate wire within the parallel cable. So
we can say parallel interface is synchronous.
Working of Parallel interface
The parallel interface uses the various parallel paths (wires) to transfer many bits
once within the same cable in synchronization with the help of a single clock. The clock
uses these parallel paths and specifies the timing for transmission in the form of a
constant clocking signal.

Figure 5.17 Working of Parallel interface

• A huge amount of bits are transferred at the same time with the help of various
parallel paths.
• There are different ways of an order of received bit string, and it depends on
various factors like available bandwidth, source distance, and location. The
skipping in video calls and internet calls is an example of it.

5.9.3 Difference between Serial and Parallel communication

• The serial communication is able to send only one bit at a single time. That's
why serial communication needs fewer input/output lines. It also occupies more
resistance and less space to cross talk.
• Serial communication has the bigger advantage that the cost to build the whole
embedded system becomes very cheap. It can also be able to transmit the data
over a long distance with the help of only a single wire or line.
5.32 Memory and I/O

• In the DCE devices (Data communication Equipment) such as a modem, serial

communication is mostly used. All the major computer networks or
communication mostly prefer serial communication.
• Nowadays, the most common and popular mode for small distance is serial
buses because the parallel buses disadvantages prevail over their advantage of
simplicity.
• The parallel communication is able to send a chunk of data (around 32 bits) at a
time. That's why in parallel communication, a separate physical input/output is
needed for each bit of data.
• Parallel communication also has a good advantage: it is very fast, but it also
requires more number of I/O lines, which is the drawback of parallel
communication. The computers use parallel communication so that they can
interconnect audio, video, RAM (Random access memory), modems, network
hardware, and CPU (Central processing unit). The configuration of parallel
communication is very lengthy and complex. That's why its establishment cost is
also very high.
 Digital Principles and System Design 5.33

5.9.4 Advantages of Serial communication over Parallel communication

• Mostly people have a misconception that the parallel ports/buses are faster than
the serial ports/buses because, in serial communication, the data transmission is
only a bit per unit of time. Even the parallel buses will be clocked considerably
at a slower rate as compared to the serial buses. There are various factors that are
used to specify that serial communication is better than parallel communication,
which is described as follows:
o No Clock Required: If there is a case of the asynchronous and unclocked
type of serial communication, the problem related to the clock skew
between channels will not exist.
o Need less Space: At the time of configuration of serial communication, it
needs less amount of space because the serial connection needs less amount
of cable. Hence because of this feature, we will have an additional space,
which can be used to provide better isolation of data lanes/channels from the
components of neighboring communication.
o No Cross Talks: The serial communication contains fewer amounts of
conductors in the nearby space. That's why the possibility of cross-talk is
rare.
o Low cost: The serial communication contains the serial link. The cost of
this link is less than the parallel link.

5.10 INTERRUPT I/O

• The CPU issues commands to the I/O module then proceeds with its normal
work until interrupted by I/O device on completion of its work.
• For input, the device interrupts the CPU when new data has arrived and is ready
to be retrieved by the system processor. The actual actions to perform depend on
whether the device uses I/O ports, memory mapping.
• For output, the device delivers an interrupt either when it is ready to accept
new data or to acknowledge a successful data transfer. Memory-mapped and
DMA-capable devices usually generate interrupts to tell the system they are
done with the buffer.
• Although Interrupt relieves the CPU of having to wait for the devices, but it is
still inefficient in data transfer of large amount because the CPU has to transfer
5.34 Memory and I/O

the data word by word between I/O module and memory.

• Below are the basic operations of Interrupt:
1. CPU issues read command
2. I/O module gets data from peripheral whilst CPU does other work
3. I/O module interrupts CPU
4. CPU requests data
5. I/O module transfers data

5.10.1 Interrupt hardware

• Most computers have several I/O devices that can request an interrupt. A single
interrupt request line may be used to serve n devices.
Enabling and Disabling Interrupts
• All computers fundamentally should be able to enable and disable interruptions
as desired. Again reconsider the COMPUTE and PRINT example.
• When a device activates the interrupt-request signal, it keeps this signal
activated until it learns that the processor has accepted its request.
• When interrupts are enabled, the following is a typical scenario:
▪ The device raises an interrupt request.
▪ The processor interrupts the program currently being executed.
▪ Interrupts are disabled by changing the control bits in the processor status
register (PS).
▪ The device is informed that its request has been recognized and deactivates
theinterrupt request signal.
▪ The action requested by the interrupt is performed by the interrupt-service
routine.
▪ Interrupts are enabled and execution of the interrupted program is resumed.

5.10.2 Handling multiple devices

While handling multiple devices, the issues concerned are:
• How can the processor recognize the device requesting an interrupt?
• How can the processor obtain the starting address of the appropriate routine?
 Digital Principles and System Design 5.35

• Should a device be allowed to interrupt the processor while another interrupt is

being serviced?
• How should two or more simultaneous interrupt requests be handled?

5.10.3 Vectored interrupts

• A device requesting an interrupt may identify itself (by sending a special code)
directly to the processor, so that the processor considers it immediately.

5.10.4 Interrupt nesting

• The processor should continue to execute the interrupt-service routine till
completion, before it accepts an interrupt request from a second device. Privilege
exceptionmeans they execute privileged instructions.
• Individual interrupt-request and acknowledge lines can also be implemented.
Simultaneous requests
• The processor must have some mechanisms to decide which request to service
when simultaneous requests arrive.
• Here, daisy chain and arrangement of priority groups as the interrupt priority
schemes are discussed.
• Priority based simultaneous requests are considered in many organizations.
Controlling device requests
At the device end, an interrupt enable bit determines whether it is allowed to
generate an interrupt request. At the processor end, it determines whether a given
interrupt request will be accepted.

5.10.5 Exceptions
• The term exception is used to refer to any event that causes an interruption.
Hence, I/O interrupts are one example of an exception.
▪ Recovery from errors – These are techniques to ensure that all hardware
components are operating properly.
▪ Debugging – find errors in a program, trace and breakpoints (only at specific
pointsselected by the user).
▪ Privilege exception – execute privileged instructions to protect OS of a
computer.
5.36 Memory and I/O

5.11 INTERCONNECTION STANDARDS: USB, SATA

• A computer consists of a set of components or modules of three basic types
(processor, memory, I/O) that communicate with each other. In effect, a
computer is a network of basic modules. Thus, there must be paths for
connecting the modules.
• The collection of paths connecting the various modules is called the
interconnection structure. The design of this structure will depend on the
exchanges that must be made among modules.
• The interconnection structure must support the following types of transfers:
Memory to processor: The processor reads an instruction or a unit of data from
memory.
Processor to memory: The processor writes a unit of data to memory.
I/O to processor: The processor reads data from an I/O device via an I/O
module.
Processor to I/O: The processor sends data to the I/O device.
I/O to or from memory: For these two cases, an I/O module is allowed to
exchange data directly with memory, without going through the processor, using
direct memory access.

5.11.1 USB
• Universal Serial Bus ( USB) is a system for connecting a wide range of
peripherals to a computer, including pointing devices, displays, and data
storage and communications products.
• The Universal Serial Bus is a network of attachments connected to the host
computer.
• These attachments come in two types known as Functions and Hubs.
• Functions are the peripherals such as mice, printers, etc.
• Hubs basically act like a double adapter does on a power-point, converting
one socket, called a port, into multiple ports.
• Hubs and functions are collectively called devices.
• When a device is attached to the USB system, it gets assigned a number
called its address. The address is uniquely used by that device while it is
connected.
 Digital Principles and System Design 5.37

• Each device also contains a number of endpoints, which are a collection of

sources anddestinations for communications between the host and the device.
• The combination of the address, endpoint number and direction are what is
used by the host and software to determine along which pipe data is
travelling.
List of USB devices
In modern times, to connect with the computer, there are many different USB
devices. Some common are as follows:
o Keyboard
o Smartphone
o Tablet
o Webcams
o Keypad
o Microphone
o Mouse
o Joystick
o Jumpdrive aka Thumb drive
o Scanner
o Printer
o External drive
o iPod or other MP3 players
o Digital Camera
Where are the USB ports?
In modern times, all computers contain at least one USB port in different
locations. Below, a list is given that contains USB port locations on the devices that
may help you out to find them.
Laptop computer: A laptop computer may contain one to four ports on the left or right
side, and some laptops have on the behind of the laptop computer.
Desktop computer: Usually, a desktop computer has 2 to 4 USB ports in the front and
2 to 8 ports on the backside.
5.38 Memory and I/O

Tablet computer: On the tablet, a USB connection is situated in the charging port and
is sometimes USB-C and usually micro USB.
Smartphone: In the form of micro USB or USB-C, a USB port is used for both data
transfer and charging, similar to tablets on smartphones.
USB connector types
There are different shapes and sizes available for the USB connector. Also, there
are numerous versions of USB connectors, such as Mini USB, Micro USB, etc.

Figure 5.18 USB Connectors Types

1. Mini -USB: Mini USB is used with digital cameras and computer peripherals
and divided into A-type, B-type and AB-type. It is also known as mini-B and is
the most common type of interface. On the latest devices, Micro-USB and USB-
C cables have largely replaced the mini-USB. It transfers data and power
between two devices as it is made of coaxial cable. Also, it is applied to MP3
players, digital cameras, and mobile hard drives. In a mini USB cable, one-end
is a much smaller quadrilateral hub, and the other end is a standard flat-head
USB hub. Thus, it is easily plugged into mobile devices. The mini USB can also
be used to transfer data between computers with at least one USB port but is
mainly used for charging devices. It includes two advantages: Water proofness
and Portability.
2. Micro-USB: It is a reduced version of the USB (Universal Serial Bus). It was
announced in 2007 and designed to replace mini-USB and developed for
connecting compact and mobile devices such as digital cameras, smartphones,
GPS devices, Mp3 players and photo printers.
Micro A, micro B and micro USB 3 are the three varieties of Micro-USB. The
type Micro-A and Micro-B have a connector size of 6.85 x 1.8 mm, although the
 Digital Principles and System Design 5.39

Micro-A connector has a greater maximum over mild size. USB 3 micro is more
similar to micro B, but it has better speed as compared to micro B because it
includes an additional collection of pins on the side for twice the wires. Micro
versions are hot-swappable, and plug-and-play like standard USB and micro-
USB is still widely used with electronic devices.
3. USB Type-C: On most modern newer Android smart phones and other USB-
connected devices, a USB Type-C cable is a relatively new type of connector. It
is used for delivering data and power to computing devices. As compared to
other forms of USB connections, USB-C cables are reversible; they can be
plugged either way in the devices, whether they are upside down.

5.11.2 SATA
• SATA is abbreviated as Serial AT Attachment. The name "AT" Attachment was
introduced after the invention of the IBM personal computer in 1984.
• Serial ATA or SATA is a computer bus interface for connecting the storage
disks or drives to the motherboard of computer systems. SATA standards help in
transferring data from hard drives and optical disk drives to computer systems.
• Serial ATA (SATA) was created by the serial ATA working group in 2000.
Serial ATA was introduced to provide various benefits over the previous Parallel
ATA interface, which was announced around the 1980s. In January 2003,
Seagate Barracuda SATA V was the first hard disk drive in the world. In 2008,
the Serial ATA hard drive replaced the parallel ATA in the consumer's desktop
and laptop computers.
• The first version of SATA (SATA 1.0) can easily communicate 1.5 Gbps of
performance to each storage drive within a disk array. In comparison to earlier
ribbon cables which are used with ATA drives, the cable of serial ATA provides
the best airflow in the computer systems and makes the routing easier.
• SATA also uses external hard drives through external SATA. External SATA is
commonly referred to as eSATA.
• eSATA drives are hot-swappable and providing high transmitting speed with no
USB and FireWire issues.
• Fast transmission speed, high performance, and outstanding storage capacity are
the two main characteristics of SATA hard drives.
5.40 Memory and I/O

SATA Cables
The SATA cables are long, and both end-points of the cable are thin and flat.
SATA cables are of different types, but the following two are the main types of
SATA cables:
1. SATA Data Cables: These cables typically have seven pins for transferring
data. These connect the drives to the motherboard of the computer systems. One
end of the SATA cable plugs into the back of the hard drive of the computer
system and the other end plugs into the computer's motherboard.
2. SATA Power Cables: These cables typically have fifteenth pins. These connect
to the power supply.
Other Types of SATA Cables
Some other different types of SATA cables are given below:
1. e-SATA: This cable joins the external devices into our computer systems with a
length ranging from 0.5 - 2 meters long.
2. SATA Bracket: It is a dual-port eSATA expansion bracket which makes our
computer output compatible with the SATA external devices.
3. SATA Bridge: This SATA cable connects the ATA devices to the SATA
motherboard or PCI cards. This interface is a bridge between the SATA devices.
4. Low Profile SATA: It is a quite thin SATA cable with a very simple and low
profile connector. This SATA cable can be used easily with longer graphic
cards.
5. Micro SATA: This SATA cable is used for internal disks and backplane
applications.
6. SATA-SATA: It is a standard data cable which is available in various lengths
and can be used for standard SATA applications.
Revisions of SATA Interface
Following are the three major different revisions of the SATA interface:
SATA I: This interface is formally called SATA 1.5Gb/s. It is the first generation of
SATA, whose speed is running at 1.5 Gigabit per second.
SATA II: This interface is formally called SATA 3Gb/s. It is the second generation of
SATA, whose speed is running at 3.0 Gigabit per second.
 Digital Principles and System Design 5.41

SATA III: This interface is formally called SATA 6Gb/s. It is the third generation of
SATA, whose speed is running at 6.0 Gigabit per second.

Figure 5.19 Revisions of SATA