Fixed point and Floating point representation:

There are two major approaches to store real numbers (i.e., numbers with fractional component) in
modern computing. These are (i) Fixed Point Notation and (ii) Floating Point Notation. In fixed point
notation, there are a fixed number of digits after the decimal point, whereas floating point number
allows for a varying number of digits after the decimal point.

Fixed-Point Representation –

This representation has fixed number of bits for integer part and for fractional part. For example, if
given fixed-point representation is IIII.FFFF, then you can store minimum value is 0000.0001 and
maximum value is 9999.9999. There are three parts of a fixed-point number representation: the sign
field, integer field, and fractional field.

We can represent these numbers using:

 Signed representation: range from -(2(k-1)-1) to (2(k-1)-1), for k bits.

 1’s complement representation: range from -(2(k-1)-1) to (2(k-1)-1), for k bits.
 2’s complementation representation: range from -(2(k-1)) to (2(k-1)-1), for k bits.

2’s complementation representation is preferred in computer system because of unambiguous

property and easier for arithmetic operations.

Example −Assume number is using 32-bit format which reserve 1 bit for the sign, 15 bits for
the integer part and 16 bits for the fractional part.

Then, -43.625 is represented as following:

Where, 0 is used to represent + and 1 is used to represent. 000000000101011 is 15 bit binary value
for decimal 43 and 1010000000000000 is 16 bit binary value for fractional 0.625.

The advantage of using a fixed-point representation is performance and disadvantage is relatively

limited range of values that they can represent. So, it is usually inadequate for numerical analysis as
it does not allow enough numbers and accuracy. A number whose representation exceeds 32 bits
would have to be stored inexactly.
These are above smallest positive number and largest positive number which can be store in
32-bit representation as given above format. Therefore, the smallest positive number is 2-16 ≈
0.000015 approximate and the largest positive number is (215-1)+(1-2-16)=215(1-2-16) =32768,
and gap between these numbers is 2-16.

We can move the radix point either left or right with the help of only integer field is 1.

Floating-Point Representation –

This representation does not reserve a specific number of bits for the integer part or the
fractional part. Instead it reserves a certain number of bits for the number (called the mantissa
or significand) and a certain number of bits to say where within that number the decimal
place sits (called the exponent).

The floating number representation of a number has two part: the first part represents a
signed fixed point number called mantissa. The second part of designates the position of the
decimal (or binary) point and is called the exponent. The fixed point mantissa may be fraction
or an integer. Floating -point is always interpreted to represent a number in the following
form: Mxre.

Only the mantissa m and the exponent e are physically represented in the register (including
their sign). A floating-point binary number is represented in a similar manner except that is
uses base 2 for the exponent. A floating-point number is said to be normalized if the most
significant digit of the mantissa is 1.

So, actual number is (-1)s(1+m)x2(e-Bias), where s is the sign bit, m is the mantissa, e is the
exponent value, and Bias is the bias number.

Note that signed integers and exponent are represented by either sign representation, or one’s
complement representation, or two’s complement representation.

The floating point representation is more flexible. Any non-zero number can be represented
in the normalized form of ±(1.b1b2b3 ...)2x2n This is normalized form of a number x.

Example −Suppose number is using 32-bit format: the 1 bit sign bit, 8 bits for signed
exponent, and 23 bits for the fractional part. The leading bit 1 is not stored (as it is always 1
for a normalized number) and is referred to as a “hidden bit”.

Then −53.5 is normalized as -53.5=(-110101.1)2=(-1.101011)x25 , which is represented as

following below,
Where 00000101 is the 8-bit binary value of exponent value +5.

Note that 8-bit exponent field is used to store integer exponents -126 ≤ n ≤ 127.

The smallest normalized positive number that fits into 32 bits is

(1.00000000000000000000000)2x2-126=2-126≈1.18x10-38 , and largest normalized positive
number that fits into 32 bits is (1.11111111111111111111111)2x2127=(224-1)x2104 ≈
3.40x1038 . These numbers are represented as following below,

The precision of a floating-point format is the number of positions reserved for binary digits
plus one (for the hidden bit). In the examples considered here the precision is 23+1=24.

The gap between 1 and the next normalized floating-point number is known as machine
epsilon. the gap is (1+2-23)-1=2-23for above example, but this is same as the smallest positive
floating-point number because of non-uniform spacing unlike in the fixed-point scenario.

Note that non-terminating binary numbers can be represented in floating point representation,
e.g., 1/3 = (0.010101 ...)2 cannot be a floating-point number as its binary representation is
non-terminating.

Data Hazards and its Handling Methods

Data Hazards occur when an instruction depends on the result of previous instruction and
that result of instruction has not yet been computed. whenever two different instructions use
the same storage. the location must appear as if it is executed in sequential order.

There are four types of data dependencies: Read after Write (RAW), Write after Read
(WAR), Write after Write (WAW), and Read after Read (RAR). These are explained as
follows below.

 Read after Write (RAW) :

It is also known as True dependency or Flow dependency. It occurs when the value
produced by an instruction is required by a subsequent instruction. For example,
 ADD R1, --, --;
SUB --, R1, --;

Stalls are required to handle these hazards.

 Write after Read (WAR) :

It is also known as anti dependency. These hazards occur when the output register of
an instruction is used right after read by a previous instruction. For example,
  ADD --, R1, --;
SUB R1, --, --;
 Write after Write (WAW) :
It is also known as output dependency. These hazards occur when the output register
of an instruction is used for write after written by previous instruction. For example,
 ADD R1, --, --;
SUB R1, --, --;
 Read after Read (RAR) :
It occurs when the instruction both read from the same register. For example,
 ADD --, R1, --;
SUB --, R1, --;

Since reading a register value does not change the register value, these Read after Read
(RAR) hazards don’t cause a problem for the processor.

Data hazards occur when instructions in a pipeline depend on the results of previous
instructions. To ensure smooth execution, various hazard-handling techniques like
forwarding and stalling are used. provides an in-depth exploration of these techniques,
ensuring you’re well-prepared for competitive exams and real-world applications

Handling Data Hazards :

These are various methods we use to handle hazards: Forwarding, Code reordering , and Stall
insertion.

These are explained as follows below.

1. Forwarding :
It adds special circuitry to the pipeline. This method works because it takes less time
for the required values to travel through a wire than it does for a pipeline segment to
compute its result.

2. Code reordering :
We need a special type of software to reorder code. We call this type of software a
hardware-dependent compiler.

3. Stall Insertion :
it inserts one or more stall (no-op instructions) into the pipeline, which delays the
execution of the current instruction until the required operand is written to the register
file, but this method decreases pipeline efficiency and throughput.

What are Structural Hazards?

Hardware resource conflicts among the instructions in the pipeline cause structural hazards.
Memory, a GPR Register, or an ALU might all be used as resources here. When more than one
instruction in the pipe requires access to the very same resource in the same clock cycle, a resource
conflict is said to arise. In an overlapping pipelined execution, this is a circumstance where the
hardware cannot handle all potential combinations.
Take a look at the illustration above. In an IF machine cycle, instructions are retrieved from memory
in any system. Depending on the instruction, Result Writing (RW) in the 4-stage pipeline may access
memory or one General Purpose Register. Instruction-1(I1) is in the RW stage at t4, while
Instruction-4(I4) is in the IF stage. Alas! If I1 is a STORE instruction, both I4 and I1 are accessing the
same resource, which is memory. In a timed condition, how can it be possible to access memory
with two commands from the same CPU? Impossible. This is referred to as structural dependency.
What would be the solution?

Solution

The figure above shows a bubble that blocks the pipeline. I4 isn’t allowed to proceed at t4
and is instead delayed. It might have been allowed in t5, but there would have been a conflict
with I2 RW. I4 is not allowed in t6 for much the same reason. Finally, only at t7 could I4 be
allowed to progress (stalled) in the pipe.
This delay is passed on to all future commands as well. As a result, while the ideal 4-stage
system would require 8 timing states to execute 5 instructions, it instead takes 11 timing
states due to structural dependency. This isn’t it. You’ve probably figured out that this threat
will occur in every fourth instruction. This is not a good solution for a large CPU load. Is
there a better way to do things? Yes!

Here, a better solution would be to boost the system’s structural resources using one of the
options listed below:

 The pipeline can be expanded to five or more stages, with the functionality of the
stages appropriately redefined and the clock frequency adjusted. This resolves the
hazard at every fourth instruction in the four-stage pipeline.
 Instruction memory and Data Memory are two types of memory that can be
physically separated. Instead of dealing with Main memory, it would be better to
build Cache memory in the CPU. Instruction memory is used in IF, and Data Memory
is used in Result writing. These two resources become independent of one another,
eliminating reliance.
 Multiple levels of cache in the CPU are also possible.
 There is a chance that ALU will become resource-dependent. Instructions in the IE
machine cycle may require ALU, whereas another instruction in the IF stage may
require ALU to calculate Effective Address dependent on addressing mode. Either
stalling or having an exclusive ALU for the calculation of address would be the
solution.
 GPRs are replaced with registered files. Register files feature exclusive read and write
ports and multiport access. This allows access to one write register, and one read
register at the same time.

Difference between Data Hazards and Structural Hazards: