MICROPROCESSOR
PART 14
SIBIN K
Electrical Subject Matter Expert
Counters and Timers
● Two 16 bit up Timer/ counter registers
● Timer 0 (T0) and Timer 1 (T1)
● Both can be operate either as a timers or event counters
● Timer: programmed to count internal clock pulses
● Counter: programmed to count external pulses
● Both 16 bit registers are divided into two 8-bit registers
● TL0 and TH0
● TL1 and TH1
● 2 special purpose registers TMOD and TCON
• microcontroller oscillator uses quartz crystal for its operation
• The largest value it can store is 65 535
• In case of exceeding this value, the timer will be automatically cleared and counting starts
from 0. This condition is called an overflow.
● A single machine-cycle instruction lasts for 12 quartz oscillator periods
● by embedding quartz with oscillator frequency of 12MHz, a number stored in the timer
register will be changed million times per second, i.e. each microsecond.
Timer Control (TCON) Register
• Only 4 bits of this register are used for this purpose, while rest of them is used for interrupt
control.
• TCON is an 8-bit register having address 88H
● TF1 bit is automatically set on the Timer 1 overflow.
● TR1 bit enables the Timer 1.
1 - Timer 1 is enabled.
0 - Timer 1 is disabled.
● TF0 bit is automatically set on the Timer 0 overflow.
● TR0 bit enables the timer 0.
1 - Timer 0 is enabled.
0 - Timer 0 is disabled.
● IE1: external interrupt 1 edge flag. Set to 1 when high to low edge signal is received at
INT1. Cleared when the process vectored to ISR
● IE0: external interrupt 0 edge flag. Set to 1 when high to low edge signal is received at
INT0. Cleared when the process vectored to ISR
● IT1: External interrupt 1 type control bit. Set to 1 to enable INT1 to be triggered by falling
edge signal
Set to 0 to enable a low-level signal to generate an interrupt
● IT0: External interrupt 0 type control bit. Set to 1 to enable INT0 to be triggered by falling
edge signal. Set to 0 to enable a low-level signal to generate an interrupt
TMOD Register (Timer Mode)
● The TMOD register selects the operational mode of the timers T0 and T1.
● the low 4 bits (bit0 – bit3) refer to the timer 0, while the high 4 bits (bit4 – bit7) refer to the
timer 1.
● There are 4 operational modes
GATE1 enables and disables Timer 1 by means of a signal brought to the INT1 pin (P3.3):
● 1 – Timer 1 operates only if the INT1 bit is set.
● 0 – Timer 1 operates regardless of the logic state of the INT1 bit.
C/T1 selects pulses to be counted up by the timer/counter 1:
● 1 – Timer counts pulses brought to the T1 pin (P3.5). COUNTER
● 0 – Timer counts pulses from internal oscillator. TIMER
T1M1, T1M0 These two bits select the operational mode of the Timer 1
T1M1 T1M0 MODE DESCRIPTIONS
0 0 Mode 0 13-bit timer
0 1 Mode 1 16-bit timer
1 0 Mode 2 8-bit auto-reload
1 1 Mode 3 Split mode
Mode 0
● This mode configures timer as a 13-bit timer which consists of all 8 bits of TH0 and the
lower 5 bits of TL0.
● As a result, the Timer uses only 13 of 16 bits
● Counts from 0000H to 1FFFH
mode 1 (16-bit timer)
● Mode 1 configures timer as a 16-bit timer comprising all the bits of both registers TH0 and
● TL0.
● That’s why this is one of the most commonly used modes.
● Timer operates in the same way as in mode 0, with difference that the registers count up
to 65 536 as allowable by the 16 bits
mode 2 (Auto-Reload Timer)
● Mode 2 configures timer 0 as an 8-bit timer.
● Actually, timer uses only one 8-bit register for counting and never counts from 0, but from
an arbitrary value (0-255) stored in another (TH0) register.
Mode 3 (Split Timer)
● Mode 3 configures timer 0 so that registers TL0 and TH0 operate as separate 8-bit
timers.
● the 16-bit timer consisting of two registers TH0 and TL0 is split into two Independent 8-bit
timers.
● This mode is provided for applications requiring an additional 8-bit timer or counter.
● The TL0 timer turns into timer 0, while the TH0 timer turns into timer 1.
● all the control bits of 16-bit Timer 1 now control the 8-bit Timer 1.
