185

APPLICATIONS OF OPERATIONAL AMPLIFIER

INTEGRATED CIRCUITS
the upper trip point of the
184 . When the integrator output reaches comparator again switches
terminals of the FET. In the circuit shown, the oscillator output -comparator which is (-Vos R,|R2),The wave forn periods Ti-and Te
fltered operation repeats.
voltage V, is rectified by the diode D and Áltcred by RsCa. Ihis states and the
output is adjusted in magniiude by potentiometer R, and is applied are given by
RDs lakes
to the gale of the FET. Such arrangCment ensures that [Vost-Vos]
on that value just neçessary to maintain aaparticular amplitude of ...(853)
oscillation. The signal amplitude applied to the bridge must be T1= Vost/RO
Small enough to ensure tbat the FET is working. in the ohmic.
gion and [Vos-Vos ]
iaagatar Wave Generator T ...(8'54)
circuit for triangular wave generator which also
generates square waves is shown in Fig. 835 (a). It consists of an -For Vost-Vos, T1=T and the frequency of oscillation is
ntegrator and a regenerative comparator connected in a positive given by
feedback loop. Precise triangular wave can be obtained by integra R ...(8:55)
tion of the square wave which is fcd back from the output of the
comparator to the input of the integrator. With the comparator =4R,CR
of the circuit are determined by
ouput at its positive saturation level the . integrator output The performance limits
comparator slew rate and integrator band width at the higher
frequencies and by integrator drift at the lower frequencies.
R
R1 R

W
Vas/ee

(a) Basic triangular wavefrom generator generating square wave simultancously.

-Vos

-.-Vo5(R,/R,)

(6) Waveform details.

Fig. 8'35
decreases approximately linearly at the rate of (-Vos|Rc)volt/sec.
until it reaches the lower trip point of the comparator which is
(-YoatR1/R2); The comparator output then switches rapidly to its
negative saturation level Vos and the. integrator output then
increases approxímately linearly at the rate (-Vost/RO) volt/sec.
 22
TABLE 7-6 Oscilator Types.
Frequency of Types of waveform
Types of components oscillation generated
used
Audio frequency (AF) Sinusoidal
RC oscillator
LC oscillator Radio frequency (RF) Square wave
Crystal oscillator Triangular wave
Sawtooth wave, etc.

7-11-3 Frequencyy Stability

The ability of the oscillator circuit to oscillate at one exact frequency is called
frequency stability. Although a number of factors may cause changes in oscilla
tor frequency, the primary factors are temperature changes and changes in the dc
power supply. Temperature and power supply changes cause variations in the op
amp's gain, in junction capacitances and resistances of the transistors in an op
amp, and in external circuit components. In most cases these variations can be
kept smallby carefuldesign, by using regulated power supplies, and by temper
ature control.
Another important factor that determines frequency. stability is the figure of
merit Q
of the circuit. The higher the 2, the greater the stability. For this reason.
crystal oscillators are far more stable than RC.or LC oscillators, especially at
higher frequencies. LCcircuits and crystals are generally used for the generation
of high-frequency signals, while RC components are most suitable for audio-tre
quency applications. Here we discuss audio-frequency RC oscillators on!y. We be
gin with the sinusoidal oscillators.

-12 PHASE SHIFT OSCILLATOR

Figure 7-18 shows aphase shift oscillator, which consists of an op-amp as the
amplifying stage and three RC cascaded networks as the feedback circuit. The
feedback circuit provides feedback volage from the output back to the input of
the amplifier. The op-amp is used in the inverting mode; therefore, any signal
that appears at the inverting terminal is shiiredby 180° at the output. An addi
tional l80° phase shift required for oscillation is provided by the cascaded RC
networks. Thus the total phase shift around the loop is 360° (oÍr 0°). At some
specific frequency when the phase shift of the cascaded RC networks is exactly
180° and the gain of the amplifier is sufficiently large, the circuit will oscillate
at that frequency. This frequency is called the frequency of oscillation. f,. and is
given by
0.065
f, = (7-22a)
2r V6RC RC

7-12 Phase Shift Oscillator 281

 output amplitude, however, can be obtained with
Amplifier
R. tion (7-22a). A desired terminal.
Re output
connected at the
I 33 kn back zeners
+Voc
t+15 V
|741/351 Design the phasesiifoSeillatorötFigürE

LwoRoM -VEE
-15 V
D1 IN4735
6.2 V SOLUTION
33 kN D2 V,
Vor Vo, - 0.7V Equation (7-22a),
Let C = 0.1 F. Then, from
0.065 = 3.25 k2
R =
(200)(10-)
(Use R = 3.3 kN.)
0.1 F 0.1 uF RC networks, it is nece
To prevent the loading of the amplifier because of
0.1 uF
from Equation (1
3.3 k $3.3 k2 3.3 k2 that R, > 10R. Therefore, let R, = 10R = 33 kh. Then,
Rp = 29(33 k2) = 957 k
Feedbeck
circuit
(Use Rp = 1-MO potentiometer.)
When choosing an op-amp, type 741 can be used at lower frequen
(<IkHz); however, at higher frequencies, an op-amp such as the LM3|
LF351 is recommended because of its increased slew cate.

WIEN BRIDGE OSCILLATOR

(V, + Vor)
-6.9 V Because of its simplicity and stability, one of the most commonly used auðie
t (ms) quency oscillatörs is the Wien bridge: Figure 7-19 shows the Wien bridg g
-tV, + Voz) lator in which the Wien bridge circuit is connected between the amplifier
-6.9V f, -0085
RC terminals and the output terminal. The bridge has a series RC network in one
5 ms
and a parallel RC network in the adjoining arm. In the remaining two arma(
bridge, resistors R, and Re are connected (see Figure 7-19).
FIGURE 7-18 Phase shift oscillator ond its output waveform. The phase angle criterion for oscillation is that the total phase shift n
the circuit must be 0°. This condition occurs only when the bridge is balan
that is, at resonance. The frequency of oscillation f, is exactly the resonâan
At this frequency, the gain A, must be at least 29. That is, quency of the balanced Wien bridge and is given by
1 0.159
29
2rRC RC
or
assuming that the resistors are equal in value, and the capacitors are equa
Rp = 29R, (7-22b) in the reactive leg of the Wien bridge. At this frequency the gain requirea
For the derivation of Equation (7-22a) and (7-22b), refer to Appendix C. Thus tained oscillation is given by
the circuit will produce a sinusoidal waveform of frequency f, if the gain is 29 1
and the total phase shift around the circuit is exactly 360°. For adesired frequency A., =
of oscillation, choose a capacitor C, and then calculate the value of Rfrom Equa
282 Active Filters and Oscillators 7-13 Wien Bridge O_cillator
 Amplifier
(7-23b),
R Then, from Equation
Now, let R, = 12 k2. =24 kN
12k2 50 k Re = (2) (12 k2)
Pot at 24 k)
potentiometer.)
(Use Re= 50 k2
|+15 V
4 3.3 kfn
741351 3.3 kO RZ 7-14 GQUADRATURE OSCILLATOR
0.05 F
+Voc
signals (ina.
quadrature oscillator generates two
-15V 0.05 F As its name implies, the that is, out of phase by 90°.Although the
|741/351
sine) th¡t are in-guadrature,
cosine is arbitrary, in the quadrature oscillator of
cation of the sine and cosine
R
7-20 the output of A, is labeled a sine and the output of A, is a
three RC combinations. The frct
33 kA
0,05 F 12 k27 cillator requires a dual op-amp and and appears as a noninverting înto
mode
R is operating in the noninverting as a pure integrator. Furthernore. 4.
The second op-amp A, is working of R
50 k pot at 24 k
and C,. The divider network f
a.0s F lowed by a voltage divider consistingform the amplifier stage.
feedback circuit, whereas A, and A, for oscillaton i
The total phase shift of 360° around the loop required H
Foedback
circuit
tained in the following way. The op-amp A, is a pure integrator and inverte.
FIGURE 7-19 Wien bridge oscillator. Amplifier
R. C.

That is, 100 ks2

H Sine
0.01 uF

I+ Re =3 4+Vc
R, R C
or A1 W
100 k 0.01uF
Rp = 2R, (7-23b) 4+Vee
For the derivation of Equations (7-23a) and (7-23b), refer to Appendix C.
Wien bidge oscillator is designed using Equations The
lustrated in Example 7-13. (7-23a) and (7-23b), as il A2

100 k
Lm
RoM

DesienheaNien brndgeoscilator of Figure 119:so that 965 Hz Ra

100 k2
SOLUTION C,0.01 F
Let C = 0.05 F. Therefore, from Equation
(7-23a),
0.159 Foedback
R= =3.3 k) circuit
(5)(10-) (965)
FIGURE 7-20 Quadrature oscillator. A, and A, dual
284 Active Filters and Oscillators opamp: 1458/353.
7-14 Quadraure OscillaLor
Z-15SQUARE WAVE GENERATOR
In contrast to sine wave oscillators, square wave outputs are generated when the
op-amp is forced to operate in the saturated region, That is, the output of the op
amp is forced to swing repetitively between positive saturation + V ( +Vcc)
and negative saturation -V,a(-VeE), resulting in the square-wave output. One
such circuit is shown in Figure 7-21(a). This square wave generator is alsc called
afree-running orastable multivibrator- The output of the op-amp in this lcircuit
will be in positive or negative saturation, depending on whether the differential
voltage va is negative or positive, respectively.
ASsume that the voltage across capacitor Cis zero volts at the instant the dc
supply voltages +Vcc and --VEE are applied. This means that the voltagd at the
inverting terminal is zero initially. At the same instant, however, the voltage v, at
the noninverting terminal is a very small finite value that is a function of the out
put offset voltage VooT and the values of resistors R, and R,. Thus the differential
input voltage vi is equal to the voltage v, at the noninverting terminal. Akhough
very small, voltage v will start to drive the op-amp into saturation. For example,
suppose that the output offset voltage Voor iS positive and that, therefore, voltage
U, is also positive. Since initially the capacitor Cacts as a short circuit, the gain
of the op-amp is very large (A); hence v, drives the output of the op-amp to its
positive saturation +V With the output voltage of the op-amp at +satthe ca
pacitor C starts charging toward +Vsat through resistor R. However, as soon as

Output Voltage scros

voltage capacitor
C R

10 k2 +VarVoc
0.05 F
Rs
+Vcc

|741/351
R,
10 k2 W
Re

11.6 k2 (20-k2 pot.)

(a)
2RC
(b

output voltage v, ond

FIGURE 7-21 (a) Square wave generator. (b) Waveforms of
capacitor voltage , of the square-wave generator.
7-15 Square Wave Generatot 287
 the voltage , across
the op-amp is forced tocapacitor C is slightly more positive than
output voltage at negativeswitch to a negative 'saturation, Va. With
v,, the output of.
ative, since saturation, -V,,the voltage v, across R,theisop-amp's
also neg
R
R, + R (-V) (7-25a)
Thus the net diffcrential
put of the voltage v,= U, - v, 0s negative, which
op-amp in negative
tion until the capacitor C saturation. The output remains in negativeholds the out
discharges and then recharges to a negative satura
slightly higher than -v,. (See
voltage U, becomes more negative Figure 7-21(b).] Now, as soon as the voltage
capacitor'
comes positive and hence drives the than -v, the net differential voltage v, be
s
uration +Va This completes one cycle. output of the op-amp back to its positive sat
noninverting input is With output at + Va voltage U, at the

RË
R, + R, (+V,) (7-25b)
The time period T of the output
waveform is
given by
T= 2RCIn/2R +R, (7-26a)
R,
Or

2RC In[ (2R, + R)/R,] (7-26b)

Equation (7-26b)
tion of the RC tineindicates that the frequency of the output f, is not only a
constant but also of the relationship func
example, if R, = 1.16R,, Equation between R, and R,. For
(7-26b) becones
1
2RC (7-27)
Equation (7-27) shows that the smaller the RC time constant, the
put frequency fo and vice versa. As with sine higher the out
wave oscillators, the highest fre
quency generated by the square wave generator is also set by the slew
op-amp. An attempt to operate the circuit at relatively higher rate of the
the oscillator's output to become triangular. In frequencies causes
inverting terminal needs a series resistance R; topractice,
prevent
each inverting and non
current flow because the inputs of the op-amp are subjectedexcessive differential
to large differential
voltages. The resistance R, used should be 100 k2 or higher. A
peak output voltage swing can be obtained in the square-wave reduced peak-to
ure 7-21(a) by using back-to-back zeners at the generator of Fig
output terminal.

Active Filters and Oscillators

 34
R RAJA PRABHÅ * Sec. 5.] INTEGRATED CIRCUITS: FABRICATION AND CHARACTERISTICS

puritics. The most complicated component fabricated is the transistor, and

all other elements are constructed with one or more of the processes required
to make a trangistor. In the fabrication of all the above elements it is neces
Hary to. distribute impurities in certain precisely defined regions within the
second (n-type) layer. The selective diffusion of impurities is accomplished im
by using SiO, as a barrier which protects portions of the wafer against
purity penetration. Thus the third layer of material is silicon diöxide, and
it also provides protection of the semiconductor surface against contamination.
In the regions where diffusion is tó take place, the Si0; layer is etched away,
5 INTEGRATED CIRCUITS: leaving'the rest of the wafer protected against diffusion. To permit selective
etching, the SiO layer must be subjected to a photolithographic process, de
scribed in Sec. 5-4. Finally, a'fourth meta ic (aluminum) layer is added
FABRICATION AND to supply the necessary interconnections between components.
The p-type substrate which is required as a foundation for the integrated
circuit is obtained by growing an ingot (1 to 2 in. in diameter and about 10
CHARACTERISTICS in. long) from a silicon melt with a predetermined number of impurities. The
crystal ingot is subsequently sliced into round wafers approximately 6 mils
thick, and one side of each wafer is lapped and polished to eliminate surfacc
imperfections.
An integrated circuit consists of a We are now in a position to appreciate some of the significant advantages
cally 50 by 50 mils in cross section, single-vrystal chip of silicon, typi
elements and their interconnections.containing both active and passive
Such circuits are produced by
the same processes used to fabricate individual transistors and diodes.
These processes include epitaxial growth, masked impur1ty diffusion,
oxide growth, and oxide etching, using
definition. A photolithography for pattern
method of batch processin:g is employed which offers
excellent repeatability and is adaptable to the production of large
numbers of integrated circuits at, low ost. In this (a)
describe the basic processes involved in fabricating an chapter we
integrated
circuit. -Diode junctions
Resistor Diodes Transistor
Aluminum
2 19 5 metallzation
Sllcon dioxlde
5-1 INTEGRATED-CIRCUIT TECHNOLOGY -Collector
The fabrication of integrated circuits is based on materi¡ls, processes, p-type contact n'
n* Emltter
and design principles which constitute a nighly developed semicon
ductor (planar-diffusion) technology. The basic structure of an inte.. p-type substrate Base
Collector
grated circuit is shown in Fig. 5-1b, and corsists of four distinet layers
of material. The bottom layer (6)
(6 mils thick) is p-type silicon
and serves as- a substrate upon which the ntegrated circuit is to be Fig, 5-1 (a) A circuit containing aresistor, two diodes, and a trcn
built.. The second layer is thin (typically 25 um = 1mil) n-type sistor. (b) Cross-sectiongl view of the circuit in (a) when transformed
material which is grown as a single-crystal extension of the substrate. into a monolithic form (not drawn to scale). The four layers are
This process is called epilarial growth. All active and passive com substrate, n-type crystal containing the integrated circuit, O silicon
ponents are built within the thin n-type layer using a series of dif dioxide, and aluminum metalization. (Not drawn to scale.)
fusion steps. These components are transistors, diodes, capacitors,
And resistors, and they are made by diffusing p-type and n-type im
90
 CHARACTERISTICS /
FABRICATION AND
INTEGRATED CIRCUITS:
Sec. 5-2
92 / ELECTRONIC FUNDAMENTALS AND APPLICATIONS Sec. 5-2 polishing
n-type layer. After
are chosen for the formed over
of the integrated-circuit technology. Let us consider a 1-in.-square wafer di Values of 0.1 to 0.5 n-cm (0.5 um =5000 ¢) of oxide, SiO, is
layer exposing the
vided into 400 chips. of surface area 50 by 50. mils. We demonstrate in and cleaning, a thin shown in Fig. 5-2a. T'he SiO, is grown byabout 1000°C
entire wafer, as heated to
this chapter that a reasonable area under which acompoent (say, a transis the atmosphere while being
preventing the diffusion of
tor) is fabricated is 50 mils?.. Hence each chip (ehÝh integrated circuit) con epitaxial layer to an oxygen
fundamental property of
dioxide has the the following steps.
tains 50 'separate components, and there are 50 X 400 20,000 compo Silicon this property is made in
nents/in.? on each wafer. impurities through it. Usa of
shown with the
If we process 10 wafers in a bGh we can manufacture 4,000 integrated In Fig. 5-2b the wafer isremovàl is accom
circuits simultaneously, and thee cuntäin 200,000 components. Some of the Step 2. Isolation Ditfusion
places on the surface. This
chips will contain faults due to ections in the manufaçtutng process, oxide removed 1n iour diferent described in Sec. 5-4.
pho:olithographic etching pro cess acceptor impurities
but the yield (the percentage of fault-free chips per wafer) is'eNtiemely large. plished by means of a as a mask for the diffusion 'of
The following advantages are offered by itegrated-cirùit techhology as The remnaining SiO, serves wafer is now subjected to the so-called isolation
(in this case, boron). Th: re
compared with discrete components interconnected by conyentional temperature and for the .time interval
difusion, which takes place at the itypê epitaxial layer and
techniques:
quired for the p-type impurities to penetrate the in Fig.
leave the shaded n-type regionsBecause
1. Low cost (due to the large quantities processed). reach the p-type substrate. We thus regtans,
isolation islands, or isolated
5-2b. These sections are :alled przjnctions. Their purpYse is to
2. Small size. back-to-b£ck
3. High reliability. (Al components are fabricated
simultaneously, and they are separated by two cirouit components.For, example,
allow electrical isolation between different
there are no soldered joints.) region
section that:a differene isölation
4. Improved-performance. (Because of the low cost, more complex cir it will become apparent later in this
each separate transistor. The p"typé süb
functional characteristics. ) must be used for the collector of
cuitry may be used to obtain better
strate must always be held at a negative potential with respect to the isolation
reverse-biased. If these iodes were
processes required to fabricate an islands in order that the p-n junctions be
In the next sedtions we examine the to becomne forward-biased in an operating circuit, then, of course, thÇ isolation
integrated circuit. would be lost.
It should be notec. that the concentration of acceptör
atoms,
(NË 5X 1020 cm-) in the region between isolation islands willgenerally
MONOLITHIC INTEGRATED CRCUITS be much higher (and hence indicated as p*) than in the p-type substrate. The
reason for this higher density is to prevent the depletion region of the reverse
various techniques and processes required biased isolation-to-substrae junction from extending into p*-type material
We now examine in some detail the integrated form,(as shown in Fig. 5-1b. (Sec. 2-6) and possibly coniecting' two isolation islands.
Fig. 5-la in an
to obtain the circuit of monolithic integrated circuit because it is
formed
Parasitic Capaçitance It is now important to consider that these isola"
This coniguration is called a word "monolithic" is derived from the Greék tion regions, or junctions; are connected by a significant barrier, or transition
The
on a single silicon chip. Thus a monolithic cir
lithos, meaning "stone." Capacitance Cra, to the ptype substrate, which capacitance can afect the
monos, meaning "single," and or single rystal. operation of the circuit. Since Cr, is an undesirable by-product of the isola
cuit is built into a single stöhe, qualitatively a complete epitaxial-diffused fab tion process, it is çalled the parasitic capacitance.
In this section we describecircuits. The logic circuit of Eig. 5-Ia is chosen The parasitic capacitance is the sum of two components, the capacitance
rication process for integrated a resisto:, diodes, and
contains typical components: small Ci from.the bottom of the n-type region to the substrate. (Tig. 5-2b) and C:
for discussion because it capacitors with values of capaci
transistor. These elements (and
also
circuits. The monolithic
fronn the sidewalls of the is Tlation islands to the pt region. The bottom com
a encountered in integrated ponent, Ci, results from an essentially step junction due to the epitaxial growtn
tances) are the components indicated.in Fig. 5-2 and
described below.
Sec. 5-3), and Ance varies invergely as the square root of the voltage V
steps
circuit is formed by the between the isolation region and the aubstrate (See. 2-6). The sidewall capaci
epitâxial layer, typically 25 m ance Cis' associnted witB. a diffusd' graded junction, and it.varies as V.
Epitaxial Growth An n-type has a resistivity of typically; for this component the juction area is equal to the perimeter of the isolation
Step 1. p-type substrate tvhioh re[istivity of the
thick, is grown onto a Na = 1.4 X 1015 'atoms/cm³. The the substrate. wtegion times the thickness y of the epitaxial n-type làyer. The total cspaci
0-cm, corresponding to independently of that of tpnce is of the order of a few picofarads.
10 can be chosen
n-type epitaxial layer
 35
94 / ELECTRONIC FUNDAMENTALs AND APPLICATIONS Sec. 5-2 Sec. 5-2 INTEGRATED CIRCUITS: FABRICATION AND CHARACTERIS TICS / 95

0.5 i
umSlicon dloxide
Step 3. Base Diffusion During this process a new layer of oxide is
formed over the wafer, and the photolithographic process is used again to
impurities
n-type epitaxial layer create the pattern of openings shown in Fig. 5-2c. The p-type
(boron) are diffused through these openihgs. In this way are formed the
|1 mil = 25 m
junction
transistor base regions as well as resistors, the anode of diodes, and
this diffusion so
capacitors (if any) It is important to control the depth of The resistivity
p-type substrate 6 mils

(a) that it is shallow and does not penetrate to the substrate.

of the isolation
of the base layer will generally be much higher than that
Isolation lslands
regions.
Sidewall C,
formed over.the
n-type n-type Step 4. Emitter Diffusion A layer of oxide is again
entire surface, and the masking and etching processes arce used again to open
p-type substrate Bottomn C,
openings
windows in the p-type regions, as shown in Fig. 5-2d. Through thesc transistor
diffused n-type impurities (phosphorus) for the fornation of
(6) are
emitters, the cathode regions for diodes, and junction capacitors.
Resistor Anode of diode Base Additional windows (such as W, and W, in Fig. 5-2d) are often made
aluminum as the
into the n regions to which a lead is to be connected, using
ohmic contact, or interconnecting metal. During the diffusion of phosphorus
with
p a heavy concentration (called n) is formed at the points where contact
aluminum is to be made. Aluminum is a p-type impurity in silicon, und a
large concentration of phosphorus prevents the formation of a p-n junction
(c) when the aluminum is alloy cd to form an ohmic contact.
Cathodes of diodes n W, W, Step 5. Aluminum Metalization All p-n junctions and resistors for the
circuit of Fig. 5-la have been formed in the preceding steps. It is now eUs
dic
Emitter n sary to interconnect the various components of the integrated circuit aa
tated by the desired circuit. To make these connections, a fourth set of win
p

dows is opened into a newly formed SiO, layer, as shown in Fig 5-2e, at the
points where contact is to be made. The interconnections arc made first, using
(d). vacuum deposition of a thm even coating of aluminum over the entire wafer.
The photoresist technique is now applied to etch away all undesired aluminum
areas, leaving the desired pattern of interconnections shown in Fig. 5-2e be
Resistor Dlodes Transistor

2 1 4C
wAluminum tween resistors, diodes, and transistors. sucl1
SiO, In production a large number (several hundred) of identical cireuits
After
as that of Fig. 5-la are manufactured simultaneously on a single wafer.
p n
..Pn*i. the metalization process has been completed, the wafer is scribed with t
diamond-tipped tool and separated into individual chips. Eaclh chip is then
pack
mounted on a ceramic wafer and is attached to a suitable header. The
p-type substrate

(e) age leads are connected to the integrated circuit by stitch bonding of a l-inil
Fig. 5-2 The steps involved in fabrica ting a monolithic circuit (not aluminum or gold wirc from the terminal pad on the circuit to the package
lead.
drawn to scale). (a) Epitaxial growth; (b) isolation diffusion
(c) base diffusion;(d) emitter diffusion ; (e) aluminum metalization. of fabricating
Summary In thËs section the epitaxia]-diffused method
following proccsses:
integrated circuits is described. We have encountered the
96 / CHARACTERISTICS /
ELECTRONIC FUNDAMENTALS AND INTEGRATED CIRCUITS: FABRICATION AND
APPLICATIONS Sec. 5-4 Sec. 5.5
1. Crystal growth of a
2. Epitaxy substrate Ultraviolet Polymerized
photoreslst
3. Silicon dioxide
4. Photoetching growth MasK

Photoresist -
5. Diffusion
SIO,
SIO.
S.Vacuum evaporation of aluminum -SUlcon chip
SIllcon chlp
Tsing these techniqucs, it is possilble to producc the
same chip: transistors, diodes, following clements on the (a) (6)
intcrconncctions. rosistors, capacitors, and aluminum exposure to
Fig. 5-3 Photoetching technique. (o) Masking and
development.
ultraviolet radiation. (b) The photoresist after

EPITAXIAL GROWTH removes the osido

mersed in an etching solution of hydrofluoric acid, which
The cpitaxial process produces a thin ilm of single-crystal from the areas through which dopants are to be diffused. Those portions of
silicon from the acid.
gas phase upon an existing crystal wafer of the same
material. The epitaxinl the SiO, which are protected by the photoresist are unaffccted by tho
layer may be cither p-type or n-type. The growth of an epitaxial film of After etching and diTusion of impurities, the resist mask is removed (strinped)
purc silicon is obtained from the hydrogen reduction of silicon
tetrachloridc with a chemical solvent (hot II,SO,) And by means of a mechanical abrasion
at 1200°C. The substrate wafers are
placed in an oven containing these process.
chemicals, and the crystâl continues to grow by capturing the silicon atoms
rclcased in the chemical reaction. Since it is required to produce epitaxial
fil1ms of specifc impurity concentrations, it is necessary to introduce impuritics
such as phosphine for n-typc doping or biborane for p-type doping into the s-5 t DIFFUSION OF IMPURITIES
silicontetrachloride-hydrogen gas stream. The junction formed in this man he most important process in the fabricntion of integratced circuits is
ner is an approximately abrupt step p-n junction similar to that shown in the diffusion of impurities into the silicon chip. Reasonable difusion times
Fig. 2-7. (say, 2 hours) requ re high diffusion tenperatures (~1000°C). Therefore a
high-temperature diffusion furnace, having a closely controlled temperature
over the length (20 in.) of the hot zone of the furnace, is standard equipment
in a facility for the fabrication of integrated circuits. Impurity sources uset
5-9 MASKING AND ETCHING
The monolithic technique deseribed in Sec. 5-2\requires the selective removal Gas
outlet
of the Si0, to form openings through which impurities may be difused. The Quartz diffuslon tube
photoctehing incthod used for this rernoval is illustrated in Fig. 5-3. During
the photolithographic process the wafer is coated with a uniform film of a Sllcon wafers
photosensitive cmulsion (such as the Kodak photoresist KPR). A large
black-and-white layout of the desired pattern of openings is made and then -N, O:
reduccd photographically. This negative, or stencil, of the required dimen input
sions is placed as a mask over the photoresist, as shown in Fig. 5-3a. By
exposing the KPR to ultraviolet "light through the mask, the photoresist be -Furnace
comes polymerized under the transparent regions of the stencil. The mask Llquid POCI,
is now removed, and the wafer is "developed" by using a chemical (such as
trichlorocthylenc) which dissolves the unexposed (unpolymerized) portions of
the photoresist flm and leaves the surface pattern as shown in Fig. 5-36. The Thermostated bath
cmulsion which was not removed in development is now fired, or cured, so Fig. 5-4 Schematic representation of typical
that it becones resistant to the corrosive ctches used next. The chip is im (Courtesy of Mororold, Inc.) apparatus for POCI, diffusion.
 CHARACTERISTICS / 99
Sec. 5-6 INTEGRATED CIRCUITS: FABRICATION AND
98/ ELECTRONIC FUNDAMENTALS AND APPLICATIONS Sec. 5-6
geometry offer the greatest flexibil
in connection with diffusion furnaces can be gases, liquids, or solids. For ex inaterial. Of all these factors the sizé and schedules are determined by
The doping levels and diffusion
ample, POCI,, which is a liquid, is often used as a sourcc of phosphorus. ity for design. desired transistors in the inte
the standard pro cessing schedulc used for the
Figure 5-4 shows the apparatus used for POCl, diffusion. In this apparatus
grated circuit.
a carrier gas (mixture of nitrogen and oxygen) bubbles through the liquid
diffusant source and carries the diffusant atoms to the silicon wafers. Figure 5-6 shows a typical
Impurity Profiles for Integrated Transistors
profile for a monolithic integrated circuit transistor. The back
impurity
concentration Nne is shown as a dashed linc
5-65 TRANSISTORS FOR MONOLITHIC CIRCUITS ground, or epitaxial-collector, is high (5 X 101 atoms/cn) at
boron
in Fig. 5-6. The concentration N of
into the silicon as indicated in Fig. 5-6.
K planar transistor made for monolithic integrated circuits, using epitaxy and the surface and falls off with distanee the net
V cquals the concentration Nuc,
diffusion, is shown in Fig. 5-5a. Here the collector is clectrically separated At that distance x = T,, at which concentration is positive,
from the substrate by the reverse-biased isolation diodes. Since the anode For z <Ij, the net impurity
impurity density is zero. the
Hence t, represents the distance fron
of the isolation diode covers the back of the entire wafer, it is necessary to and for r>i, it is negative. formed. For the transistor whosc
make the collector contact on the top, as shown in Fig. 5-5. It is now clear collector junction is
surface at which the
um.
that the isolation diode of the integrated transistor has two undesirable effects: impurity profile is indicated in Fig. 5-6, z, = 2.7 from a much higher surface
starts
it adds a parasitic shunt capacitance to the collector and a leakage current The emitter difÉusion (phosphorus) 10* atoms/c1n', and is
path. In addition, the necessity for a top connection for the collector increases concentration (close to the solid solubility) of about is formed. This junc
the collector-current patlh and thus incrcases the collector rcsistance and un, where the emitter junction
iffused to a denpth of 2
the base and emitter distributions of
Ves,snt: All these undesirable efccts are absent from the liserete epitaxial tion corresponds to the intersection of thickness for this monolithic transistor
transistor shown in Fig. 5-5b. IWhat is then the advantage of the nonolithic impurities. We now sce that the base
step- graded
transistor? A significant improvement in performance arises from the fact is 0.7 un. The emitter-to -base junction is usually treated as a
considered a linearly graded
that integrated transistors are located physically close together and their elec junction, whercas the base-to-collector junction is
trical characteristics are closely matched. For example, integrated transistors junction.
spaced within 30 mils (0.03 in.) have Vux natehing of better than 5 mV with
deter
less than 10 4V/°C drift and an yx match of t 10 percent. These matched
yat Monolithic Transistor Layout The physical size of a transistor
capacitance.
transistors make excellent difference amplifiers (Sec. 12-12). mincs the parasitic isolation capacitance as well As the junction
The electrical characteristics of a transistor depend on the size and geome
try of the transistor, doping levels, diffusion schedules, and the basic silicon N(x)|

Emitter contact Base contact 1031

Collector contact

1020
p-type lsolation Phosphorus
emltter difusion
diffusio
eSESAal oolectot +(n-type)
Fig. 5-5 Comparison of Fig. 5-6 A typical 5 X 10
Fsbatrate cross sections of (a) a impurity profile in a 10!
Boron
(a) monolithic integrated cir monolithic integrated base dLffusion
cuit transistor with (b) a -(p-type). Epitaxial
transistor. [Note that 101 concentration
Emitter contact Base contact discrete plarar epitaxial N(z) is plotted on a -+Nac
transistor. (For a top logarithmic scole.]
view of the transistor in l044
0.7u n
(a) see Fig. 5-7.)
104
2
Collector contact -Collector
-Emitter
(6)
 CHARACTERISTICS / 14
100 / ELECTRONIC FUNDAMENTALS AND APPLICATIONS Sec. 5-7 INIEGRATED CIRCUITS: FABRICATION AND
Sec. 5-6
It is therefore necessary to use
small-geometry transistors if the integrated
circuit is designed to operate at high
Bave
Collector
frequencies or high switching specds. The
geometry of a typical monolithic transistor is shown in Fig. 5-7. The emitter
rectangle measures 1 by 1.5 mils, and is diffused into a 2.5- by Fig 5-8 A p-n-p lateral
region. Contact to the base is made through two 4.0-mil base P
side of the emitter. The metalized stripes on either transistor. 1mtter
rectangular metalized arca forms the ohmic contact neplatl lyer
to the collector region. The rectangular
collcctor contact of this transistor re
duces the saturation rcsistan ce. The substrate in this structure is located
p substrate

about 1 inil below the surface. Since diffusion proceeds in thrcc

it is clcar that the lateral-difusion distance will also be 1 mil. dimensions,
The dashed p regions
rcctangle in Fig. 5-7 represcnts the substrate area and is 6.5 by 8 mils. Vhile the .p base for the n-p-n transistor is made, the two adjacent in Eir
transistor shown
are diffused for the emitter and collector of the p-n -p
collector. Becauso
Lateral p-n-p Transistor The standard integrated-circuit transistor is 5-8. Note that the current flows laterally from emitter to diffusion, the base
an n-p-n type, as we hgve already emphasizcd. In some applications it is of inaccuracies in masking, and because, also, of lateral
required to have both n-p-n and p-n-p. transistors on the same chip. The width between emitter and collector is large (about 1 mil compared with 1
lateral p-n-p structure shown in Fig. 5-8 is the most common form of the inte uin for an n-p-n base). Hence the current gain of the p-n-p transistor is very
grated p-7-p transistor. This p-n-p uses the standard diffusion techniqucs as low (0.5 to 5) instead of 50 to 300 for the n-p-n device. Since the base-p
the n-p-n, but the last n diffusion (used for the n-p-n transistor) is climinated. resistivity of the n-p-n transistor is relatively high, the collector and emitter
resistances of the p-t-p device are high.

8.5 Vertical p-n-p Iransistor This transistor uses the substrate for the p
Indicates
contacts
collector ; the n epitaxial layer for the base; and the p base of the standard
n-p-n transistor as the emitter of this p-n-p device. We have already empha
1.0
sized that the substrate must be connccted to the most negative potential in
-2.5 the circuit. Hence n vertical p-n-p transistor can be used only if its collector
is at a fixed negative voltage. Such a configuration is called an emitter fol
lower, and is discussed in Sec. 10-4.

æ.25¬ -1.5 5-7

'ONOLITHIC DIODES
1.0| 10,0 The diodes utilized in integrated circuits are made by using transistor strue"
tures in one of five possible connections (Prob. 5-4). The three most
diode structures are shown in Fig. 5-9. They are obtained from a popular
0.2s

Emitter dffusion transistor

2.0 structure by using the emitter-base diode, with the collector short-circuited
to the base (a); the emitter-base diode, with the
collector-base diode, with the emitter open-circuitedcollector open (b); ana 6
(or not fabricated at al
Base diffuslon (c). The choice of the diode type used depends
1.0
circuit performance desired. upon the application #
0.25 -o.26 base voltage-breakdown rating Collector-base diodes hAVe the higher collector
of the collector junction (~12 V
Isolation diffusion The emitter-base diffusion is very popular for minimum).
provided that the reverse-voltage requirement of thethecircuit
fabrication of exceed
does not ou
Fig. 5-7 A typical double-base stripe geometry of
an integ rated the lower base-emitter
breakdown
can easily be made with the voltage (~7 V). Common-anode ar
circuit transistor. Dimensions are in mils. (For a side view of the emitter-base difEusion by using a
transistor see Fig. 5-5.) (Courtesy of
Motorola Monitor.) transistor within a single isolation arca, as shown in Fig. 5-10. multiple-eml
The collece
 103
Sec. 5-8 INTEGRATED CIRCUITS: FABRICATION AND CHARACTERISTICS
102 / ELECTRONIC FUNDAMENTALS AND APPLICATIONS Sec. 5-8

Fig. 5-9 Cross section of

p* P p various diode structures.
(a) Emiter-base diode
p
with collector shorted to Fig. 5-11 Pertaining to sheet re
base; (b) emitter-base sistance, ohms per square.
diode with collector open ;
(c) collector-base diode
(no emitter d1ffusion).

(a) (6) (c)

may be either open or shorted to the base. The diode pair in Fig. 5-1 is con Note that Rx is independent of the size of the squarc. Typicully,
the shect
structed in this manner, with the collector floating (open). The diode-conncted resistance of the base and emitter diffusions whose profiles are given in Fig.
transistor (emitter-base diode with collector short-cireuited to the base) pro 5-6 is 200 N/squarc and 2.2 n/square, respectivcly.
vides the highest conduction for a given forward voltage. The construction of a basc-diffused rcsistor is shown in Fig.
5-1 and is
repcated in Fig. 5-12. A top view of this resistor is shown in Fig. 5-120.
The resistance value may be conputed from
5-8 INTEGRATED RESISTORS yas pl (3-2)
|A resistor in a monolithic integrated circuit is very often obtained by utilizing R= = Rs
the bulk resistivity of one of the diffused areas. The p-type base diffusion
where l and u are the length and width of the diffused arca, ns shoWn in the
is most commonly used, although the n-type emitter diffusion is also employed. top view. For example, a basc-diffused-resistor stripe l mil wide and 10 mils
Since these diffusion layers are very thin, it is convenient to define a quantity
known as the sheet resistance Rs. long contains l0 (1 by 1 mil) squares, and its value is 10 X 200 = 2,000 2.
Empirical corrcctions for the end contacts are usually included in caleulations
Sheet Resistance If, in Pig. 5-11, the width w equals the length l, we of R.
have a square l by lof material with resistivity p, thickness y, and cross-sec
tional area A = ly. The resistance of this conductor (in ohms per square) Resistance Values Since the sheet resistance of the base and emitter
is difusions is fixcd, the only variables available for difuscd-resistor design are

(5-1)
R 19

p resis tor
Isolation Fig.5-10 A multiple-emit n lsolation reglon p
region, p*
ter n-p-n transistor. (o) p substrate
Schematic, (b) monolithic Fig. 5-12 A monolithic resistor. (a) Cross (a)
surface pattern. If the sectional view; (b) top view.
B base is connected to the
collector, the resultis a
OE.
n multiple-cathode diode
p structure with a common
(6)
anode.
(a) (b)
 / 10s
FABRICTION AND CHARACTERISTICS
INTEGRATED CIRCUITS:
104 / ELECTRONIC FUNDAMENTALSs AND APPLICATIONS Sec. 5.8 Sec. 5.9

INDUCTORS
stripe length and stripe width. Stripe widths of less than 1 mil (0.001 in.) INTEGRATED CAPACITORS AND transition
by utilizing the
are not normally used because a line-width variation of 0.0001 in. due to mask
drawing error or mask misalignment or photographic-resolution error can result Capacitors in integrated circuts may be obtained a thin-film technique.
reverse-biased p-n junction or by
in 10percent resistor-tolerancc error. capacitance of a
The range of values obtainable with difused resistors is limited by the junction capacitor is
cross-sectional view of a.reverse-biased
size of the area required by the resistor. Practical range of resistancc is 20 Junction Capacitors A is forrned by the
junction
capacitor
to 30 K for a base-difused resistor and 10n to 1 K for an emitter-diffuscd shown in Fig. 5-14a. The upper p-type diffusion
resistor. The tolerance which results from profile variations and surface epitaxial n-type layer from the n-type epitaxial planc
Ja, which separates the the
J, appears between associated with this re.
geometry errors is as high as 10 percent of the nominal valuc at 25°C, with areas. An additional junction parasitic capacitance C is
ratio tolerance of #1 percent. For this reason the design of integrated circuits and the substrate, and a equivalent circuit of the junction
capacitor is
should, if possible, emphasize resistance ratios rather than absolute values. verse-biased junction. The capacitance C2 should be as large as
desired
The temperature coefficient for these heavily doped resistors is positive and shown in Fig. 5-14b, where thevalue of C, depends on the junction area and
is 0.06 percent/°C from -55 to 0°C and +0.20 percent/°C from 0 to
125°C. possible relative to C,. The junction is essentially linearly graded,
C,
impurity concentration. Since this R (10 to 50 2) represents the resistance
varies as V-!. The series resistance
Equivalent Circuit A model of the diffused resistor is shown in Fig. 5-13, of the n-type layer.
isolation-sub the mnost negative voltage so as
where the parasitic capacitances of the base-isolation (C,) and It is clear that the substrate must be at
junctions are included. In addition, it can be sccn tlhat a parasitic other elements by keeping junc
to mimize C, and isolate the capacitorbefrom
strate (C;)
collector, the isolation n-type pointed out that the junction capaci
p-n-p transistor exists, with the substrate as ennitter. The collector tion J, reverse-biased. It should also
region as base, and the resistor p-type material as the must always be reverse-biased.
at the mnost negative potential. tor C, is polarized since the p-n junction J,
is reverse-biased because the p-tyne substrate is
necessary that the emitter be reverse-biascd to kecep the parasitic ([OS) nonpolarized
It is also
maintained by placing all resistors in Thin-Film Capacitors A metal-oxide-semiconductor
transistor at cutoff. This condition is surround capacitor is indicated in Fig. 5-15a. This structure is a parallel-plate capaci
n-typc isolation region
the same isolation region and connecting the present in the circuit. Typical tor with Si0, as the dielectric. A surface thin ilm of metal
(aluminum) is
ing the resistors to the most positive voltage
range fron 0.5 to 5. the top plate. The bottora plate consists of the heavily doped n* region that
values of hre for this parasitic transistor is formed during the emitter diffusion. A typical value for capacitance is 0.4
vapor thin-flm deposition can also be
pF/mil? for an oxide thickness of 500 A, and the capacitance varies inversely
Thin-Film Resistors A technique of circuits. The metal (usually with the thickness.
resistors for integrated
used to fabricate a thickness of less than 1 m) on the
deposited (to
Nichronme NiCr) flm is to produce the desired geome
etching is used
silicon dioxide layer, and maskedcovered by an insulating layer, and apertures Al metalization C,0.2pF/m1?
try. The metal resistor is then layer. Typical B
opened through this insulating A
W
for the ohmic contacts areNichrome thin-flm resistors are 40 to 400 N/square, R=
sheet-resistance values for P type C,
from about 20 to 50 K.
Jtetp-tVypepesubs060ctrate th J, 10-500
resulting in resistance values
J SIO,
n-type layer

50-cm
R
1 player C,

C, circuit
Fig. 5-13 The equivalent Substrate
on lsolation reglon
of a diffused resistor. (a) (6)
Fig. 5-14 (o) Junction monolithic capacitor. (b) Equivalent circuit. (Çourtesy
-op Bubstrate of Motorola, Inc.)
106 / ELECTRONIC FUNDAMENTALS AND .APPLICATIONS Sec. 5-10 Sec, 5-10 INTEGRATED CIRCUITS: FABRICATION AND CHARACTERIS TICS/ 107

CN0.25pF/mil? diode was investigated many years ago, but until the late 1960s commercial
Schottky diodes 'were not available because of problems encountered in their
Al metalization
R=
5-100 manufacture. It 'has turned out that most of the fabrication difficulties are
due to surface effects; by employing the suríace-passivated integrated-cireuit
SIO, techniques described in this chapter, it is possible to construct almost ideal
9.30-cm J, metal-semiconductor diodes very economically.
p-type substrate, 50-cm As mentioned in Sec. 5-2 (step 4), aluminum scts as a p-type impurity
p-type substrate when in contact with silicon. If Al is to be attached as a lead to n-type Si,
an ohmic contact is desired and the formation of a p-n junction must be pre
(a) (b) vented. It is for this reason that n diffusions are madc in the n regions near
Fig. 5-15 An MOS capacitor. (o) The structure ; (b) the equivalent circuit. the surface where the Al is deposited (Fig. 5-2d). On the other hand, if the
n* diffusion is omitted and the Al is deposited directly upon the n-type Si,
The equivalent circuit of the MOS capacitor is shown in Fig. 5-15b, where an equivalent p-n structure is formed, resulting in an excellent metal-senicon
C, denotes the parasitic capacitance of the collector-substrate junction J,, and ductor diode. In Fig. 5-16 contact 1 is a Schottky barrier, whereas contact
R is the srmall series resistance of the n* region. 2 is an ohmic (nonrectifying) contact, and a metal-semiconductor diode exists
between these two terminals, with the anode at contact 1. Note that the fabri
Inductors No practical inductance values have been obtained on silicon cation of a Schottky diode is actually simpler than that of a p-n diode, which
substrates using semiconductor or thin-ilm techniques. Therefore their use requires an extra (p-type) diffusion.
The external volt-ampere characteristic of a metal-semiconductor diode is
is avoided in circuit design wherever possible. If an inductor is rcquired, a essentially the same as that of a p-n junctiont, but the physical mechanis1s
discrete component is connected externally to the integrated circuit.
involved are more complicated. Note that in the forward direction electrons
from the n-type Si cross the junction into the metal, where electrons arc plenti
Characteristics of lntegrated Components Based upon our discussion ful. In this sense, this is a najority-carrier device, whereas minority carricrs
of integrated-circuit technology, we can summarize the significant characteris account for a p-n diode characteristic. There is a delay in switching a p-n
tics of integrated circuits (in addition to the advantages listed in Sec. 5-1). diode fron oN to oFF (called the storage time) because the minority carriers
1. A restricted range of values exists for resistors and capacitors. Typi stored at the junetion must first be removed. Schottky diodes have a negligi
cally, 10 nsRS30 Kand C< 200 pF. ble storage time t, because the current is carried predoninantly by majority
2. Poor tolerances are obtained in fabricating resistors and capacitors of carriers. (Electrons from the n side enter the aluninum and become indistin
specific magnitudes. For example, t 20 percent of absolute values is typical. guishable from the electrons in the metal, and hence are not "stored" near
Resistance ratio tolerance can be specified to #l percent because all resistors the junction.)
aremade at the same time using the same techniques. It should be nuentioned that the voltage drop across a Schottky diode is
3. Components have high-temperature coefficie:1ts and may also be much less than that of a p-n diode for the same forward current. Thus, u
voltage-sensitive. cutin voltage of about 0.3 V is reasonable for a metal-semiconductor diode
4. High-frequency rsponse is limited by parasitic capacitances.
5. The technology is very costly for small-quantity production.
Fig. 5-16 (o) A Schottky
6. No practicalinductors or transormers can be integrated.
diode fo rmed by IC tech
niques. The aluminum and
the lightly doped n region SiO,
5-10 THE METAL-SEMICONDUCTOR CONTACT form arectifying contact 1, 1
Two types of metal-semiconductor junctions are possible, ohmic and rectify whereas the metal and the
Anode
ing. The former is the type of contact desird when a lead is to be attached heavily doped nt region
to a semiconductor. On the other hand, the rectifying contact results in a form an ohmic contact 2. p-type substrate
metal-semiconductor diode (called a Schottky b¡rrier), with volt-ampere char (b) The symbol for this
acteristics very similar to those of a p-n diode. The metal-semiconductor metal-semiconductor diode. (a) (6
 substrate. havea already J'Ou
the involved
in processes basic ive the List 5-3
assuming an of
IC, fabrication assuming
you (1C),
substrate. haveaalready
monolithic fabricatinga involved
in steps five the List 5-2
circuitintegrated four the are What
circuits? integrated advantages
of 5-1
QUESTIONS REVIEW
5-17c. Fig. symbol
in the by
presented transistor,
isand Schottky a rferred
as to isThis 5-17a. Fig.
circuit
of tequivalent
he to 5-17b
is Fig. device
in Thecollector. and base
between
metal-semiconductor
diode formsaprocedure simple This section).
intervening
n* without
an (but region collector n-type the with alsocontact .
make allowed
to lead
is base metalization
the for aluminum th5-17b,
e Fig. /n
indicated constructed.
As transistor
is the that time samc the fabricatcd
at
becan diodeclamping Schottky the steps,
processing additional no
With
(Sec.
4-8). saturation enter not docs tor
transis the V), (a0.5 voltage cutin the than forward-biased
less by junction
is
collector the Since 0.4about
V. limited voltage
is
to basc-to-collcctor the and
conducts, drops,
D voltage collector current,
the base increasing
the bytor
transis saturate
this to
made attempt
is an
collector.
If and base tbetwecn
he
clamp adias
odeSchottky usinag 5-17a,
by Fig. indicated
in achieved,
as be
condition
can Thisaturation.
s cntering fromprevented bemust
transistor n
words, other transistors.
In all in
timestorage clinminate desirable
to isgatc,
it
logicpropagation-delay
ain
time threduce
e Transistor
To Schottky The
latter. the than liode
ideal the closer
to former
is the Hence harrier. p-n afor V
against
0.6 as
(a). shown
in abbreviation
that for an which
is symbol, transistor Schottky
diode-transistortombinotiön
The (c) (o). in equivalent
the to lithic
IC
mono section
a of cross The saturation.
(b) prevent collector
to and
basebetween Schottky-diode
clamp transistor
awith A(o) 5-17 Fig.
(c) (6) (a)
substrate p
collector n
p p+
base p B
()
D
8 E C
5.10 Sec. APPLICATIONS FUNDAMENTALS
AND ELECTRONIC 108