Last name: ………………………......... First name: ……………………….........

Task:
Design a Synchronous Hexadecimal Up-Counter which counts 16 Digits from
0 to F (0, 1,2, …9, A, B, …, F), and displays the value in a 7-Segment Display.
The counter depends in Rising edge clock, also It has a Reset button to start over.
- To turn a segment on, the state must be ‘0’;
- To turn a segment off, the state must be ‘1’;

1- Draw the truth table of this Task; 04 pts

Answer:
1- The Truth Table: 0.25 /Row

Count a b c d e f g h Display
0 0 0 0 0 0 0 1 1 0
1 1 0 0 1 1 1 1 1 1
2 0 0 1 0 0 1 0 1 2
3 0 0 0 0 1 1 0 1 3
4 1 0 0 1 1 0 0 1 4
5 0 1 0 0 1 0 0 1 5
6 0 1 0 0 0 0 0 1 6
7 0 0 0 1 1 1 1 1 7
8 0 0 0 0 0 0 0 1 8
9 0 0 0 0 1 0 0 1 9
10 0 0 0 1 0 0 0 1 A
11 1 1 0 0 0 0 0 1 b
12 0 1 1 0 0 0 1 1 C
13 1 0 0 0 0 1 0 1 d
14 0 1 1 0 0 0 0 1 E
15 0 1 1 1 0 0 0 1 F

-1-
 1st Solution for Test 1
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL; 0.5 pt
3 use IEEE.NUMERIC_STD.ALL;
4
5 entity TEST_1 is
6 Port (
7 clk_12mhz : in STD_LOGIC := '0'; -- 12 MHz clock input
8 RESET : in STD_LOGIC := '1'; -- Active low reset
9 01 pt second_clk : inout STD_LOGIC := '0'; -- 1 Hz Clock
10 SEGMENT : out STD_LOGIC_VECTOR(7 downto 0) -- 7-segment display (a-h)

11 );
12 end TEST_1;
13
14 architecture Behavioral of TEST_1 is
15
16 SIGNAL counter : INTEGER := 0; 0.5 pt
17 SIGNAL val : INTEGER := 0;
18 SIGNAL SEG : STD_LOGIC_VECTOR(7 downto 0) := "11111111";
19
20 begin
21
22 PROCESS(RESET, clk_12mhz, second_clk, val) is
23 BEGIN
24 if (RESET = '0') then
25 counter <= 0;
26 second_clk <= '0';
27 val <= 0;
0.5 pt
28 SEG <= "11111111";
29
30 elsif (rising_edge(clk_12mhz)) then
31 counter <= counter + 1;
32
33 if (counter > 6000000) then -- Cycle = f_in/(2*f_out) 12 000 000
Hz/(2*1 Hz) = 6 000 000
34 counter <= 0; 0.5 pt
35 second_clk <= NOT(second_clk);
36 end if;
37 end if;
38
39 if (rising_edge(second_clk)) then
40 val <= val + 1;
41 if (val > 15) then
42 val <= 0; 0.5 pt
43 end if;
44
45 case val is
46 -- Format: seg(7 downto 0) = "abcdefgh"
47 -- Segment ON when '0', OFF when '1'
48 when 0 => SEG <= "00000011"; -- 0
49 when 1 => SEG <= "10011111"; -- 1
50 when 2 => SEG <= "00100101"; -- 2
51 when 3 => SEG <= "00001101"; -- 3
52 when 4 => SEG <= "10011001"; -- 4
53 when 5 => SEG <= "01001001"; -- 5
54 when 6 => SEG <= "01000001"; -- 6 02 pt
55 when 7 => SEG <= "00011111"; -- 7
56 when 8 => SEG <= "00000001"; -- 8
57 when 9 => SEG <= "00001001"; -- 9
58 when 10 => SEG <= "00010001"; -- A
59 when 11 => SEG <= "11000001"; -- b
60 when 12 => SEG <= "01100011"; -- C

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61 when 13 => SEG <= "10000101"; -- d
62 when 14 => SEG <= "01100001"; -- E
63 when 15 => SEG <= "01110001"; -- F
64 when others => SEG <= "11111111"; -- All off
65 end case;
66 end if;
67 END PROCESS;
68 SEGMENT <= SEG; 0.5 pt
69 end Behavioral;

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 2nd Solution for Test 1
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3 use IEEE.STD_LOGIC_UNSIGNED.ALL;
0.5 pt
4 use IEEE.STD_LOGIC_ARITH.ALL;
5
6 entity TEST1_2 is
7 Port (
8 clk_12mhz : in STD_LOGIC := '0'; -- 12 MHz clock input
9 01 pt RESET : in STD_LOGIC := '1'; -- Active low reset
10 SEGMENT : out STD_LOGIC_VECTOR(7 downto 0) -- 7-segment display (a-h)
11 );
12 end TEST1_2;
13
14 architecture Behavioral of TEST1_2 is
15 SIGNAL DIGIT : INTEGER := 0;
16 SIGNAL COUNTER : INTEGER := 0; 0.5 pt
17 SIGNAL SEG : STD_LOGIC_VECTOR(7 downto 0) := "11111111";
18 begin
19
20 PROCESS(RESET, clk_12mhz, COUNTER, DIGIT) is
21 BEGIN 0.5 pt
22 if (RESET = '0') then
23 COUNTER <= 0;
24 DIGIT <= 0; 0.5 pt
25 SEG <= "11111111";
26 elsif (rising_edge(clk_12mhz)) then
27 COUNTER <= COUNTER + 1;
28 if (COUNTER = 12000000) then
29 COUNTER <= 0;
30 DIGIT <= DIGIT + 1; 0.5 pt
31 if (DIGIT > 15) then
32 DIGIT <= 0;
33 end if;
34 case DIGIT is
35 -- Format: seg(7 downto 0) = "abcdefgh"
36 -- Segment ON when '0', OFF when '1'
37 when 0 => SEG <= "00000011"; -- 0
38 when 1 => SEG <= "10011111"; -- 1
39 when 2 => SEG <= "00100101"; -- 2
40 when 3 => SEG <= "00001101"; -- 3
41 when 4 => SEG <= "10011001"; -- 4
42 when 5 => SEG <= "01001001"; -- 5
43 when 6 => SEG <= "01000001"; -- 6
44 when 7 => SEG <= "00011111"; -- 7 02 pt
45 when 8 => SEG <= "00000001"; -- 8
46 when 9 => SEG <= "00001001"; -- 9
47 when 10 => SEG <= "00010001"; -- A
48 when 11 => SEG <= "11000001"; -- b
49 when 12 => SEG <= "01100011"; -- C
50 when 13 => SEG <= "10000101"; -- d
51 when 14 => SEG <= "01100001"; -- E
52 when 15 => SEG <= "01110001"; -- F
53 when others => SEG <= "11111111"; -- All off
54 end case;
55 end if;
56 end if;
57
58 END PROCESS;
59 SEGMENT <= SEG; 0.5 pt
60 end Behavioral;

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