Power Supply and Clock Pins

1.​ VCC (Pin 40): This pin is connected to a +5V DC power supply. It powers the
internal circuitry of the microprocessor.​

2.​ GND (Pins 1 and 20): These are ground pins used as a reference voltage for
internal operations.​

3.​ CLK (Pin 19): The clock input provides the basic timing signal to synchronize
internal operations. The frequency of CLK determines the speed of operation.​

4.​ RESET (Pin 21): This input is used to reset the processor. When RESET is
activated, the program counter is set to FFFF0H, the instruction queue is cleared,
and the processor enters a known startup state.

Address/Data and Address/Status Bus

1.​ AD0 - AD15 (Pins 2 to 16 and 39): These are multiplexed address/data lines.​

a.​ During the first clock cycle (T1), these lines carry the 16-bit address.
b.​ During the next clock cycles (T2, T3, and T4), they carry data between the
processor and memory or I/O devices.​

2.​ A16/S3 - A19/S6 (Pins 35 to 38):​

a.​ During T1 state, these pins carry the high-order address bits A16 to A19.
b.​ During T2, T3, and T4, they carry status signals S3 to S6. These status
signals help in system control, particularly in multiprocessor configurations.

Control and Status Signals

1.​ ALE (Address Latch Enable) (Pin 25): ALE indicates the presence of a valid address
on the multiplexed address/data bus. It is used to latch the lower 16-bit address
externally using a latch like 74LS373.
DT/̅R (Data Transmit/Receive) (Pin 27): This signal controls the direction of data flow
through the data transceivers.

High: Processor is transmitting data.

Low: Processor is receiving data.

DEN (Data Enable) (Pin 26): Enables the external data transceivers to allow data to flow
to or from the processor.

M/̅IO (Memory/Input-Output) (Pin 28): This signal distinguishes between memory

operations and I/O operations.
High: Memory operation.
Low: I/O operation.​

READY (Pin 22): This input is used to insert wait states into the timing of the
microprocessor. If READY is low, the processor will wait before completing the current
operation, allowing slower memory or I/O devices to function properly.

INTA̅ (Interrupt Acknowledge) (Pin 24): This output is used to acknowledge an interrupt
request from an external device.

Interrupt and DMA Signals

INTR (Interrupt Request) (Pin 18): A maskable interrupt input. It is checked

at the end of each instruction cycle.

NMI (Non-Maskable Interrupt) (Pin 17): A non-maskable interrupt input

with higher priority than INTR. It is generally used for critical events like
power failures.

TEST (Pin 23): Used in conjunction with the WAIT instruction. If TEST is
low, the processor enters a wait state until TEST goes high.

Minimum Mode Specific Pins (Single Processor Mode)

When the MN/̅MX̅ pin is high, the processor operates in Minimum Mode, and the following
pins are used:

1.​ WR̅ (Write) (Pin 29): This output signal indicates that the processor is performing
a write operation.
2.​ HOLD (Pin 31): External devices can use HOLD to request the bus control from the
processor.
 3.​ HLDA (Hold Acknowledge) (Pin 30): This output indicates that the processor has
granted the bus control to another master.

Maximum Mode Specific Pins (Multiprocessor Mode)

When the MN/̅MX̅ pin is low, the processor operates in Maximum Mode, and the following
pins are used:

1.​ S2, S1, S0 (Pins 26, 27, 28): These status lines indicate the type of operation
being carried out (e.g., interrupt acknowledge, I/O read, I/O write, memory read,
memory write).​

2.​ LOCK̅ (Pin 29): This output is activated to prevent other bus masters from gaining
control of the system bus during critical operations.​

3.​ RQ̅/GT0 and RQ̅/GT1 (Pins 30 and 31): These pins are used by other bus masters
to request control of the system bus. Grant signals are used to acknowledge such
requests.

Mode Selection

1.​ MN/̅MX̅ (Pin 33): Mode selection input.​

a.​ High: Minimum Mode (single processor environment).​

b.​ Low: Maximum Mode (multiprocessor environment).

Other Important Pins

1.​ BHE/̅S7 (Bus High Enable/Status) (Pin 34): BHE̅ is used to select the higher byte
(D8-D15) of the data bus during read/write operations. It is important in
accessing 8-bit data in a 16-bit system
1. Bus Interface Unit (BIU)
Functions
1.​ Fetches instructions from memory into the prefetch queue.
2.​ Supplies physical addresses for memory and I/O operations by combining segment
and offset.
3.​ Reads from and writes data to memory or I/O ports.
4.​ Performs instruction queuing (6-byte queue) to enable pipelined fetch and
execution
Components
1.​ Instruction Queue: A 6-byte FIFO that stores prefetched instructions, allowing
overlap of fetch and execution.
2.​ Segment Registers (16-bit):
a.​ CS (Code Segment): Base address of the code segment.
b.​ DS (Data Segment): Base address of the data segment.
c.​ SS (Stack Segment): Base address of the stack segment.
d.​ ES (Extra Segment): Base address of an additional data segment.
 3.​ Instruction Pointer (IP): Holds the offset of the next instruction to be executed.
4.​ Address Generation Unit (AGU): Merges segment and offset to form a 20-bit
physical address.
5.​ Memory Interface: Connects the BIU to external memory for fetch and data
operations.​

2. Execution Unit (EU)

Functions
1.​ Receives instructions from the BIU, decodes them, and issues control signals.
2.​ Executes arithmetic and logical operations on data.
3.​ Manages internal registers and flag updates.​

Components
1.​ General Purpose Registers:
a.​ AX, BX, CX, DX (16-bit, each split into high and low bytes: AH/AL, BH/BL,
CH/CL, DH/DL) used for data manipulation and arithmetic.​

2.​ Pointer & Index Registers:

a.​ SP (Stack Pointer) and BP (Base Pointer) for stack operations; SI (Source
Index) and DI (Destination Index) for string and array operations.​

3.​ Arithmetic Logic Unit (ALU): Performs all arithmetic (+, –, ×, ÷) and logical (AND,
OR, XOR, NOT) operations.
4.​ Flag Register: A 16-bit register with conditional and control flags (Zero, Carry,
Sign, Overflow, Parity, Trap, Interrupt Enable, Direction, Auxiliary Carry) that
reflect operation outcomes and control processor behavior.
5.​ Control System: Decodes fetched instructions and generates timing and control
signals to coordinate EU and BIU activities