Tutorial 09
Finite State Machine (FSM)
What is an FSM?
A Finite State Machine (FSM) is a mathematical model used to design digital circuits that
transition between states based on inputs. FSMs are widely used in CPU control units, vending
machines, elevators, traffic lights, and many other systems.
FSMs are classified into two types:
1. Moore Machine – Output depends only on the current state.
2. Mealy Machine – Output depends on both the current state and inputs.
FSM Components
An FSM consists of:
● States: Defined conditions the system can be in.
● Inputs: External signals affecting state transitions.
● Transitions: Rules for moving from one state to another.
● Outputs: Signals based on states (Moore) or states + inputs (Mealy).
FSM Block Diagram
[ Inputs ] → [ State Logic ] → [ Next State ] → [ Outputs ]
FSM Implementation in Verilog
FSMs in Verilog are implemented using 3 always blocks:
1. State Register: Stores the current state (clocked).
2. Next State Logic: Defines transitions (combinational).
3. Output Logic: Determines outputs (combinational).
Example: Simple FSM (Moore Machine)
Let's design an FSM that detects a specific sequence of bits (1011) in a serial input stream.
FSM State Diagram
[IDLE] → [S1: '1'] → [S2: '10'] → [S3: '101'] → [S4: '1011' →
Output '1']
Verilog Code for Sequence Detector (FSM)
module sequence_detector(
input wire clk,
input wire rst,
input wire in_bit,
output reg detected
);
typedef enum reg [2:0] {IDLE=3'b000, S1=3'b001, S2=3'b010, S3=3'b011, S4=3'b100}
state_t;
state_t state, next_state;
always @(posedge clk or posedge rst) begin
if (rst)
state <= IDLE;
else
state <= next_state;
end
always @(*) begin
case (state)
IDLE: next_state = state_t'(in_bit ? S1 : IDLE);
S1: next_state = state_t'(in_bit ? S1 : S2);
S2: next_state = state_t'(in_bit ? S3 : IDLE);
S3: next_state = state_t'(in_bit ? S4 : S2);
S4: next_state = state_t'(in_bit ? S1 : S2);
default: next_state = state_t'(IDLE);
endcase
end
always @(*) begin
detected = (state == S4);
end
endmodule
FSM Testbench
module sequence_detector_tb;
reg clk, rst, in_bit;
wire detected;
sequence_detector uut (.clk(clk), .rst(rst), .in_bit(in_bit), .detected(detected));
always #5 clk = ~clk;
initial begin
$monitor("Time: %0t | Input: %b | Detected: %b", $time, in_bit, detected);
clk = 0; rst = 1; in_bit = 0;
#10 rst = 0;
#10 in_bit = 1;
#10 in_bit = 0;
#10 in_bit = 1;
#10 in_bit = 1;
#10 in_bit = 0;
#20 $finish;
end
endmodule
Submission LINK
Lab Submission Requirements
1. Implement the FSMs on EDA Playground.
2. Simulate and test each FSM with a testbench.
3. Submit a report in PDF format.
Lab Tasks
Task 1: Simple Traffic Light Controller (Moore FSM)
● Description: Implement a Moore FSM that cycles through Red -> Green -> Yellow ->
Red.
● States: RED, GREEN, YELLOW
● Inputs: Clock and Reset
● Outputs: Traffic light signals
Task 2: Vending Machine (Mealy FSM)
● Description: Implement a Mealy FSM that releases an item after two 10¢ coins are
inserted.
● States: WAIT, COIN1, RELEASE
● Inputs: Coin input (10¢), Reset
● Outputs: Dispense signal
Task 3: Elevator Controller (FSM)
● Description: Implement an FSM to control an elevator moving between three floors.
● States: FLOOR_1, FLOOR_2, FLOOR_3
● Inputs: Up/Down button, Reset
● Outputs: Current floor indicator
Lab Submission Form
Lab Title:
Student Name: ____________________
Student ID: ____________________
Date of Submission: ______________
1. Lab Objectives
● Understand the fundamentals of FSMs (Moore and Mealy machines).
● Implement FSMs using Verilog.
● Simulate and verify FSM behavior using testbenches.
2. Design Approach
Describe the modules you created and their functionalities.
3. Verilog Code
🔗 EDA Playground Link: [Insert URL Here]
4. Testbench and Simulation Results
🔗 EDA Playground Link (Testbench): [Insert URL Here]
Simulation Output:
5. Conclusion
Summarize what you learned from this lab
