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DLD Lab

The document outlines tasks for designing and implementing digital logic circuits using Logisim. It includes constructing Karnaugh Maps for Boolean functions, simplifying expressions, and creating S-R latches and JK flip-flops using NAND and NOR gates. Each task involves circuit design, truth table development, and verification of outputs for various inputs.

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8 views3 pages

DLD Lab

The document outlines tasks for designing and implementing digital logic circuits using Logisim. It includes constructing Karnaugh Maps for Boolean functions, simplifying expressions, and creating S-R latches and JK flip-flops using NAND and NOR gates. Each task involves circuit design, truth table development, and verification of outputs for various inputs.

Uploaded by

kanokfaishalhaque018
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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1.

Given Boolean Function:

F(A,B,C,D)=Σm(0,1,2,5,8,9,10,14)

Task Breakdown:

1. Construct a 4-variable Karnaugh Map (K-Map).


2. Simplify the Boolean function using K-map grouping (pairs, quads, octets).
3. Implement the simplified Boolean expression using basic logic gates in Logisim.

2. Given Boolean Function:

F(A,B,C)=Σm(1,3,5,6,7)

where Σm represents minterms.

Task Breakdown:

1. Construct a 3-variable K-map with A, B, C as variables.


2. Group minterms into pairs, quads, or octets to simplify the function.
3. Write the simplified Boolean expression.
4. Design and implement the simplified function in Logisim using basic logic gates (AND,
OR, NOT).
5. Verify the circuit’s output for all possible inputs.

3. Design and implement an S-R (Set-Reset) Latch using NAND gates in Logisim.

Task Breakdown:

1. Construct an S-R Latch using only NAND gates.


2. Develop the truth table to describe the latch's behavior.
3. Implement the circuit in Logisim and verify its operation.
4. Test the circuit with different combinations of S (Set) and R (Reset) inputs, and observe
the output behavior.
Hints: The circuits and truth table is given below:

4. Design and implement an S-R (Set-Reset) Latch using NOR gates in Logisim.

Task Breakdown:

1. Construct an S-R Latch using only NOR gates.


2. Develop the truth table to describe the latch's behavior.
3. Implement the circuit in Logisim and verify its operation.
4. Test the circuit with different combinations of S (Set) and R (Reset) inputs, and observe
the output behavior.

Hints: The circuits and truth table is given below:

5. Construct a JK flip-flop circuit using NAND gates within the Logisim digital logic simulator.

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