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Chapter 3

This document provides an overview of computer organization, focusing on the components of the CPU, types of memory, and memory operations. It explains the roles of the Control Unit and Arithmetic Logic Unit, as well as the functioning of registers and buses in data processing. Additionally, it covers memory hierarchy, capacity, and byte ordering in computer systems.

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0% found this document useful (0 votes)
16 views55 pages

Chapter 3

This document provides an overview of computer organization, focusing on the components of the CPU, types of memory, and memory operations. It explains the roles of the Control Unit and Arithmetic Logic Unit, as well as the functioning of registers and buses in data processing. Additionally, it covers memory hierarchy, capacity, and byte ordering in computer systems.

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2024661568
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© © All Rights Reserved
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Edited on March

2020
Upon completion of this chapter, students should understand about:

Components of the CPU (CU and ALU)


Registers, Buses, and Clock

Types of Memory (Magnetic core, RAM, and


ROM)
Memory Hierarchy
Memory Operations (read/write)
Memory Capacity
Interprets and carries out basic instructions
that operate a computer.
It controls the action, performs the calculations, &
manipulates the data.
Also called the processor
✧ With the advent of integrated circuit
technology, the entire CPU of today, resides in a
micro chip Microprocessor.
✧ Miniature silicon chip found in computers that
is the heart of the computer.
MICROPROSSEOR
The processor contains four key components:
Contains the micro program (contains the entire instruction set, resides in

an internal ROM).

It coordinates and directs most of the operations in the computer.

Controls and interprets the execution of instructions, by following a


sequence of actions that corresponds to fetch-execute instruction
cycle .
Retrieve instructions from memory then movement of data or
address from one part of the CPU to another.
To determine which instruction to be executed, CU reads the contents
of the
program counter (PC)/ instruction pointer (IP).
CONTROL UNIT

Instruction Decoder
▪ Instruction decoding is the process whereby
the microprocessor interprets the bit pattern
appearing in the instruction decoder register.
▪ The microprocessor knows “how” to add
(through the instruction set) but does not
know “when” or “what” to add.
▪ The word or instruction to add needs to
be decoded or interpreted by the
instruction decoder.
Performs arithmetic and logical operations on input

data. It performs these operations as directed by the CU.


Comparator
• Compares the magnitude of two numbers placed in buffer registers. The
comparator, used in conjunction with Status Register, will output the results of
the comparison.
Logic Register
• Performs such logic operations as AND, OR, XOR, etc.

Control of ALU
• provides input path for control signals and facilitate the

sequencing and operation of each individual block of circuits.

Shifter
• move the contents of a register one or more positions left or right.
Can also perform a unique operation called rotate when used with
status register.
CSC159 | COMPUTER ORGANIZATION | CH3 |ZAZALEENA ZAKARIAH
.

.
Four primary operations by
registers:

Loaded with values from other locations

Added or subtracted

Shifted or rotated right or left by one or


more bits

Can be tested for certain conditions


(zeros, negative, etc).
Holds the current instruction being executed.
Both a counter and a register
The address in the program counter register is always the
address of the next instruction to be executed
When the current instruction is finished, the program
counter generates an address and places it on the address bus
It then increments, that is, adds 1 to the address it just
generated and puts the number in the counter register
As the current instruction finished, it places the new address on
the address bus and again adds 1 to the register
The program counter continually generates sequential address
Memory Address Register
• Holds the address of a memory location.

Memory Data Register


• Also known as Memory Buffer Register (MBR).

• Holds data value that is being stored to or retrieved from

the memory location currently addressed by the memory

address register.
Allow computers to keep track of special condition

such as:

Arithmetic carry and overflow

Power failure

Internal computer error


A device that produces periodic sequence of pulses to control the
timing of all computer operations
These pulses define machine cycles

During each machine cycle, some activity occurs, such as the execution of
a micro-instruction
The interval between corresponding edges of two consecutive pulses
is called the clock cycle time
The clock speed is measured by the number of ticks per second
Pulse frequencies are currently in the gigahertz range which
corresponds to billions of ticks per second
The faster the clock speed, the more instructions the

processor can execute per second


CLOCK

Generates precisely timed electronic pulses


Synchronizes all computer operations
Each tick is a clock cycle that determines when the
next machine cycle will occur
MHz – one million ticks per second of system clock
– theoretically, capable of executing
one million instructions per second
GHz – one billion ticks per second of system clock
CLOCK
Memory
Types of Memory
Types of Memory
Types of Memory
Volatile/RAM
THREE TYPES OF
RAM

▪ Less expensive, • Faster access

R
S
require less electrical compared to

MRA
DRA

power, and can be DRAM


made smaller, with
more bits of storage • Useful in very high
in a single integrated speed computers and
circuit. for small amounts of
▪ Requires extra high speed memory.
electronic • Does not require
circuitry that refreshing.
“refreshes” • More expensive
memory
periodically. and require more
chips.
Types of Memory
Non Volatile/ROM
THREE TYPES OF
RAM
w into those
r cells.
i
▪ Can be • Contents can be t
programmed
EEPRO programmed and i
EPRO

by the user erased by the user n


▪Contents of • writable memory g
EPROM can be using a concept n
called Fowler-
Merased by MNordh
e
w
exposing it to
ultra-violet light. eim d
tunneling a
• Rewriting can be t
done by erasing a
memory cells
selectively, then
▪ Similar to
EEPROM (erased
and written).
▪ The only difference is that
FLASH

it is faster and more flexible


ROMthan EEPROM.
▪ Can erase and write
data in blocks rather
than one byte at a
time.
Memory Hierarchy
Speed

• Measured by access time and data transfer rate.


• Access time: average time it takes a computer
to locate data and read it
millisecond = one-thousandth of a second
• Data transfer rate: amount of data that moves
per second
Memory operation
(read / write)
The processor needs to read data from memory and write data to
memory.
This requires the use of:

Bus Memory Memory Data


Register/
(address bus, Address
Memory Buffer
data bus and Register
control bus) (MAR) Register
(MDR/MBR)
Memory operation: Little Man Computer
Memory operation: Little Man Computer
Memory operation

Registers differ from memory:


• Used to hold a binary value temporarily for storage,
for manipulation, and/or for simple calculations.
• Unlike memory, where every address is just like every
other address each register wired within , each register
wired within the CPU serves a particular purpose.
• They are not addressed as a memory location would
be, but instead are manipulated directly by the CU
during execution of instructions.
Memory operation
BUS
Memory operation
MEMORY ADDRESS REGISTER
(MAR)
Holds the address in
the memory that is
to be “opened” for
data
Connected to a
decoder that
interprets the
address and
activate a single
address line into
the memory.
Memory operation
MEMORY DATA REGISTER (MDR)
Connected to every
cell in the memory
unit
Each bit of the MDR is
connected in a column
to the corresponding bit
of every location in
memory (but only a
single row of cells is
activated at any given
time, thus, only one
memory location is
addressed at any one
time)
A

B
Memory operation
READ OPERATION
CPU copies an address from some register in the CPU to the
memory address register (MAR)
At the same time, the CPU sends a message to the
memory unit that the memory transfer is retrieval (READ) from
memory
CPU then momentarily turns on the switch that
connects the MDR with the register, and transfer takes
place between MDR and memory
The data will then be transferred to the
appropriate register in the CPU

*Memory content will remain intact while the content of MDR will
be replaced by the new data from memory
Memory operation
WRITE OPERATION
CPU copies an address from some register in the CPU
to the memory address register (MAR)
At the same time, the CPU sends a message to the memory
unit that the memory transfer is store (WRITE) to memory.
CPU then momentarily turns on the switch that connects the
MDR with the register, and data transfer takes place between the
register and MDR.
The data will then be transferred from the MDR to the
memory location as specified in the MAR
Memory Capacity

The size of a memory is defined by the


address scheme

If an address scheme has m bits, the


maximum number of cells directly
addressable is 2^m.
If a memory has n cells, the cells will
have addresses 0 to n-1.
Eg: A memory with 32 cells would
have addresses 0 to 31
Memory Capacity
Memory Capacity
Eg: If the address scheme consists of 16 bits, the
size of the memory would be 64K
16
16 bit address = 2 => size of memory is 64K
Note:
◦1 byte = 8 bits
◦1 word = 16 to 64 bits
Memory Capacity
Eg Question:
Given a computer’s memory specification is 128MB
RAM. Calculate the:
◦ memory capacity in bytes
◦ address size
◦ largest address
(5 marks)
Memory Capacity
Eg Question:
Given a computer’s memory specification is 128MB
RAM. Calculate the:
1) memory capacity in bytes
2) address size
3) largest address
(5 marks)
Memory Capacity
Solution:
1) 1K = 1024 bytes = 2^10
1M = 1024 x 1024 = 2^10 x 2^10 = 2^20
Memory capacity = 128 * 1024 * 1024
= 134217728 bytes
(2 marks)
Memory Capacity
2) Address size
128 MB = 128 * 2^20
= 2^7 * 2^20
= 2^27
= 27 bits
(2 marks)
3) Largest address = 134217728 –1
= 134217727

(1 mark)
Byte Ordering
There are two types of bytes ordering

▪ Bytes are ▪ Bytes are

Little endian
Big endian

numbered from numbered from


left to right right to left
▪ Usually for ▪ Usually for
Motorola family Intel family
(6800)
(8086)
Byte Ordering
Big endian
Register Content
Given the following AX 22FF
contents in register
AX: MOV [8002],AX Register AX

22 FF
The following
instruction is Memory Address Content
executed:0 8002 22
8003 FF
Byte Ordering
Little endian
Given the following Register Content
contents in register 22 FF
AX: MOV [8002],AX
Register AX
The following 22 FF
instruction is Memory Address Content
executed: 8002 FF
8003 22

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