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Analog Part Theory

The document outlines two laboratory exercises focused on CMOS logic gates. Lab 02 involves constructing a 2-input CMOS NOR gate, verifying its functionality, measuring delays, and increasing drive strength, while Lab 03 focuses on constructing a schematic using a Boolean expression and analyzing delays. Both labs emphasize the importance of pull-up and pull-down networks in CMOS design and the issues related to contention and high impedance states.

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8 views2 pages

Analog Part Theory

The document outlines two laboratory exercises focused on CMOS logic gates. Lab 02 involves constructing a 2-input CMOS NOR gate, verifying its functionality, measuring delays, and increasing drive strength, while Lab 03 focuses on constructing a schematic using a Boolean expression and analyzing delays. Both labs emphasize the importance of pull-up and pull-down networks in CMOS design and the issues related to contention and high impedance states.

Uploaded by

rspratheeksha6876
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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LAB – 02:

2 – INPUT CMOS NOR GATE

Objective:
(a) Capture the Schematic of a 2 – input CMOS NOR Gate having similar delay as
that of CMOS Inverter computed in Lab – 01. Verify the functionality of the NOR
Gate and also find out the delay for all the four possible combinations of input
vectors. Tabulate the results. Increase the drive strength to 2X and 4X and tabulate
the results.
(b) Draw the layout of NAND with 𝑊𝑃 𝑊𝑁 =40 20 , use optimum layout methods.
Verify DRC and LVS, extract the parasitics and perform the post layout simulation,
compare the results with pre layout simulations. Record the observations.
Theory:
The pull up and pull down network consist of combination of transistor,where two
or more transistors in series are ON only if all of the series transistors are ON. Two
or more transistors in parallel are ON if any of the parallel transistors are ON. This
is illustrated in Figure 2 for nMOS and pMOS transistor pairs. By using
combinations of these constructions, CMOS combinational gates can be constructed.
In general, when we join a pull-up network to a pull-down network to form a logic
gate as shown in Figure 1, they both will attempt to exert a logic level at the output.
When both pull-up and pull-down are OFF, the high impedance or floating Z output
state results. This is of importance in multiplexers, memory elements, and tristate
bus drivers. The crowbarred (or contention) X level exists when both pull-up and
pull-down are simultaneously turned ON. Contention between the two networks
results in an indeterminate output level and dissipates static power. It is usually an
unwanted condition.
LAB – 03:
Construct the schematic using Boolean Expression using CMOS-Logic
(Y = AB+CD+E)’
Objective:
Verify the functionality of the expression find out the delay td for some combination
of input vectors.
Theory:
The pull up and pull down network consist of combination of transistor,where two
or more transistors in series are ON only if all of the series transistors are ON. Two
or more transistors in parallel are ON if any of the parallel transistors are ON. This
is illustrated in Figure 2 for nMOS and pMOS transistor pairs. By using
combinations of these constructions, CMOS combinational gates can be constructed.
In general, when we join a pull-up network to a pull-down network to form a logic
gate as shown in Figure 1, they both will attempt to exert a logic level at the output.
When both pull-up and pull-down are OFF, the high impedance or floating Z output
state results. This is of importance in multiplexers, memory elements, and tristate
bus drivers. The crowbarred (or contention) X level exists when both pull-up and
pull-down are simultaneously turned ON. Contention between the two networks
results in an indeterminate output level and dissipates static power. It is usually an
unwanted condition.

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