UNIT = Ui. = Embedded systems Data Transmission: In data transmission if the data ean be transmitted and received, itis a duplex transmission, Simplex: Data is transmitted in only one direction i.e. from TX to RX only one TX and one RX me i.e. (Wo TX's, two aif duplex: Data stansmitted in vo di itd in to drestions but only one w RX’s and one line ~~ Data is transmitted both ways at the same time ive. two TX's. to RX’s and two Full dupte lines A Protocol is a set of rules agreed by both the sender and receiver on © How the data is packed + How many bits constitute a character ‘+ When the data begins and ends Seriat Synchronous oan mae Data transter Protocol ‘Asynchronous rate (kbps) UART “Asynchronous peertoxpeer Fall-duptex 20 BC Synchronous Taliemaster | Fasduplex [3400 SPI Synchronous Tralismaster | Falleduplox | >1000 MICROWIRE | Synchronous wmasterlave | Fallduplex [> 625 TAWIRE Aaynchronous mastering Talkduplex [16 Baud Rate Concepts: Data transfer rate in serial communication is measured in terms of bits per second (bps). ‘This is also called as Baucl Rate. Baud Rate and bps ean be used inter changeably with respect 0 UART. Ex: The total number of bits gets transferred during 10 pages of text, each with 100 x 25 characters with 8 bits per character and I start & stop bit is: For each character a total number of bits are 10. The total number of bits is: 100 * 25 » 10=25,000 bits per page. For 10 pages of data it is required to transmit 2, 50,000 bits. Generally Page [3Embedded Systems SIETK baud rates of SCI are 1200, 2400, 4800, 9600, 19,200 etc, To transfer 2, 50,000 bits at a baud rate 0f 9600, we need: 250000/9600 = 26.04 seconds (27 seconds). Synchronous/Asynchronous Interfaces (like UART, SPI, I2C, and USB): ial communication protocols can be categorized as Synchronous and Asynchronous protocols. In synchronous communication, data is transmission and receiving is a continuous stream at a constant rate. Synchronous communication requires the clock of transmitting device and receiving device synchronized. In most of the systems, like ADC, audio codes, potentiometers, transmission and reception of data occurs with same frequency. Examples of synchronous communication are: I2C, SPI etc. In the case of asynchronous communication, the transmission of data requires no clock signal and data transfer occurs intermittently rather than steady stream. Handshake signals between the transmitter and receiver are important in asynchronous communications. Examples of asynchronous communication are Universal Asynchronous Receiver Transmitter (UART), USB, CAN etc. Synchronous and asynchronous communication protocols are well-defined standards and can be implemented in either hardware or software. In the early days of embedded systems, Software implementation of °C and SPI was common as well as a tedious work and used to take Jong programs. Gradually, most the microcontrollers started incorporating the standard communication protocols as hardware sores. This development in early 90s made job of the embedded software development easy for communication protocols. Microcontroller of our interest TM4C123 supports UART. CAN, SPI, I?C and USB protocols. The five (UART, CAN, SPI, I°C and USB) above mentioned communication protocols are available in most of the modern day microcontrollers. Before studying the implementation and t is required to understand basic standards, programming details of these protocols in TM4C123, features and applications. UART COMMUNICATION PROTOCOL In UART communication, two UARTs communicate directly with each other. The transmitting UART converts parallel data from a controlling device like a CPU into serial form, transmits it in serial to the receiving UART, which then converts the serial data back into parallel data for the receiving device. Only two wires are needed to transmit data between two UARTS. Data flows from the Tx pin of the transmitting UART to the Rx pin of the receiving UART: UARTs transmit data asynchronously, which means there is no clock signal to synchronize the output of bits from the transmitting UART to the sampling of bits by the receiving UART. Instead of a clock signal, the transmitting UART adds start and stop bits to the data packet being transferred. These bits define the beginning and end of the data packet so the receiving UART. knows when to start reading the bits. Page lsEmbedded Systems SIETK 1g bits at a specific When the receiving UART detects a start bit, it starts to read the incor frequency known as the baud rate, Baud rate is a measure of the speed of data transfer, expressed in bits per second (bps). Both UARTs must operate at about the same baud rate. The baud rate between the transmitting and receiving UARTs can only differ by about 10% before the timing of bits gets too far off. Both UARTs must be configured to transmit and receive the same data packet structure. Wires Used 2 ‘Maximum Speed ‘Any speed up to 115200 baud, usually 9690 baud synchronous or Asynchronous? Asynchronous Serial or Parallel? Serial Max # of Masters 1 |Max # of Slaves 1 HOW UART WORKS The UART that is going to transmit data receives the data from a data bus, The data bus is used to send data to the UART by another device like a CPU, memory, or microcontroller. Data is transferred from the data bus to the transmitting UART in parallel form. Afier the transmitting UART gets the parallel data from the data bus, it adds a start bit, a parity bit, and a stop bit, creating the data packet. Next, the data packet is output serially, bit by bit at the Tx pin. The receiving UART reads the data packet bit by bit at its Rx pin. The receiving UART then converts the data back into parallel form and removes the start bit, parity bit, and stop bits. Finally, the receiving UART transfers the data packet in parallel to the data bus on the receiving end.eth Embedded Systems DATA BUS UART 2 DATA BUS bito——>> if —— bt bit 1———> f= ———> bits bit 2———> —— pitz | pit 3 ——— > ‘ —> vite bit 4—> ee “s —> nits bits ———> = — it bit 6 ———> «| i bit 7 > # fh packet contains | start bit, 5109 data bits UART transmitted data is organized into packets. i, and 1 or 2 stop bits: (depending on the UART), an optional parity Packet ; Tit Ht start Fa iio2 ji 510.9 data bils | parit bit || Vibeed Malt PBEA| one | 218° PLE Data Frame START BIT (gh not transmitting data. To start the ion line from high to low for one clock begins reading the ‘The UART data transmission line is normally held at a hi transfer of data, the transmitting UART pulls the transmis cycle. When the receiving UART detects the high to low voltage transition, bits in the data frame at the frequency of the baud rate. DATA FRAME: ‘The data frame contains the actual data being transferred. It can be 5 bits to 9 bits long if'a parity bit is used. If no parity bit is used, the data frame can be 8 bits long. In most cases, the data is sent with the least significant bit first. PARITY Parity describes the evenness or oddness of a number. The parity bit is a way for the receiving UART to tell if any data has changed during transmission. Bits can be changed by electromagnetic radiation, mismatched baud rates, or long distance data transfers. After the receiving UART reads the data frame, it counts the number of bits with a value of | and checks if the total is an even or ‘odd number. Ifthe parity bit is a 0 (even parity), the | bits in the data frame should total to an even number. If the parity bit is a 1 (odd parity), the 1 bits in the data frame should total to an oddSIETK Embedded Systems number. When the parity bit matches the data, the UART knows that the transmis qrrors, But ifthe parity bit isa 0, and the total is odd: or the parity bit is a 1, and the total is even, the UART knows that bits in the data frame have changed, STOP BITS The Stop Bit, as the name suggests, but often only on bit is used. In order to e' high voltage (1). PS OF UART TRANSMISSION marks the end of the data packet. It is usually two bits long nd the transmission, the UART maintains the data line at e The transmitting UART receives data in parallel from the data bus: bit, parity bit, and the stop bit(s) to the data frame: The transmitting UART adds the start TRANSMITTING UART 3, The entire packet is sent serially from the transmitting UART to the receiving UART. The jving UART samples the data line atthe pre-configured baud rate: RECEIVING UART recei ind stop bit from the data frame: RECEIVING 4, The receiving UART discards the start bit, parity bit, CART TRANSMITTING UARTEmbedded systems SIETK 5. The receiving UART converts the serial data back 2 Mo parallel and transfers it to the data bus on the receiving end: RECEIVING UART DATA BUS ADVANTAGES AND DISADVANTAG! PS OF U ARTS ‘No communication protocol is perfect, but UARTs are pretty good at what they do. Here are some pros and cons to help you decide whether or not they fit the needs of your project: ADVANTAGES Only uses two wires No clock signal is necessary Has a parity bit to allow for error checking ‘The structure of the data packet can be changed as long as both sides are set up for it Gee Ge Ga) cl ‘Well documented and widely used method DISADVANTAGES D The size of the data frame is limited to a maximum of 9 bits 1 Doesn't support multiple slave or multiple master systems The baud rates of each UART must be within 10% of each other UART or Universal Asynchronous Receiver Transmitter is a dedicated hardware associated with serial communication, The hardware for UART can be a circuit integrated on the microcontroller na dedicated IC. This is contrast to SPI or 12C, which are just communication protocols. UART is one of the most simple and most commonly used Serial Communication techniques. Today, UARTT is being used in many applications like GPS Receivers, Bluetooth Modules, GSM and GPRS Modems, Wireless Communication Systems, RFID based applications ete.Embedded Systems SIETK SPI COMMUNICATION PROTOCOL \y different devices. For example, SD card Jess transmitter/receivers all use SPI to SPI is a common communication protocol used by im; modules, RFID card reader modules, and 2.4 GHz communicate with microcontrollers. can be transferred without interruption. Any One unique benefit of SPI is the fact that number of bits can be sent or received in a continuous stream. With 12C and UART, data is sent in packets, limited to a specific number of bits. Start and stop conditions define the beginning and end of each packet, so the data is interrupted during transmission. Devices communicating via SPI are in a master-slave relationship. The master is the controlling device (usually a microcontroller), while the slave (usually a sensor, display, or memory chip) takes instruction from the master. The simplest configuration of SPI is a single master, single slave system, but one master can control more than one slave (more on this below). Master MOSI (Master Output/Slave Input) ~ Line for the master to send data to the slave. MISO (Master Input/Slave Output) Line for the slave to send data to the master SCLK (Clock) — Line for the clock signal. SS/CS (Slave Select/Chip Select) — Line for the master to select which slave to send data to. 'Wires Used Maximum Speed Theoretically unlimited” Max # of SlavesEmbedded Systems SIETK «In practice, the number of slaves is limited by the load capacitance of the system which reduces the ability of the master to accurately switeh between voltage levels, HOW SPI WOR! THE CLOCK ‘The clock signal synchronizes the output of data bits from the slave. One bit of data is transferred in each clock cycle, so the speed o! the frequency of the clock signal, SPI communication is alway’ initiat master configures and generates the clock signal. master to the sampling of bits by the {fdata transfer is determined by ed by the master since the 1 where devices share a clock signal is known as synchronous. SPI is @ also asynchronous methods that don’t use a clock ‘Any communication protocol figured baud rate that dictates the speed and synchronous communication protocol. There are signal, For example, on, in both sides are set to a pre-cont smission. timing of data ‘The clock signal in SPI can be modified using the properties of clock polarity and clock phase. er to define when the bits are output and when they are sampled. ‘allow for bits to be output and sampled on either the rising ‘can be set for output and sampling to occur on either regardless of whether itis rising or falling. ‘These two properties work togeth Clock polarity can be set by the master to or falling edge of the clock cycle. Clock phase the first edge or second edge of the clock cycle, SLAVE SELECT The master can choose which slave it wants to talk to by the slave select line is kept at a high volt tiple slaves to be wired in parallel. If only’ setti a low voltage level. In the idle, age level. Multiple CS/SS pins may one CS/SS. non-transmitting state, be available on the master, which allows for mul ‘an be wired to the master by daisy-chaining pin is present, multiple slaves ¢ SLAVES MULTIPLE, MasterEmbedded Systems SiETK SPlcan be set up to operate with a single master and a single slave, and it ean be set up with multiple slaves controlled by a single master. There are two ways to connect multiple slaves to the master. If the master has multiple slave select pins, the slaves can be wired in parallel like this: fonly one slave select pin is available, the slaves can be daisy-chained like this: MOSI AND MISO The master sends data to the slave bit by bit, in serial through the MOSI line. The slave receives the data sent from the master at the MOSI pin. Data sent from the master to the slave is usually sent with the most significant bit first. The slave can also send data back to the master through the MISO line in serial. The data sent from the slave back to the master is usually sent with the least significant bit first. STEPS OF SPI DATA TRANSMISSION 1. The master outputs the clock signal: 2. The master switches the SS/CS pin to a low voltage state, which activates the slave:3. The master sends the data one bit at a time to the slave along the MOSI line. The slave reads the bits as they are received: 4. If a response is needed, the slave returns data one bit at a time to the master along the MISO line. ‘The master reads the bits as they are received: Ls First ADVA. 1. No start and stop bits, so the data can be streamed continuously without interruption 1D. No complicated slave addressing system like 12C D Higher data transfer rate than 12C (almost twice as fast) 1D Separate MISO and MOSI lines, so data can be sent and received at the same time DISADVANTAGES 1 Uses four wires (I2C and UARTs use two) CD No acknowledgement that the data has been successfully received (12C has this) D_No form of error checking like the parity bit in UART 2 Onlyallows fora single master. Page [42embeded systems 6S yell sem ote LOCOL > COMMU! ATION V1 Inter IC (i2e) (IIC) is important serial communication protocol in modern electronic systems. Philips invented this protocol in 1986. The objective of reducing the cost of production of television 1s to invent this protocol, IIC is a serial bus interface, can be remote control motivated Phil implemented in software, but most of the microcontrollers support 1IC by incorporating it as hard IP (Intellectual Property). HC can be used to interface microcontroller with RTC, EEPROM and different variety of sensors. IIC is used to interface chips on motherboard, generally between a processor chip and any peripheral which supports IIC. IIC is very reliable wireline communication protocol for an on board or short distances, 12C is a serial protocol for two-wire interface to connect low-speed devices like microcontrollers, EEPROMs, A/D and D/A converters, V/O interfaces and other similar peripherals in embedded systems See ee eae nea 12C combines the best features of SPl and UARTs. With I2C, you can connect multiple slaves 2c;combines the, best fealuies ol Sea toa single master (like SPI) and you can have multiple masters controlling single, or multiple slaves. This is really useful when you want to have more than one microcontroller logging data to a single memory card or displaying text to a single LCD. IIC protocol uses two wires for data transfer between devices: Serial Data Line (SDA) and Serial Clock Line (SCL). The reduction in number of pins in comparison with parallel data transfer is evident. This reduces the cost of production, package size and power consumption. IIC is also best so referred as two wire serial interfac suited protocol for battery operated devices. IIC is ————__—_____ MasterEmbedded Systems SIETK. MOSI AND MISO rhe master sends data to the slave bit by bit, in serial through the MOSI line, ‘The slave receives the data sent from the master at the MOSI pin. Data sent From the master to the slave is usually sent with MISO line in the most significant bit first.The slave ean also send data back to the master through the serial, The data sent from the slave back to the master is usually sent with the least significant bit First STEPS OF SPI DATA TRANSMISSION 1. The master outputs the clock signal: Master 2. The master switches the SS/CS pin to a low vollage state, which activates the slave: Slave 4. The master sends the data one bit at a time to the slave along the MOSI line. The slave reads the bits as they are received: Master 41000010 5. Ifa response is needed, the slave returns data one bit at a time to the master along the MISO line. The master reads the bits as they are received: MasterEmbedded Systems SUETK ADVANTAGES 1D Nosstart and stop bits, so the data can be streamed continuously without interruption 2 G_ No complicated slave addressing system like I2C 1D Higher data transfer rate than 12C (almost twice as fast) Q Separate MISO and MOS! lines, so data can be sent and received at the same time DISADVANTAGES O._ Uses four wires (12C and UARTs use two) G_ No acknowledgement that the data has been successfully received (12C has this) No form of error checking like the parity bit in UART Only allows for a single master. 12C COMMUNICATION PROTOCOL, Inter IC (i2c) (IC) is important serial communication protocol in modern electronic systems. Philips invented this protocol in 1986. The objective of reducing the cost of production of television is a serial bus interface, can be implemented remote control motivated Philips to invent this protocol. II in software, but most of the microcontrollers support 1C by incorporating it as hard IP (Intellectual Property). HC can be used to interface microcontroller with RTC, EEPROM and different variety of sensors, IIC is used to interface chips on motherboard, generally between a processor chip and any peripheral which supports IIC. IIC is very reliable wireline communication protocol for an on board or short distances. I2C is a serial protocol for 1wo-wire interface to connect low-speed devices like microcontrollers, EEPROMs, A/D and D/A converters, I/O interfaces and other similar peripherals in embedded systems IC combines the best features of SPI and UARTs. With 12C, you can connect multiple slaves toa single master (like SPI) and you can have multiple masters controlling single, or multiple slaves. This is really useful when you want to have more than one microcontroller logging data to a single memory card or displaying text to a single LCD. serial Data Line (SDA) and Serial | data transfer is evident. IIC protocol uses two wires for data transfer between device Clock Line (SCL). The reduction in number of pins in comparison with parallel Pare [15Embedded systems suETK This reduces the cost of production, package size and power consumption. IIC is also best suited protocol for SDA (Serial Data) ~ The line for the master and slave to send and receive data. SCL (Serial Clock) - The line that carries the clock signal 12C is a serial communication protocol, so data is transferred bit by bit along a single wire (the SDA line).Like SPI, I2C is synchronous, so the output of bits is synchronized to the sampling of bits by a ‘Wires Used ‘Maximum Speed Standard made= 100 kbps : Fast mode= 400 kbps High speed! mode= 3.4 Mbps i Ultra fast made= 5 Mbps ‘synchronous or Asynchronous? Syuchro Serial or Parallel? Serial | Max # of Masters Uniimited " ‘Max # of Slaves 1008Embedded Systems SIETK HOW I2c WORKS With 12C, data is transferred in messages. Messages are broken up into frames of data, Each message has an address frame that contains the binary address of the slave, and one or more data frames that contain the data being transmitted. The message also includes start and stop conditions, read/write bits, and ACK/NACK bits between each data frame: jon: The SDA line switches from a high voltage level to a low voltage level before the SCL. line Start Coné switches from high to low. Stop Condition: The SDA line switches from a low voltage level to a high voltage level after the SCL line switches from low to high. ‘Address Frame: A 7 of 10 bit sequence unique to each slave that identifies the slave when the master wants to talk to it A single bit specifying whether the master is sending data to the slave (low voltage Read/Write Bit level) or requesting data from it (high voltage level). ACKINACK Bit: Each frame in a message is followed by an acknowledge/no-acknowledge bit. If an address frame or data frame was successfully received, an ACK bit is returned to the sender from the receiving device. Message $$ start} {7-07.10 Bits, nace] 8 Bits, |nack] Stop] Dat Frame 1 Oata Fra , ' ° Stop Condition Address Frame Start Condition START ADDR RIW “ACK —_