GATE - 2024

ELECTRICAL ENGINEERING

Electrical

2001 - 2023
GATE Previous Year Questions

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 Contents

ANALOG ELECTRONICS
GATE Solved Questions

Sr. No. Topic Pages

1. Diode Circuit ................................................................................................ 1 - 12

2. BJT and FET Biasing ................................................................................... 13 - 27

3. Small Signal Analysis ................................................................................. 28 - 31

4. Frequency Response ................................................................................. 32 - 33

5. Operational Amplifier .................................................................................. 34 - 69

6. Feedback Amplifiers & Oscillators ............................................................ 70 - 75

7. Function Generator & 555 Timer ................................................................ 76 - 78

ANALOG Soil Mechanics & Foundation
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1
DIODE CIRCUIT
1. The cut-in voltage of both zener diode Dz and D shown in Figure is 0.7 V, while breakdown voltage of
the zener is 3.3 V and reverse break down of D is 5 V. The other parameters can be assumed to be
the same as those of an ideal diode. The values of the peak output voltage (V0) are
1k
I

1k
~ 10sint V0
=314 rad/sec

(a) 3.3 V in the positive half cycle and 1.4 V in the negative half cycle.
(b) 4 V in the positive half cycle and 5 V in the negative half cycle.
(c) 3.3 V in the both positive and negative half cycle.
(d) 4 V in the both positive and negative half cycle.
[1 Mark : GATE-2002]
2. The forward resistance of the diode shown in figure is 5 and the remaining parameters are same as
those of ideal diode. The DC component of the source current is
D

Vi ~ 45
Vi = Vm sin t
 = 314 rad/sec

Vm Vm Vm 2Vm
(a) (b) (c) (d)
50 50 2 100 2 50 2
[1 Mark : GATE-2002]
3. In the single phase diode bridge rectifier shown in figure, the load resistor is R = 50. The source
voltage is V = 200 sin t, where  = 2 × 50 rad/sec. The power dissipated in the load resistor R is

R
V ~ A
B

3200 400
(a) W (b) 400 W (c) W (d) 800 W
 
[2 Marks : GATE-2002]
 2 GATE Previous Solved Questions
4. A voltage signal 10 sin t is applied to the circuit with ideal diodes as shown in figure. The maximum
and minimum values of the output waveform of the circuit are respectively
10K
+
D1 D2
~ Vi 4V
4V
V0

10K
–
(a) +10V and –10V (b) +4V and –4V
(c) +7V and –4V (d) +4V and –7V
[2 Marks : GATE-2003]
5. The current through the zener diode in the given circuit is

2.2K
+
Iz
10V RL 3.5V
VZ = 3.3V
RZ = 100 –

(a) 33 mA (b) 3.3 mA (c) 2 mA (d) 0 mA

[1 Mark : GATE-2004]
6. Assuming that the diodes are ideal in figure the current in the diode D1 is

1K 1K

D2
5V D1
8V

(a) 8 mA (b) 5 mA (c) 0 mA (d) –3 mA

[2 Marks : GATE-2004]
7. Assume that D1 and D2 in figure are ideal diodes, the value of current I is

D1
2k
1mA
(DC) I
D2 2k

(a) 0 mA (b) 0.5 mA (c) 1 mA (d) 2 mA

[1 Mark : GATE-2005]
 ANALOG Soil Mechanics & Foundation
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8. What are the states of the three ideal diodes of the circuit shown in figure?
1
1

D2

1 5A
D1 D3
10V

(a) D1-ON, D2-OFF, D3-OFF (b) D1-OFF, D2-ON, D3-OFF

(c) D1-ON, D2-OFF, D3-ON (d) D1-OFF, D2-ON, D3-ON
[1 Mark : GATE-2006]
9. Assuming the diodes D1 and D2 of the circuit shown in the figure to be ideal ones, the transfer characteristics
of the circuit will be
D1 V0

2 D2
RL=
Vi

10V 5V

Vo Vo
10

10
(a) (b) 5

Vi Vi
10 5 10

Vo Vo

10

(c) (d)
5
Vi 10 Vi
5

[2 Marks : GATE-2006]
10. The equivalent circuits of a diode, during forward and reverse bias, is shown in figure.
0.7V
+ –  + –

– +  – +
10k

10sint ~ V0 10k
5V
 4 GATE Previous Solved Questions
If such diodes are used in the clipper circuit of figure given above, the output voltage (V0) of the circuit
will be

+5V +5.7V

(a)    t (b)    t
–5V –10V

10V +5.7V
(c)    t (d)    t
–5.7V –5V

[1 Mark : GATE-2008]
11. In the voltage doubler circuit shown in figure, the switch ‘S’ is closed at t = 0. Assuming diodes D1 &
D2 to be ideal, load resistance to be infinite and initial capacitor voltages to be zero, the steady state
voltage across capacitors C1 & C2 will be

t=0 Vc1 D2
+ –
S C1 +
5sint ~ D1 C2
–
Vc2 Rload

(a) VC1 = 10V, VC2 = 5V (b) VC1 = 10V, VC2 = –5V

(c) VC1 = 5V, VC2 = 10V (d) VC1 = 5V, VC2 = –10V
[2 Marks : GATE-2008]
12. The following circuit has a voltage source Vs as shown in the graph. The current through the circuit is
also shown

a b

VS +
– R 10k

15 1.5
10 1.0
Current (mA)
VS(volts)

5 0.5
0 0
-5 -0.5
-10 -1.0
-15 -1.5
0 100 200 300 400 0 100 200 300 400
Time (ms) Time (ms)
ANALOG Soil Mechanics & Foundation
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The element connected between ‘a’ and ‘b’ could be
(a) a b (b) a b

(c) a b (d)
a b
[1 Mark : GATE-2009]
13. Assuming that the diodes are ideal in the given circuit, the voltage V0 is
10k

D1 D2
10k
10V V0 15V
10k

(a) 4V (b) 5V (c) 7.5V (d) 12.12V

[1 Mark : GATE-2010]
14. A clipper circuit is shown below

1K

+
D
Vi ~ Vz =10V – Vo

5V

Assuming forward voltage drops of the diodes to be 0.7V, the input-output transfer characteristics of the
circuit is

V0 V0

10V
4.3V
(a) 4.3V (b)

Vi Vi
4.3V 4.3V

V0
V0
10V

5.7V -5.7V
(c) (d)
Vi
-0.7V 10V
Vi
0.7V 5.7V -5.7V

[2 Marks : GATE-2011]
 6 GATE Previous Solved Questions
15. The i-v characteristics of the diode in the circuit given below are

 v  0.7
 A, v  0.7V
i   500
0A, v  0.7V

The current in the circuit is

1k
i
+ +
10V V
– –

(a) 10 mA (b) 9.3 mA (c) 6.67 mA (d) 6.2 mA

[1 Mark : GATE-2012]
16. In the circuit shown below, the knee current of the ideal zener diode is 10 mA. To maintain 5 V across
RL, the minimum value of RL in  and the minimum power rating of the Zener diode in mW respectively
are

100

IL
10V

Vz = 5V RL

(a) 125 and 125 (b) 125 and 250 (c) 250 and 125 (d) 250 and 250
[2 Marks: GATE-2013]
17. A voltage 1000 sin t Volts is applied across YZ. Assuming ideal diodes, the voltage measured across
WX in Volts is

1k
W X
Y
Z

1k

(a) sin t (b) (sin t + |sin t|) / 2

(c) (sin t – |sin t|) / 2 (d) 0 for all t
[2 Marks : GATE-2013]
ANALOG Soil Mechanics & Foundation
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20
18. The sinusoidal ac source in the figure has an rms value of V. Considering all possible values of R ,
L
2
the minimum value of RS in  to avoid burnout of the Zener diode is

RS

20 V 5V RL
1/4W
2

[1 Mark : GATE-2014]
19. Assuming the diodes to be ideal in the figure, for the output to be clipped, the input voltage vi must be
outside the range

10k

vi 10k v
o

1V 2V

(a) –1 V to –2 V (b) –2 V to –4 V
(c) +1 V to –2 V (d) +2 V to –4 V
[2 Marks : GATE-2014]
20. A non-ideal diode is biased with a voltage of -00.03 V, and a diode current of I1 is measured. The thermal
voltage is 26m V and the ideality factor for the diode is 15/13. The voltage, in V, at which the measured
current increases to 1.5I1 is closest to
(A) -4.50 (B) -0.09
(C) -0.02 (D) -1.50
[2020 : 2 Marks]
21. Consider the diode circuit shown below. The diode, D, obeys the current-voltage characteristic

  V  
ID  IS  exp  D   1 , +
  nVT  
where n > 1, VT > 0, VD is the voltage across the diode and ID is the current through it. The circuit is
biasedso that voltage, V > 0 and current, l < 0. If you had to design this circuit to transfer maximum
power fromthe current source (I1) to a resistive load (not shown) at the output, what values R1 and R2
would you choose?
 8 GATE Previous Solved Questions

(A) Small R1 and small R2 (B) Large R1 and large R2

(C) Small R1 and large R2 (D) Large R1 and small R2
[2020 : 2 Marks]
22. In the circuit shown, a 5 V Zener diode is used to regulate the voltage across load R0. The input is an
unregulated DC voltage with a minimum value of 6 V and a maximum value of 8 V. The value of Rs
is 6W. The Zener diode has a maximum rated power dissipation of 2.5 W, Assuming the Zener diode
to beideal, the minimum value of R0 is__________W

[2021 : 1 Marks]
23. For the circuit shown below with ideal diodes, the output will be

(A) Vout = Vin for Vin > 0 (B) Vout = Vin for Vin < 0
(C) Vout = -Vin for Vin > 0 (D) Vout = -Vin for Vin < 0
[2022 : 1 Marks]
24. All the elements in the circuit shown in the following figure are ideal. Which of the following statements
is/are true?
ANALOG Soil Mechanics & Foundation
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(A) When switch S is ON, both D1 and D2 conducts and D3 is reverse biased.
(B) When switch S is ON, D1 conducts and both D2 and D3 are reverse biased.
(C) When switch S is OFF, D1 is reverse biased and both D2 and D3 conduct.
(D) When switch S is OFF, D1 conducts, D2 is reverse biased and D3 conducts
[2023 : 2 Marks]


 10 GATE Previous Solved Questions

SOLUTIONS
SOLUTIONS
1. Ans. (b) DC component is
During the positive half cycle, when Vi > 4 V
 Vm 
zener diode is replaced by V2 (ON) & D is   V 
replaced by 0.7 V IdC =  50    m 
    50 
1k
+ During negative half cycle,
3.3V Diode is reverse biased & is replaced by open
Vi ~ 0.7
1k Vo=4V circuit.

–
 I= 0

During the negative half cycle, 3. Ans. (b)

Zener diode becomes forward biased and PN The given circuit can be redrawn as
junction diode becomes reverse biased, then
1k
D1 D4
+
R
Vi ~ Vo ~ C D
1k
– D2 D3

Vi B
Vo =
2
= 5sin t R
Vomax = –5V V(t) ~ i(t)
2. Ans. (a)
During positive half cycle,
During the positive half cycle of the input then
Diode is forward biased & is replaced by 5
D1 & D3 – ON,  short circuit
5
D2 & D4 – Off  open circuit
V  t  200sin t
Vi ~ 45 i(t) = 
R 50
= 4 sin t Amp.
Vi During the negative half cycle of the input,
D1 & D3 – Off  open circuit
D2 & D4 – ON  short circuit

I
V(t) ~ R

Vi V t
i(t) = i(t) =  4sin t
50 R
Vm In full wave rectifier, power dissipated in the
i(t) = sin t
50 load resistor R is
ANALOG Soil Mechanics & Foundation
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V(t) 5. Ans. (c)
Given that Vo= 3.5V
t
0
VZ = 3.3V

i(t) Then zener diode offers Rz = 0.1 k of dynamic

resistance.
t
0 So, Vz + IzRz = 3.5
 3.5  3.3 
V t  i t  200 4 Iz =  R   2mA
P=  =   z 
2 2 2 2
6. Ans. (c)
P = 400W
In the circuit, D2 must be forward bias where
4. Ans. (d) D1 is first replaced by open circuit
For positive half cycle Apply Nodal analysis at node 1
(i) When Vi>4V, D2  ON, D1  OFF then
V1  5 V1  8
Vo = 4V  0
3
10 10
(ii) When Vi<4V, D1 & D2  OFF
1K V1 1K
 Vo = Vi
10k 1
+ 5V 8V

~ Vi 4V 4V Vo=4V
10k
– V1  5  V1  8 = 0
For negative half cycle, D1  ON, & D2OFF
2V1 = –3
10 k
V1 = –1.5V
+
 D1 is Reverse biased
I
Vi ~ 4V Vo
ID1 = 0
10 k
– 7. Ans. (a)
Vi – 10I + 4 – 10I = 0 The current always search the low resistance
path. D1-ON and D2-OFF.
 Vi  4  The I directed from N type to P–type of D2
I=   mA
 20  (D2–R.B) As D2 is reverse biased & is replaced
When Vi = –10V (maximum negative value) by open circuit.
 I =0
6
I= mA
20
Vo + 4 – 10I = 0
Vo = 10I – 4

 6 
= 10    4
 20 
= 3  4  Vo  7V
 12 GATE Previous Solved Questions
in parallel and voltage across them must be same.
D1 2k So that the value of output voltage from potential
1mA divider network is
(DC) I
D2 2k
 10  Vi
Vo = Vi    Vo  5sin t
 10  10  2
8. Ans. (a)
Therefore, voltage across diode is always less
In the given circuit, we can analyse that the
than 0 V, VD < 0 i.e., diode is reverse biased for
diodes
the given input.  V0 = 5 sint
1K
11. Ans. (d)
1K At t = 0, switch is closed and During the positive
D2 half cycle of input,
10V 1K 5A
D1 D1 is forward biased & D2 is reverse biased
‘C’, will charge upto +5V
D1 – ON VC1 = 5V

D2 – ON & + –
D3 – OFF then +
But no current flows through D2 because current –
~ Vi

always search the low resistance path (through

short circuit path D1) Therefore D2 also OFF During the negative half cycle of input voltage
9. Ans. (a) D1 – Off

When Vi =0, Dl-OFF and D2 also OFF D2 – ON

VC1
+ –
+ +
2 D2 +
Vi RL= Vo
Vi ~ –
C2
10V 5V
– –
Vo = 10V Apply KCL
Vi + VC2 + VC1 = 0
When Vi > 10V, D1–ON and D2–OFF VC2 =  Vi  VC1
+ + = –5 – 5
2 = –10V
Vi V0
10V  C2 will charge upto –10V
– –
12. Ans. (a)
Vo
During the positive half cycle, diode gets forward
10V biased then Vo = Vi.
During negative half cycle, diode gets reverse
Vi biased then Vo = 0
0 10V
13. Ans. (b)

10. Ans. (a)

Diode branch and 10k resistor are connected
ANALOG Soil Mechanics & Foundation
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1k
10K i
I V0 +
+
10V 10V v
10K – –

D1 is forward biased (ON),

D2 is reverse biased (Off). From (1) and (2)
10
I =  0.5mA 10  1000i  0.7 9.3
20  103 i= =  2i
500 500
V0 = 10  103 I
V0 = 5V 9.3
 3i =
500
14. Ans. (c)
During positive half cycle of the input. 3.1
i= A  6.2mA
500
When Vi < 5.7V, diode will be off and Zener
diode will not operate in breakdown region 16. Ans. (b)
Therefore, Vo = Vi
When Vi > 5.7V, diode will be ON, as it is on, Is
Vo = 5.7V
Rs =100
Zener diode will never operate in break down
region (i.e., it will always be in off state)
During negative half cycle of input, IL
Vs =10V Iz
Diode is reverse baised and Zener diode gets
+
forward biased when Vi  – 0.7V Vz = 5V RL
–
Vo

5.7V

–0.7V
Vi Given, knee current of zener diode,
0.7V 5.7V
Iz knee = 10 mA
Then, Vo = –0.7V Current supplied by source,
When Vi > –0.7V, diode will be off and zener
diode get reverse biased. Vs  Vz 10  5
Is =   50mA
Rs 100
Then, V0 = Vi
15. Ans. (d) Maximum load current
i – v characteristic of the diode : IL max = Is – Iz knee

 IL max = 50 – 10 = 40 mA
v  0.7
i= A, v  0.7V ...(1) Minimum load resistance,
500
From the given circuit, Loop equation : Vz 5
RL = I   125
min
L max 40  103
v = 10 – 1000 i, v  0.7V ...(2)
Maximum current in zener diode = Iz max
 14 GATE Previous Solved Questions
Maximum power dissipation of Zener diode 19. Ans. (b)
determines the minimum power rating of zener Case-I: Vi  – 4V
diode. Maximum current in Zener diode gives
maximum power dissipation in diode which occurs D2  ON
when load current is zero. Maximum current in D1  OFF
diode flows when load is open circuited.
So, Vo = –2V
Maximum current in Zener diode,
Case-II: –4 V  Vi  –2 V
Iz max = Is = 50 mA
Both the diodes will be OFF.
Maximum power dissipation in zener diode,
PD = Vz Iz Vo = V1'
max max

= 5 × 50 × 10–3 W Case–III: Vi  –2V

 PD max = 250 mW D1  ON
Minimum power rating of diode, D2  OFF
Pz = PD max = 250 mW Vo = –1 V
17. Ans. (d) 20. Ans. (B)
For positive half cycle
0.03
1k  
I1  I0 e15/1326 mV  1
W Y X  
Z As, VD = -ve‘1’ cannot be neglected in diode
current equation
1k

VWX = 0 I1  I0  e 30 mV/30 mV  1

For negative half cycle

1k  I0 [e 1  1]  0.64 I0 ...........(i)

W Y X
Z 1.5I1  I0 e VD /30 mV  1

1k - 1.5 ´ 0.64I0 = I0  e VD /30 mV  1

 
Short circuit condition
0.96  e VD 2 /30 mV  1
VWX = 0
1  0.96  eVD /30 mV  0.04  eVD /30 mC
18. Ans. 299 to 301
30 mV in(0.04)  VD  VD  0.96 V
IS  IZ + IL
21. Ans. (C)
1 20 – 5
 (Putting IL = 0 ) R2
20 Rs R1 , low, R 2 high : VD  V 
R1  R 2
 RS   300 
If R2 is large Vd (high). R1 is less VD = V
Hence, R Smin = 300 So for maximum power to deliver to load R1 is
small and R2 is large.
 ANALOG Soil Mechanics & Foundation
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22. Ans. (30)
To calculate R0 min, we must find IL max
Is min = Iz min + IL max

Vi min  Vz
 I z min  I L max
Rs
For ideal zener diode, Iz min = 0

Vi min  Vz 65
 I L max   I L max
Rs 6

1
IL max  A
6

Vz 5
R 0min    30 
I L max 1/ 6

23. Ans. (A)

Positive half cycle

D1 and D2 will be ON.

For Negative half cycle

D1 and D2 will be OFF.
 16 GATE Previous Solved Questions

The output waveform

So, V0 = Vin for Vin > 0

24. Ans. (B, C)

When switch on,

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D3 off by observation

Assume D1 and D2 off

KCL is being violated. Assume D1 on, D2 off

18 GATE Previous Solved Questions
\ D2 is reverse biased, \ our assumption is correct, i.e., D1 = ON and D2 = OFF and D3 = OFF.
When switch is off,

\ D1 is reverse biased, \ D1 is OFF

Switch off : D1 off, D2 and D3 on.


ANALOG Soil Mechanics & Foundation
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2
BJT AND FET BIASING
1. An N-channel JFET having a pinch-off voltage (Vp) of –5V shows a Transconductance (gm) of 1 mA/
V when the applied Gate to Source voltage (VGS) is –3V. Its maximum Transconductance (in mA/V) is
(a) 1.5 (b) 2.0 (c) 2.5 (d) 3.0
[2 Marks : GATE-2001]
2. For the circuit shown in Figure, IE = 1 mA,  = 99 and VBE = 0.7 V determine

15V

RF RC=1K
V0
IC
IB

17K R1
1K

(a) Current through R1 and RC

(b) The output voltage V0
(c) The value of RF
[5 Marks : GATE-2002]
3. In the circuit of figure shown, assume that the transistor has hfe = 99 and VBE = 0.7V. The value of
collector current IC of the transistor is approximately

3.3k
IC
33k
12V
4V 3.3k

(a) [3.3/3.3] mA (b) [3.3/(3.3+0.33)] mA

(c) [3.3/.33] mA (d) [3.3/(33+33)] mA
[1 Mark : GATE-2003]
4. For the n-channel enhancement MOSFET shown in figure, the threshold voltage Vth = 2V. The drain
current ID of the MOSFET is 4 mA when the drain resistance is 1k. If the value of RD is increased
to 4k, the drain current ID will become
 20 GATE Previous Solved Questions
10V
ID RD

(a) 2.8 mA (b) 2.0 mA (c) 1.4 mA (d) 1.0 mA

[2 Marks : GATE-2003]
5. In the circuit shown, the current gain ‘’ of the ideal transistor is 10. The operating point of the transistor
(VCE, Ic ) is
10
IC
0.5A
40V
15V

(a) (40V, 4A) (b) (0V, 4A) (c) (40V, 5A) (d) (15V, 4A)
[2 Marks : GATE-2003]
6. Two perfectly matched ‘Si’ transistors are connected as shown in figure. The value of the current I is
3V

1k
I

=1000 =1000
0.7 V

–5V
(a) 0 mA (b) 2.3 mA (c) 4.3 mA (d) 7.3 mA
[1 Mark : GATE-2004]
7. A bipolar junction transistor (BJT) is used as a power control switch by biasing it in the cutoff region
(OFF) or in the saturation region (ON state). In the ON state, for the BJT
(a) both Base-Emitter and Base-collector junction are reverse biased
(b) the Base-Emitter junction is reverse biased and Base-collector junction is forward biased
(c) the Base-Emitter junction is forward biased and Base-collector junction is reverse biased
(d) both Base-Emitter & Base-collector junctions are forward biased
[1 Mark : GATE-2004]
8. Assume that N-channel MOSFET shown in figure is ideal and its threshold voltage is 1V, the voltage Vab
between nodes ‘a’ and ‘b’is
ANALOG Soil Mechanics & Foundation
EE Engg.
21

1k 1k
a

D
G
10V 2k Vab
S
2V
b

(a) 5V (b) 2V (c) 1V (d) 0V

[1 Mark : GATE-2005]
9. The common emitter amplifier shown in the figure is biased using a 1mA ideal current source. The
approximate base current value is -
VCC=5V

RC=1k
Vout

 = 100
+
~ 1mA
Vin

(a) 0 A (b) 10 A (c) 100 A (d) 1000 A

[2 Marks : GATE-2005]
Common Data Question : 10 & 11
Assume that the threshold voltage of the N-channel MOSFET shown in figure is 0.75 V the output
characteristics of the MOSFET are also shown
VDD=5V
IDS=4(mA)
R=10k
4 VGS=4V
Vout
VGS=3V
3
+ VGS=2V
2
Vin=2mV ~
–
VGS=1V
2V 1
0
VDS(V)

10. The Transconductance of the MOSFET is

(a) 0.75 mS (b) 1 mS (c) 2 mS (d) 10 mS
[2 Marks : GATE-2005]
 22 GATE Previous Solved Questions
11. The voltage gain of the amplifier is
(a) +5 (b) –7.5 (c) +10 (d) –10
[2 Marks : GATE-2005]
12. Consider the circuit shown in figure. If the  of the transistor is 30 and ICBO is 20 nA and the input voltage
is 5V then the transistor would be operating in

+12V

2.21k

15 k
Vi
100 k Q

–12V

(a) Saturation region (b) Active region

(c) Break down region (d) Cut-off region
[2 Marks : GATE-2006]
13. The common emitter forward current gain of the transistor shown is F = 100. The transistor is operating
in

+10V

1k

270k
1k
10V

(a) Saturation region (b) Cut-off region

(c) Reverse active region (d) Forward active region
[1 Mark : GATE-2007]
14. The three terminal linear voltage regulator is connected to a 10 load resistor as shown, power dissipated
in the transistor?
+10V
1k
Vin RL=10
6.6V
Zener diode

(a) 0.6 W (b) 4.2 W (c) 2.4 W (d) 5.4 W

[1 Mark : GATE-2007]
 ANALOG Soil Mechanics & Foundation EE Engg.23
15. Two perfectly matched silicon transistors are connected as shown in the figure. Assuming the  of the
transistors to be very high and forward voltage drop to be 0.7V, the value of current I is

1k D +5V
I
Q1 Q2

–5V

(a) 0 mA (b) 3.6 mA (c) 4.3 mA (d) 5.7 mA

[2 Marks : GATE-2008]
16. The transistor circuit shown uses a ‘Si’ transistor with VBE = 0.7V, Ic  IE and a DC current gain of 100.
The value of V0 is

+10V

10k 50k

V0
100

(a) 4.65 V (b) 5 V (c) 6.3 V (d) 7.23 V

[2 Marks : GATE-2010]
17. The transistor is used in the circuit shown below has a  of 30 and ICBO is negligible.

15k 2.2k

1k
VBE= 0.7V
VCE(SAT)= 0.2V
D
VZ=5V

–12V

If the forward voltage drop of diode is 0.7V. Then the current through collector will be
(a) 168 mA (b) 108 mA (c) 20.54 mA (d) 5.36 mA
[2 Marks : GATE-2011]
 24 GATE Previous Solved Questions
18. The voltage gain AV of the circuit shown below is

13.7 Volts

12k

C
100k v0
C

10k =100
vi ~

(a) |AV|  200 (b) |AV|  100 (c) |Av|  20 (d) |AV|  10
[2 Marks : GATE-2012]

19. The transistor in the given circuit should always be in active region. Take VCE  sat   0.2V, VBE  0.7V .
The maximum value of RC in  which can be used, is

Rc

Rs=2k
=100 +
5V
+
5V

[1 Mark : GATE-2014]
20. In the given circuit, the silicon transistor has  = 75 and a collector voltage VC = 9 V. Then the ratio
of RB and RC is

15V

RC
RB
VC

[1 Mark : GATE-2015]
21. When a bipolar junction transistor is operating in the saturation mode, which one of the following statements
is TRUE about the state of its collector-base (CB) and the base-emitter (BE) junctions?
(a) The CB junctions is forward biased and the BE junction is reverse biased.
ANALOG Soil Mechanics & Foundation
EE Engg.
25
(b) The CB junctions is reverse biased and the BE junction is forward biased
(c) Both the collector base and base emitter junctions are forward biased
(d) Both the collector base and base emitter junctions are reverse biased
[1 Mark : GATE-2015]
22. In the following circuit, the transistor is in active mode and VC = 2V. To get VC = 4V, we replace RC
R 'C
with R 'C . Then the ratio R is
C

+10 V

RC
RB
VC

[1 Mark : GATE-2015]
23. For the circuit shown in the figure below, assume that diodes D1, D2 and D3 ideal.

The DC components of voltage v1 and v2, respectively are

(a) 0V and 1V (b) -0.5V and 0.5V
(c) 1V and 0.5V (d) 1V and 1V
[1 Mark : GATE-2017]
 26 GATE Previous Solved Questions
24. In the circuit shown in the figure, the bipolar junction transistor (BJT) has a current gain  = 100. The
base-emitter voltage drop is a constant, VBE = 0.7V. The value of the Thevenin equivalent resistance
resistance RTh (in ) as shown in the figure is_____(upto 2 decimal places)

[2 Marks : GATE-2018]
25. Given Vgs is the gate-source voltage, Vds is the drain source voltage, and Vth is the threshold voltage of an
enhancement type NMOS transistor, the conditions for transistor to be biased in saturation are
(a) Vgs < Vth ; Vds  Vgs - Vth (b) Vgs > Vth ; Vds  Vgs - Vth
(c) Vgs > Vth ; Vds  Vgs - Vth (d) Vgs < Vth ; Vds  Vgs - Vth
[1 Mark : GATE-2019]
26. The enhancement type MOSFET in the circuit below operates according to the square law. nCox = 100A/V2,
the threshold voltage (VT) is 500mV. Ignore channel length modulation. The output voltage Vout is

(a) 100mV (b) 500mV (c) 600mV (d) 2V

27. In the circuit shown in the figure, the bipolar junction transistor (BJT) has a current gain b = 100. The
base-emitter voltage drop is a constant, VBE = 0.7 V. The value of the Thevenin equivalent resistance
RTh (in W)as shown in the figure is _______ (upto 2 decimal places).
ANALOG Soil Mechanics & Foundation
EE Engg.
27

28. The enhancement type MOSFET in the circuit below operates according to the square law. mn Cox =
100mA/V2, the threshold voltage (VT) is 500 mV. Ignore channel length modulation. The output voltage
Vout is
[2 Marks : GATE-2019]

(A) 2 V (B) 500 mV

(C) 100mV (D) 600 mV
[2019 : 2 Marks]
29. Given, Vgs is the gate-source voltage, Vds is the drain source voltage, and Vth is the threshold voltage
ofan enhancement type NMOS transistor, the conditions for transistor to be biased in saturation are
(A) Vgs > Vth ; Vds £ Vgs - Vth
(B) Vgs < Vth ; Vds ³ Vgs - Vth
(C) Vgs > Vth ; Vds ³ Vgs - Vth
(D) Vgs < Vth ; Vds £ Vgs - Vth
[2019 : 1 Marks]
30. A common-source amplifier with a drain resistance, RD = 4.7 kW, is powered using a 10 V power supply.
Assuming that the transconductance, gm is 520 mA/V, the voltage gain of the amplifier is closest to:
(A) 1.22 (B) -1.22
(C) 2.44 (D) -2.44

[2020 : 1 Marks]
 28 GATE Previous Solved Questions

31. In the BJT circuit shown, beta of the PNP transistor is 100. Assume VBE = -0.7 V.
The voltage across Rc will be 5 V when R2 is _________kW. (Round off 2 decimal places).

32. The Zener diode in circuit has a breakdown voltage of 5 V. The current gain b of the transistor in the
active region in 99. Ignore base-emitter voltage drop VBE. The current through the 20 W resistance in
milliamperes is _________ (Round off to 2 decimal places).

[2020 : 1 Marks]


ANALOG Soil Mechanics & Foundation
EE Engg.
29

SOLUTIONS
SOLUTIONS
1. Ans. (c) Then I = I1  IB
Given that Vp = –5 V
= 100 A + 10 µA = 110 µA
gm = 1mA/V when VGS = –3 V
(a) Current passing then through R1 is 100 µA
2IDSS  VGS  Current passing through RC is IC + I
1
That gm = VP  VP  = 0.99 mA + 110 A
= 1.1 mA
2I DSS  3 
1 10 3 = 1   (b) The output voltage
5  5 
V0 = 15 – 103 (IC + I)
2 2
= IDSS   = 15  103 1.1  103 
5 5
= 13.9 Volts
25
IDSS = mA  V0  VB 
4
(c) RF =  
 I 
 The maximum transconductance occurs when
VGS = 0 13.9  1.7
=  110.91 k
2IDSS 2  25 110 106
gm = 
VP  5  4
3. Ans. (b)
gm = 2.5 mA/V
12V
2. Solution :
3.3K
Given that IE = 1 mA
33K
   IB + IC
 I  0.99mA
V
IC =  BE
= –
 1   4V 0.7
3.3K

IC
IB =  10A
 Apply KVL to Base-emitter loop
15V
4  33  103 I B  0.7  3.3  103 I E  0
(IC +I)
RF 1k 3.3  33  103 I B  3.3  103 1    I B
V0 [IE = (1 + )IB]
I IC
B
VB 3.3
IB + IB =
I1 VBE –  33  330   103
R1 IE
17k 3.3
1k  IC =  I B   99
 33  330   103
Potential at Base is 3.3
= mA
VB – VBE – IE × l03 = 0  33  330 
 
VB = 0.7 + 1 = 1.7 Volts  99 
VB 3.3
Then I1 =  100A mA
17K IC =
3.33  0.33
 30 GATE Previous Solved Questions
4. Ans. (c)  ID = 2.84 (or) 1.407mA
10V For N-channel E–MOSFET VGS > Vth
ID
VGS = 10  4  2.84  = –1.372 volts
RD
VDS and VGS = 10  4 1.407 
= 4.372 volts
 ID = 1.407 mA
VGS is always positive. So, ID = 1.407 mA.
Given that Vth = 2V,
5. Ans. (b)
VD = VG , VS  0
Given that IB = 0.5 Amp.
 VDS = VGS Assume transistor is in Active,
We know ID = 4 mA, RD = 1 k IC = IB =5 Amp

10 – IDRD – VDS = 0 then VCE = 40 – 10 × 5 = –10V

As VCE is negative, Q operated in saturation.
VDS = 10  4  6V
 VCE = 0V then 40  10Ic  VCE  0
VDS = 6V  VGS
IC = 4 Amp.
2
Then ID = k  VGS  Vth  6. Ans. (c)

2 3V
4 = k   6  2 IR
1 1k I
 k=mA / V 2
4 IC1 I'
But, when RD changes to 4k then  = 1000
IB1 IB2
VGS = VDS = 10 – 41D
(ID in mA)
–5V
2
Then, ID = k  VGS  VGS  t n  
This is a current mirror circuit. So,
1 2 1 2
ID = 10  4ID  2 = 8  4I D  I C1  I & I B1  I B 2  I B
4 4
IR = IC1  2IB
ID = 4  2  I D 2
2IC1
= IC1 
ID = 4  I 2D  4  4I D  

IR = IC1 1  2 /  
 I2D  4.25I D  4  0
Apply KVL from ground to –5 V,
2
ID =
4.25   4.25   16 0 – 103 IR – 0.7 + 5 = 0
2 IR = 4.3 mA
4.25  1.436
ID =
2 IR 4.3  103
IC1 = 
= 2.843mA (or) 1.407mA 1 2 /  1.002
ANALOG Soil Mechanics & Foundation
EE Engg.
31
= 4.2914mA G Id
+ +
IC1 = I = 4.3 mA
7. Ans. (d) ~V i
Vgs gm Vgs rd 10k V0
IL
Base-Emitter Base-Collector Operations
–
Junction Junction of Mode –
S
Reverse Bias Reverse Bias Cutoff (OFF) Current through 10k, IL = –ID = –gmVgs
Reverse Bias Forward Bias Inverse Active V0 = 10 × l03IL
(Attenuator) = –104 × Id
Forward Bias Reverse Bias Active (Amplifier) V0 = –104 × 10–3 Vi
Forward Bias Forward Bias Saturation(ON) V0
8. Ans. (d) Vi = A V  10

VG  2V  12. Ans. (b)

VGS = 2V V  0V  Assume that the transistor in the active region.
 S 
Vth = 1V To calculate base current
12V
VDS  sat  = VGS  Vth  1V 2.2k
Due to 10V, VDS > VDS (sat), then N-channel Rth
MOSFET will operate in saturation, high current
+
flows from drain to source so that it acts as a 0.7
short circuit, Vab = 0V –
Vth
9. Ans. (b)
Given that IE = 1 mA
15k
 5V Vth
IC  1   I E  0.99mA
I 100k
IC
IB =  9.909A
 –12V
 IB  10A
10. Ans. (b)  5  12 
I=  
 115  103 
 I D 
gm =  V  Vth  100  103 I  12  0
 GS  VDS  constant

 2  1  103  17 
=  1mS Vth =  12  100  
 2  1  115 
 gm = 1mS Vth = 2.783 Volts
11. Ans. (d) 15  100
Rth =
The small signal model of the given amp is 115
Rth = 13.043k

Vth  0.7
IB =  0.1597mA
R th
 32 GATE Previous Solved Questions
IC =  I B  4.79mA = 0.7 mA

Then apply KVL in collector emitter loop IL = I E  I1  IE  IL  I1

12 – 2.2(4.79) – VCE = 0 = 0.59  0.7  103 = 0.5893 Amp.
 1.46 Volts  J C  R.B  Assume that IE  Ic = 0.5893 Amp.

So 0.2V  VCE  12V J E  F.B 
Therefore, the power dissipated in the transistor
 Transistor will be in Active region. is
13. Ans. (d) PD= VCE × Ic
Apply KVL from 10V to Ground through base- = 4.1 × 0.5893 = 2.416 W
emitter terminals
15. Ans. (c)
10  103 IE  0.7  270  103 I B  0 This is a current mirror circuit, since  is very
large,
103 1    IB  270  103 IB  9.3
IC1  I C2 = IC  I E1  I E2  I E
9.3
IB =  25.06A
 270  101  103 & I B1  I B2  I B
IC = 2.506mA The potential at base of the transistor
 IE = 2.5318mA VB – 0.7 + 5 = 0  VB = –4.3 Volt
Apply KVL from 10V to ground through collector  D is Forward biased
to emitter terminals
Current passing through diode is
10 – 103IE – VCE –103 IC = 0
0  VB
VCE = 10  103  IC  I E  I=  4.3mA
1k
= 10 – 103 × 5.0378 × 10–3 16. Ans. (a)
= 4.962 volts Apply KVL from 10V to Ground through base
Transistor will be in forward active mode. emitter terminals
14. Ans. (c) 10 – 104 IB – VBE – 100IE = 0
IC IE E 10 – 0.7 = 104IB + 100IC
+
– IC

IB 0.7V IL = 10  100IC
+ 
x
Vin I1 1K 9.3 = 100I C  100I C
10
6.6V
9.3
 IC =  46.5mA
200
–
V0 = 100IC
VE + 0.7 – 6.6 = 0
 V0 = 4.65 Volts
VE = 5.9 Volts then
17. Ans. (d)
VE
IL = = 0.59 Amp Assume that the transistor operates in active
10
region then,
Apply KVL, Vin – VCE – VE = 0
Apply KVL to base – emitter loop.
VCE = 10 – 5.9 = 4.1 Volt
5 – 103IB – 0.7 – 0.7 + 12 = 0
Vx  VE 6.6  5.9 IB = 15.6 mA
I1 = 3

10 103
IC = 0.468 Amp.
ANALOG Soil Mechanics & Foundation
EE Engg.
33
Apply KVL to Collector – emitter loop Consider the circuit shown in figure
3
0 – 2.2 × 10 IC – VCE + 12 = 0 15V
VCE = 2200IC – 12 IE=IB+IC
RC
= 1017.6 Volts
RB
As 0 < VCE < VCC, Not Satisfying this Condition. VC = 9V
So, Transistor is operating in Saturation region; IB
IC
VCE(sat) = 0.2 V
Apply KVL, 0 – 2.2IC – 0.2 + 12 = 0 +
0.7V –
IC = 5.36 mA
18. Ans. (d)
Voltage – Shunt (or) VC = 9 V
Shunt – Shunt Negative Feedback (See figure) 15 – 9
So, R C = IE
Rf
V0 6
RS R C = IE
Rf = 100K
IS RS = 10K 9  0.7
and R B = IB
VS ~
8.3
So, R B = IB
V 
V0 =  Is  R f =   s  R f IE 6 RB
 Rs  So, =
IB R C  8.3
V0
AV = V = voltage gain RB  6
s ( + 1) =
R C  8.3
Rf
=  RB
Rs
AV = –10 R C = 105.13
21. Ans. (c)
A V  10
In saturation mode, both the collector base and
19. Ans. 22 to 23 base emitter junctions are forward biased
In input loop: 22. Ans. 0.75
5  0.7 4.3 +10 V
Ib = 2 k = 2 k = 2.15 mA
IB IC
So, Ic =  × Ib
RC
= 100 × 2.15 mA
RB
Now KVL in output loop: VC
Vce = 5 – 0.215 RC
For active region Vce > 0.2 V
 0.215 RC < 5 – 0.2
4.8
 Rc, min =  22.32 Apply KVL
0.215
20. Ans. 105.13
 34 GATE Previous Solved Questions
ie = 10ib
10  0.75  9.3
IB = RB RB 10 - 10ib - 101ib = 0
10  VC 111ib = 10
IC = BIB  RB
RC
10
If we replace RC by R 'C ib = =0.09mA
111×1000
IB is constant and hence IC is also constant ib = 101  ib = 9.09mA
10  2 10  4 Short circuit current
R 'C = RC
R 'C 6 3
  0.75
RC = 8 4
23. Ans. (b)
For high wave rectifier
+
–
V
VDC = m
π +
–
V1 = Vdc for positive pulse and +Vdc for negative
pulse
There will be no curretn in 1K
π  π 1
= +  -  = -1=-0.5V hence iN = ie
2π  π  2
Also using KVL in output Loop
π 10.7 - 10ib - 0.7 = 0
V2 = +0=0.5V
2π
ib = 1mA
24. Ans. (90) ie = 101  ib = 101mA

9.09
Rth = =90
101×10-3
25. Ans. (b)

+ For saturation region

–
Vgs > Vth
+
–
and
Vds  Vgs - Vth

VOC 26. Ans. (c)

Rth = ISC VS = 0V and VD = Vout

The open circuit voltage across ab VDS = Vout

= Vm Vgs = Vg - VS = Vout
Using KVL in output Loop Vth = 0.5
10.7 - 10 ib - 0.7 - 1  ie = 0 VdS (sat) = Vgs - Vth
given  = 100 = V0 - 0.5
ANALOG Soil Mechanics & Foundation
EE Engg.
35
As, VdS > VdS (sat)
10 k
R Th  1k | |
The transistor in saturation region 1 
= 1 kW | | 99.0099 = 90.09 W
1 w 2
I D = μ n C ox    VCS -VT  28. Ans. (D)
2 L
 

1 2
5×10-6 = ×100×10-6 ×10  VGS -VT 
2
2
 VGS -VT   102

VGS - VT = 10-1
VGS = VT + 0.1
VGS = 600mV

27. Ans. (90.09)

As, VDS = VGS

MOSFET is in saturation,

1 W
ID   n Cax   (VGS  VT )2
2  L

1
5  106   100  106  10 (VGS  0.5) 2
2
VGS = 0.6 V
V0 = 600 mV
29. Ans. (C)
To calculate RTh D.C. voltage should be short- For NMOS transistor to be in saturation the
circuited. condition will be
Vgs  Vth and Vds  Vgs  Vth
30. Ans. (D)
Given data: RD = 4.7 kW,gm = 520 mA/V
Voltage gain of CS amplifier
= -gmRD
= - 520 mAV ´ 4.7 kW = -2.44
31. Ans. (17.06)
 36 GATE Previous Solved Questions

5V
IC   1.515 mA
3.3k
IE = 1.53 mA
IB = 0.0151 mA
- 12 + 1.2k ´ 1.53 m + 0.7 + VB = 0
VB = 9.464 V

12  VB 12  9.464
Ix    0.539 mA
4.7k 4.7k
Ix + IB = Iy
Iy = 0.5396 + 0.0151
Iy = 0.5546 mA
VB = 0.5546 m ´ R2 = 9.464
R2 = 17.06 kW
32. Ans. (250)

Assume Zener off

ANALOG Soil Mechanics & Foundation
EE Engg.
37

25 = 7 K ´ IB + IE (10W + 20W)
25 = 7 K ´ IB + (1 + b) IB (30W)
25 = 7 K ´ IB + 3000W ´ IB
25 = 7 K ´ IB + 3K IB
25 = 10K ´ IB

25
IB   2.5mA
10K
IE = (1 + b) IB = (1 + 99) ´ 2.5 mA
= 100 ´ 2.5 mA = 250 mA
VX = 0.25 ´ 20 = 5 V; VB = 25 – (2.5 ´ 7) = 7.5 V
 VZ  7.5  5,  V2  OFF


 38 GATE Previous Solved Questions

3
SMALL SIGNAL ANALYSIS
1. In the single stage transistor amplifier circuit shown in figure, the capacitor CE is removed then the ac
small signal midband voltage gain of the amplifier

VCC
RC
R1
V0
C1
C2
+

Vi R2 RE CE
–

(a) Increases (b) Decreases (c) Is unaffected (d) Drops to zero

[ 1 Mark : GATE-2001]
2. The transistor in the amplifier circuit shown in figure is biased at IE = 1 mA. Use

 kT 
vT     26mv, o  200 ; rb  0 and ro  
 q 

VCC

RC=1K
V0
25K
Vi

 RE CE

 Vo 
(a) Determine the AC small signal midband voltage gain  V  of the circuit
 i
(b) Determine the required value of CE for the circuit to have a lower cutoff frequency of 10Hz.
[ 5 Marks : GATE-2001]
3. The transconductance gm of the transistor shown in figure is 10 mS. The value of input resistance Rin
is
ANALOG Soil Mechanics & Foundation
EE Engg.
39
VCC

RC
10K
V0
C= C=
VS
=50
10K
1K C=

(a) 10 k (b) 8.3 k (c) 5 k (d) 2.5 k

[ 2 Marks : GATE-2004]
4. The magnitude of the mid-band voltage gain of the circuit shown in figure is (assuming hfe transistor to
be 100)

+VCC

10K
C
vo
C 10k
hfe = 100

vi
1k C

(a) 1 (b) 10 (c) 20 (d) 100

[1 Mark : GATE-2014]


 40 GATE Previous Solved Questions
SOLUTIONS
SOLUTIONS
1. Ans. (b) 2. Solution :
(a) The small signal model is
The small signal approximate model of the given
circuit is
With CE

Ib +
hie
hfe Ib
Vi RB Vbe RC Vo

RB = R1 | | R 2
V0 =  h fe I b  R c
Vbe 26mV
Zi = I  h ie , A1   h fe re =
b IE
re = 26 
Vo  I CR C h fe R C
AV = V  h I  h r =  re = 5.2 k
be ie b ie
Vi = I b  25  103   re 
Without CE :
= Ib  30.2   103
IC
Ib V0  h fe R c
hie + Av = =  R  r 
Vi s e
hfe Ib
Vi RB Vbe RC Vo 100  1000
Av =  A V  6.62
Re (1+ hfe)Ib 30.2  10
(b) The small signal model simplified model is
–
Rs(+1)
re
Vbe Ib  h ie   1  h fe  R eIb IE E
Zi = 
Ib Ib
RE CE

Zi = h ie  1  h fe  R e  Zi increase
Re

Vo  Rs 
AV = V Re = R E ||  re 
be  1   

100  150.37
h fe R C =  60.06
= h  1 h R 250.37
ie  ie  e
 r  R S  26  124.37  150.37 
 e 1   
 AC Voltage gain decreases.
ANALOG Soil Mechanics & Foundation
EE Engg.
41
1 = 5 k
fL = 2 R C
e E Rin = RB | | r
1
CE =  265F = 0.265 mF = 2.5 k
2R e f L
4. Ans. (d)
3. Ans. (d)
AC model
Given that gm = 10 mS
Vo
gm r =   50 10k

50 Vi hfeIB 10 k
 r = 3
 5k
10  10

Zi = 10 k

Zi = 10 k
Mid band voltage gain

A IR L
Av = Zi

–h fe R L
RB = R1 | | R2 Av = Zi

–100  10k
= = –100
10k
|AV| = 100


 42 GATE Previous Solved Questions

4
FREQUENCY RESPONSE
1. The typical frequency response of a two-stage direct coupled voltage amplifier is as shown in figure

|Gain|
(a)
Frequency

|Gain|
(b)
Frequency

|Gain|
(c)
Frequency

|Gain|
(d)
Frequency

[2 Marks : GATE-2005]
2. The op-amp shown in the figure is ideal. The input impedance Vin/iin is given by

R1 R2
(A) Z R (B)  Z R
2 1

R2
(C) X (D)  Z R  R
1 2

[2018 : 1 Marks]
 ANALOG Soil Mechanics & Foundation
EE Engg. 43
3. In the circuit below, the operational amplifier is ideal. If V1 = 10 mV and V2 = 50 mV, the output voltage
(Vout) is

(A) 400 mV (B) 500 mV

(C) 600 mV (D) 100 mV
[2019 : 2 Marks]
4. The steady state output (l/out), of the circuit shown below, will

(A) saturate to +VDD (B) saturate to VEE

(C) become equal to 0.1 V (D) become equal to –0.1 V
[2022 : 1 Marks]
5. The current gain (Iout/ Iin) in the circuit with an ideal current amplifier given below is
 44 GATE Previous Solved Questions

Cf  Cf
(A) C (B) C
c c

Cc  Cc
(C) C (D) C
f f

[2022 : 2 Marks]
6. The output impedance of a non-ideal operational amplifier is denoted by Zout. The variation in the
magnitude of Zout with increasing frequency, f, in the circuit shown below, is best represented by

(A) (B)

(C) (D)

[2022 : 2 Marks]
7. consider the OP AMP based circuit shown in the figure. Ignore the conduction drops of diodes D1 and
D2.All the components are ideal and the breakdown voltage of the Zener is 5 V. Which of the following
statements is true?
ANALOG Soil Mechanics & Foundation
EE Engg.
45

(A) The maximum and minimum values of the output voltage V0 are + 15 V and –10 V, respectively.
(B) The maximum and minimum values of the output voltage V0 are +5 V and –15 V, resp.
(C) The maximum and minimum values of the output voltage V0 +10V and –5V, resp..
(D) The maximum and minimum values of the output voltage V0 are +5 V and –10 V, resp..

[2023 : 2 Marks]


 46 GATE Previous Solved Questions
SOLUTIONS
SOLUTIONSSOLUTIONSSOLUTIONSSOLUTIONSSOLUTIONSSOLUTIONS
SOLUTIONS
1. Ans. (b)
4. Ans. (B)
The direct coupled (or) DC coupled amplifier, it
KCL at Node (i)
provides a gain at low frequency and for a two-
I1 + I2 = 0
stage direct coupled voltage amplifier, it provides
a gain at zero frequency. V1  0 d
 C1  (Vout  0)  0
2. Ans. (B) R1 dt
According to virtual ground,
VA = VB = Vin dVout V
 i
dt R 1C1
At node A,
Vin  V0
 iin ……… (i)
Z

 1 1  V  R  R2 
Vin     0 Vin  1   R 1  V0
 R 2 R1  R1  R1 R 2 
SOLUTIONS
SOLUTIONS
 R  R2 
V0  Vin   1  ...........(ii)
 R2 

 R  R2  VA = 0 Vout
Vin  V0 Vin  Vin   1 
 iin  R2   i
Z in 1
Z Vout    Vi dt V- = 0.1 V
R1C1 I

Vin  R 1  R 2  Vin  R 2  R 1  R 2 
1  Z  Z 1 0.1
iin  R2  iin  R2  Vout    0.1  dt   t
R 1C1 R 1C1
Vin R Vout = - k ´ t
  Z. 2
i in R1 The output will be constant i.e., -VEE.
3. Ans. (B) 5. Ans. (C)

R2 100k
V0  (V2  V1 )  (50mV  10 mV) 1 I
R1 10k Vx   Iin  dt  in  t
Cf Cf
= 10 (40 mV) = 400 mV
ANALOG Soil Mechanics & Foundation
EE Engg.
47

dVx dI  I
Iout  CC  Cc   in  t   Cc  in
dt dt  Cf  Cf

I out Cc

Iin Cf
6. Ans. (C)
Analysis:
It is a voltage series feedback.

1 I
Vx   Iin  dt  in  t
Cf Cf

dVx dI  I
Iout  CC  Cc   in  t   Cc  in
dt dt  Cf  Cf

I out Cc

Iin Cf
7. Ans. (C)
Analysis:
It is a voltage series feedback.
Voltage is a shunt connection, Zout feedback,
Z0 Z
Zof   0 [Buffer,   1]
1 A 1 A
 48 GATE Previous Solved Questions

5
OPERATIONAL AMPLIFIER
1. For the oscillator circuit shown in figure, the expression for the time period of oscillations can be given
by (where  = RC)

C R
– Vo
+
R

(a)  ln 3 (b) 2 ln 3 (c)  ln 2 (d) 2 ln 2

[2 Marks : GATE-2001]
2. An op-amp having a slew rate of 62.8 V/ sec is connected in a voltage follower configuration. If the
maximum amplitude of the input sinusoidal is 10 Volts. Then the minimum frequency at which the slew
rate limited distortion would set in at the output is
(a) 1 MHz (b) 6.28 MHz (c) 10 MHz (d) 62.8 MHz
[2 Marks : GATE-2001]
3. For the op-amp circuit shown in figure, determine the output voltage Vo. Assume that the op-amps are
ideal

2k 4k 8k

1V
1k
–
–
+ Vo
–1V +

3k
1k

[5 Marks : GATE-2001]
4. A simple active filter as shown in figure. Assume ideal op-amp Derive the transfer function Vo/Vi of the
circuit and state the type of filter (ie., high-pass, low-pass, band-pass or band-reject). Determine the
required values of R1, R2 and C in order for the filter to have a Cutoff (or) 3-dB frequency of 1kHz, a
high frequency input resistance of 100 k and a high frequency gain magnitude of 10.
R2

R1 C If
–
Vi + V0

[5 Marks : GATE-2001]
 ANALOG Soil Mechanics & Foundation
EE Engg. 49
5. The output voltage (V0) of the Schmitt trigger shown in figure swings between +15V and –15V. Assume
that the operational amplifier is ideal. The output will change from +15V to –15V when the instantaneous
value of the input sine wave is
100
Vi=10sint –
+ Vo
10

3k

2V
(a) 5 V in the positive slope only
(b) 5 V in the negative slope only
(c) 5 V in the positive and negative slopes
(d) 3 V in the positive and negative slopes
[2 Marks : GATE-2002]
6. For the circuit shown in figure with an ideal op-amp, the maximum phase shift of the output V0 with
reference to the input Vin is
R

R
–
Vin V0
+
R
C

(a) 0º (b) –90º (c) +90º (d) ±180º

[1 Mark : GATE-2003]
7. Assuming the operational amplifier to be ideal. The gain V0/Vi for the circuit shown in figure
10k 10k

1k

1k
Vi
Vo
+

(a) –1 (b) 20 (c) –100 (d) –120

[2 Marks : GATE-2003]
8. The input resistance RIN (= Vx/Ix) of the circuit in the figure is
 50 GATE Previous Solved Questions

10K 100K

–
V0
+
VX
IX 1M

(a) 100 k (b) 100 k (c) 1 M (d) –1 M

[2 Marks : GATE-2004]
9. In the Schmitt trigger circuit shown in figure, if VCE (sat) = 0.1V, the output logic low level (VOL) is
+5V

200
V
Vi=0 Q1 Q2

1k
I=1.25mA

(a) 1.25 V (b) 1.35 V (c) 2.5 V (d) 5.0 V

[2 Marks : GATE-2004]
10. In the active filter circuit shown in figure if Q = 1, a pair of poles will be realized with 0 equal to

R1=200k

1nF 1nF
R2

–
+

(a) 10000rad/sec (b) 100 rad/sec (c) 10 rad/sec (d) 1 rad/sec

[2 Marks : GATE-2004]
11. Consider the inverting amplifier using an ideal operational amplifier shown in figure. The designer wishes
to realize the input resistance seen by the small signal source to be as large as possible, while keeping
the voltage gain between –10 and –25. The upper limit on RF is 1M. The Value of R1 should be
ANALOG Soil Mechanics & Foundation
EE Engg.
51
Rf

Vin –
R1 Vout
+

(a) infinity (b) 1 M (c) 100 k (d) 40 k

[2 Marks : GATE-2005]
12. In the given figure., if the input is a sinusoidal signal, the output will appear as shown

+V
R
–

Vin +
+
0 t R RL Vout
–V
–

Vout
Vout

t
(a) (b)
t

Vout
Vout
(c) (d)
t
t

[2 Marks : GATE-2005]
13. For given sinusoidal input voltage, the voltage waveform at point P of the clamper circuit shown in figure
will be

Vin +12V
–
C RL
~ Vin + P
–12V
 52 GATE Previous Solved Questions

(a) (b) 12V

-0.7V

+0.7V
(c) (d)
-12V

[1 Mark : GATE-2006]
14. A relaxation oscillator is made using op-amp as shown in figure. The supply Voltage of the op-amp are
± 12 the voltage waveform at point ‘P’ will be
R1

R2
C
–
+
2k

P 10k

10k

6 10

(a) –10 (b) –6

6 10

(c) (d)
–10 –6

[2 Marks : GATE-2006]
15. The circuit shown in figure is

+ R1
+
V R2 –
Load

r
ANALOG Soil Mechanics & Foundation
EE Engg.
53

rV
(a) A voltage source with voltage R || R
1 2

r | | R2
(b) A voltage source with voltage V
R1
r | | R2 V
(c) A current source with current R  R  r
1 2

R2 V
(d) A current source with current R  R  r
1 2

[1 Mark : GATE-2007]
16. The switch ‘S’ is the circuit of the figure is initially closed. It is opened at time t = 0. You may neglect
the zener diode forward voltage drops. What is the behaviour of VOUT for t > 0

+10V +10V

1k
–
Vout
+
+10k Vz= 5.0V
0.01µF

S
–10V
VZ= 5.0V
100k

–10V

(a) It makes a transition from –5V to +5V at t = 12.98 sec.

(b) It makes a transition from 5V to +5V at t = 2.57 sec.
(c) It makes a transition from +5V to 5V at t = 12.98 sec
(d) It makes a transition from +5V to 5V at t = 2.57 sec
[2 Marks : GATE-2007]
17. The block diagram of two types of half wave rectifiers are shown in figure. The transfer characteristics
of the rectifiers are also shown within the block

P Q
V0
Vin 0 V0 Vin V0

0 Vin

It is desired to mark full wave rectifier using two halfwave rectifiers. The resultant circuit will be
 54 GATE Previous Solved Questions
R
R

Vin R
Vin R P –
P – V0
V0 R +
(a) R + (b) Q
Q

R R R

Vin R
Q –
V0 –
P + Vin R V0
(c) R (d) P +
Q
R

[2 Marks : GATE-2008]
Linked Answer Questions : 18 & 19
A general filter circuit is shown in figure
R2

Vi R1 C
– Vo
R3
+
R4

18. If R1 = R2 = RA and R3 = R4 = RB, the circuit acts as a

(a) All pass filter (b) Band pass filter
(c) High pass filter (d) Low pass filter
[2 Marks : GATE-2008]
19. The output of the filter in above is given to the circuit shown in figure
The gain Vs frequency characteristic of the output (V0) will be
RA/2

Vin C Vo

Gain Gain

(a) (b)

 
ANALOG Soil Mechanics & Foundation
EE Engg.
55

Gain Gain

(c) (d)

 

[2 Marks : GATE-2008]

20. The following circuit has R = 10k, C = 10 F. The input voltage is a sinusoidal at 50HZ with an RMS
values of 10V. Under ideal conditions, the current IS from the source is
R
VS=10Vrms, 50Hz

iS 10k
a +
Opamp
~ b –

10k
R
C Vb=Va=Vs
10F
(a) 10  mA leading by 90º (b) 20  mA leading by 90º
(c) 20  mA lagging by 90º (d) 10  mA lagging by 90º
[2 Marks : GATE-2009]
21. An ideal op-amp circuit and its input waveform are shown in the figures. The output waveform of this
circuit will be

3
2 +6V
1 t4 t5 t6 1k
V0 Vin –
-1
t1 t2 t3 t Vout
+
-2 2k
-3 –3V
1k

6 6

v v

(a) t3 t6 (b) t3 t6
0 0
t t
–3 –3
 56 GATE Previous Solved Questions

6 6

v v

t6 0 t2 t6
(c) 0 (d) t4
t2 t4 t t
–3 –3

[2 Marks : GATE-2009]
22. Given that the op-amp is ideal, the output voltage V0 is

2R

R +10V
–
V0
+
–10V
+2V

(a) 4 V (b) 6 V (c) 7.5 V (d) 12.12 V

[1 Mark : GATE-2010]
23. A low pass filter with a cutoff frequency as 30 Hz is cascadded with a high pass filter with a cutoff
frequency of 20Hz. The resultant system of filters will function as
(a) All pass filter (b) An all-stop filter
(c) A band stop filter (d) A Band pass filter
[1 Mark : GATE-2011]
24. For the circuit shown below, the correct transfer characteristics is

R +12V
+12V
–
Vi –
+ V0
–12V +
R R
–12V

R R
ANALOG Soil Mechanics & Foundation
EE Engg.
57

Vo Vo
+12V +12 V

Vi
–6 +6 Vi
–6 +6
(a) (b)

–12V –12V

Vo Vo
+12V +12V

Vi Vi
–6V 6V –6V 6V
(c) (d)

–12V –12V

[1 Mark : GATE-2011]
25. The circuit shown is a
R2

C R1 +5V
+ – +
Input Output
+ –
–
–5V

1
(a) low pass filter with f3dB =  R1  R 2  C rad/sec
1
(b) high pass filter with f3dB = R C rad/sec
1
 58 GATE Previous Solved Questions

1
(c) low pass filter with f3dB = R C rad/sec
1

1
(d) high pass filter with f3dB =  1 R 2  C rad/sec
R 
[2 Marks : GATE-2012]
26. In the circuit shown below what is the output voltage (Vout) if a silicon transistor Q and an ideal op-amp
are used?

+15V Q
1k
–
+ Vout
5V +
–
–15V

(a) –15 V (b) –0.7 V (c) +0.7 V (d) +15 V

[1 Mark : GATE-2013]
27. In the circuit shown below the op-amps are ideal. Then Vout in Volts is

1 k 1 k
–2V
+15 V
+15 V
–
–
+ Vo
Vout
+
1 k –15 V
–15 V
+1V
1 k 1 k

(a) 4 (b) 6 (c) 8 (d) 10

[2 Marks : GATE-2013]
28. An operational-amplifier circuit is shown in the figure.
ANALOG Soil Mechanics & Foundation
EE Engg.
59

R +Vsat
+Vsat
vi
vo
–Vsat
–Vsat

R1 R2

The output of the circuit for a given input vi is

 R2   R2   R2 
(a)   R  vi (b)   1  R  vi (c)  1  R  vi (d)  Vsat or  Vsat
 1  1   1 
[1 Mark : GATE-2014]
29. Given that the op-amps in the figure are ideal, the output voltage V0 is
V2
R

R R
V0
2R
R R
R

V1

(a)  V1  V2  (b) 2  V1  V2  (c)  V1  V2  / 2 (d)  V1  V2 

[2 Marks : GATE-2014]
30. In the figure shown, assume the op-amp to be ideal. Which of the alternatives gives the correct Bode
Vo  
plots for the transfer function ?
Vi  
+VCC
1k
Vi
Vo
1F
–VCC

Rf
 60 GATE Previous Solved Questions

20log Vo( ) 
Vi()

0 0 10 102 103 
2
1 10 10 103  1
(a) -10 -/4
-20 -/2
-30


20log Vo( )
Vi() /2
/4
3
0 0 10
2
1 10 10 103  1 10 10 2 
(b) -10 -/4
-20 -/2
-30


20log Vo( )
V i( ) /2
/4
0 102 0 10
3

3
1 10 10  1 10 102 
(c) -10 -/4
-20 -/2
-30


20log Vo( )
V i( ) /2
/4
0 0
1 10 102 103  1 10 102 103 
(d) -10 -/4
-20 -/2
-30

[2 Marks : GATE-2014]
31. The transfer characteristic of the Op-amp circuit shown in figure is

+Vsat
R
+Vsat
vi R

vo
R –Vsat
R –Vsat
ANALOG Soil Mechanics & Foundation
EE Engg.
61

vo
vo 1
–1

(a) (b)
vi vi

vo vo
(c) (d)
vi vi
1 –1

[2 Marks : GATE-2014]
32. An oscillator circuit using ideal op-amp and diodes is shown in the figure.

+5V

C Vo
–5V
3k

1k
1k

t1 t 2
The time duration for +ve part of the cycle is t1 and for –ve part is t2. The value of e RC will be

[2 Marks : GATE-2014]
33. Consider the circuit shown in the figure. In this circuit R = 1k and C = 1µF. The input voltage is
sinusoidal with a frequency of 50Hz, represented as a phasor with magnitude Vi and phase angle 0 radian
as shown in the figure. The output voltage is represented as a phasor with magnitude Vo and phase angle
 radian. What is the value of the output phase and (in radian) relative to the phase angle of the input
voltage?
R

C
–
vi = Vi 0 vo = V o
+
C
R
 62 GATE Previous Solved Questions

 
(a) 0 (b)  (c) (d) 
2 2

[1 Mark : GATE-2015]
34. The operational amplifier shown in the figure is ideal. the input voltage (in Volt) is Vi = 2 sin(2 × 2000t).
The amplitude of the output voltage Vo(in Volt) is

0.1µF

1 k
1 k
Vi –
Vo
+

[1 Mark : GATE-2015]
35. The filters F1 and F2 having characteristics as shown in figure (a) and (b) are connected as shown in
figure (c).

F1 F2
Vo/Vi Vo/Vi
Vi Vo Vi Vo
f1 f2
f f
f

R/2

+Vsat
R –
F1
Vi + Vo
–Vsat
F2
R

The cut-off frequencies of F1 and F2 are f1 and f2 respectively. If f1 < f2, the resultant circuit exhibits
the characteristic of a
(a) Band-pass filter (b) Band-stop filter
(c) All pass filter (d) High-Q filter
[1 Mark : GATE-2015]
36. The four characteristics given below, which are the major requirements for an instrumentation amplifier?
P. High common mode rejection ratio
Q. High input impedance
R. High linearity
S. High output impedance
(a) P, Q & R only (b) P & R only
(c) P, Q & S only (d) Q, R & S only
ANALOG Soil Mechanics & Foundation
EE Engg.
63
[1 Mark : GATE-2015]
37. The op-amp shown in the figure has a finite gain A = 1000 and an infinite input resistance. A step-voltage
Vi = 1 mV is applied at the input at time t = 0 as shown. Assuming that the operational amplifier is not
saturated, the time constant (in millisecond) of the output voltage Vo is

C = 1µF

R=1k
–
VA
1mV + +
+ Vi A = 1000
– Vo
t=0 s
–

(a) 1001 (b) 101 (c) 11 (d) 1

[2 Marks : GATE-2015]
38. The saturation voltage of the ideal op-amp shown below is ± 10V. the output voltage Vo of the following
circuit in the steady state is

1 k

+10 V
0.25 µF + Vo
– 2k
–10 V

2k

(a) Square wave of period 0.55 ms

(b) Triangular wave of period 0.55 ms
(c) Square wave of period 0.25 ms
(d) Triangular wave of period 0.25 ms
[2 Marks : GATE-2015]
39. A transistor circuit is given below. The Zener diode breakdown voltage is 5.3 V as shown, Take base
to emitter voltage drop to be 0.6V. The value of the current gain  is____.
 64 GATE Previous Solved Questions

[1 Marks : GATE-2016]

VCC
40. For the circuit shown in the figure below, it is given that VCE = . The transistor has = 29 and VBE
2
= 0.7 V when the B-E junction is forward biased.

RB
For this circuit, the value of is
R
(a) 43 (b) 92 (c) 121 (d) 129
[2 Marks : GATE-2017]
41. The logical gate implemented using the circuit shown below where, V1 and V2 are inputs (with 0V as
digital 0 and 5V as digital 1) and Vout is the output, is
ANALOG Soil Mechanics & Foundation
EE Engg.
65

(a) NOT (b) NOR (c) NAND (d) XOR

[2 Marks : GATE-2017]
42. The circuit shown in the figure uses matched transistors with a thermal voltage VT = 25 mV. The base
currents of the transistors are negligible. The value of the resistance R in k that is required to prove
1 A bias current for the differential amplifier block shown is____. (Give the answer up to one decimal
place.)

[2 Marks : GATE-2017]
43. For the circuit shown below, assume that the op-amp is ideal.
 66 GATE Previous Solved Questions

Which one of the following is TRUE?

(a) v0 = vS (b) v0 = 1.5vS (c) v0 = 2.5vS (d) v0 = 5vS
[2 Mark : GATE-2017]
44. The approximate transfer characteristic for the circuit shown below with an ideal operational amplifier and
diode will be

[2 Mark : GATE-2017]

vin
45. The op-amp shown in the figure is ideal. The input impedance is given by
iin
ANALOG Soil Mechanics & Foundation
EE Engg.
67

R1 R2 R1
(a) Z R (b) -Z R (c) Z (d) -Z
2 1 R1 +R 2
[1 Mark : GATE-2018
46. In the circuit below, the operational amplifier is ideal. If V1 = 10mV and V2 = 50 mV, the output voltage (Vout)
is

(a) 100mV (b) 400mV (c) 500mV (d) 600mV

[2 Marks : GATE-2019]

47. A current controlled current source (CCCS) has an input impedance of 10W and output impedance of
100 kW. When this CCCS is used in a negative feedback closed loop with a loop gain of 9, the closed
loop output impedance is
(A) 10 W (B) 100 kW
(C) 1000 kW (D) 100 W
[2019 : 1 Marks]


 68 GATE Previous Solved Questions
SOLUTIONS
SOLUTIONSSOLUTIONSSOLUTIONSSOLUTIONSSOLUTIONSSOLUTIONS
SOLUTIONS
1. Ans. (b)  Vsat
Vc =
2
This circuit is Astable multivibrator (or) square
 Vsat   Vsat 
wave generator. = Vsat    Vsat  e  T1 
2  2 
Assume that V0 = +Vsat then
 Vsat  T 
 R   Vsat =  Vsat  e 1
Vx = V0   2 2
 2R  2

 eT1 = 3  T1   ln 3

R For T2 :

 Vsat
C Vf = Vsat ,Vi  ,   RC
2
–
V0
+  Vsat
R at t = T2, VC =
2
VX
R  Vsat  Vsat  
= Vsat    Vsat  eT2
2  2 

Vsat 3Vsat  T2 
As V0 = +Vsat is given to capacitor, ‘C’ charges = e
2 2
towards Vsat through ‘R’ with  = RC. when Vc
just exceeds Vx,  e T2  = 3  T2   ln 3
V0 = –Vsat. As V0 = –Vsat, then Vx becomes
 T = T1  T2
 Vsat
therefore ‘C’ discharges towards 0 but T = 2 ln 3
2
2. Ans. (a)
 Vsat
when Vc < , V0 = +Vsat
2 V0 = Vi  Vm sin t
Time period:
dV0
For T1 : =  Vm  cos t
dt
+Vsat
Vsat
+
2
T2 Vo
t Vi +
Vsat T1
–
2
–Vsat  dV0 
  = SR  Vm  2fVm
 dt max
Vc = Vf   Vi  Vf  e t 

2fVm 2fVm
 Vsat SR = 6 6
 V  sec
Vf = Vsat ,Vi  ,   RC, 10  10 106
2
at t = T1 SR  106
f=
2Vm
 ANALOG Soil Mechanics & Foundation
EE Engg.
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62.8  106  V0 
f = V0 = 6    1
2  10  4 

f = 106 Hz = 1MHz 2.5V0 = 1

3. Solution : 1
V0 =
2.5
2k 8k  V0 = 0.4 volts.
1k I4 I6
1V a –
4k 4. Solution :
I3 + – Vo
b V1 -1V
+
I5 Since vd  0
b 3k –1V
va  0
I
I1 1k 2
R2

R1 C If
Vi –
a V0
Apply KCL at ‘a’ Z d +
I
I3 = I4

1  Va Va  V1
3 = Then I = If
10 2  103
Vi Vo
2  2Va = Va  V1
=
Z R2
V1 = 3Va  2
Apply KCL at 'b'  V0 R2 R2
I1 + I2 = 0
 Vi = Z =  1  sCR 2 
 
 sC 
Vb Vb  V0
3
 =0
10 3  103
V0 R 2  sC 
3Vb  Vb  V0 = 0 V1 = R 1  s  1/ R 1C 


V0
Vb = V0 R 2  s 
4 =
V1 R 1  s  1/ R 1C 

Apply KCL at inverting terminal of op-amp ‘2’
I5 = I6 Given that  first order high pass filter circuit
(i) The high frequency impedance R1 = 100
V1  1 1  V0 k
=
4  103 8  103 R2

2V1  2 = 1  V0 R1 If
Vi –
V0 = 2V1 3 Ii a V0
+
Ri
= 2  3Va  2   3

= 6Va  4  3 (ii) high frequency gain magnitude of 10,

= 6Va  1  6Vb  1
 70 GATE Previous Solved Questions
6. Ans. (d)
R2
 10  R2 = 1000k
R1 R

R2 = 1M If
 R a
Vi –
(iii) 3-dB Cutoff frequency is I
b V0
+
1 R
f  = 2R C I1
1
C
I2
1
C = 2R f Apply KCL at ‘b’
11

1 Vi  Vb
=  1.5912nF = Vb  SC
5
2  10  10 3 R

5. Ans. (a) Vi  Vb = Vb  SCR

When V0 = +15 V,  Vi 
Vb = 
The potential at non – inverting terminal is UTP,  1  SCR 

 R2  Apply KCL at ‘a’, I = If

VUTP = Vref   V0  Vref   
 R1  R 2  Vi  Va Va  V0
=
R R
 3
VUTP = 2  15  2    V0 = 2Va  Vi = 2Vb  Vi
 13  
= 5V
 1  SCR 
= Vi 
When VUTP > Vi  V0 = +15V 1  SCR 
VUTP < Vi  V0 = –15V
When V0 = –15V, the potential at non-inverting V0 1  jCR 
Vi = 1  jCR 
terminal is LTP  

10V  V0 1  
5V
t
 V  2 tan CR 
 i 
–1.923V
–10V
For 90º    90º
+15V  = ±180º
t
0
–15V 7. Ans. (d)
Apply KVL at 'a'
 3
VLTP = Vref   V0  Vref   
 13  Vi Vx
I = I1  3

10 10  103
 3
= 2   17   
 13  Vx = –10Vi
 VLTP = –1.923V
 The output will change from +15V to –15V when
the instantaneous value of the input sine wave is
5 V in the positive slope only.
ANALOG Soil Mechanics & Foundation
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71
1k x 1k 5 – Ic × 200 = V0 and
I3 5 – Ic × 200 – VCE (sat) – 1.25 × 10–3 × 103 = 0
I1 1k
I2 V0 – 0.1 – 1.25 = 0
1k
Vi – V0 = 1.35 volts
a V0
I +
b 10. Ans. (a)
The transfer function of the bridged T-network
Apply KVL at 'b' is

 Vx
I1 = I2  I3   1
s2   
1  1

1
10  103 
 C1 C 2  R1 C1C 2 R 1R 2
T(S) =  1 1 1  1
Vx Vx  V0 s2  s   
=  C R C R C R  C C R R
10 3
10  103  1 1 1 2 2 1 1 2 1 2

Vx = 10Vx  Vx  V0 The pole polynomial of the active filter circuit

V0 = 12Vx  120Vi will be equal to the numerator polynomial of the
bridged T-network
V0
 Gain = V  120 0
i s2  s   02
Q
8. Ans. (b)
 1 1  1 1
The gain of the op-amp circuit is = s2  s     
 C1 C 2  R 1 C1C 2 R 2 R 1
V0  100 
= 1   1
Vx  10  Then = and
C1C 2 R1R 2
V0
Vx = 11 1
 C1C2 R1R 2  1  
Q = 
R1  C  C 
V0   1 
2 
Vx =
11
Given that Q = 1, C1 = C2 = 1 nF
Apply KCL at Non inverting terminal,
and R1 = 200K
Vx  V0 Vx  11Vx
Ix = 
106 106 1 109  109  200  103 R 2  1 1 
 3  9  9 
Q 200  10  10 10 
 Vx  10 Vx
Ix = 6
  100k
10 Ix
Rin = 100k 1 R 2  2  1013
1   2  109 
Q 2  105
9. Ans. (b)
When Vi = 0, R 2  4.472  10 3  1
Q1 (cutoff) – off and Q2 – ON(sat)
R2 = (223.606)2
VCE(sat) = 0. IV
 R2 = 50k
Then Apply KVL from 5V to Ground through
transistor Q2 C-E terminals
 72 GATE Previous Solved Questions

1
0 = C1C 2 R1R 2 C
–
Vi
+ P
1 D
RL
=
109  109  200  103  50  103

0 = 10,000 rad/sec
During the negative half cycle of input, Diode D
11. Ans. (c) will be forward biased and its equivalent circuit
R F is
Gain of the inverting amplifier is A = R given
1
that RF = 1M, A  –10 & –25 then C
–
Vo
106 + P
R1 = = 105 = 100 k when A = –10
Vi ~ 0.7V
10

106
R1 =  40k when A = –25 The op-amp has high open loop gain so it goes
25
into the saturation and Vp = 0.7V. During the
The designer wishes the input resistance should +ve cycle of input, diode will be reverse biased
be as large as possible and no feedback to the op–amp then Vp = –12V
 R1 = 100k
+12V
12. Ans. (c) Vi –
The op-amp is in the open-circuited mode i.e. no + Vp
feedback is given. The op-amp has high open RL
–12V
loop gain and is forced to operate in saturation
region, for the given input waveform of the op- 14. Ans. (c)
amp
Given circuit is A stable multivibrator whose
V0 = A OL  0  Vi  output is square wave and waveform across
capacitor is exponential waveform. Therefore
During the positive half cycle of input (Vi > 0), potential across ‘C’ and ‘P’ are same.
the op-amp saturated to V0 = –V. When output voltage is + 12V, the ‘C’ changes
During the negative half cycle of input (Vi < 0), towards maximum value through R1. And max
The op-amp saturated to V0 = +V. voltage is given by
13. Ans. (d) Vo = 12V, D1 is ON & D2 is OFF

12  10  6 V
VP =
10  10
When output voltage is –12V, ‘C’ discharges
towards –12V through R2. To calculate this,
consider the circuit at non inverting terminal. At
this
Vo = –12V, D1 is OFF & D2 is ON

12 10  10V

VP =
10  2
ANALOG Soil Mechanics & Foundation
EE Engg.
73
12V
 100  10
+6V Vx = V0    V0
 110  11

-10V When output changes from +5V to –5V, the

-12V capacitor changes and
15. Ans. (d)
10
Vd  0 20 1  e  t   = 5
11
V+ – V– = 0
V+ = V – 5
1  e t  =
22

R1 5 t
+  1 = e 
V V1 22
–
IL
R2   RC  103  0.01  10 6 ,
0
V1 22
i 
r
et =
17

Assume that t 22
= ln
 17
V+ = V 1
Since   10 sec
R2 
V1 = V  
 R1  R 2 
 22 
Therefore V– = V 1 t =  ln  
 17 
V1 R2 V
Then i = r  R R  r = 105  0.257829 = 2.578 sec.
1 2
Current entering into the op-amp is zero
17. Ans. (b)
V  R2  From the transfer characteristic of the rectifier
 IL = i 
r  R 1  R 2  P is
Vo = –Vi for Vi > 0
This is voltage to current converter. Therefore a
Vo = 0 for Vi < 0
 R2  V Vo
current source with a current  R  R   r .
 1 2 
t
0
P
16. Ans. (d)
Initially VC = 0 From the transfer characteristic of the rectifier
When the switch ‘S’ is opened, the capacitor Q is
charges towards the maximum value of 20V and V0 = 0 for Vi > 0
is given by
V0 = –Vi for Vi < 0
–t/
VC = 20(l – e ) ...(1)
This is at inverting terminal of the op-amp. But
the voltage at Non-inverting, terminal is
 74 GATE Previous Solved Questions
Vo
Vi  2  sCR A   1 
= 2  1  sCR   Vi  1  sCR 
Q  A   A 
t
0
Vi  sCR A 
=
1  sCR A 1  2  1
To make full wave rectifier, the half wave
rectifier ‘P’ must be connected to inverting and Vi  sCR A 
‘Q’ must be connected to non-inverting terminal = 2  1  sCR 
 A 
of the op-amp.
Vo Vi  s 
V0 = 2  s  1/ R C 
 A 
–P Q
t High pass filter.
0
19. Ans. (d)
18. Ans. (c) Vi  s 
Vin = 2  s  1/ R C 
Assume Z = R2 || 1/sC  A 

As input to LPF
Z
If  1 
R1
Vi  sC 
I a – then V0 = Vin  
I1 Vo R
+  A  1 
R3 b
 2 sC 
R4 Vd  0
I2 Vb  Va  2 
= Vin  2  sCR 
 A 

R 2 1/ sC  R2
=  Vi  s  1 
R 2  1/ sC 1  sCR 2 =  
2  s  1/ R A C   s2 
 R A C   
RA   R AC  
Z = 1  sCR
A
Apply KCL at ‘b’  2 
I1 = I2 Vi  s   R A C 
= 2  s 1   s  2 
Vi  Vb Vb V   
=  Vb  i  A   A 
R C  R C
R3 R4 2
Transfer function of BPF.
Apply KCL at ‘a’ I = If
20. Ans. (d)
Vi  Va Va  Vo
= Apply KCL at ‘b’
RA Z
Vb  0 Vb  Vo
 Z   Z   0
V0 = Va  1  R   Vi  R 
1/ Cs  R

 A   A
Vb  sCR  Vb  Vo  0
 1   1 
= Vb 1    Vi    Vo 
 1  sCR A   1  sCR A  Vb =  
 1  sCR 
Apply KCL at 'a'
ANALOG Soil Mechanics & Foundation
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Va  V0 Vb  Vb  Vb sCR 0  Va Va  Vo
IS = = =
R R R 2R
VbsCR  Vo = 3Va  3  2 
Is   =  jC Vb   jCVs
R
‘Is’ lags behind the applied voltage Vo = 6V
23. Ans. (d)
–90º VS
Vi LPF HPF Vo

fc=30Hz fc=20Hz

IS The Cutoff freq. of LPF is greater than that of

HPF  Band pass filter
|Is| =  C V s = 2  f  C  Vs

= 2  50  10 10 6 10 = 10 103

= 10 mA lagging by 90º
21. Ans. (d)
0 20 30
Given that Vsat = 6V, –Vsat = –3V f
24. Ans. (c)
Where V0 = +6V, the potential at non-inverting
The first Stage of the given circuit represents
terminal is,
subtracter. As Vi  than its output is V01= –Vi
 R2  1 Then
VUTP =  Vsat   = 6    2V +12V
 R1  R 2  3
Vi –
At instantaneous value of Vi = 2V, V0 = +6V Vo
+
If VUTP > Vi  V0 = +6V
–12V R
VUTP < Vi  V0 = –3V
When V0 = –3V, the potential at non-inverting
termmal is VLTP = –3(1/3) = –1V
R
At t < t4, V0 = –3V
i.e, VLTP < Vi  V0 = –3V
When VLTP > Vi  V0 = +6V  R 
VUTP = 12    6V
22. Ans. (b)  2R 
2R VLTP = –6V

R If
a
I b Vo

2V Va=Vb=2V

Given that Non inverting Op-amp circuit

Apply KCL at ‘a’
I = If
 76 GATE Previous Solved Questions
V0  s  R 2 sCR 2
10V H(s) =  
+6V Vi  s  Z 1  sCR1
t
0
R2  s 
–6V = 
R1 s  1 

 
–10V  R1C 
+12V
t
|H(j)| increases from 0 at  = 0
0
to (R2/R1) as    with 3dB
–12V 1
= R C rad sec
1
When
 The given circuit is HPF with f3dB
Vi < 6V  Vo = +12V
1 1
Vi > 6V  Vo = –12V = 2R C Hz = R C rad sec
1 1
When
26. Ans. (b)
Vi > –6V  Vo = –12V
Vi < –6V  Vo = +12V
+15V Q
The transfer characteristic curve is
1k
Vo –
0V + Vout
12V
5V +
–
–15V

Op-amp is ideal.
Vi
-6V 6V So, V– = V+ = 0
As input 5V is applied on inverting input terminal
i.e. Differential input
Vid = V+ – V– = negative (very
-12V
small)
25. Ans. (b)
So, output Vout = negative
For the given circuit
So, Si-Transistor Emitter-Base junction is forward
R2 biased.
Hence, VBE = 0.7
C R1
+  VB – VE= 0.7
–
Input V0  0 – Vout= 0.7
Z +
–
 Vout= –0.7 V
27. Ans. (c)

1 1  sCR1
Z = R1  
sC sC
Transfer function,
ANALOG Soil Mechanics & Foundation
EE Engg.
77
1 k I 1 k Vo
1V I Vx = = 4V
–2V 2
0A +15 V
+15 V
 Vo = 8V
–
– 28. Ans. (d)
0A + Vx Vo
1V Vout
+ The circuit of op-amp ‘1’ is a schmitt trigger,
1 k –15 V
–15 V therefore
+1V Vx V01 = ±Vsat
1 k 1 k
and the circuit of op-amp ‘2’ is a non-inverting
amplifier
For ideal op-amp
 V0  1 R 
   =  
+15 V V
 01   R 
 Vo = 2V01
–
Vx Vo Vout Where, V01 = ±Vsat
+
0A which is not possible, hence the answer is  Vsat.
–15 V
Vx 29. Ans. (b)
1 k 1 k Op-amp ‘3’ circuit is a differential amplifiler
So, Vo = V01 – V02 ...(i)

Vo Vo Now, apply KCL at node ‘2’

Vx = × 1 =
11 2
V2 – V1 V2 – V02
Vo + =0 ... (ii)
2R R
1k and apply KCL at node ‘1’
V1 – V2 V1 – V01
Vx + =0 ...(iii)
2R R
From equation (i), (ii) and (iii), we get
1k
Vo = 2(V1 – V2)
30. Ans. (a)
1 k I 1 k Rf
–2V
1V I
0A +15 V
–
– R=1 k Vo
Vx Vi +
0A +
1V
1µF
1 k –15 V
+1V
This filter is considered as low-pass filter (LPF)
1  ( 2)
I = = 3 mA The transfer function for LPF
1
Vx – 1 = 1 × I
 Vx = 1 + 3 = 4V
 78 GATE Previous Solved Questions

R
R +Vsat
– Vi
1 k Vo – R
Vi + –
+
1µF –Vsat + Vo
Buffer R
R

Low Pass
1 Hence Vo = 0
Vo sC 1 Case-II: Vi < 0, the circuit will look like
Vi = 1 =
R 1  sCR
sC
1 R
R +Vsat
= Vi
1  j(103 )(10 –6 ) – R +Vsat
+ V01 –
1 –Vsat + Vo
= R –Vsat
1  j(10 –3 ) R

1000
= 1000  j
V01 R
–
Vi = R
1
= 1 s V01 = –Vi
1000
Vo R
c (corner frequency) = 103 rad/sec and V01 = –
R
At f = 0,
Vo = –V01
the gain at low frequencies
From equation (ii),
  Vo = Vi
Corner
frequency 32. Ans. 1.2 to 1.3
2 3 2 3 In the circuit shown the output voltage
0 10 10 10  0 10 10 10
1 
1
–10 –/4
R
–20 –20 dB/dec –/2
–30 0A +5V
i Vo
+ c
Vc C
– –5V
1 1 R1 =3k D1
Av = = = 1
1  sCR 1 Vx
D2
31. Ans. (c) R2 =1k
R3 =1k
Case-I: Vi > 0, the circuit will look like

Vo = +Vsat = +5V if Vx > Vc

ANALOG Soil Mechanics & Foundation
EE Engg.
79
Vo = Vsat = –5V if Vx < Vc
So, –2.5 = –5 + 6.25 e
  RCt 
2

If Vo = +5V only
D1  ON t 2
 = 0.92
RC
and D2  OFF
From t2 < t < t 3
Vo V
Vx = 1  o  5 C is charged from –2.5 V through +5 V & R
1 3 4 4

= 1.25 = Vutp  t
Vc(t) = 2.5  5  (2.5) 1  e CR 
Vutp = upper threshold voltage
 t
Similarly if Vo= –5V only D2  ON = 5 – 7.5 e CR

5 After t1 (during which Vo = +5 V)

Vx =   2.5V  Vltp
2
Vc = Vutp = 1.25 V
Vltp  Lower threshold voltage
t1
Let initially Vc(0) = 0V & Vo = +5V 
 1.25 = 5  7.5e CR

So, C is charged through R upto

t1
Vo = +5V  = 0.69
CR
dVc
ic = C
dt t1  t 2
 = 0.69 – 0.92 = –0.23
Ric + Vc = Vo CR
dVc t1t 2
 RC  Vc  5  = e0.23  0.8
dt e CR

Vc(t) = 5 1  e RC 
t
 Vc
Vutp = 1.25
At t1, when Vc = Vutp = +1.25 t2
0 t1 t3 t
Vo changes from +5V to –5V
At, t = t1; Vc = 1.25 Vltp = –2.5

as Vo = –5V Vo t2 t1

The capacitor is charging towards –5V +5V
At t = t 2, 0 t
–5V
when Vc = –2.5V
Vo changes from –5V to +5V
33. Ans. (d)
t1 < t < t 2
The circuit is
 t
Vc(t) = 1.25  (5  1.25) 1  e RC 

 t
 Vc(t) = –5 + 6.25 e RC

So during t2; Vo = –5 V
At t2, Vc = –2.5 V
 80 GATE Previous Solved Questions
I R 0.1µF

C
– 1 k
B Vo 1 k
V i –+ Vi –
+
I Vo
+
C
I R

 Zeq 
Since, circuit has negative feedback, so with help Vo = Vin  R 
 1 
of virtual short VA = VB
So, KVL in the loop from A to B given, 622.67
= 2
1000
 1   1 
I   – Vi + I   = 0
 sC   sC  Vo = 1.254 V
sCVi 35. Ans. (b)
So, I=
2
Filter (f1) pass low frequency component signal up
So, VA = –IR
to (f1) and stops the higher frequency components.
sCRVi
VA = – Filter (F2) pass high frequency component signal
2
and VA = V B up to (f2) and stop the lower frequency components

sCRVi Then characteristic like

VB = 
2
VB – Vo
Now, =I
R
So, Vo = VB – IR
sCRVi sCRVi
Vo = – –
2 2
= –sCRVi
So this characteristic, like “Band stop filter”
So, Vo = – jRCVi
36. Ans. (a)
So, Vo lag Vi by 90o or phase of Vo
Instrumentation amplifer have high common mode
w.r.t. Vi is –90o.
rejection ratio, high input impedance and high
34. Ans. 1.1 to 1.4 linearity.
Reactance of Capacitor
37. Ans. (d)
1 1 The circuit is
 C = 4 00 t  1 0  7
= 795.77 
Equivalent feedback impedance
(R )(  j  C)
Zeq = R  j C
= 622.97  51.488
ANALOG Soil Mechanics & Foundation
EE Engg.
81

C = 1µF Since, pole is at (1/1.001).

So, time constant is approx ‘1’.
R=1000
– 38. Ans. (a)
VA Vo
+ The given circuit in a astable multivbrators so
+ Vi A = 1000
– output will be a periodic square wave and from
the circuit  = 0.5
1 k
Now, the gain of op-amp is 1000.
+10 V
so, Vo = 1000 (V+ – V–)
0.25 µF + Vo
since, V+ = 0 (grounded) – 2k
–10 V
V– = VA
The above circuit can be redrawn as 2k

C = 1µF

R=1000
Vo
1 
So, time period will be 2Ln 1    
VA
+ V + –1000 VA
– i –
T = 2 × RC Ln 11  0.5
0.5

T = 0.55 ms
so, Vo = – 1000 VA
39. Ans. (19)
Now, KCL at node ‘A’
5.3  10
VA – Vi  VA – V0  IE 
=   4.7  103
1000  1 / sC 
IE = 1 mA
VA – Vi VA – (–1000VA ) IB = 1 - 0.5  0.5 mA
=
1000 1 / sC IE = ( + 1) IB

VA – Vi = (1001 VA) sC  1000

0.01
1+β= =20
VA – Vi = (1001) × 1000 sC VA 0.5×10-3
VA – Vi = s(1001000×10–6) VA
β=19
VA– s1.001 VA = Vi
40. Ans. (d)
 Vi 
VA=   VCC 10
 1 – s(1.001)  Given VCE = = =5V
2 2
Since, Vo = – 1000VA 10 = (1 + ) IB  4R + IBRB + 0.7 + (1 + )
IB.R
1000
= V 9.3 = IB [150R + RB] ...(1)
1  s(1.001) i
Applying loop:-
10 = 4R (1 + ) IB + VCE + (1 + ) IBR
 82 GATE Previous Solved Questions

5 1 Vx Vx -Vy
IB = = ....(ii) + =0
150 R 30 R R R
Subsitute (ii) in (i)
2VS
2Vx = Vy ; Vy =  VS ]
1 2
9.3 = 150+R B 
30 R at node (3)

RB
=129
Vy
+
 V -V  +  V -V  =0
y x y 0
R R R R
41. Ans. (b)
5VS
V0   2.5VS
2
V 1 V2 Q1 Q2 Vout Logic Level
0 0 OFF OFF 5V 1 44. Ans. (a)
0 1 OFF ON 0V 0
The Given Circuit is Hay wave Rectifier with
1 0 ON OFF 0V 0
1 1 ON ON 0V 0 Vin  0; V0 = Vin
Vin < 0; V0 = 0

hence given circuit act as a NOR gate. 45. Ans. (b)

42. Ans. (170 to 174)

VT  IC1 
R= n  
I C2  IC2 

IC1 = 1 mA; IC2 = 1 A +

–

25×10-3  1×10-3 
R= n  -6 
 172.7KΩ
1×10-6  1×10 

43. Ans. (c)

From, the circuit

R2
V’ = V0 ...(i)
R1 +R 2
Vy
Vx
V''-V0
Vx Also, = Iin
Z
For ideal op-amp
V = V

at node (non inverting) R 2 V0

= V0 + IinZ
R1 +R 2
VS ×2R VS
Vx = =
4R 2
at node (inverting)
ANALOG Soil Mechanics & Foundation
EE Engg.
83

 R2   10 
V0  -1 = I Z V0 =11   V2 -10V1
 R1 +R 2  in  11 

V0 = 10(V2-V1)
 -R1 
V0   = Iin Z ...(ii) = 10  40  10-3
 R1 +R 2 
= 400mV
From circuit
47. Ans. (C)
Vin = V = V
“CCCS” [Current Controlled Current Source
Amplifier]
R 2 V0
Vin = Given, Z0 = 100 kW
R1 +R 2
Loop gain, Ab = 9
ZOF = Z0 [1 + Ab]
 R1 +R 2 
 V0 = Vin [High impedance CS]
R2
= 100 kW [1 + 9]
From equation (ii) = 100 kW ´ 10 = 1000 kW

Vin
 R1 +R 2  - R1 
  = IinZ
R2  R1 +R 2 

Vin R2
= - Z
Iin R1
46. Ans. (b)

KCL at I1 = I2

V1 -Va Va -V0
=
10K 100K
10V1 - 10Va = Va - V0
V0 = 11Va - 10V1
 84 GATE Previous Solved Questions

6
FEEDBACK AMPLIFIERS & OSCILLATORS
1. An op-amp has an open-loop gain of 105 and an open loop upper cutoff frequency of 10 Hz. If this op-
amp is connected as an amplifier with a closed loop gain of 100, then the new upper cutoff frequency
is
(a) 10 Hz (b) 100 Hz (c) 10 KHz (d) 100 KHz
[1 Mark : GATE-2001]
 Vy 
2. Determine the transfer function   for the RC network shown in figure (a). The network is used as
 Vx 
a feedback circuit in an oscillator circuit shown in figure (b) to generate sinusoidal oscillations. Assuming
that the operational amplifier is ideal, determine the value of RF for generating these oscillations. Also
determine the oscillation frequency if R = 10 k and C = 100 pF.
RF
R C
1k
–
VX C R VY vo
+

C R
R C

Figure(a) Figure (b)

[5 Marks : GATE-2002]
3. The feedback used in the circuit shown figure can be described as
VCC

RC
RF C=
V0
C

RL
RS RB RC Ce

(a) Shunt-Series feedback (b) Shunt-Shunt feedback

(c) Series-Shunt feedback (d) Series-Series feedback
[1 Mark : GATE-2004]
4. The nature of feedback in the op-amp circuit shown is
ANALOG Soil Mechanics & Foundation
EE Engg.
85

1k +6V
2k
–
+ Vout

Vin ~ –6V

(a) Current-current feedback (b) Voltage-Voltage feedback

(c) Current-Voltage feedback (d) Voltage-Current feedback
[1 Mark : GATE-2009]
5. As shown in the figure, a negative feedback system has an .amplifier of gain 100 with ±10% tolerance
in the forward path and an attenuator of value 9/100 in the feedback path. ‘The overall system gain is
approximately.

+
100±10%
–

9/100

(a) 10 ± 1% (b) 10 ± 2% (c) 10 ± 5% (d) 10 ± 10%

[1 Mark : GATE-2010]
6. In the feedback network shown below, it the feedback factor k is increased, then the

Vin+
– V1 +
– A0 +
– Vout

Vf=kVout +
– k

(a) Input impedance increases and output impedance decreases.

(b) Input impedance increases and output impedance also increases.
(c) Input impedance decreases and output impedance also decreases.
(d) Input impedance decreases and output impedance increases.
[1 Mark : GATE-2013]
7. In the Wien Bridge oscillator circuit shown in figure, the bridge is balanced when

C1

R1
+VCC

R3
–VCC

C2 R2 R4
 86 GATE Previous Solved Questions

R 3 R1 1 R 2 C2 1
(a) R  R , 
R1C1R 2 C 2 (b) 
R1 C1
, 
R1C1R 2C 2
4 2

R 3 R1 C 2 1 R 3 R1 C 2 1
(c) R  R  C ,   R1C1R 2 C 2 (d) R  R  C ,   R C R C
4 2 1 4 2 1 1 1 2 2

[1 Mark : GATE-2014]
8. The cross-section of a metal-oxide-semiconductor structure is shown schematically. Starting from an
uncharged condition, a bias of +3 V is applied to the gate contact with respect to the body contact. The
charge inside the silicon dioxide layer is then measured to be +Q. The total charge contained within the
dashed box shown, upon application of bias, expressed as a multiple of Q (absolute value in Coulombs,
rounded off to the nearest integer) is__________

[2020 : 1 Marks]
9. A CMOS Schmitt-trigger inverter has a low output of 0 V and a high output level of 5 V. It has input
thresholds of 1.6 V and 2.4 V. The input capacitance and output resistance of the Schmitt-trigger are
negligible. The frequency of the oscillator shown is ___________ Hz. (Round off to 2 decimal places.)

[2021 : 2 Marks]


ANALOG Soil Mechanics & Foundation
EE Engg.
87

SOLUTIONS
SOLUTIONSSOLUTIONSSOLUTIONSSOLUTIONSSOLUTIONSSOLUTIONS
SOLUTIONS
1. Ans. (c) But Vy(s) = I 2  s   R
Given that
VY  s  
AOL = 106  2  3sCR  s C R  1
2 2 2
=
sCR
f2 = 10 Hz and
ACL = 100 VY  s  sCR
  = 2 2 2
A OL Vx s s C R  3sCR  1
ACL = 1   A
OL

A OL 105 1
  1000 VY  s 
1   A OL  =
A CL 102 = sCR  3  1 
Vx  s   sCR 
Due to feedback, the upper cutoff frequency is
increased and lower cutoff frequency is If this is connected as feedback in the op-amp
decreased by a factor (1 + AOL) circuit then feedback factor
f2f = f2 (l + AOL)
Vf
= 10 (103) = V
0
 f2f = 10 kHz
2. Solution : RF
1k
R 1/sC –
v0
1 2 +
VX I2 R
I1 R VY Vf
1/sC
C
R C
Apply KVL to loop (1)
 1  1
Vx  s  = I1  s   R    I2 s  
 sC  sC
...(1) 1 1
= =
Apply KVL to loop (2) 1  1 
sCR  3  3  j CR  
sCR  RC 
 1   2 
 I1  s     I2 s   R  0
 sC   sC  To get the undamped oscillations, the imaginary
part of the feedback factor is zero.
1  2  sCR 
I1  s   = I2 s  
sC  sC  CR 
1
=0
CR
I1  s  = I 2  s   2  sCR  ...(2)
1 1
Substitute equation (2) in (1), then 2 = C 2 R 2    RC
 1  sCR 
Vx  s  = I 2  s  2  sCR    The frequency of oscillations is given by
 sC 
1 1 1
 I 2 s  
sC f0 = =
2RC 2  10  10  100  1012
3

I2  s  
=  1  sCR  2  sCR   1 = 159.12 KHz
sC
 88 GATE Previous Solved Questions
1
Then = 1 10%
3 = = 1%
1  (9 /100)  100
To get sustained oscillation |A| = 1
 A
A = 3 Af = = 10
  1  A

RF
A = 1 3 6. Ans. (a)
103
RF Ii Ii
3 =2 + Vin
10 – V1 + A0 –+ Vout
+ Vf – –
 RF = 2 K Rif Ri Ro Rof
3. Ans. (b)
As one terminal of feedback element is connected
Vf =kVout
+ k + Vout
to output voltage, so it is voltage sampling (or) – –
shunt sampling and another terminal of feedback Rx
element connect connected to base of the
At the output voltage V0 is sampled so it is
transistor, it is shunt mixing hence it is Shunt-
voltage feedback.
Shunt feedback amplifier.
At the input Vf is connected in series
4. Ans. (b)
V1 = Vin – Vf
The equivalent circuit of the given amplifier is
So, it is series feedback.
Hence voltage-series feedback is used here.
Input impedance
R0
+
Vi
V0 V1
+ + AVi Ri = I
– i
Ri
Vin
Rif =
Ii
Hence Rif > Ri
2K
1K So input impedance increases
Using voltage feedback Rof > Ro
As Rof > Ri | | Rx is input impedance of feedback
The feedback network samples the o/p voltage network ‘k’
and given to the inverting terminal of the op-amp So, if k is increased
is shunt mixing (or) voltage mixing.
Input impedance increases and output impedance
 The feedback is voltage-shunt (or) voltage- decreases.
voltage 7. Ans. (c)
5. Ans. (a) For an oscillator, the op-amp should operate in
dA its linear part of the characteristics.
= 10%,
A
 = 9/100,
A = 100

dAf 1 dA
= 
Af 1  A A
ANALOG Soil Mechanics & Foundation
EE Engg.
89

C2 R 2 R 2 R 3
C1 Then, R1  C = R
1 4
Z1
R1 R3 R 1 C2
+VCC = 
R4 R 2 C1
Vx  0A
Vo 8. Ans. (0)
Vx R3
–VCC
Vx
 0A
Z2 C2 R2 R4

VoR 4 Vo Z2
Vx = R  R = Z  Z ...(1)
3 4 1 2

1
Where, Z1 = R1 + jC
1 Overall charge in side the box q + q – q – q =
charge
1
Z2 = R2 jC 9. Ans. (3157.56)
2

R2
= 1  jC R
2 2

From equation (1)

R4
 Z2 = R  R (Z1  Z2 )
3 4

Z1  Z2 R3  R 4
 Z2 = R4 vc (t)  vcfinal  [vinitial  vc 'final ] e  t/ RC

Z1 R3 Charging, v c (t)  5  [1.6  5] e  t/ RC

 Z2 = R4
= 5 – 3.4 e-t/RC
R1  1/ jC1  R3 t = t2, vc(t) = 2.4 V
 R /(1  jC R ) = R
2 2 2 4 2.4 = 5 – 3.4 e-t/RC
 C2R 2   1  R 2R 3 3.4 e-t/RC = 26
  R1  C   j C2R1R 2  C  = R
 1   1 4
 3.4 
for the oscillation, imaginary part should be zero. t1  In   RC  0.268  RC
 2.6 
1
C2R1R2 – C = 0 Discharging,
1

1 vc(t) = 0 + (2.4 – 0) e-t/RC


R1C1R 2C 2
90 GATE Previous Solved Questions
-t/RC
= 2.4e
t = t 2, vc(ta) = 1.6 V
-t2/RC
1.6 = 2.4e

 2.4 
t 2  In   RC  0.405  RC
 1.6 
T = t1 + t2 = (0.268 + 0.405)RC
T = 0.673 RC

1
f
0.673RC

1

0.673  10  47  109
4

f = 3157.46 Hz


ANALOG Soil Mechanics & Foundation
EE Engg.
91

7
FUNCTION GENERATOR & 555 TIMER
1. The circuit of figure shows a 555 timer IC connected as an Astable multivibrator. The value of capacitor
‘C’ is 10 nF. The value of the resistors RA and RB for a frequency of 10 kHz and a duty cycle of 0.75
for the output waveform are
VVCC

RA

Th
Vout
RB
555
Tr
C

(a) RA = 3.62 k, RB = 3.62 k (b) RA= 3.62 k, RB = 7.25 k

(c) RA= 7.25 k, RB = 3.62 k (d) RA= 7.25 k, RB = 7.25 k
[2 Marks : GATE-2003]
2. The charge distribution in a metal-dielectric-semiconductor specimen is shown in the figure. The negative
charge density decreases linearly in the semiconductor as shown. The electric field distribution is as shown
in
+ –
+ –
+ –
X
Metal X1 Dielectric X2 Semi X3
Conductor
|E|
(a)
X
|E|
(b)
X
|E|
(c)
X
|E|
(d)
X
[2 Marks : GATE-2005]
 92 GATE Previous Solved Questions
3. IC 555 in the adjacent figure is configured as an Astable multivibrator. It is enabled to oscillator at t =
0 by applying a high input to pin 4. The pin description is l Gnd, 8-supply; 2-trigger; 4-reset; 6-threshold;
7-discharge. The wave form appearing across the capacitor starting from t = 0 observed on the CRO is
+

RA
10K 8
7
RB IC 555 3
10K 2,6
4 1

(a) (b)

(c) (d)

[2 Marks : GATE-2007]


ANALOG Soil Mechanics & Foundation
EE Engg.
93

SOLUTIONS
SOLUTIONSSOLUTIONSSOLUTIONSSOLUTIONSSOLUTIONSSOLUTIONS
SOLUTIONS
1. Ans. (c) 2. Ans. (a)
Given that f = 10 kHz,
Inside metal,
D = 0.75,
C = 10 nF |E| = 0

The frequency of Oscillations from 555 Astable In dielectric,

1
timer is f = 0.69 R  2R C |E| = Constant
 A B
In semi conductor, |E| follows the charge density
1 across the specimen.
R A  2R B =
0.69fC
3. Ans. (b)
1
= Let ‘C’ is initially relaxed then,
0.69  10  10  109
4

When the ‘C’ charges, D-ON and charging time

 R A  2R B = 14.492k (ON) is

 RA  RB  TH = 0.69RAC
and D =  R  2R   0.75  = 10k × C
 A B 

RA = RB = 10k
R A  R B = 0.75  R A  2R B 
‘C’ discharges through RB & C & D – R.B
= 10.869k
TL = 0.69 RBC
 RB =  R A  2R B    R A  R B 
 T = TH + TL = 0.69 (RA+RB)C
= 14.492  10869 D = 50%
= 3.623k
 Charging Time = Discharging time.
 RA = 10.869  3.623  7.246 k

