Lecture Notes from the class

Electron Devices and Components

Course Professor: Luca Selmi
Lab Professor: Paolo Pavan
Universitá degli studi di Modena e Reggio Emilia
A.A 2023/2024

drafted by the students Matteo Biscolli, Giacomo Carletti, Gregory Cordisco,

Matteo Dianati, Oleksandr Kyryliv, Jacopo Nicolini, Lisa Tondelli
Date: October 10, 2024at 16:46

Disclaimer:

This text is an extended verbose commentary to the lectures’ slides. It started as a collaborative
endeavor among students who eventually decided to make them available to Prof. Luca Selmi for
the benefit of future students. Since then, the text received a preliminary scrutiny to eliminate
the main inaccuracies. However, the text still reports only a few of the figures and illustrations in
the slides and by no means is currently complete nor 100% accurate, nor can it substitute critical
scrutiny and study of the other materials provided for preparing the exam (slides, homeworks,
additional, ...).
As of today, besides mere errors, the text could also contain repetitions and relevant omissions
of contents. The symbols are not fully consistent, but if not obvious, their meaning is explained
when they are used. For instance, vectors are denoted as ⃗x or sometimes in boldface characters
(x) notation, or the Fermi level is denoted either as Ef or EF . In general, the mathematical
notation has not been fully aligned yet.
Luca Selmi will be grateful to all students who point out residual errors, typos, inconsistencies,
lack of clarity, and whatsoever suggestions to improve the quality of this material. To this end,
he suggests using the Class Notebook activated for this purpose on Teams.
Contents
0 Introduction 6
0.1 A bird’s eye view of micro- and nano-electronics . . . . . . . . . . . . . . . . . . . 6
0.2 Elements of classical electrodynamics . . . . . . . . . . . . . . . . . . . . . . . . . 6
0.3 Elements of quantum mechanics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
0.4 Elementary solutions of the Schrödinger equation . . . . . . . . . . . . . . . . . . 9

1 Electron and Holes 11

1.1 Elementary notions about Crystals . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2 Silicon Crystal Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3 Band structure model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.4 Energy band diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5 Direct and Indirect band gap materials . . . . . . . . . . . . . . . . . . . . . . . . 19
1.6 Donors and Acceptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.7 Electrons and Holes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.8 Effective Mass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.9 Carrier concentrations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.9.1 Density of States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.9.2 The occupation function . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.10 Electron and holes concentrations . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.11 Fermi level and carrier concentrations . . . . . . . . . . . . . . . . . . . . . . . . 32
1.12 General theory of n and p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1.13 Carrier concentrations at extremely high and low temperatures . . . . . . . . . . 35
1.14 Infrared detectors based on freeze-out . . . . . . . . . . . . . . . . . . . . . . . . 36

2 Device Fabrication Technology 38

2.1 Oxidation of Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.2 Lithography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.3 Projection printing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.3.1 Resolution limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.4 Exposure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.5 Stepper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.6 Resist Lithography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.7 Electron beam lithography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.8 Clean Room . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.9 Pattern Transfer–Etching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.10 Reactive-ion Etching system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.11 Ion implantation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.12 Schematic of an Ion Implanter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.12.1 Channeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.13 Annealing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.14 Thin-Film Deposition/growth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

2
 2.15 Sputtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.16 Chemical Vapor Deposition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.17 Epitaxy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.18 Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.19 Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
2.20 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.21 CMOS fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3 PN Junction 68
3.1 Structure and IV curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.2 Energy Band Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.2.1 Built-in Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.3 Depletion-Layer Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.4 Reverse-Biased PN Junction and Breakdown Effect . . . . . . . . . . . . . . . . . 75
3.4.1 Junction Breakdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.4.2 Zener Tunneling vs. Impact Ionization . . . . . . . . . . . . . . . . . . . . 84
3.4.3 p-i-n diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.5 Forward Biased Junction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.5.1 Current Continuity Equation . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.6 PN diode I-V characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
3.7 PN Junction as Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.8 Contribution from Depletion Regions . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.9 Capacitance-Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 95
3.9.1 Charge in PN Junction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

4 Metal-Semiconductor Junction 99
4.1 Band diagram of the metal-semiconductor junction . . . . . . . . . . . . . . . . . 99
4.2 Fermi Level Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.3 MS junction electrostatics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.4 Thermionic Emission Theory of MS junction current . . . . . . . . . . . . . . . . 108
4.5 Schottky Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4.5.1 Applications of Schottky diodes . . . . . . . . . . . . . . . . . . . . . . . . 114
4.6 Image force barrier lowering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.7 Quantum Mechanical Tunneling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.8 Ohmic Contacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4.9 Dielectric Relaxation Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.10 MESFETs and HEMTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

5 Junction-based Optoelectronic Devices 130

5.1 Photo-generation and photon absorption . . . . . . . . . . . . . . . . . . . . . . . 130
5.2 Carriers Photo-generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.3 Avalanche Photo Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.4 Solar Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

3
 5.4.1 Short-Circuit Current and Open-Circuit Voltage . . . . . . . . . . . . . . 136
5.4.2 Output Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.4.3 Spectral response and efficiency . . . . . . . . . . . . . . . . . . . . . . . . 139
5.4.4 Multi-Junction solar cells . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.5 Light Emitting Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
5.5.1 LED Materials and Structure . . . . . . . . . . . . . . . . . . . . . . . . . 141
5.5.2 LED forward (turn-on) voltage . . . . . . . . . . . . . . . . . . . . . . . . 145
5.5.3 Light transmission efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . 146
5.5.4 White light generation for lightning . . . . . . . . . . . . . . . . . . . . . . 147

6 MOS capacitance 148

6.1 Band structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.2 Surface accumulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
6.3 Surface Depletion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
6.4 Threshold Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
6.5 Strong inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
6.6 Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
6.7 MOS C-V characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
6.8 Non-idealities of the MOS capacitor . . . . . . . . . . . . . . . . . . . . . . . . . 164
6.9 Consequences of fixed Qox and variable Qss . . . . . . . . . . . . . . . . . . . . . 166
6.10 Poly-Silicon Gate Depletion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
6.11 Inversion and accumulation layer and quantum mechanical effect . . . . . . . . . 169
6.12 Equivalent circuit for MOS Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . 171
6.13 Supply of inversion charge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
6.14 Application of MOS Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
6.14.1 CDD Imager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
6.15 CMOS Imager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

7 MOSFET 176
7.1 MOSFET structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
7.2 MOSFET drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
7.3 MOS threshold Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
7.4 Body Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
7.5 Inversion charge for MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
7.6 Channel length Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
7.7 Carrier mobility in MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
7.8 Velocity saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
7.9 Subthreshold region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
7.10 Parasitic source-drain Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
7.10.1 Extraction of the series Resistance and Effective channel length . . . . . . 208

4
8 Advanced MOSFET Concepts 210
8.1 Short Channel Effects (SCE): Threshold voltage roll-off . . . . . . . . . . . . . . 210
8.2 MOSFET scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.3 Mitigation of Short Channel Effects (SCE) . . . . . . . . . . . . . . . . . . . . . . 218
8.4 Alternative gate dielectrics and High K materials . . . . . . . . . . . . . . . . . . 224
8.5 Main issues in conventional Bulk MOSFET . . . . . . . . . . . . . . . . . . . . . 228
8.6 Strained-Silicon technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
8.6.1 Issues with strained-SiGe technology . . . . . . . . . . . . . . . . . . . . . 231
8.7 CESL concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
8.8 Fully Depleted MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
8.8.1 Ultra-Thin-Body SOI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
8.8.2 Producing Silicon-on-Insulator (SOI) Substrates . . . . . . . . . . . . . . . 238
8.9 Advantages of FD (SOI) MOSFET architectures . . . . . . . . . . . . . . . . . . 240
8.10 Multi-gate Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
8.10.1 FinFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
8.11 Device and Process Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
8.12 Future Innovations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
0 Introduction

0.1 A bird’s eye view of micro- and nano-electronics

See slides of the introductory presentation to the course.

0.2 Elements of classical electrodynamics

In classical physics matter is described in terms of point particles, fully described by their inertial
mass m, position ⃗r and momentum p⃗ = m⃗v . Position and momentum can be determined exactly
at any point in time and fully defined the state of a paricle, meaning that once the ⃗r and p⃗
are given at a time instant, the entire particle trajectories in time (future and past) are also
known. Conversely, in classical electrodynamics, we describe electromagnetic radiation with
waves, unambiguously put in evidence by measurable interference and diffraction effects.
In the absence of relativistic effects, classical electrodynamics describes charged particles (e.g.,
electrons) as point charges with rest mass m0 = 0.91 · 10−30 kg and charge −q = −1.6 · 10−19 C.
The particle (electron) position ⃗r and momentum p⃗ = m0⃗v can be simultaneously specified
with arbitrary precision. Electric and magnetic fields exert on the electron a force F orce
⃗ =
−q(E ⃗ where E
⃗ + ⃗v × B), ⃗ is the electric field, ⃗v is the velocity and B
⃗ is the magnetic induction
field. If the force F orce(⃗
⃗ r, t) is known, then given the position and momentum (⃗r, p⃗) of the
particle at the initial time time t0 the particle trajectory is completely and uniquely determined
at all times t by the solution of the equation of motion (Newton’s law)

d⃗
p d⃗v
⃗ =
F orce = m0 . (0.1)
dt dt

Maxwell’s equations in homogeneous isotropic materials can be expressed in terms of an

electrostatic scalar potential ϕ (V) and a vector potential A
⃗ (Vs/m) as:

1 ∂2A⃗
⃗−
∇2 A = −µ0 J⃗ (0.2)
c2 ∂t2
1 ∂2ϕ ρ
∇2 ϕ − 2 2 = − (0.3)
c ∂t ϵ

where ρ is the charge density (C/m3 ), i.e. the Coulombic charge per unit volume, and is generally
a function of space ⃗r and time t, J⃗ the current density (A/m2 ), c the speed of light (m/s). The
scalar and vector potentials A
⃗ and ϕ, respectively, are related to the electric and magnetic
induction fields E
⃗ and B,
⃗ respectively, by the relations

⃗
⃗ r, t) = −∇ϕ(⃗r, t) − ∂ A(⃗r, t)
E(⃗ (0.4)
∂t
⃗ ⃗
B(⃗r, t) = ∇ × A(⃗r, t) (0.5)

The solution of Maxwell’s Eqs.0.3 can be formulated in terms of retarded potentials and reads

6
(R = |⃗r − r⃗′ |):
Z
µ0
⃗
A(⃗r, t) = R−1 J(
⃗ r⃗′ , t − R/c)dr⃗′ (0.6)
4π r⃗′
Z
1
⃗
ϕ(⃗r, t) = R−1 ρ(r⃗′ , t − R/c)dr⃗′ (0.7)
4πϵ r⃗′

The physical dimensions of electron devices are most often much smaller than λ = c/f for all
frequencies of interest. For instance, the dimensions of devices for digital VLSI microelectronics
are Rdev ≪1 µm= 1 · 10−6 m, while the cut-off frequency fT of some of the fastest electron
devices nowadays are ≈ 1 THz= 1012 Hz; therefore, λ = c/f ≃ 3 · 108 /1012 ≃ 3 · 10−4 m≫
R. Consequently, for devices (but not necessarily for the interconnections among them) the
dimensions are much smaller than the signal wavelength and we can embrace a quasi-static
approximation neglecting propagation effects. For a homogeneous isotropic medium this leads
to:

⃗ = −µ0 J⃗
∇2 A (0.8)
ρ
∇2 ϕ = − (0.9)
ϵ

where ϵ is the dielectric permittivity. For inhomogeneous isotropic media, whose material prop-
erties are space-dependent scalar quantities, i.e. functions of ⃗r but otherwise independent of the
direction (e.g. ϵ = ϵ(⃗r)), we have

⃗ = ∇ · (ϵE)
∇·D ⃗ = −ρ . (0.10)

In the special case of homogeneous materials, which will be often considered in the following
chapters, Eq.0.10 boils down to Eq.0.9, which is often referred to as Poisson’s equation. Eq.0.10 is
of key importance in the study of electron device operation, since it rules the device electrostatics.
An expression for the ρ in semiconductors to be used in Eq.0.10 will be derived in the following
chapters.
Notice that to study electron devices, a continuous mean field approximation is used. There-
fore ϕ is the electrostatic potential due to averaged charge distributions and externally imposed
electric fields which vary smoothly over large distances compared to the atomic distance (i.e.,
neglecting the ensemble of Coulomb potentials generated by the atom).

7
0.3 Elements of quantum mechanics
As exploration of the properties of nature proceeded toward the atomic distance scale, it became
evident that classical mechanics was inadequate to provide comprehensive and detailed descrip-
tions and predictions of mechanical and electrical phenomena. Quantum mechanics and more in
general quantum physics extended the realm of classical mechanics starting at the beginning of
the XXth century.
According to quantum mechanics, at the atomic distance scale matter can be described by
functions of real space and time (i.e., fields), usually named wavefunctions in the context of
quantum mechanics, and denoted in the following as Ψ = Ψ(⃗r, t). The wavefunction is a scalar
(as opposed to vector) complex field (i.e., constituted of a real and an imaginary part). While it
is difficult to attribute a clear physical meaning to the wavefunction Ψ of a particle, it is generally
accepted that the squared modulus of Ψ can be interpreted as the probability of finding a particle
in a specific point in time and space. In other words, |Ψi(⃗r, t)|2 is the probability density function
(PDF) of the particle distribution in space at time t.
In quantum mechanics particles are classified in two families: Fermions (e.g. electrons) are
the ones that obey the Pauli exclusion principle which states that at most two Fermions with
opposite spin can occupy a given quantum state. Bosons (e.g. phonons) who do not obey such
principle. In addition to Pauli exclusion principle, it is important to highlight that in quantum
mechanics, pairs of physical quantities exist whose values cannot be simultaneously determined
with precision. A notable example of one such pair is the position ⃗r and momentum p⃗ of
a particle. The unavoidable uncertainty resulting when performing the measurements cannot
be eliminated by using more accurate instrumentation. This is usually known as Heisenberg
uncertainty principle.
wavefunctions are determined as the solutions of the Schrödinger equation. In particular,
the wavefunction of a particle with mass m in an electrostatic force field of potential energy
U satisfies the Schrödinger equation (hereafter expressed in the engineering notation; physicists
notation adopts a sign change which has no practical consequence on our calculations):

∂Ψ(⃗r, t) h̄2 2
jh̄ = ∇ Ψ(⃗r, t) − U (⃗r, t)Ψ(⃗r, t) (0.11)
∂t 2m
√
where h̄ = h/2π = 1.05 · 10−34 Js and j = −1. Eq.0.11 is homogeneous in Ψ. Therefore, Ψ
and AΨ with constant A are both solutions of the Schrödinger equation and the amplitude of
the wavefunction cannot be determined uniquely by Eq.0.11.
However, if the particle is contained in a region of space Ω, then the probability of finding it
in Ω must be equal to one. Therefore, the wavefunction is subject to the normalization condition
Z
|Ψ(⃗r, t)|2 d⃗r = 1 . (0.12)
Ω

Imposing the normalization condition to the solution of the Schrödinger equation allows us to
calculate the wavefunction amplitude, that is the proportionality coefficient A such that AΨ
satisfies Eq.0.12.
The interpretation of |Ψ(⃗r, t)|2 as the PDF of the particle described by Ψ(⃗r, t) entails that

8
the probability to find the particle in a volume V within Ω is the given by:
Z
PΨ = |Ψ(⃗r, t)|2 d⃗r . (0.13)
Ω

Due to the normalization condition PΨ will then be a number between 0 and 1, as it should be
for a probability.
The dualism established by quantum physics between particles and waves (fields) extends
beyond the boundary of mechanics. Indeed, in quantum physics the electromagnetic waves
(fields) can be described in terms of particles denoted photons with energy given by Eph = hν =
h̄ω where h is Plank’s constant (6.62 · 10−34 J s) and h̄ = h/2π. Similarly, mechanical oscillations
of the atoms around their rest positions which propagate in the material as elastic (sound) waves,
can be described not only as waves but also as particles, denoted phonons. We will encounter
phonons again when examining charge carriers’ motion in the semiconductors.

0.4 Elementary solutions of the Schrödinger equation

Let the potential energy U = U (⃗r) be independent of time and let’s assume the wavefunction
can be factorized in the form: Ψ(⃗r, t) = Ψ(⃗r) · ϕ(t). Substituting this expression in Eq.(0.11)
and dividing both terms by Ψ(⃗r, t) we get:

h̄2 2
  
∂ϕ(t) 1 1
jh̄ = ∇ − U (⃗r) Ψ(⃗r) (0.14)
∂t ϕ(t) 2m Ψ(⃗r)

The RHS is a function of t only while the LHS is a function of ⃗r only; since the two terms
must be equal for any ⃗r and t they must be equal to the same constant. Let’s denote the constant
−E, (E is the total particle energy, not shown in these notes). We get:

dϕ(t) E
= j ϕ(t) (0.15)
dt h̄

h̄2 2
∇ Ψ(⃗r) + (E − U (⃗r)) Ψ(⃗r) = 0 (0.16)
2m
Eq.(0.15) entails:
ϕ(t) = A · exp (jEt/h̄) = A · exp (jωt) (0.17)

Eq.(0.16) is called Schrödinger equation for steady states or stationary Schrödinger equation,
and its solution Ψ(⃗r) describes a steady state with precisely defined energy E and clearly with
constant probability density versus time, since |ϕ(t)|2 =|Aexp (jωt) |=A2 is independent of time.
Let’s consider the special case where U = U (⃗r) is actually independent of position (U =constant).
Since the gradient of the potential energy is zero the particle is free to move in space with given
energy E and momentum p⃗. The wavefunction for this particle is (engineering notation):

Ψ(⃗r, t) = A · exp(jωt)exp(−j⃗k · ⃗r) (0.18)

as is easily proven by substitution of Eq.0.18 into Eq.0.16. The angular frequency ω and the

9
propagation vector ⃗k obey the so called Einstein relations:

E = hf = h̄ω (0.19)

p⃗ = h̄⃗k . (0.20)

Substituting Eq.(0.18) in the Schrödinger equation (propagation along x: ⃗k ·⃗r = kx x) we get:

h̄2 kx2
E = h̄ω = +U (0.21)
2m

which is the classical expression of the particle energy as the sum of a potential and a kinetic
energy term:
p|2
|⃗
E= +U (0.22)
2m
Thus, the Schrödinger equation reveals an important physical meaningas expression of the total
energy of the particle according to quantum mechanics. With an appropriate choice of the energy
reference we can set U = 0; thus:
h̄2 k 2
E(k) =
2m
which is named dispersion relation for the wavefunction of the free particle. As in similar wave
propagation problems (e.g. in electromagnetism), the dispersion relation links the angular fre-
quency of the waves ω with the wavevector ⃗k, and it is derived by substituting the functional form
of the solution Ψ(⃗r) into the stationary Schrödinger equation. In semiconductor device physics
the dispersion relation is also denoted band structure of the material is and given in terms of
E = E(⃗k). The ⃗k is a vector parallel to the direction of propagation with unit measures of an
inverse length (|⃗k| = 2π/λ). ⃗k and the phase velocity of the waves are related as: ⃗vp · ⃗k = ω. the
direction of ⃗vp coincide with those of ⃗k.
The plane wave in Eq.(0.18) is a solution of Eq.(0.11). The corresponding solutions of the
stationary equation 0.16 in one spatial dimension x take the forms exp(±jkx x), sin(kx x) or
cos(kx x).
Equation 0.18 describes a particle with precisely defined energy (corresponding to the angular
frequency ω = E/h̄, Eq. 0.19) and momentum (related to the propagation vector as in Eq. 0.20.
Such particle is completely de-localized in real space (as it is in time any solution of the stationary
Schrödinger equation), because |Ψ(⃗r, t)|2 = Ψ(⃗r, t) · Ψ(⃗r, t)∗ = A2 is independent of ⃗r and t, so
there is no preferential time or location where to find the particle.

10
1 Electron and Holes
1.1 Elementary notions about Crystals
A 3D crystal can be represented by a Bravaix lattice and a base. The Bravaix lattice in three
dimensions is a set of points with coordinates

3
X
⃗ ⃗n =
R ni⃗ai (1.1)
i=1

where ⃗ai are non-coplanar vectors, and the ni are integers ⃗n=(n1 ,n2 ,n3 ). The Bravaix lattice
defines the symmetries of the crystal. Observers located at the symmetry points see the same
arrangement of atoms while looking around themselves in all space directions.
In general, the choice of the ⃗ai vectors is not unique. The base defines the position of the
atoms around each symmetry point with respect to the Bravaix lattice.
Notable examples of Bravaix lattices are the: cubic (a), body centered cubic (b), and face
centered cubic (c) lattices in figure 1.1.

Figure 1.1: Cubic, body centered cubic (BCC) and face centered cubic (FCC) reticles.

Denoting x̂, ŷ and ẑ the unit vectors along the Cartesian axes we have:
Cubic lattice: ⃗a1 =a0 x̂, ⃗a2 =a0 ŷ, ⃗a3 =a0 ẑ
Body centered cubic (BCC) lattice: two points for each cube located at (0, 0, 0) and a0
2 (x̂, ŷ, ẑ)
Face centered cubic (FCC) lattice: four points in each cube located at (0, 0, 0), a0 (x̂ + ŷ)/2,
a0 (ŷ + ẑ)/2, a0 (ẑ + x̂)/2.
Figure 1.2a introduces a convenient method for denoting the orientation of directions and
planes in silicon crystals. The cube represents the silicon unit cell, with darkened surfaces
representing crystal planes. Each of these crystal planes is characterized by a specific set of
Miller indices, such as the (100) plane, perpendicular to the x-axis of the cubic cell, the (011)
plane, the (111) plane, perpendicular to the cube diagonal, and so forth.

11
Figure 1.2: (a) A system for describing the crystal planes. (b) Silicon wafers are usually cut
along the (100) plane. This sample has a (011) flat to identify wafer orientation during device
fabrication.

Individual planes are by convention denoted with Miller indexes within round parenthesis,
as in the examples above. The specific direction perpendicular to a given plane is denoted with
Miller indexes closed by square parenthesis, e.g. [010] for the positive y-axis direction. The
corresponding negative direction is usually denoted [010] or [01’0]. In general, crystal planes are
not equivalent to each other. For instance, the area density of atoms on the surface of a (100)
plane is not the same as that of a (111) plane. The atoms’ density on the surface of the wafer is
especially relevant, impacting factors like the rate of oxidation and the electronic quality of the
oxide/semiconductor interface. Therefore, it is important to know the orientation of the crystal
planes and crystal axis directions with respect to the wafer surface upfront of fabrication.
In order to precisely orient the wafer as desired during the fabrication process, a flat or a notch
is cut along the (011) direction. Silicon wafers, fundamental components in the production of
semiconductor devices, are most often cut along the (100) plane to ensure uniformity and optimal
device performance.
Notice that numerous equivalent directions exist due to the diamond crystal’s cubic structure;
for instance, the x-, y-, and z-axis are perfectly equivalent. Similarly, the (011), (101), and (110)
planes feature the same arrangement of atoms and atoms’ area density. when reference has to be
made to sets of equivalent directions or equivalent planes, then the Miller indexes are grouped
by angled or curled parenthesis, respectively. In summary, the following convention applies to

12
denote directions and planes with Miller indexes.

[100] specific direction (1.2)

<100 > set of equivalent directions (1.3)
(100) specific plane (1.4)
{100} set of equivalent planes (1.5)

In summary: one plane: (i,j,k); one direction: [i,j,k]; a family of equivalent planes: {i,j,k}; a
family of equivalent directions ⟨i,j,k⟩
Last but not least, we remind that the crystal periodicity in three dimensions is determined by
the translation vectors R⃗ ⃗n where all points in the reticle can be expressed as (integers n1 , n2 , n3 ):

⃗ ⃗n = n1 a⃗1 + n2 a⃗2 + n3 a⃗3

R .

For novel materials of interest in modern nanoelectronics, such as transition metal dichalcogenides
and other so-calledtwo-dimensional (2D) materials the mathematical framework illustrated above
still holds provided only two vectors ⃗a1 and ⃗a2 are considered.

1.2 Silicon Crystal Structure

The structural arrangement of atoms in pure silicon crystals is represented in Figure 1.3, where
a large cubic unit called the unit cell is depicted. Each sphere within this unit cell represents a
silicon atom, and this unit cell serves as the foundational element of this material. By repeating
extensively this cubic cell in all three spatial dimensions a complete silicon crystal is formed.
A key parameter of the cubic crystalline lattice is the lattice constant, usually denoted a0 ; it
represents the length of the edge of the cube. For silicon a0 =5.43 Å=0.543 nm. The periodicity
of the crystal structure is defined by the locations of its symmetry points. For silicon, these
points lie at the vertices and at the centers of the faces of the cube. Hence, the name of this
structure; namely: face-centered cubic (FCC). Each symmetry point is associated to one and the
same group of atoms, called the base. For silicon, the base is made of two atoms; one located
at the symmetry point; the second one located along the cube diagonal, at one-fourth of the
distance to the opposite vertex of the cube.
In the Silicon crystal, the atoms lie at all symmetry points of two FCC lattices (each having
an edge of length a0 =5.4 at room temperature) one shifted by 1/4 of the cube diagonal with
respect to the other. We can think of the Si lattice as an FCC lattice with diatomic base.
In other words, we can generate the silicon crystal by: 1) interleaving two FCC reticles
displaced along the cube diagonal direction by one-fourth its length, and 2) placing one atom at
each symmetry point of the two reticles.
Notice that the cubic cell is not the smallest cell that can generate the whole crystal upon
periodic repetition.

13
Figure 1.3: The cubic unit cell of the silicon crystal. Each sphere is a Si atom. Each Si atom has
four nearest neighbors as illustrated in the small cube with darkened atoms. The interatomic
distance of nearest neighbor atoms is 0.235 nm = 2.35 Å.

Intriguingly, every silicon atom within the crystal has four other silicon atoms as its nearest
neighbors. These atoms are located at the vertices of a regular tetrahedron having the atom
at the center. Silicon, a Group IV element on the periodic table, is endowed with four valence
electrons, which naturally form four covalent bonds with its neighboring silicon atoms. The angle
between any two bonds is 109.5o . These bonds form a strong covalent crystalline structure with
high stability and integrity.
This structural configuration, known as the diamond structure, shares its name with the
diamond crystal, where each sphere represents a carbon atom. It is worth noting that germanium
(Ge), another semiconductor material of great significance, also exhibits the diamond crystal
structure. A few binary compound semiconductors, for instance Gallium Arsenide, are formed
by pairs of group III and group V atoms, and share with Silicon the FCC symmetry. In this
case, however, the crystal is of the so-called zinc-blend type.

1.3 Band structure model

The energy band model is a fundamental concept in understanding the electrical and optical
properties of materials, and the behavior of charge carriers therein.
To introduce the concept of energy bands we start by reminding within an atom with atomic
number Z, the charge of the Z protons in the nucleus (+Zq) is balanced by that of an equal
number of electrons. The Coulomb force field generated by the nuclei is inversely proportional
to the distance squared and can be described by a scalar potential

U (⃗r) = −Zq 2 /4πϵ0 r , (1.6)

where r = |⃗r|; that is, a spherical potential well with amplitude inversely proportional to the
distance.
This potential well tends to confine the electrons in proximity to the nucleus and the confine-

14
ment induces quantization of the energy levels. Indeed, electrons distribute themselves on the
discrete energy levels (orbitals) inside the potential well. The corresponding wavefunctions have
oscillatory behavior in the classically permitted region where the electron energy is larger than
U and rapidly decay toward zero in the classically forbidden region where E < U .1
However, when two identical atoms come close, a significant change occurs due to the Pauli
exclusion principle. This principle states that in an electron system, such as an atom, molecule,
or crystal, each quantum state can be occupied by no more than two electrons with opposite spin.
As a result, if atoms are close enough to generate a significant overlap between the respective
electron wavefunctions in the same state, then their energy levels must split.
Let us now perform a so-called gedankenexperiment 2 , that is, a thought experiment mentally
conducted according to the law of physics, usually assuming idealized conditions free of additional
phenomena that could disturb such an experiment, or even make it impossible in practice. In
particular, imagine extending the above test to a bulk crystal where many 3 atoms, equally
spaced along the x-, y- and z-axis, are brought into close proximity by reducing their interatomic
distance.

Figure 1.4: Energy levels of a multitude of atoms as a function of atomic distance.

In other words we build-up a crystal from many separate atoms whose atomic spacing a is
progressively decreased until the equilibrium value a0 is reached. As visible in Fig.1.4, when a
is large the atom interations are essentially negligible and each atom will behave as if it where
isolated in space. As a result, only the discrete energies of the atomic orbitals are seen at the
right of the figure, As a is reduced the electron’s wavefunctions of the highest energy orbitals
interfere with each, and the atoms behave as part of the same system. The quantized energy
levels start splitting apart and spreading over a finite energy interval because Pauli’s principle
excludes the possibility for them to keep having all the same value as in the isolated atom. These
1
This point is easily demonstrated projecting the stationary Schrödinger equation, Eq.0.16 in one direction
(e.g., x) and recognizing that if E − U is positive (classically permitted region), then the wavefunction Ψ and its
second order derivative (curvature) have opposite sign; hence, Ψ necessarily oscillates. Conversely, if E − U is
negative (classically forbidden region) then Ψ and its second-order derivative (curvature) have the same sign, and
then Ψ is forced to decay to zero.
2
The terminology "gedankenexperiment" became popular after its extensive use by Albert Einstein for illus-
trating relativity theory. However. the introduction of thought experiments can be traced back to the Dutch
chemist Hans Christian.
3
In this context we can think of "many" as a quantity in the order of Avogadro’s number NAv ≃ 6, 022 × 1023

15
intervals (called energy bands) are separated by gaps where no electron state is present. In other
words the shift in energy generates bands of allowed energy states separated by band gaps. (see
figure 1.5).

Figure 1.5: Schematic illustration of the transition between orbitals in atoms and energy bands
in a uniform homogeneous semiconductor crystal slab at equilibrium and room temperature. The
x-axis represents real space.

The energy difference between consecutive levels is so tiny (due to the very large number of
interacting atoms in the crystal) that we can neglect energy quantization and assume a continuum
of allowed electron energy states within a band.
The first bands to form when the atoms are still well separate, correspond to the highest
energy orbitals, i.e. those hosting the outermost (valence) electrons, whose wavefunctions extend
to larger distances from the nuclei. The electrons represented by these wavefunctions will be the
first ones to interact as we reduce the atomic distance.
An energy band is an energy range containing a very large number of energy states essentially
forming a continuum, each of which can be occupied (or not) by an electron. The ensemble of all
bands and band gaps is denoted as the band structure of the material. Electrons have a natural
tendency to fill up the lower energy bands first. As we move lower in energy, the bands become
entirely filled. In a semiconductor, for instance, most of the low energy bands are fully occupied
at absolute zero temperature, while the higher energy bands remain predominantly empty.
As discussed in more detail in Sect.1.4, the highest (in energy) fully occupied band at zero
Kelvin, i.e. when all electrons collapse in the lowest energy (ground) states available, is defined
valence band. The lowest energy band which is partly or fully unoccupied (empty) at zero Kelvin
is called the conduction band, and immediately follows the valence band as we increase energy.
The band gap between the conduction and valence bands is a material property; therefore, in
a uniform semiconductor, the band gap remains constant throughout the material as illustrated
in Fig.1.5. The band gap weakly decreases with increasing temperature4 and is essentially un-
affected by the electric field. The band energy model is crucial for understanding the electrical
properties and the behavior of semiconductors, which are vital components in modern electronics.
As temperature increases, electrons can jump from states in fully occupied band to states in a
partially or completely empty band, these transitions being more likely if the band gap is small.
Therefore, for a semiconductor, both the valence and the conduction band states are partially
4
For instance in silicon EG ≃1.17 eV at 0 K and EG ≃1.12 eV at 300 K

16
filled by electrons at temperatures larger than zero Kelvin.
The valence and the conduction bands are of particular significance in semiconductors. The
reason for this special interest is that the average ensemble velocity of electrons within a fully
occupied band is mathematically equal to zero. Therefore, electrons in a fully occupied band
cannot contribute to net current conduction, much like water in a completely filled bottle doesn’t
slosh about. Similarly, an empty band cannot contribute to current conduction, for the simple
reason that it contains no charge carriers.
The electron states of the conduction and valence bands correspond to de-localized electron
probability density, similar to the case of free particles described by de-localized plane waves.
Electrons occupying these states behave as a gas of quasi-free particles partly analogous to an
ideal gas of classical particles. Provided the band is not completely empty or completely full,
electrons in the conduction and valence bands can move over macroscopic distances thanks to
their quasi-free particle nature. Therefore, it is the valence band and the conduction band that
play pivotal roles in enabling current flow within a semiconductor over macroscopic distances.
Achieving controlled current flow under specific stimuli is exactly what we want to obtain in
electron devices.

1.4 Energy band diagram

An energy band diagram is a visual representation of the most relevant energy levels that electrons
can stably occupy in a crystalline material as a function of position. It provides a succinct and
clear view of the energy distribution of the energy levels that electrons can occupy in stationary
(not necessarily equilibrium) conditions within a material. The vertical axis of an energy band
diagram is the electron’s total energy. The horizontal axis is used to depict the spatial position
within the material. In a uniform, homogeneous bulk semiconductor of infinite size, and in the
inner part of a uniform and homogeneous semiconductor slab with finite dimensions large enough
that any perturbation induced at the boundaries by the termination of the crystal continuity
has decayed to zero, the allowed energy levels will be independent of position and, therefore,
the band diagram will be flat, that is, all relevant energies will be constant and independent of
position, as depicted in Fig.1.6. The energy band diagram usually comprises the highest energy
level belonging to the valence band (denoted EV ) and the lowest energy level belonging to the
conduction band (denoted EC ). The energy interval between these two levels is the Energy gap,
whose amplitude is denoted EG .

17
 Figure 1.6: The energy band diagram of a semiconductor.

Conductors, Semiconductors, Insulators

As illustrated in Fig.1.7 a conductor is a material where at 0 K the conduction band is partially

filled by electrons.
A semiconductor is a material where at 0 K the conduction band is completely empty and the
valence band is completely full of electrons.
An insulator is also a material where at 0 K the conduction band is empty and the valence
band is full (as for semiconductors). Still, in this case, the band gap is usually much larger than
for semiconductors (several eV, as opposed to about 1 eV). Indeed, semiconductors with large
band gaps are sometimes denoted as semi-insulators. It is clear that in general numerous band
gaps exist, separating the energy bands that originate from the different electron shells in the
atoms. However, since we restrict our interest to electronic processes involving the conduction
and valence bands, we will call band gap the one separating the conduction and valence bands,
(as if it were the only existing band gap). For completeness, we underline that the concept of
energy bands naturally follows from the principles of quantum mechanics applied to crystalline
materials. However, numerous materials (mostly insulators) are used in microelectronics in dis-
ordered or amorphous forms (e.g., SiO2 , HfO2 , Si3 N4 , IGZO, etc.). For our purposes, and based
on experimental observations, in most cases we can treat these insulators as having conduction
and valence bands and band gaps as if they were crystalline, but also having additional states
distributed across the band gap in the form of band tails and/or discrete localized states (traps).
More on this topic will be explained when discussing heterogeneous interfaces, MOSCAPs and
MOSFETs.

18
Figure 1.7: Energy band diagrams for a semiconductor (a), an insulator (b), and a conductor
(c).

1.5 Direct and Indirect band gap materials

We can classify materials according to the direct or indirect nature of their band gap. To
understand this definition, we are forced to recall some basic concepts of quantum mechanics
Electrons in the conduction and valence bands of bulk crystalline materials can be described
either as quasi-free particles or as quasi-plane waves with rather uniformly distributed probability
density. In fact (see Sec.0.4), according to quantum mechanics, a free particle is described as a
plane wave with wavefunction (in one dimension):

ψ(x, t) = Ae−jkx x ejωt (1.7)

2π
kx = (1.8)
λ

where kx is the wavevector and λ the wavelength. According to Einstein relations the particle
energy (E) and momentum (px ) relate to ω and kx as:

E= h̄ω (1.9)
px = h̄kx , (1.10)

(similar equations hold for the y and z directions). By analogy with the free electron case, we
can think that the quasi-free electron states of the crystal will be characterized not only by their
energy (related to the angular frequency of the wavefunction) but also by their wavevector.
In crystals, energy and wavevector of stationary electron states are not independent; instead,
for each wavevector only a precise sequence of discrete energies is allowed. For each momentum
and energy, at most two electrons with opposite spin can occupy the state. The energy-wavevector
relation of quantum mechanics is often denoted as band structure (E(⃗k)) of a given material.
The band structure is a periodic function of ⃗k; in the simple case of cubic, FCC and BCC
lattices the period is given by 2π/a0 . Each material has its band structure; the band structure
defines many of the fundamental electrical and optical properties of the material. Let us now
draw the E(⃗k) relation in an energy-wavevector plane comprising the band extremes EC (k⃗C ) and
EV (k⃗V ) (Fig.1.8)5 . In this diagram, the edges of the valence band (EV ) and the conduction band
5
For the most relevant semiconductor devices k⃗V = 0

19
(EC ) correspond to a maximum and a minimum of the E(k) curves, respectively. The distance
between kC and kV is obviously smaller than the period of E(⃗k) (2π/a0 for cubic crystals). If the
maximum and the minimum occur at the same point in wavevector space, then the material has
a direct band gap. In this case, an electron transitioning from the valence band to the conduction
band with the minimum possible energy exchange can do so by changing only its energy without
altering its momentum (Fig.1.8a).
Conversely, in materials with an indirect band gap, the band maximum and minimum are
located at different positions in wavevector space. This means that electrons transferring from
the valence band to the conduction band must also change their momentum.

Figure 1.8: Band structure of a: (a) direct band gap material; (b) indirect band gap material.
CORREGGERE GRAFICO

The interband transition of electrons from a stationary state in one band to a different sta-
tionary state in another band is a transient process and entails the interaction of the electron
with other particles. Since the transition must conserve total energy and momentum, the addi-
tional particle(s) involved must carry energy in the order of the band gap energy and, for indirect
band gap materials, momentum in the order of the difference between the wavevectors at the
two extremes.
Photons (that is, quanta of electromagnetic radiation) can carry appreciable energy

c 1.24
Eph [eV ] = hν = h = , (1.11)
λ λ[µm]

where λ is the photon wavelength, ν the frequency, and c the speed of light. However, they have
negligible momentum. In fact:

2π 2πEph 2π
kph [eV ] = = ≪ . (1.12)
λ hc a0

Therefore, radiative processes across the band gap, involving only electrons in states near
the minima/maxima of the conduction/valence bands6 and the emission/absorption of photons
can only occur in direct band gap materials. The direct or indirect nature of the band gap has
a significant impact on the electro-optical properties of semiconductor materials, which involve
radiative processes.
6
For a detailed analysis of the average energy of electrons in the conduction and valence band refer to section??

20
In materials with a direct band gap, it is more likely for electrons to be excited from the valence
band to the conduction band (or fall back from the conduction to the valence band) with ra-
diative processes involving the interaction of the electron with only a photon. This makes them
ideal for optoelectronic applications such as light-emitting diodes (LEDs), lasers, and solar cells.
In materials with an indirect band gap, the efficiency of this process is definitely smaller7 . When
photons interact with electrons, they can alter the energy of electrons without significantly affect-
ing their momentum. Typically, a third particle, known as a phonon, has to be involved, which
facilitates changes in momentum. Most often, such particles are the phonons. Phonons represent
atomic scale atoms’ displacements and vibrations within the material’s lattice structure. Most
phonons carry small or negligible energy compared to Eg , but significant momentum compared
to |kV − kC |. It is then clear that interband transitions in indirect band-gap materials should be
assisted by both photons and phonons, in a complex multiparticle process that is generally much
less likely to occur than a relatively simple radiative transition. In some scenarios, when an elec-
tron absorbs a photon’s energy, it can be promoted to a higher energy band. If the energy of the
photon exceeds the band gap (Eg ), the electron can reach the conduction band. This interaction
results in the creation of a hole in the valence band and a free electron in the conduction band,
which can conduct electric current.

Figure 1.9: Photon-electron interaction.

Radiative transitions can be usefully exploited to determine the band-gap energy (Eg ). One
common approach involves measuring the absorption of light by the semiconductor as a function
of the photon energy (hν). Strong absorption occurs when the photon energy (hν) is greater
than or equal to the band gap (Eg ). As the photon energy is reduced below the band gap (Eg ),
the material becomes transparent to the incident light. This critical photon energy, where the
transition from absorption to transparency occurs, is used to determine Eg . This phenomenon
is known as Radiative Generation while the complementary process is Radiative Recombination,
where an electron loses energy and can recombine with a hole, potentially emitting a photon in
the process.
7
Of course the material can still be useful in non-optoelectronic applications, such as the fabrication of tran-
sistors (BJTs), etc

21
1.6 Donors and Acceptor
In a perfectly periodic crystal structure, the allowed energy states for electrons are grouped in
bands, with an essentially continuous distribution of states in energy. These are extended states,
corresponding to wavefunctions distributed over the whole crystal. If some of the atoms are
replaced with different ones it is reasonable to believe that a local perturbation will be generated
in the band structure, possibly resulting in electron states that do not belong to the valence or
the conduction band of the original pure crystal.
A notable example of this situation takes place when atoms belonging to groups of the periodic
table adjacent to the one forming the crystal (e.g., group III and group V atoms for a silicon
crystal), substitutionally replace some of the crystal atoms. In this situation, the substitutional
impurity forms z+1 or z-1 bonds with its nearest neighbors (where z is the valence of the atom).
The excessive (or missing) electron corresponds to a localized energy state with limited extension
around the impurity and with slightly different energy w.r.t. the band edges of the material.
Impurities with this behavior are called dopants; they can appreciably alter the electronic and
optical properties of the material.
If the additional states lie slightly below the conduction band edge we refer to them as donors;
if slightly above the valence band edge we denote them acceptors. Collectively, we denote them
dopants. Therefore, in the band model, two additional energy levels play a significant role: the
donor energy level Ed and the acceptor energy level Ea , as illustrated in Figure 1.10. As long as
the doping concentration is much smaller than the crystal atoms concentration these impurities
will be well separated in the crystal and essentially non-interacting. Therefore Pauli’s principle
will have negligible effect and we can regard them as localized and independent discrete states,
not forming a continuous band in the same sense we introduced the band concept.

Figure 1.10: Energy levels of donors and acceptors.

Donor atoms introduce additional electrons into the semiconductor lattice. For these extra
electrons to become conduction electrons and contribute to electrical conductivity, they need to
be liberated from the donor atoms, by supplying them energy, which is typically around a few
tens of meV, that is, comparable to the electron average kinetic energy per particle at room
temperature. This energy is also referred to as thermal energy and it is predicted by statistical
mechanics as
3
Eth = kB T ≃ 40 meV at room temperature (300 K) . (1.13)
2
If carriers are captured or released in these extra states of the dopant atom, then an ion will
form or disappear at the fixed position of the dopant. Thus, Ec − Ed and Ea − EV represent the
donor/acceptor ionization energy, that is, the energy needed to add or subtract the additional

22
electron from the pool of electrons occupying extended band states, and therefore available to
participate in conduction. With reference to donors, the release of the electron from the donor
state to the conduction band state leaves behind a positively charged ion at the fixed location
of the group V atom. Note that if the ionization energy is in order of the average thermal
kinetic energy per carrier Ek = 23 kB T the electron can frequently and spontaneously jump into
the conduction band by itself, with no need of any additional energy contribution from external
sources. Therefore, even at equilibrium, We expect most of the donors to be ionized and most
of the respective electrons in the donor states to be transferred to the conduction band.
Similarly, acceptor atoms act by accepting electrons from the valence band, thus leaving an
unoccupied, empty state in the valence band (denoted as a hole). The energy required for this
capture is known as the acceptor ionization energy, represented as Ea − Ev . This energy
represents the amount needed for a neutral acceptor atom to capture an extra electron from the
valence band, thus transforming into a negatively charged fixed ion at the dopant location and
creating a mobile positive charge (the hole) in the extended states of the valence band. In the
context of silicon, elements of the group V of the periodic table, for instance: As (arsenic), P
(phosphorus), Sb (antimony), and atoms of the group III such as B (boron) and In (Indium) are
frequently used as dopants to introduce donor or acceptor levels.

1.7 Electrons and Holes

As already mentioned in section ??, the conduction and the valence bands are the only ones
partially filled by electrons at the temperatures of interest for electron device operation. Since
electrons in a completely full or empty band do not contribute to the macroscopic current,8 Since
our interest goes mostly to the current carried by the semiconductor devices, then it is clear that
unless otherwise stated when we refer to electrons we actually mean electrons in these two bands.
As regards electrons, the energy band diagram illustrates that a higher position in the energy
band corresponds to a higher electron energy. The minimum energy level for electrons in the
conduction band is by definition Ec . According to a quite general result of quantum mechanics
applied to crystalline solids9 EC represents the potential energy of the electrons in the conduction
band. Any contribution to the total electron energy in excess of Ec represents the electron’s
kinetic energy. Electrons can gain kinetic energy by accelerating in an electric field or lose
energy due to collisions with imperfections within the crystal lattice. Holes, on the other hand,
represent the absence (vacancy) of electrons in the valence band. It can be demonstrated that the
hole energy increases in the opposite direction as the electron energy, i.e. moving downward in
the energy band diagram. Furthermore, according to quantum mechanics the top of the valence
band, i.e. EV , represents the potential energy of the holes. For the purpose of electrostatics and
charge transport studies, the holes (i.e. the unoccupied states of the valence band) behave as
positively charged particles, carrying a charge of +q. Therefore, we can compute the contribution
of the valence band to the total current either by counting the contribution of each electron with
8
This non-trivial statement stems from the symmetry properties of the bands. In any band, for any state with
wavevector k and energy E there is another state with wavevector −k at the same energy. These states correspond
to electrons moving with the same velocity but in opposite directions, therefore giving a net zero current. Since
this is true for all ks and all energies in the band, then electrons in a completely full band carry no current.
9
The so-called effective mass theorem.

23
its negative charge or by counting the holes and attributing them a positive charge +q.

Figure 1.11: Representation of the electron’s and the hole’s energy in the band model.

A lower position on the y-axis of the energy diagram represents a higher energy level for holes.
Moving a hole "downward" in the band diagram at an energy below EV means increasing the
hole’s total energy. Any excess hole energy with respect to EV corresponds to kinetic energy,
acquired either by external electric fields or by interactions with, e.g., photons or phonons.
Visualizing holes as bubbles floating upwards within the energy band provides a helpful analogy,
while electrons can be thought of as water droplets that tend to descend to the lowest energy
states in the band.

1.8 Effective Mass

In order to describe the motion of electrons and holes with the laws of motion applicable to
classical particles, that is, Newton’s law, we must assign an inertial mass to them. For the quasi-
free electrons and holes in semiconductors, it turns out that this mass is not the rest mass of
the particle (that is m0 = 9, 11 · 10−31 kg for electrons) but a different, effective value. In order
to derive the expression of the effective mass, we remind that in order to describe a spatially
confined distribution of waves (as necessary to describe a particle) a superposition of numerous
waves has to be used, that is, a wavepacket. The velocity of a wavepacket is given by the so-
called group velocity, which is not the phase velocity, but the derivative of the dispersion relation
with respect to the wavevector (dω/dk). Using Einstein’s relation the dispersion relation for the
electron wavefunction is the band structure ω = E(k)/h̄. Therefore the particle velocity is:

1 dE dE
v= = (1.14)
h̄ dk dp

Assuming that a vector electric field F accelerates an electron, the vector force is -qF and the
(scalar) acceleration in the direction parallel to the field is:

dv dv dp 1 d2 E dp F orce −q|F|
a= = = 2 2 = = (1.15)
dt dp dt h̄ dk dt m m

h̄2
Effective mass: m =   (1.16)
d2 E
dk2

24
Here, h̄ is the reduced Planck’s constant and E(k) is the band structure of the material. The
second derivative of energy with respect to the wavevector (proportional to momentum according
to Einstein’s relation) characterizes the curvature of the energy band in the energy-momentum
plane. Therefore, the band structure also affects the effective mass of the electrons; hence:
their dynamic inertial properties. Depending on the specific band structure of the material, the
effective mass can be anisotropic, meaning it can vary in different directions. So electrons and
holes have different effective masses and acceleration according to the direction of the force. In
practice, however, a unique effective mass averaged over all spatial directions is used in most
instances, hereafter denoted mn and mp for electrons and holes, respectively The ratios mn
m0 and
mp
m0 are used to understand how much the carrier is accelerated in the semiconductor compared
to vacuum.

Figure 1.12: Effective mass ratio for some useful elemental and binary compound semiconductor
materials.

It is worth underlying the importance of this result. The effective mass is a parameter that
allows us to regard the electrons and holes as classical particles (and not complex packets of
waves) and to keep using the simple equations of motion of classical mechanics (i.e. Newton’s
law) subject only to external fields applied via the electrodes of the device (and not the additional
complex field distribution generated by all nuclei and electrons in the crystal). Based on this
result, we will use classical physics to describe the motion of electrons and holes, with only a few
exceptions when quantum mechanical tunneling plays a relevant role in device operation.

Cyclotron Resonance Technique

A way to measure the effective mass of an electron or hole in a semiconductor is by using cyclotron
resonance. Consider an electron in an N-type semiconductor in a magnetic field B. ⃗ It will trace
out a circular path in a plane normal to B.
⃗ The magnetic field exerts a Lorentz force of F⃗ = qv B,
⃗
where v is the velocity.

Centripetal force = Lorentzian Force (1.17)

mn v 2
= qv B⃗ (1.18)
r
⃗
q Br
v= (1.19)
mn
v ⃗
qB
fcr = = (1.20)
2πr 2πmn

fcr usually falls in the microwave range. If a circular electric field of the same frequency is
applied, the electron strongly absorbs the microwave energy. By measuring the frequency at the
peak of the energy absorption, fcr is experimentally found; it is then possible to calculate mn

25
based on the equations above.

1.9 Carrier concentrations

In general terms, the current density is always equal to J⃗ = ρ⃗v [A/m2 ] where ρ is the density of
the mobile charges (charge per unit volume) and the average velocity of these charges. Therefore,
the two quantities that we need to determine to study an electron device are the concentration
of mobile charges and the average velocity of mobile charges we have.
In semiconductors, electrons in the c.b. and holes in the v.b. can move through macroscopic
distances. The electrons’ charge density is ρ = −qn; that of holes is ρ = −qp, where n and p are
the electron and hole concentrations (number of electrons/holes per unit volume).
To calculate n and p we need to know how many electrons we have in the conduction band or
how many holes we have in the valence band, so how many states are available to host electrons in
the conduction band and holes in the valence band (including spin). Then we need to know how
many of these states are occupied (or not occupied) by electrons in the conduction and valence
bands, respectively. To this end, we need to introduce two relevant quantities: the density of
states (DoS) and the occupation function.

1.9.1 Density of States

The density of states (DOS) of a semiconductor is by definition the number of electronic states
per unit energy range and per unit volume that are available for electrons or holes to occupy,
that is, g(E) [states/m3 /Joule] or [states/m3 /eV]. The DOS is a function of energy denoted as
D(E) or g(E). The number of available states is proportional to the volume because a larger
volume entails a proportionally larger number of atoms, hence of atomic orbitals that mix in
forming the bands. The density of states can be measured or calculated as:

number of states in∆E

 
1
g(E) = D(E) = (1.21)
∆E · volume eV · cm3

where E is the energy. In the context of semiconductors, there are different expressions for the
density of states in the conduction band and the valence band. When calculating the DOS it is
always very important to clarify if the expression accounts for the electron spin in the definition
of the state or not. If it doesn’t, then the density of states must be multiplyed by 2 before using
it for calculations of carrier concentrations.

Figure 1.13: Density of state function.

26
 Clearly g(E) = 0 in the band gaps. In the proximity of the conduction band and valence
√
band edges g(E) (including spin) has an approximately E dependence on energy expressed as
(Fig.1.13):
p
8πmn 2mn (E − Ec )
Dc (E) = gc (E) = (1.22)
h3
with E > Ec .
p
8πmp 2mp (Ev − E)
Dv (E) = gv (E) = (1.23)
h3
with E < Ev .

The dependence of the DOS on energy is strictly related to the dimensionality of the crystal,
that is, to the degrees of freedom of the carriers. If we consider

• 3D semiconductor materials g(E) goes as E 1/2

• 2D semiconductor materials (e.g., graphene) g(E) is constant

• 1D semiconductor materials (e.g. carbon nanotube) g(E) goes like E −(1/2)

Density of States for heavy doped semiconductors

When the doping level in a semiconductor is very high, it can have significant effects on the
material’s electronic properties and behavior. Indeed, at high concentrations, the localized states
of the donor/acceptor dopants interact with each other because of the proximity.
According to the Pauli principle, the dopant states start to assume slightly different energy levels.
This means that the DOS of the Donors is not concentrated on a single energy level, but it is
distributed on a band.
The impurity band can then merge with the main band, thus leading to an effective Band
Gap Narrowing (BGN). This reduction of the band gap can be described with the following
expression:
Eg (with BGN ) = Eg (without BGN ) − ∆Eg (1.24)

where ∆Eg is a function of the dopants’ concentration. BGN in silicon becomes increasingly rele-
vant for impurity density approximately above 1018 [atom/cm3 ]. A heavily doped semiconductor
where band gap narrowing effects start to become relevant is often denoted degenerate.

27
 Figure 1.14: Dos with BGN.

Figure 1.15: BGN in silicon.

band gap narrowing is very relevant in modern devices, and in some instances (e.g. bipolar
transistor technologies) it is a major source of performance loss.

28
1.9.2 The occupation function

Under equilibrium conditions, the electrons distribute themselves in the available energy states,
occupying firstly the lowest energy ones as allowed for by Pauli’s exclusion principle. Because of
agitation by thermal energy at T 0 K, electrons transition in many different ways from higher
to lower energy states and many different configurations of the electrons in the available states
correspond to a given temperature at equilibrium. We are not able to say exactly which states are
occupied or not at a given energy and time but, based on the principles of statistical mechanics,
it is possible to calculate the probability that a given state at a given energy is occupied at the
equilibrium. The result of the calculation is the Fermi-Dirac distribution, otherwise called
Fermi occupation function or Fermi-Dirac statistics. It is an analytical expression for the above
probability as a function of energy. The Fermi-Dirac distribution represents the statistical energy
distribution of particles subject to Pauli’s exclusion principle at equilibrium. The probability of
finding a particle at energy E, that is, the probability of a state energy E being occupied by an
electron must be in the 0 ÷ 1 interval, and it is given by the Fermi-Dirac distribution as:

1
0 ≤ f (E) = ≤1 . (1.25)
1+ e(E−EF )/kT

where kT is thermal energy (equal to 26 meV at 300 K), EF is the so-called Fermi energy or
Fermi level, that represents the energy at which the probability of finding an electron is exactly
0.5, so 50%. The Fermi distribution is strongly dependent on temperature; in fact, as the
temperature decreases, the function becomes steeper, meaning that the transition between zero
and one occurs in a smaller energy range. The limit case is at absolute zero, so 0K, where the
function is discontinuous and reduces to a step function when the energy is exactly at the Fermi
level, so E = EF .

Figure 1.16: Fermi-Dirac occupation function plotted using energy as the y-axis.

This can be observed in Fig.1.16, where the Fermi function is depicted at 0 K (red) and finite
temperature (blue). We observe a rapid transition from f = 1 to f = 0 in a small energy interval
(a few units of kT around EF ). Therefore, roughly speaking, EF can be seen as the energy level

29
that separates (mostly) occupied states (f ≃ 1) from (mostly) empty states (f ≃ 0)10 .
More precisely, Eq. 1.25 shows that if |E − EF | ≥ 3k, then f (E) is either smaller than 0.05
(that is essentially 0) or larger than 0.95 (that is, essentially 1. Therefore, even at temperatures
different from 0 K, we can say that within a small energy interval ±3kT ≃150 meV at 300 K
centered at the Fermi energy, the occupation probability of electron states drops from almost 1
to almost 0. With this degree of approximation, we can think of the Fermi energy as the energy
level that separates filled electron states (at E < EF ) from empty electron states (at E > EF ).
It can be demonstrated that the Fermi level at equilibrium is constant in space regardless of
the composition/materials/interfaces in the system and there is only one Fermi level at equilib-
rium. This entails that the occupation probability is independent of position at equilibrium. In
fact, given two adjacent energy states at the same energy the transition rates from (1) to (2) and
vice-versa must be equal so that the net flux is zero, as it should at equilibrium. Hence:

P1→2 = g1 (E)f1 (E)g2 (E)(1 − f1 (E)) (1.26)

P2→1 = g2 (E)f2 (E)g1 (E)(1 − f1 (E)) . (1.27)

By imposing P1→2 = P2→1 , it follows f1 (E) = f2 (E); hence: EF 1 = EF 2 ; that is, the Fermi
energy is the same at any two locations in the system at equilibrium.
Since by definition at T = 0 K the v.b. is completely filled with electrons and the c.b. is
partly or totally empty, the Fermi energy (Fermi level) is located inside the band gap between
v.b. and c.b. for semiconductors and insulators, it lies in the conduction band for metals. The
position of the Fermi level of a doped semiconductor relative to the band edges is influenced by
doping and by temperature, in fact as the temperature increases, electrons gain thermal energy,
and some may transition to higher energy states.
The expression of the Fermi function does not always lend itself to easy analytical elabora-
tions. A useful approximation is given by the so-called Maxwell-Boltzmann distribution, which
is:

f (E) ≃ exp(−(E − EF )/kT ) E − EF ≫ kT (1.28)

f (E) ≃ 1 − exp(−(EF − E)/kT ) E − EF ≪ −kT . (1.29)

Interestingly, the Maxwell Boltzmann distribution is the energy distribution of a gas of free
particles which do not obey Pauli’s exclusion principle. When the Maxwell-Boltzmann statistics
can be safely adopted and EV + 3 · KT ≤ EF ≤ EC − 3 · KT , the semiconductor is said to be in
a non-degenerate condition.
A final remark is due about out of equilibrium conditions. In this case, the occupation prob-
ability of the electron states is a function not only of energy but also of the electron wavevector
⃗k and of position and time, i.e., f = f (⃗r, ⃗k, t). Even in the simple case of stationary conditions,
when f is independent of time, no exact and general formula exists to express this probability
in analytical form. As a matter of fact, f (⃗r, ⃗k, t) must be calculated by numerically solving the
coupled electrostatics and transport problems by taking full account of all the collision processes
that change the electron states in time; a topic that goes well beyond the goals of these notes.
10
At 0 K this is actually an exact definition of the Fermi level.

30
 Let us now consider a non-uniformly doped semiconductor region (or an hetero-structure
made of different materials, possibly including metals and insulators, as further discussed in
Sect.??) the Fermi energy is constant but, accoding to Eqs.?? the position of EC and EV w.r.t.
the Fermi level change with position (doping and material dependence). Therefore EC and EV
change with position.

1.10 Electron and holes concentrations

Figure 1.17: Energy distribution of the Fermi occupation function, the DoS, and their product.

To derive the electron and hole concentrations in the conduction and valence bands we recall
1.21 and the definition:

number of electrons
 
n= (1.30)
volume in conduction band

we can then compute the number of electrons in a certain energy span ∆E as the product between
the occupation probability (i.e., the Fermi function f (E)) and the density of states Dc (E). So, to
calculate the total number of electrons in the conduction band we have to compute the integral
over all energy levels above the conduction band edge. The same reasoning applies to the holes;
we just need to consider the number of holes in the valence band per unit volume. To calculate
the hole concentration we will need to integrate [1 − f (E)]D(E) instead of f (E)D(E) which we
used for the electrons.
By doing this we have derived the following expressions:
Z top of conduction band
n= f (E)Dc (E)dE (1.31)
Ec
Z Ev
p= [1 − f (E)]Dv (E)dE (1.32)
bottom of valence band

where f (E) is a probability, hence, unitless. The integral cannot be solved analytically if the
full expression of the Fermi function is considered. However, if the conduction band edge is high
enough above the Fermi level, then we can approximate the Fermi function with the Boltzmann
expression. In addition, since the Fermi function decays exponentially far from the Fermi Energy,
we can safely replace the upper and lower c.b. and v.b. extremes, respectively, with infinity.

31
Therefore, we obtain:
√
8πmn 2mn ∞ p
Z
n= E − Ec e−(E−Ef )/kT dE (1.33)
h3 Ec
√
8πmn 2mn −(Ec −Ef )/kT E−Ec p
Z
= e E − Ec e−(E−Ec )/kT d(E − Ec ) (1.34)
h3 0

n = Nc e−(Ec −Ef )/kT (1.35)

2πmn kT 3/2
 
where Nc = 2 . (1.36)
h2

Nc is called the effective density of states of the conduction band. It represents the situation as
if all the energy states in the conduction band were squeezed into a single level located at EC
which contains Nc electrons per unit volume. At last, effective because in reality, every state has
its own occupation probability.
Similarly for the holes:

p = Nv e−(Ef −Ev )/kT (1.37)

2πmp kT 3/2
 
where Nv = 2 (1.38)
h2

Nv is called the effective density of states of the valence band. At room temperature we can
calculate NC,V = (2.5 × 1019 cm−3 )(m∗n,p /m0 )3/2 . Therefore, the c.b. and v.b are slightly asym-
metrical according to their effective masses. For silicon we have : NC ≃ (2.8 × 1023 cm−3 ),
NV ≃ (1.1 × 1023 cm−3 ), which shows the asymmetry is very small.
The closer EF moves up toward EC , the larger n becomes; the closer EF moves down toward
EV , the larger p becomes instead.

1.11 Fermi level and carrier concentrations

When the semiconductor is heavily doped the Fermi level approaches the band edges and we
can not use anymore the Boltzmann approximation; so, Pauli’s exclusion principle produces
not negligible effects. The np product and the intrinsic carrier concentration of non-degenerate
semiconductors are:

n = Nc e−(Ec −Ef )/kT and p = Nv e−(Ef −Ev )/kT (1.39)

np = Nc Nv e−(Ec −Ev )/kT = Nc Nv e−Eg /kT (1.40)
ni = Nc Nv e−Eg /2kT
p
(1.41)
np = n2i (1.42)

where Eg is the band gap, the equation of np is independent from Fermi level, because p balance
n and opposite so if n increases p decreases and vice versa. The expression of the np product is
often denoted law of mass action for its analogy with the expression of the equilibrium constant
of reactions in chemistry.

32
In an intrinsic (undoped) semiconductor n = p = ni , and there is no doping that shifts the
Fermi level. The ni is the intrinsic carrier concentration (the number of n and p remain the
same), and it’s around ∼ 1010 cm−3 for Silicon. Also, ni is strongly dependent on the band gap
and determines the background carrier concentration in the semiconductor, hence, the residual
conductivity of the semiconductor material and the intensity of unavoidable leakage currents.
Large band gap means lower leakage and ni so semi-insulating behaviour.
The introduction of the intrinsic carrier concentration allows to derive alternative convenient
expressions for n and p:

n= Nc e−(Ec −Ef )/kT (1.43)

p= Nv exp −(Ef − Ev )/kT (1.44)
n = ni = Nc exp −(Ec − EF i )/kT (1.45)
p = ni = Nv exp −(EF i − Ev )/kT (1.46)
n= ni exp (EF − EF i )/kT (1.47)
p= ni exp (EF i − EF )/kT (1.48)
 
EF = EF i + kT ln nni (1.49)
 
EF = EF i − kT ln npi (1.50)
(1.51)

The Fermi level moves upward above EF i in N-type semiconductors and moves downward below
EF i in P-type semiconductors. By taking the p/n ratio we get:
 
(EC + EV ) kB T NV
EF i = + ln (1.52)
2 2 NC

where EF i denotes the position of the intrinsic Fermi level.

(EC +EV )
The 2 is the positionof the
 Fermi level at 0 K, which corresponds to the midpoint of the
energy gap. Instead 2 ln NC is the offset of the Fermi level due to the difference between
kB T NV

conduction and valence band effective density of states, it’s zero if NC = NV ; but in reality,
NV and NC are never perfectly equal so the intrinsic Fermi level is not precisely at the mid-gap
point. Considering Silicon, in order to have the same n and p at the intrinsic state, the Fermi
level will not be perfectly at the mid-energy gap but slightly shifted below it (NV is smaller than
NC in silicon).
If n > ni the logarithm is positive because its argument is larger than 1 and the Fermi level is
pushed above EF i toward EC .

33
 Figure 1.18: Shift of Fermi level in function of doping.

1.12 General theory of n and p

The charge density ρ which is relevant for the Poisson equation can be computed neglecting all
the electrons and protons in the lower energy states and considering only the contribution of
valence and conduction band electrons and dopants. It reads:

+
ρ = q(p + ND − n − NA− ) (1.53)

where ND
+
and NA− represent the concentrations of ionized donors and acceptors, respectively.
In a uniform semiconductor slab at equilibrium, charge neutrality holds; therefore, we have that
ρ = 0. Assuming complete ionization of the dopants we get:

n + Na = p + Nd (1.54)

By combining this equation with the law of mass action, that is np = n2i , and solving for n and
p, we obtain the following expressions (in which we drop the negative solution of the second
order equation since concentrations are positive quantities by definition):
" 2 #1/2
Na − Nd Na − Nd
p= + + n2i (1.55)
2 2
" 2 #1/2
Nd − Na Nd − Na
n= + + n2i (1.56)
2 2
(1.57)

Nd −Na Na −Nd
In most instances the terms 2 and 2 are much greater than n2i and so the n2i term can
be neglected in the expression. Note that the above equation only accounts for valence electrons
and ionized impurity charges, that’s because charge due to all other electrons and protons is
neutralized on the large scale of the inter-atomic distance and so it does not contribute to
macroscopic charge distributions, which is the one we are interested in.

34
 • N-type

Nd − Na ≫ ni (1.58)
n = Nd − Na Majority carrier (1.59)
p = n2i /n Minority carrier (1.60)
(1.61)

If the condition Nd ≫ Na holds, then we can neglect Na and so we obtain n = Nd and p = n2i /Nd .

• P-type

Na − Nd ≫ ni (1.62)
p = Na − Nd Majority carrier (1.63)
n = n2i /p Minority carrier (1.64)
(1.65)

If instead Na ≫ Nd , then we can neglect Nd ; so the expressions assume the following form
p = Na and n = n2i /Na .

1.13 Carrier concentrations at extremely high and low temperatures

The interest in having semiconductors that operate in harsh environments, hence at very low
and very high temperatures, suggests to investigate in more detail the temperature dependence
of carrier concentrations in a uniform semiconductor slab at equilibrium. At high temperatures,
the carrier concentration is expressed as follows:
p
n = p = ni = Nc Nv e−Eg /2kT (1.66)

The expression predicts an exponential growth of the intrinsic carrier concentrations, which
brings the semiconductor closer to an intrinsic behaviour and reduces dramatically the ability to
determine the carrier concentrations and type of conduction by means of the doping. If we want
the device to operate at a high temperature, we then need a semiconductor with a large band
gap, so that less electrons with high thermal energy make the jump to the conduction band.
Heating up the crystal too much, sooner or later will lead it to a regime where it will behave as
intrinsic regardless of its doping level. That is because it will generate a lot of free carriers due
to the temperature. At low temperatures instead, the carrier concentration is:
 1/2
Nc Nd
n= e−(Ec −Ed )/2kT (1.67)
2

At very low temperature (cryogenic temperature), the device enters the freeze-out regime (in-
complete ionization). This is caused by insufficient energy to make the jump from the donor state
to the conduction band, or from the valence band to the acceptor state. The dopants do not
ionize completely, and so there are less free charges than dopant atoms and the doping becomes

35
equally ineffective.
Applications like quantum computers contain components like the qubits and the qubit readout
circuits, that operate at cryogenic temperature, ≃ 7K. Silicon works nicely at least down to
77K and cryogenic CMOS circuits have been demonstrated for operation down to 4K and even
below.

Figure 1.19: Carrier concentration as a function of temperature.

1.14 Infrared detectors based on freeze-out

Often it is desirable to detect or image the radiation emitted by warm objects, for example, to
detect tumors (which restrict blood flow and produce cold spots), to identify inadequately insu-
lated building windows, to detect people and vehicles at night etc. This requires a photodetector
that responds to photon energy around 0.1 eV. For this purpose, one can use a semiconductor
photoconductor with Eg less than 0.1 eV, such as HgPbTe operating in the mode shown in Figure
1.20.

Figure 1.20: Eg can be determined from the minimum energy (hν) of photons that are absorbed
by the semiconductor.

This solution, however, is impractical due to the well-known toxicity of some of the materials
involved and the limited degree of development of the technology. Alternatively, it is possible
to use a more common semiconductor such as doped Si operating in the freeze-out mode. Con-
duction electrons are created when the infrared photons provide the energy to ionize the donor
atoms, which are otherwise frozen-out. The result of the electron hole creation is a lowering of

36
the detector’s electrical resistance which can be detected.
At a long enough wavelength or low enough photon energy hν, light will no longer to absorbed
by the specimen. That critical hν corresponds to Ec − Ed . This is a method of measuring the
dopant ionization energy Ec − Ed .

Figure 1.21: A simple electron system at room temperature for illustration of what determines
the Fermi energy, EF .

37
2 Device Fabrication Technology

(a) Oxidation: Process that allows the cre-

ation of a layer of silicon oxide. Useful for
creating an insulator layer or a protective
layer. It is an example of deposition.

(b) Lithography and Etching: Process that

removes a portion of the protective layer.

(c) Ion Implantation: It is an example of

a doping technique that changes the ma-
terial properties. Since this process dam-
ages the crystal, we need to reconstruct it.
Usually, we start with an already doped
semiconductor P-type (NA ≈ 7 · 1015 ),
then if enough donors are implanted that
ND > NA and so ND − NA > 0, it is pos-
sible to change the proprieties of the ma-
terial; in this case it becomes a N-type.

(d) Annealing and Diffusion: Diffusion is

defined as the movement of impurity atoms
in a semiconductor material at high tem-
peratures. The ion implantation damages
the material so we need a treatment that
recovers the crystallinity, hence the qual-
ity of the crystal. Diffusion is applied to
anneal the crystal defects. During the an-
Figure 2.1: Elementary sequence to fabri- nealing process the material is heated to
cate a PN juntion in a planar silicon pro- allow the atoms to return to their initial
cess. position.

Every process in the silicon technique must preserve the quality of the wafer, avoiding contam-
ination or defects in the material. A special machine is also used to control the parameters of
the wafer, such as chemistry and temperature.

2.1 Oxidation of Silicon

We can create an insulator protective layer of SiO2 with a precisely controlled thickness. This
layer is produced during IC (integrated circuits) fabrication by reacting Si with either oxygen gas
or water vapor at an elevated temperature. In either case, the oxidizing species diffuse through
the existing oxide and reacts at the Si − SiO2 interface to form more SiO2 . The relevant overall
reactions are

Si + O2 → SiO2 Dry oxidation (2.1)

Si + H2 O → SiO2 + 2H2 Wet oxidation (2.2)

38
Wet oxidation is performed by bubbling a carrier gas (Ar or N2 , extremely pure without con-
taminants). Sometimes we need to add some other inert gas (like N ) for stabilization or other
process, rough water in a heated flask or by burning O2 and H2 to form H2 O at the input of the
tube. Typically, in a manufacturing system, processes such as loading wafers, placing them into
the oven, raising the oven temperature, and gas control are all automated. The thickness of the
oxide grown depends on the furnace temperature, the oxidation time, the ambient gas, and the
Si surface orientation.

Figure 2.2: Sketch of an oxidation furnace.

To control the thickness of the oxide we act in reaction time and temperature. It’s important to
have a uniform condition on every part of the wafer to avoid defects.
Dry oxidation is used to produce a high-quality thin oxide layer, but costs more and takes longer
than wet oxidation. However wet oxidation is used to grow a very thick oxide, because this
process need less time, and so less energy is required, and for this reason it results to be cheaper
than the other oxidation.

Figure 2.3: Grown silicon dioxide thickness as a function of oxidation time for wet and dry
oxidation processing steps.

It’s important also to choose the cutting plane of the wafer, to know the amount of atoms that
react on the surface. Wafers used in IC productions are predominantly cut in the (100) plane
because the interface trap density is low due to the low density of unsaturated bonds in this

39
plane relative to the other planes. Also, the electron surface mobility is high.
It’s important to note that the silicon in oxidation’s reaction is taken from the wafer, which
means the silicon wafer is consumed during oxide growth, we call then this layer Sacrificial
oxide. Otherwise, the oxide layer is more high due to the oxygen added. To calculate how much
Si is consumed from oxidation we use this equation:

hSi VSi MSi ρSiO2

= = (2.3)
hSiO2 VSiO2 MSiO2 ρSi

in this case it turns out to be equal to 0.44.

Figure 2.4: Cross section of a silicon wafer before and after oxidation.

If on the surface there is some contamination, after oxidation, they are trapped into the SiO2
and can be etched away with etching.

40
2.2 Lithography
Spatial selection is accomplished using a process
called photolithography or optical lithography.
Using the patterning of a SiO2 film as an ex-
ample. The top surface of the wafer is first
coated with an ultraviolet (UV) light-sensitive
material called photoresist. The liquid photore-
sist is placed on the wafer, and the wafer is spun
at high speed to produce a thin, uniform coat-
ing. After spinning, a short bake at about 90 °C
is performed to drive solvent out of the resist.
The next step is to expose the resist through a
photomask and a high-precision reduction (for
example 5 to 1 reduction) lens system using UV
light as illustrated in (b). The photomask is a
quartz photo plate containing the patterns to be
produced. Opaque regions on the mask block the
UV light. Regions of the photoresist exposed to
the light undergo a chemical reaction that varies
with the type of resist being employed. This
reaction changes the physical properties of the
photoresist. In negative resists (hardened), the
areas where the light strikes become polymerized
and more difficult to dissolve in solvents.
When placed in a developer (solvent), the polymerized regions remain, while the unexposed
regions (weak)dissolve and wash away. The net result after development is pictured on the right-
hand side of (c). Positive resists (weakened) contain a stabilizer that slows down the dissolution
rate of the resist in a developer. This stabilizer breaks down when exposed to light, leading
to the preferential removal of the exposed regions as shown on the left-hand side of (c). Steps
(a) through (c) make up the complete lithography process. To give a context for lithography,
we include step (d) for oxide removal. Buffered hydrofluoric acid (HF) may be used to dissolve
unprotected regions of the oxide film. Lastly, the photoresist is removed in a step called resist
strip. This is accomplished by using a chemical solution or by oxidizing or “burning” the resist
in an oxygen plasma or a UV ozone system called an asher. It’s important to control how much
thickness we remove, because if it is too much we also etch away a part of Si.

2.3 Projection printing

The mask is separate from the wafer. It uses some optical lenses to have the highest resolutions
in the smallest possible dimension on the wafer. So it’s possible to have a larger mask than the
wafer. The most important part is optical resolution, as this process is all about refraction. The
minimal light dimension you can shine is linked to the wavelength and on a constant NA, which
contains the refraction index and angle at its expression.

41
 Figure 2.5: Projection printing. Image courtesy of J.Schmitz, Univ. Twente.

Optical diffraction limits the minimum size that can be obtained to k times the wavelength of
the light used in the optical exposure system.

λ
Wmin = k N A = n sin α = Numerical Aperture (2.4)
NA

where n is the refraction index of the projector-wafer medium, and α is the angle of focus of the
light. The main way to improve lithography is to reduce the wavelength, but this change needs
also to change the polymer aka photoresist.
Another important parameter is the Deep of Focus:

λ
DOF = (2.5)
2(N A)2

and it expresses the height range in which the wafer can be placed, concerning the focal plane,
in which we don’t lose much resolution.

Figure 2.6: DOF range that ensure to have Wmin .

To have a small Wmin also DOF must decrease, which means that it is more difficult to focus
the image in a portion of the wafer. It’s also possible to improve lithography by acting on the
NA constant. For example, a drop of highly purified water is introduced to increase NA without

42
changing α, in this case we call it Wet lithography

Figure 2.7: a) dry lithography b) wet lithography. Image courtesy of J.Schmitz, Univ. Twente.

2.3.1 Resolution limit

Historically R (resolution) is increased with decreasing λ, but that need also changes the poly-
meric material used, light lamp, optics, etc.
The light is generated by exiting atoms and relaxing it in a lamp, so we will have fixed steps of
λ. Another problem for the lamp is in the diffraction of light, in fact if λ is compatible with the
aperture of the lamp we get a nonuniform ray.

k
R≥ λ (2.6)
NA

The minimum distance Wmin can be reduced with:

• Large aperture, high-quality lens

• Stepper machine used to expose one piece of area of the wafer at a time, because wafers
are always bigger so it can’t be done in a single step, it doesn’t illuminate all at once.

• Optical proximity correction OPC: you try to compensate for diffraction (so nonuniform
light intensity shone on the focal plane) by modifying the pattern of shades in such a way
that after refraction the intensity of light is closer to ideal. It’s a pre-distortion mechanism
and requires a lot of computational resources.

2.4 Exposure
It’s a very old technique, the exposure to light causes a chemical change that allows some of the
photoresist to be removed by a special solution. Conventional lithography mask. PS: Il prof ha
detto che non vuole che ci ricordiamo l’immagine 2.8

43
Figure 2.8: Sketch of a photolitography machine. Image courtesy of J.Schmitz, Univ. Twente.

2.5 Stepper
Before steppers, wafers were exposed using mask aligners, which patterned the entire wafer at
once. Now to pattern the entire wafer, the mask is repeatedly moved, or stepped, across the
surface of the wafer. Steppers increased the possible resolution many times over that of the
aligners and were the first systems to allow features smaller than 1 micron.

Figure 2.9: Sketch of a stepper machine. Image courtesy of J.Schmitz, Univ. Twente.

2.6 Resist Lithography

If lithography light is not uniform everywhere some portion of the photo-resist does not receive the
same light intensity, this means that the photo-resist doesn’t change uniformly its characteristics,
some parts will be easier or harder to remove than others and it will then create imperfections,
especially at the edges of the resist:

44
Figure 2.10: Wafer profile after photoresist etching for different kind of light density. Image
courtesy of J.Schmitz, Univ. Twente.

• Under develop: you cut less resist than you should and these are left over so an area
larger than it should is still covered by resist.

• Severe overdevelop: you cut away more resist than you should and a rough surface will
be obtained because of inconsistent light shone on it.

Extreme UV Lithography

Figure 2.11: Extreme UV Lithography machine. Image courtesy of J.Schmitz, Univ. Twente.

Powered by ASML, it reaches 13 nm wavelength, before was λ ≃ 100nm. It’s called "extreme
UV" because it’s near to X-rays.

2.7 Electron beam lithography

In electron-beam lithography, a focused stream of electrons delivers energy to expose the electron
resist. The electron beam is scanned to write the desired pattern. The information necessary to
guide the electron beam is stored in a computer and no mask is used. Electron-beam lithography
has long been used to fabricate the photo masks used in optical lithography and for EUVL

45
(Extreme UV Lithography). For direct printing of patterns on wafers, electron lithography has
slower exposure rates (in wafers per hour) than optical lithography. The exposure rate can be
increased by employing multiple electron beams in each lithography machine. The advantage is
that if there is an error in the pattern, we need only change the project file, not redo an expensive
mask.

2.8 Clean Room

Semiconductors are extremely sensitive materials. So without a controlled clean room to man-
ufacture the chips in, you risk contamination that could lead to various production issues and
product failures. It’s essential to have a robust design of clean rooms, that helps them reach and
maintain strict cleanliness standards while also allowing for easy movement and workflow. The
clean rooms are anchored to the floor to avoid vibration, this is possible because the structure is
supported by some columns positioned into the terrain, very deep.
Operators must absolutely wear a special suit called a "bunny suit" that prevents the environ-
ment in which they operate (in the clean room) from being contaminated by external agents as
well as other agents, such as the operator’s sweat. The suits are used not only to avoid contam-
inations, but also for the safety of the operator. For example, if we consider wet oxidation, this
chemical process produces H2 that is extremely flammable, or another example is the gas, like
phosphorus; for this reason is important to wear the suit not only to avoid contamination but
also protect the operator from danger.
Furthermore, access to the clean room is preceded by an air shower, that disinfects the operator
who wishes to enter. Inside the clean room, there is also higher pressure to blow out the dust.
Additionally, air filters are present inside to enable the re-circulation of clean air.

Figure 2.12: Sketch of a clean room scheme. Image courtesy of J.Schmitz, Univ. Twente.

46
2.9 Pattern Transfer–Etching

Figure 2.13: Etching process. Image courtesy of J.Schmitz, Univ. Twente.

• Isotropic Etching: it means that the etching is without preference in direction, and it
proceeds laterally under the resist as well as vertically toward the silicon surface, the etched
features are generally larger than the dimensions of the resist patterns. This is done by
just pouring an etching solution in the gaps.

• An isotropic Etching: Etching proceeds faster in one direction than all the other ones.

Figure 2.14: Etching’s deposit. Image courtesy of J.Schmitz, Univ. Twente.

• Directional Etching: Etching proceeds along the geometry of crystal plans. Let’s assume
a non-flat wafer, it’s possible to deposit a uniform film, then with an isotropic etching we
leave some material at the edges (it also gives us the possibility to reach sub-lithography
Resolution).

Figure 2.15: Deposit of material due to directional etching. Image courtesy of J.Schmitz, Univ.
Twente.

47
2.10 Reactive-ion Etching system
In dry etching, also known as plasma etching or reactive-ion etching (RIE), the wafer with
patterned resist is exposed to a plasma, which is an almost neutral mixture of energetic molecules,
ions, and electrons that is usually created by a radio frequency (RF) electric field.
The energetic species react chemically with the exposed regions of the material to be etched,
while the ions in the plasma bombard the surface vertically and knock away films of the reaction
products on the wafer surface. The latter action is directional so that the etching is preferentially
vertical because the vertical surfaces can be covered with films of the reaction products. Low
pressures and highly one-directional electric field tend to make etching anisotropic. Dry etching
can also be designed to be isotropic or partially anisotropic if that is desired.
Suitable gases are introduced into the etch chamber based on the material to be etched. Silicon
and its compounds can be etched by a plasma containing fluorine (F ), whereas aluminum is
etched with chlorine-containing plasmas. The material selectivity of dry etching is usually not
as high as that of wet etching. The material to be etched and the underlying material (e.g.,
SiO2 and the underlying silicon) can both be significantly attacked during the etching process.
Therefore, the dry etching process must be terminated as soon as the desired layer has been
removed. This can be done with an end-point detector, which monitors the light emission from
the various etching products. There is often a trade-off between selectivity and anisotropy.
For example, bromine (Br) provides better selectivity between Si and SiO2 but poorer anisotropy
than Cl. Processing using plasma can potentially cause damage to the devices on the wafer.
This is known as plasma process-induced damage or wafer charging damage. The main damage
mechanism is the charging of conductors by the ions in the plasma, leading to an overly high
voltage across a thin oxide and causing oxide breakdown.
The worst condition is a small, thin oxide area connected to a large conductor, which collects a
large amount of charge and current from the plasma and funnels them into the small-area oxide.
The sensitivity of the damage to the size of the conductor is called the antenna effect.

Figure 2.16: Reactive-ion etching

system (RIE). Image courtesy of
Figure 2.17: Sketch of a RIE machine. Image courtesy of
J.Schmitz, Univ. Twente.
J.Schmitz, Univ. Twente.

48
2.11 Ion implantation
The ion implantation, is a technique of doping that modifies the properties of the material. The
process consists in bombarding the surface of the wafer with ions of the element that we want
to enter and modify the Si layer. The Si layer is protected using a layer, which controls the
zones of Si we want to shoot with ions of different materials. So an impurity is introduced into
the semiconductor, by accelerating the ions to high energies ranging from sub-kilo-electronvolt
to Mega-electronvolt and thus we are creating ions of the impurity.
As one might suspect, the implanted ions displace semiconductor atoms along their paths into
the crystal. Moreover, the ions themselves do not necessarily come to rest on lattice sites. After
the process it’s necessary to repair the crystal damage and also the dopant activation requires
annealing, which can cause dopant diffusion and loss of depth control. So the heat procedure
restores the structure of the crystal, which was damaged after the ion implantation, while after
annealing we have a smooth profile and also a smooth diffusion curve of the doping ion.

Figure 2.18: Schematic illustration of the doping by Ion implantation processing step.

2.12 Schematic of an Ion Implanter

Ions of the desired impurity are produced in the ion source shown at the extreme left into a
mass spectrometer. The ions are then accelerated into the mass analyzer, using a magnetic field
(thanks to Lorentz forces), that brings the injected particles into curved trajectories, and only
the desired ions pass through a window in the ion selection aperture. This aperture is like a
filter where only ions with the right mass can pass through, thanks to that we have filtered each
impurity, so we decontaminated the ion source.
The resulting ion beam, depured from impurities, is then accelerated to the implantation energy,
and finally, the ion beam is scanned over the surface of the wafer, which is mounted on a
massive metal plate. This is accomplished by either electrostatically scanning the ion beam or
by mechanically moving the wafer, or by a combination of the two methods. An electrical contact
with the wafer allows a flow of electrons to neutralize the implanted ions.

49
Figure 2.19: Sketch of an ion implanter machine. Image courtesy of J.Schmitz, Univ. Twente.

Q
For each ion shoot, it generates a current I = ∆t . By measuring the total current It and
integrating it over time we calculate the total charge that is passed through the gun.
Z
Idt = Qt = ZqN (2.7)

where Z is how many elementary charges each ion brings (valence), q is the charge and N is the
total number of ions implanted. After that, we can calculate the total ion implanted for the unit
area, called Dose.

N Qt Qt
Dose = = from N = (2.8)
A ZqA Zq

In that way, a very precise determination of the total number of implanted ions per square
centimeter is obtained. So what influences the depth of implantation is the energy of ions and
their mass. If we consider the curve implantation of phosphorous (Figure 2.20) we’ll see that if
we integrate each curve we obtain the dose and for each curve, the area under the curve will be
equal. What we change in the ion implantation curve is the electric field, and we notice that at
higher energy we reach deeper into the layer but also increase the spread.
Otherwise if consider arsenic (As) the only difference is the mass, but the dose and energy remain
the same because both (As and P) are of group V. Arsenic has a larger mass than phosphorous,
and if we want to fabricate, for example, shallow junctions we prefer to use heavier ions because
they don’t go very deep and stay near the surface.

50
 Figure 2.20: Phosphorous density profile after implantation.

The concentration profile produced by ion implantation has the general form of a Gaussian
function and is described by the peak location below the surface (R, called the implantation
range), and the spread (∆R, called implantation struggle).

Figure 2.21: Black curve is Range, Cyan curve is implantation struggle.

Ni 2 2
N (x) = √ · e−((x−R) /2∆R ) (2.9)
2π · (∆R)
With: Ni the Dose implanted, ∆R the spread or implantation struggle, and R the range of

51
depth.

2.12.1 Channeling

Due to the crystal structure of the silicon, in a certain situation, we would see all atoms aligned.
So during implantation, ions don’t collide or scatter with silicon, so they just stay there and
form a channel because they are aligned. That causes longer tails of the implantation curve
because ions penetrate more deeply thanks to the channel between silicon atoms. To prevent the
channeling effect we tilt the wafer by some degrees (approx 7°) concerning the ion beam. So we
increase the chance of collision happening.

2.13 Annealing
This is a fundamental step to repair damaged silicon from ion implantation. The wafer is heated,
which will cause also doping diffusion. According to the Fick’s first law we have:

N of particle ∂C(x, t)
ϕ= = −D (2.10)
unit area · Unit tima ∂x

where ϕ is the flux , D is the diffusivity or diffusion coefficent and ∂C

∂x is the concentration
gradient. The movement of particles is in the direction of decreasing concentration.

Figure 2.22: Area under the curve represent the total number of particles. Image courtesy of
J.Schmitz, Univ. Twente.

From Figure 2.22 we see that after annealing (purple curve) the ion concentration curve is
smoother and also that ions reach deeper into the layer with respect to the initial condition (blue
curve). That means it is possible to exploit diffusion to have a very deep implantation without
using high-energy ion beams. So we implant ions with low energy, and then the diffusion does the
work to go deeper into the crystal. All the formulas and expressions are valid for a steady-state
diffusion.
Otherwise, we must consider the second Fick’s law of diffusion. Consider a semiconductor

52
in Figure 2.23 with section area A, according to the continuity equation, the difference between
the flux is the change in concentration in the volume dV = A · dx.

Figure 2.23: Illustration of diffusion fluxes in a semiconductor slab with cross section area A.
Image courtesy of J.Schmitz, Univ. Twente.

∂C ∂ϕ
Adx · = −A(ϕ2 − ϕ1 ) = −Adx · (2.11)
∂t ∂x
In three dimensions we would consider divergence of flux, so ∇
⃗ · ϕ, instead of the singular
derivative. Also ϕ2 − ϕ1 expresses the divergence of the flux.

∂C ∂ϕ ∂ 2 C(x, t)
=− =D· (2.12)
∂t ∂x ∂x2

By substituting the Fick’s law and solving differential equations, assuming a constant dose, we
obtain the diffusion of the dopant:

N0 x2
N (x, t) = √ · e− 4Dt (2.13)
πDt
√
where N0 is the dopant atom per cm2 , t is the diffusion time, x is the distance, and Dt is
the approximate distance of dopant diffusion. To accelerate the process we must increase D.
According to Arrhenius’s law, D increases with increasing temperature as follows:
Ea
D ∝ e− kT Ea = Energy activation (2.14)

53
 Figure 2.24: Diffusion coefficient in function of inverse of temperature (1/T).

High-performance devices often require the junction depth to be kept shallow. This in turn re-
quires that the Dt product has to be minimized. However, in order to activate the dopanta and
repair the crystal damage after ion implantation, thermal annealing is required. Unfortunately,
furnace annealing may need 30 min in a furnace at 900 °C. This condition causes too much
diffusion of the dopants, especially with Boron. As it turns out, annealing can be completed at
1,050 °C in 20 s, which causes much less diffusion.
In order to heat the silicon wafer up (and to cool it off) rapidly for short-duration annealing,
a special heating technique is required. In rapid thermal annealing (RTA), the silicon wafer is
heated to high temperature in seconds by a bank of heat lamps. Cooling off is also fast because
the mass of the entire system is small. Pushing RTA further to 0.1 s annealing, one can obtain
even shallower junctions. Such short annealing is called flash annealing. For an even shorter
duration (less than a microsecond) of heating, the silicon wafer can be heated with very short
laser pulses. The process is called laser annealing, which may or may not involve melting a very
thin layer of silicon.
A fundamental aspect is called Thermal budget: we need to be careful to increase the tem-
perature as we can destroy what we’ve already done, so we need to decrease progressively the
temperature. Every step works at a certain temperature, but some steps can destroy what has
been done before. So we start with the highest temperature steps and then decrease it gradually.

2.14 Thin-Film Deposition/growth

A solid material may be crystalline, polycrystalline, or amorphous. Silicon wafers and epitaxially
deposited films fall in this category as do the high-quality gemstones such as ruby and sapphire
(Al2 O3 with impurities that produce the characteristic colors) as well as diamonds. Often, ma-
terials are polycrystalline, which means the material is made of densely packed crystals or grains
of a single crystal. Each grain has a more or less random orientation. The interface between
crystals is called a grain boundary. Each grain may be 10–10,000 nm in size. Metal films and

54
Si films deposited at higher temperatures fall in this category, as do all metal objects that we
encounter in daily life. Because each grain contains a large number of atoms, polycrystalline
materials have basically the same properties as single-crystalline materials. In particular, poly-
crystalline and crystalline silicon have qualitatively similar electronic properties. Polycrystalline
material has some localized states in the band gaps that are tremendous: there are a lot of trap
generation and recombination processes.

Figure 2.25: Thin film deposition. Image courtesy of J.Schmitz, Univ. Twente.

An amorphous material has no atomic or molecular order to speak of. It may be thought of as
a liquid with its molecules frozen in space. Thermally grown or deposited SiO2 , silicon nitride,
and Si deposited at low temperature fall in this category. At high temperature, Si atoms have
enough mobility to move and form crystals on the substrate. Carrier mobilities are lower in
amorphous and polycrystalline Si than in single-crystalline Si. However, transistors of lower
performance levels can be made of amorphous or polycrystalline Si, and are widely used in
flat-panel computer monitors and other displays. They are called thin-film transistors (TFT).

2.15 Sputtering
Sputtering is performed in a vacuum chamber. The source material, called the sputtering target,
and the substrate holding the Si wafer form opposing parallel plates connected to a high-voltage
power supply. During deposition, the chamber is first evacuated of air and then a low-pressure
amount of sputtering gas (typically Ar, most inert) is admitted into the chamber. Applying
an inter-electrode voltage ionizes the Ar gas and creates a plasma between the plates. The
target is maintained at a negative potential relative to the substrate, and Ar ions are accelerated
toward the sputtering target. The impacting Ar ions cause target atoms or molecules to be
ejected from the target. The ejected atoms or molecules readily travel to the substrate, where
they form the desired thin film. A DC power supply can be used when depositing metals, but
an RF supply is necessary when depositing insulating films. Sputtering may be combined with
a chemical reaction in reactive sputtering. For example, when T i is sputtered in a nitrogen-
containing plasma, a T iN (titanium nitride) film is deposited on the Si wafer. Sputtering is
the chief method of depositing Al and other metals. Sputtering is sometimes called a method of
physical vapor deposition (PVD).

55
 Figure 2.26: Sputtering. Image courtesy of J.Schmitz, Univ. Twente.

2.16 Chemical Vapor Deposition

While sputtering is a relatively simple and satisfactory way of depositing thin film over flat
surfaces, it is directional and cannot deposit uniform films on the vertical walls of holes or steps
in the surface topography. This is called a step coverage problem. CVD deposits a much more
conformal film, which covers the vertical and horizontal surfaces with basically no difference
in the film thickness. In CVD, the thin film is formed from gas-phase components. Either a
compound decomposes to form the thin film or a reaction between gas components takes place
to form it. The CVD process is routinely used to deposit films of SiO2 , Si3 N4 (a dielectric with
excellent chemical and electrical stability), and polycrystalline silicon or poly-Si.

Figure 2.27: Chemical Vapor Deposition (CVD). Image courtesy of J.Schmitz, Univ. Twente.

Atomic Layer Deposition

Used to deposit very thin layers such as dielectrics in MOSFET or other very small components.
First of all to initialize the reaction we deposit a catalyzer layer, called Precursor. Then, one
atomic layer of the desired material is deposited. We repeat this process as many times as we
need to be satisfied with the result.

56
2.17 Epitaxy
The process used to grow crystalline films. Whereas the deposition methods described in the
preceding section yield either amorphous or polycrystalline films, epitaxy produces a crystalline
layer over a crystalline substrate. The film is an extension of the underlying crystal.
In a CVD reactor, with special precautions to eliminate any trace of oxide at the substrate sur-
face and at sufficiently high temperature, an arriving atom can move over the surface till it stops
at a correct location to perfectly extend the lattice pattern of the substrate crystal.
Selective epitaxy is a variation of the basic epitaxy technology and has interesting device appli-
cations. In selective epitaxy deposition, an etching gas is introduced to simultaneously etch away
the material. The net deposition rate is positive, for example, atoms are deposited only over the
single crystal substrate. There is no net deposition over the oxide mask because the deposition
rate over the oxide is lower than the etching rate.
Epitaxy is useful when we want a lightly doped layer of crystal Si over a heavily doped substrate.

57
 Also, a different material may be epitaxially de-
posited over the substrate material as long as
the film and the substrate have closely matched
lattice constants. Epitaxially grown dissimi-
lar materials are widely used in light-emitting
diodes and diode lasers .The interface between
two different semiconductors is called a hetero-
junction. An application example of selective
hetero-junction epitaxial growth (of SiGe over
Si) may be found.

2.18 Interconnection
The interconnection layer on a silicon wafer is a crucial part of the integrated circuit (IC) man-
ufacturing process. It’s part of the back-end-of-line (BEOL) process, which comes after the
front-end-of-line (FEOL) steps in semiconductor fabrication.

• Front-end-of-Line (FEOL): This involves the initial stages of creating transistors and
active components on the silicon wafer. It includes processes like doping, oxidation, etching,
and the formation of the transistors, diodes, and other active elements of the semiconductor.

• Back-end-of-Line (BEOL): BEOL comes after the transistors and active components
have been created during the FEOL process. It’s primarily focused on creating the in-
terconnects that link these components to form functional circuits. The interconnection
layer involves depositing and patterning layers of metal (typically copper or aluminum)
and insulating materials (such as silicon dioxide) to create the necessary wiring between
the transistors and other components. This wiring forms the complex network that allows
electrical signals to flow between different parts of the chip.

Figure 2.28: Interconnect - Back-end process. Image courtesy of J.Schmitz, Univ. Twente.

The BEOL is interesting because it’s possible to implement inductors, capacitors or antennas.
From the first ICs, the interconnect metal has been aluminum, Al. Al interconnects suffer a
potential reliability problem called electromigration. Electron flow in the metal line, over time,
can cause the metal atoms to migrate along crystal grain boundaries or the metal/dielectric
interfaces in a quasi-random manner. Voids may develop in the metal lines as a result and cause

58
the line resistance to increase or even become open-circuited. Copper has replaced Al as the
interconnect material in advanced ICs. Cu has excellent electromigration reliability and 40%
lower resistance than Al. Copper may be deposited by plating or CVD. Because dry etching of
Cu is difficult, copper patterns are commonly defined by a damascene process. Take note that
scaling interconnections, of a factor k, increases also the resistance:

L
R=ρ (2.15)
tW
L′ L 2
R′ = ρ ′ ′ = ρ k = Rk 2 >> R (2.16)
tW tW

For this reason, we try to use very good conductivity materials like copper. But it diffuses very
rapidly in the substrate. Because Cu diffuses rapidly in dielectrics, a barrier material such as T iN
is deposited as a liner before Cu is deposited. Excess copper is removed by chemical-mechanical
polishing or CMP. In CMP, a polishing pad and slurry are used to polish away unwanted material
and leave a very flat surface.

Figure 2.29: Basic steps of forming a copper interconnect line using the damascene process: (a)
cover the wafer with a dielectric such as SiO2 ; (b) etch a trench in the dielectric; (c) deposit a
liner film and then deposit Cu; and (d) polish away the excess metal by CMP. Image courtesy
of J.Schmitz, Univ. Twente.

A flat surface is highly desirable in IC processing because it greatly improves sub-sequent optical
lithography (the whole surface is in focus) and etching. For this reason, CMP planarization may
also be performed in the front-end process, for example, in the formation of the shallow trench
isolation. Although there are several ways to perform planarization, CMP provides the best
flatness.

2.19 Testing
Testing the assembly and qualification of semiconductor parts is a critical phase in ensuring
the reliability and functionality of these components. This process involves a series of rigorous
assessments to confirm that the semiconductor parts meet specified standards and performance
criteria. The general sequence to follow is Test → choose only good ones → package.

59
Here’s an overview of the typical steps involved in the assembly and qualification of semiconductor
parts:

• Assembly Process: We attach the chip/component die to the package, and then connect
the two parts with thin wires.

• Burn-In: If we consider the Gaussian distribution that represents the production of good
chips, the tail of the graphics represents the chips/components that are not damaged but
may break when we start to use or install them. The idea behind the burn-in process is
simple, the temperature accelerates the evolution of defects so if we expose our chips/parts
to high-temperature stress we can identify the parts with potential defects.

• Final test: Evaluating the performance of the semiconductor part under various opera-
tional conditions.

• Qualification: Examining the part for any physical defects or abnormalities and providing
a certificate of compliance if the part meets all requirements.

The entire assembly and qualification process aims to guarantee that semiconductor parts not
only meet their functional specifications but also adhere to industry standards for reliability and
performance in real-world applications. If all the qualification parts are passed the components
are ready to be packaged.

2.20 Packaging
After the wafer fabrication process is completed, individual ICs are electrically probed on the
wafer to determine which IC chips are functional. The rest are marked and will not be packaged.
After this preliminary functional testing, the wafer is diced into individual circuits, or chips,
by sawing or laser cutting. Functional chips may be encased in plastic or ceramic packages or
directly attached to circuit boards. Multiple chips may be put in one package to make multi-chip
modules.
The electrical connections between the chip and the package are made by automated wire bonding
or through solder bumps. In the solder bump process, the metal pads on the IC chip are
aligned with the matching pads on the ceramic package. All connections are simultaneously
made by melting preformed solder bumps on the IC pads in what is called the flip-chip bonding
process. Finally, the package is sealed with a ceramic or metal cover before it undergoes final
at-speed testing. As the complexity of ICs increases, testing becomes more and more difficult
and expensive. Ease of testing is an important consideration in circuit design.
The quality of manufacturing and the reliability of the technology are verified with a qualification
routine performed on hundreds to thousands of product samples including an operating life
test that lasts over one thousand hours. This process is long and onerous but the alternative,
shipping unreliable parts, is unthinkable. To ensure a very high level of reliability, every chip
may be subjected to burn-in at higher than normal voltage and temperature. The purpose is to
accelerate failures in order to weed out the unreliable chips.

60
2.21 CMOS fabrication
NMOS (N-type Metal-Oxide-Semiconductor) and PMOS (P-type Metal-Oxide-Semiconductor)
transistors are the two fundamental types of transistors used in CMOS (Complementary Metal-
Oxide-Semiconductor) technology.

Figure 2.30: Cross section of a MOS transistor. Image courtesy of J.Schmitz, Univ. Twente.

Complementary MOS (CMOS) Technology:

• Integration: NMOS and PMOS transistors are integrated on the same chip to form
complementary pairs.

• Logic Implementation: CMOS logic gates are built by combining NMOS and PMOS
transistors to create efficient and low-power digital circuits.

• Applications: CMOS technology is widely used in digital integrated circuits due to its
low power consumption.
In summary, NMOS and PMOS transistors, when combined in CMOS technology, provide a
complementary pairing that is essential for creating energy-efficient digital circuits used in a
variety of electronic devices. The layout of a CMOS inverter involves placing both NMOS and
PMOS transistors on the same integrated circuit to form a complementary pair.

Figure 2.31: CMOS Inverter schematic and cross section. Image courtesy of J.Schmitz, Univ.
Twente.

61
Gate material determines the flatband VF B voltage which is a component of the threshold voltage
VT H . The cross section of the CMOS inverter is divided into two sections, the front-end is the
transistor level, back-end is everything else.

Figure 2.32: Cross section of a CMOS inverter. Image courtesy of J.Schmitz, Univ. Twente.

STI (Shallow trench isolation)

To separate adjacent transistors and prevent electrical coupling, and so electrical interference, we
need a shallow trench insulation layer (STI). To create an insulating border between the devices
we dig a trench by lithography with isolation mask and then we fill the trench with an insulation
layer, like SiO2 or other dielectric materials, this determinate the first mask (1) of the CMOS
fabrication.
There is, also, a layer of Sacox (Sacrificial Oxide) used to preserve the clean texture and to
prevent roughness due to processes and etchants. The body is p+ and it’s grown by epitaxy, in
our case the Si grown has an average doping of 7 · 1015 [1/cm−3 ].

N-well and P-well formation

We need a second mask (2) to the formation of n-wells, that is a crucial step to create isolated
regions for the fabrication of PMOS transistors.
The n-well is an area within the silicon substrate where P-type transistors will be built. The n-well
implantation performs a high-energy ion implantation of N-type dopants (typically phosphorus
or arsenic) into the exposed silicon areas. This implantation creates the n-well by introducing
N-type dopants into the P-type substrate. To avoid the ion penetration in a side that we don’t
desire to be ionized we use a photoresist thick enough to prevent this unwanted event. The same
process can be used for the p-well formation and to create isolated regions within the silicon
substrate for the fabrication of NMOS transistors. The mask used for the p-well is the same as
before (2) but we use a different photoresist.

62
Gate oxide and poly deposition
After that, there is the process of gate oxide + poly deposition, and the last one determines the
use of a third (3) mask, which is the most critical as it is needed to make the gate, which needs
to be as short as possible.
This is an example of GFT, gate-first technology, as the gate is the first component to be made to
form the final transistors. The gate oxide serves as an insulating layer between the transistor’s
gate electrode and the semiconductor substrate. It enables the control of the flow of charge
carriers between the source and drain regions. Silicon dioxide (SiO2 ) is commonly used for gate
oxide due to its high dielectric strength.
The polysilicon layer is deposited on top of the gate oxide and serves as the material for the
transistor’s gate electrode and etching it is particularly difficult. All gates at this step are the
same, so NMOS and PMOS gates are made from the same materials and later we need to
differentiate them with different materials(today the materials used are High K dielectrics).
After that, we need to define the shape of the transistor’s gate electrode on the wafer, to do this
it’s essential to apply to the gate the etch process. To remove and create the gates we can use
the two processes already explained: etching and photolithography.
This process is done as follows:

1. Deposit gate dielectric: What we need is to build the gate stack, which is done by ex-
posing the silicon, after stripping away the sacrificial oxide, and applying the gate dielectric
and then the gate material on top of it.

2. Deposit gate material: After applying the gate dielectric we need to position on top of
it the gate’s material, which is typically polysilicon (called also poly).

3. Etching the polysilicon: We need then to cut away the polysilicon everywhere except
the places where we want to have the gates. This is particularly hard as the polysilicon
needs strong etching because of its material properties.

Figure 2.33: wafer cross section in the active area region after polysilicon deposition. Image
courtesy of J.Schmitz, Univ. Twente.

63
S/D formation
After the gate etching process, which defines the gate region of the transistor, the next steps
typically involve the formation of the source and drain regions, also known as S/D formation,
using a fourth (4) mask to avoid implanting n+ in PMOS regions and do the implantation just
in NMOS regions.
The source and drain regions are formed to create the necessary regions for the flow of charged
carriers (electrons or holes) between the source and drain terminals controlled by the gate. The
source and drain regions are typically formed through an ion implantation.
Instead of relying solely on lithography to define the source and drain regions, self-alignment is
achieved by using the edges of the gate structure as a mask during the ion implantation process.
This process helps to ensure that the source and drain regions align precisely with the edges of
the gate, thus enhancing the transistor’s performance and reducing parasitic capacitance.
The right alignment, between source/drain and the gate in the junction, is essential because,
if it’s not touching the gate (outward) our transistor will not turn on as there is no contact.
Otherwise, if they are touching too much the gate (inward) there is a short circuit and we can’t
turn off the transistor. We need to do the same things for the PMOS but with the opposite
doping and using a fifth (5) mask.

Spacer formation
The formation of spacers helps define the critical dimensions of the transistor and influences its
electrical characteristics. Spacers help control the distance between the gate electrode and the
source/drain regions, influencing the effective channel length of the transistor.
A layer of spacer material, typically an insulating material like silicon nitride (SiN ) or silicon
oxide (SiO2 ), is deposited uniformly across the wafer using CVD technique.

S/D implant
Continuing we have a sixth mask (6) and a second implantation (possible thanks to the spacer
introduced which is preventing ths shortcircuit of the device) that reinforces the drain and the
source and makes it deeper to reduce the parasitic resistance (they decrease with depth). NMOS
S/D implants introduce N-type dopants (such as phosphorus) into the silicon substrate to create
the heavily doped N-type regions known as the source and drain.
In certain situations, it might be necessary to make a contact with the well region for various
reasons, such as to give a potential to the well. The process of making electrical contacts to the
well is sometimes referred to as "well contact".
In NMOS well-contact is a substrate contact that requires p+ region. To create the S/D implant
in PMOS we need a seventh mask. The PMOS S/D implant introduces P-type dopants (such as
boron) into the silicon substrate to create the heavily doped P-type regions known as the source
and drain. Like the "well contact" also here we have "substrate contact" but in this case, it’s a
n+ region. An example of the result after S/D implants is shown in Figure 2.34.

64
We need well contacts because the substrate currents (leakage) generate series resistors, and this
is an undesired condition, because it generates a substrate noise.

Figure 2.34: SEM image of CMOS digital gates after fabrication of the gate metal layer. Image
courtesy of J.Schmitz, Univ. Twente.

Salicidation
The process of fabricating CMOS continues with a step called salicidation, which uses a seventh
mask (7). Salicidation (Self-Aligned Silicide) is a crucial step in the process of forming metal
silicide on the source, drain, and gate regions of both NMOS and PMOS transistors. Salicidation
is employed to reduce the sheet resistance of these regions, enhancing the overall performance
of the transistors (as the salicide adds a small resistance in parallel to the junction one, and it
will dominate between the two). This reduction in resistance contributes to faster charge carrier
transport and improves the speed of both NMOS and PMOS transistors.
The wafer is covered by a material, typically Titanium disilicide (T iSi2 ) or Cobalt disilicide
(CoSi2 ) which is known for its compatibility with silicon, its low resistivity, and its thermal
stability, making it a suitable choice for salicidation. The process of salicidation, in this case for
titanium, is the following:

• Deposition of Ti Layer: A thin layer of titanium (T i) is deposited across the entire

wafer where the silicon is exposed.

• Annealing: The wafer is subjected to a high-temperature annealing process. During this

annealing step, the Ti reacts with the underlying silicon in the source, drain, and gate
regions, thus forming T iSi2 . The reaction will take place only where there’s silicon, not
oxide or spacers, and so the silicide is formed.

• Selective etching: After annealing, any unreacted T i is selectively etched away. The
etching process removes T i from areas where silicide formation is not desired and the
reaction didn’t occur, ensuring self-alignment to the source, drain, and gate structures.

65
An example of the result obtained after the salicidation is shown in Figure 2.35 as following:

Figure 2.35: Cross section of a MOS transistor after salicidation. Image courtesy of J.Schmitz,
Univ. Twente.

Contact formation and metallization

To conclude we have the last two masks, the eighth is used for contact formation and the last
one, the ninth, is necessary for the metallization process.
Contact formation in the semiconductor fabrication process involves creating openings in insu-
lating layers to expose specific regions on a semiconductor wafer, typically the source, drain, or
gate regions of transistors. These openings allow for the deposition of metal, forming electrical
contacts to connect different layers within the integrated circuit.
The process is made as following:

1. Deposition of dielectric and resist, then with a mask harden the resist through photons.

2. Remove the mask.

3. Etch the resist.

4. Etch also through dielectric until we reach silicon.

5. Remove the resist so obtain what we want.

Figure 2.36: Contact formation. Image courtesy of J.Schmitz, Univ. Twente.

66
As shown in Figure 2.36, if we put a hole in the mask with the gate then it will etch to the
gate, also we need only one mask for the source, drain, and gate. The etchant will etch away the
dielectric and the polysilicate until it reaches salicide gate layer.
Metallization refers to the process of depositing metal layers onto a semiconductor wafer to create
interconnections and electrical contacts between different components of an integrated circuit.

Figure 2.37: Metallization. Image courtesy of J.Schmitz, Univ. Twente.

As shown in Figure 2.37, there is a P-N junction, because of different doping of gates so,it creates
a parasitic diode but it’s short-circuited due to salicidation.
We need to do all these steps for all the levels we are trying to achieve and then at the last
level we layout a thick dielectric to prevent moisture/contaminants and to seal everything except
the contact pads. What is used here is BPSG as Boron-Phosphorus silicate glass as dielectric
resistant to these problems.

67
3 PN Junction
This chapter introduces the PN junction which is formed by imposing opposite dopings (P-type
and N-type) to two adjacent regions of the same semiconductor slab. Because the material is the
same (e.g. silicon) on both sides of the junction, we refer to it as a homojunction. As a device,
the PN junction has two terminals. The conventionally positive terminal is the one connected
to the P-side. The conventionally positive junction voltage is the potential on the P-side minus
the potential on the N-side. The conventionally positive current is taken according to the load
convention and it is the one entering the conventionally positive terminal.
A different but equally important type of junction, the metal-semiconductor junction (other-
wise denoted Schottky junction) is made of different materials; hence, it is a heterojunction.
Metal–semiconductor junctions are examined in chapter 4. Both will be analyzed firstly at
equilibrium and then in forward (V > 0 V) and reverse (V < 0 V) bias conditions.

3.1 Structure and IV curve

PN junctions can be fabricated by implanting or diffusing donors into a P-type substrate such
that a layer at the semiconductor surface is compensated and converted to N-type. It is also
possible, of course, to convert a layer of an N-type semiconductor into a P-type with acceptors.
The PN junction represents a two-terminal electron device with multiple usages, the simplest
being as an embodiment of the concept of a diode. A diode is a two-terminal passive device
characterized by a highly asymmetric IV curves, where large currents pass through the component
at one bias polarity, while extremely small currents flow in the opposite polarity.
It is instructive to start our analysis of semiconductor devices from the PN junction also because
the concepts of regional approach, quasi-neutral regions, depletion regions and the solution of the
drift-diffusion model can be put at test. The results developed in this chapter will be extremely
useful to simplify the analysis of numerous additional devices.
The static current-voltage (I-V) curve of a typical diode, the symbol to represent it in circuits,
and the conventional definition of positive voltage and current are shown in Fig. 3.1.

Figure 3.1: The I-V characteristic curve and the symbol of a PN junction.

As we can see, the curve is asymmetric and highly non-linear. We can divide it into two functional
regions that depend on the sign of the voltage applied. The first region is called the reverse-
bias region, corresponding to V < 0 V, where we have a very small, usually negligible, current.
The second one, corresponding to V > 0 V, is called the forward-bias region, where the current

68
typically is an exponential function of the applied voltage. A simple accredited model that
describes the I-V curve is:
V
I = A · Js [e ηVth − 1] (3.1)
where V is the applied voltage, Vth =kT /q, where k is the Boltzmann constant, Js is the saturation
inverse current density, A is the cross-section of the device, T is the absolute temperature in
Kelvin degrees, η is an ideality factor (usually close to one), and q is the absolute value of the
electron charge. At a room temperature of 300 K, the thermal voltage is V th = kT /q ≈ 26 meV.
It is the purpose of the following sections to show that under a limited set of approximations, Eq.
3.1 can be analytically derived with a clever use of the regional approach and the drift-diffusion
model equations.

3.2 Energy Band Diagram

Let us start building step by step the band diagram of the PN junction made of silicon or
other semiconductor material with Eg ≫ qVth . We consider a planar junction and denote x
the direction perpendicular to the junction plane (i.e., the y − z plane). We further assume the
doping to change abruptly from a uniformly doped N-type region (with a fully ionized, donor
concentration ND
+
=ND ) to a uniformly doped P-type region (with a fully ionized, acceptor con-
centration NA+ =NA ). As a general procedure (which is here proposed for the homojunction case
and will be further extended to the heterojunction case in chapter 4), we start examining the
N and P regions separately and then investigate what happens when the junction is formed
by putting the two regions in contact. It is important to underline that this ideal experiment
does not reflect the way junctions are actually fabricated. Indeed, it is practically impossible to
glue together two semiconductor crystals in a way that preserves the perfect periodic arrange-
ment of atoms and bonds across the interface. This perfection, however, is indispensable to
achieve the desired electrical properties of the junction and the behavior described by Eq. 3.1.

69
 In a PN junction at equilibrium (which is what
we eventually want to get), the Fermi level is
constant (see section 1.9.2 and top of Fig.3.2).
However, the Fermi level in the N- and P-type re-
gions, if separately taken, is given by Eqs. 1.51:
 
n
Ef N = Ef i + kT ln (3.2)
ni
 
p
Ef P = Ef i − kT ln (3.3)
ni

where the first equation applies to the N-type

material and the second one is for the P-type
material. Therefore, the conduction band
(Ec ) and the valence band (Ev ) edges in the
two regions are at different energy relative to
the intrinsic Fermi level. On the N-side the
Fermi-level is near Ec , and on the P-side it is
near Ev . That means there are many more free
electrons in the conduction band on the N-side
than on the P side, and many more free holes
on the P-side than on the N-side, consistently
with the expected effects of doping in uniform
semiconductors.
Upon formation of the junction, electrons in
the conduction band on the N-side diffuse to
the P-side, and vice-versa for the holes. This
transfer of charges from one region to the other
leaves both regions charged, and therefore shifts
the electrostatic potential energy (represented
by the conduction and valence band edges). The
process ends when the Fermi levels align to each
other, i.e. the Fermi energy is equalized across
the whole device, as expected in the equilibrium
state. Clearly, the band edges Ec and Ev are
smoothly connected to Ec and Ev on the op-
posite side, as represented by the smooth curve
across the junction plane shown in Figure C. In
every point, the bands are separated by a con-
stant Eg gap, because this is a material property
and the two sides are made of the same material.

The band diagram highlights the existence of a non-zero gradient of the band edge energies
across the junction ( ∂E
∂x =
c ∂Ev
∂x ̸= 0). We know from chapter 1 that this entails the presence of

70
an electric field in this region. The electric field is due to the fact that electron and hole diffusion
across the junction plane exposes the charge of the ionized impurities on both sides (these are
fixed charges that cannot move). Therefore, on the two sides of the junction, where the change
of doping perturbs the situation with respect to the case of a uniformly doped semiconductor, we
have two distributions of equal and non zero charge densities due to the un-compensated charges
of ionized dopants. The situation is similar to that of a capacitor, where equal and opposite
charges are located on the two plates, except that in this case there are no metallic plates; there-
fore, the charges can not pile up at the metal surface but are distributed in the form of ionized
impurities over some finite distance from the junction. It is finally reasonable to assume that,
far enough from the junction, the semiconductor recovers charge neutrality as appropriate to a
uniformly doped sample.
This analysis of the band diagram suggests that, in the perspective of using a regional approach,
we could divide the band diagram in three regions, two Quasi-Neutral regions on the sides, and
one field region in the middle, Figure D. The field region has good chances to be depleted of
free carriers, because it is the diffusion of the electrons and holes out of this region that leads to
the formation of the field. For the purpose of our analysis, we will then assume this region as
completely depleted, and then check the accuracy and adequacy of our assumption.
In the Quasi-Neutral regions, the electron and hole concentrations, n and p, are approximately
equal to the respective doping concentration, the electric field is very small, the electrostatic
potential and the band edges remain flat (see section ??).
In the Depletion Region, we see that both EC and EV are both quite separate from EF . Re-
minding that at equilibrium:
Ec (x)−Ef
 
−
n(x) = Nc e kT
(3.4)
Ef −Ev (x)
 
−
p(x) = Nv e kT
. (3.5)
and that Eg ≫ kT it is easy to see that n(x) ≪ ND and p ≪ NA , hence both negligible in
the expression of the space charge density ρ entering the Poisson equation. Therefore we can
approximate n ≃ 0 and p ≃ 0. The depletion region is defined to extend from the coordinates
xN and xP , whose value is calculated in the following sections.

3.2.1 Built-in Potential

The potential energy drop seen in the band diagram of Fig. 3.2 corresponds to a voltage drop
between the two sides of the junction, called Built-in potential (equivalently denoted with
the following symbols in textbooks and notes: ϕbi = ψ0 = ψbi > 0 V). This distortion of the
band energy levels occurs on a large distance scale compared to the interatomic distances and is
originated by the difference between the Fermi levels on the two sides of the junction.

71
To calculate the built-in potential we make use of Eqs. 3.2 and 3.3 and write:

qψ0 = Ef n − Ef p (3.6)
    
ND NA
= kT ln − −kT ln = (3.7)
ni ni
    
ND NA
= kT ln + ln = (3.8)
ni ni
  
ND NA
= kT ln (3.9)
n2i

Then:  
Ef n − Ef p kT ND NA
ψ0 = = · ln (3.10)
q q n2i
The built-in potential supports the built-in electric field necessary to balance the diffusion cur-
rent, as it creates an exactly equal and opposite drift current at equilibrium. As usual in physics,
the equilibrium state stems from the exact balance between equal and opposite phenomena.
Notice the consistency of the band diagram represen-
tation. The lower Ec entails a higher potential on
the N side compared to the P side. This is illustrated
in Figure C, which arbitrarily picks the neutral P re-
gion as the voltage reference. The electric field points
from the high the low potential and is positive (that
is, points in the positive direction of the x-axis, as
is the gradient of EC , consistently with Eq.??. The
positive electric field pushes electrons in the opposite
direction, i.e. toward the N-side electron reservoir,
thus opposing the spontaneous tendency to diffusion,
as expected. Conversely for holes on the P-side of
the junction. We also highlight that the graphs only
show the potential in the semiconductor. To contact
the junction and apply external potentials, metallic
terminals and wires will be necessary; consequently,
additional contact potential drops will develop at the
metal-semiconductor junctions. If we then try to
measure the built-in potential, ψ0 , by simply connect-
ing the PN junction to a voltmeter, no voltage will
be registered by the instrument because the net sum
of the built-in potential at the PN junction and the
semiconductor–metal contact potentials in any closed
loop is zero. Notwithstanding, it is possible to exper-
imentally measure the built-in potentials by resorting
to AC small signal capacitance measurements, as will
be explained in section ??.

72
3.3 Depletion-Layer Model
Consider a PN junction at equilibrium as divided in
three regions (two QNRs and one DR in between),
and assume valid the approximate results derived in
sections ?? and ??. In the N- and P-side of the deple-
tion region the charge density in C/cm3 is given by
the product of the signed ion valence (+1 for donors,
-1 for acceptors) times the absolute value of the el-
ementary charge (q) times the concentration of ions
per unit volume, that is:

ρN = +qND (3.11)
ρP = −qNA (3.12)

By Gauss theorem, the total flux across a closed cylin-

drical surface having base area A, extending along
the x-axis, and embracing the whole DR and parts of
the QNRs is equal to zero, because the electric field
in the QNRs is zero. Then, the absolute value of the
charges in the two parts of the Depletion Region must
be equal:

QN = QP (3.13)
qND |xn |A = qNA xp A (3.14)
|xn |ND = |xp |NA (3.15)

where |xN | and xP are the abscissae of the suppos-

edly abrupt transitions between the QNRs and the
DR. Eq.3.13 states that the side of the junction with
a higher doping level has a shorter width depletion
region, for example, if ND is larger than NA , then
the depletion region on the P-side is larger than on
the N-side. in fact: |xP | > |xN |. From the Poisson
ρ
Equation ∇ϕ = ε we can write

dEP −qNA
= (3.16)
dx ε
On the N-side, the equation is quite similar, while the boundary condition has to account for a
constant which is exactly ϕbi , and the charge density has oposite sign, so:

qND
VN (x) = ϕbi − (x − xn )2 (3.17)
2εs

73
where EP (x) is the electric field on the P-side. Upon integration over x with boundary condition
EP (xP )=0 we obtain:
qNA
EP (x) = (xp − x) (3.18)
ε
which is a linear function of x as expected based on the constant charge density −qNA . Inte-
grating once more this last equation with boundary condition V (xP )=0 we obtain the potential
V (x). The fraction of the Built-in potential developed on the P-side, becomes:

qNA
VP (x) = (xp − x)2 (3.19)
2εs

which is a branch of parabola having downward concavity and the maximum at xP , as needed to
reach a zero electric field at the xP edge of the depletion layer. The potential must be continuous
to connect the two QNRs. In fact, if the potential is discontinuous there must be a double Dirac’s
Delta layer of opposite charges on the discontinuity surface, and no such layer is present at the
junction interface. The two graphs show the curvature of the potential, which is quadratic on
both sides. We also observe that V is continuous at x = 0. The total width of the depletion
layer is given by the sum of two parts of the depletion region (notice that xN < 0):
s  
2εs ϕbi 1 1
xP − xN = Wdep = + . (3.20)
q NA ND

If the junction is strongly asymmetrical in the doping, the total depletion width can be approx-
imated as the larger between |XN | and xP . For example if NA >> ND then we can neglect xP
terms and obtain:
s
2εs ϕbi ND ∼
Wdep ≃ xN = , |xP | = |xN | =0 (3.21)
qND NA

Asymmetrical junctions are often denoted P + N (as the one in the previous example) or N + P
junctions. In the following we write NA−1 + ND−1
= N −1 and, if needed, we approximate N

to the smallest of the two dopant densities, thus implicitly assuming that the other side of the
junction behaves as a metal, with charge density distributed in a Dirac’s Delta layer of zero
thickness at the surface, and with negligible voltage drop.

74
3.4 Reverse-Biased PN Junction and Breakdown Effect
When a positive voltage VR is applied to the N
region with reference to the P region, the PN
junction is said to be reverse-biased, as shown
in the Figure. Note that according to standard
notation for passive devices, in this case the con-
ventionally positive voltage would be negative;
therefore this part of the IV curve appears on
the left half of the cartesian plot Fig.3.1. Under
reverse bias, there is very little current because
the bias polarity promotes the flow of electrons
from the P side to the N side, and of holes from
the N side to the P side, but there are very few
electrons (minority carriers) on the P side and
few holes on the N side. Therefore, the current
is negligible and so is the ohmic potential drop
R × I in the quasi-neutral N- and P- regions.
Therefore, all the (reverse) bias voltage applied
at the terminals appears across the depletion
layer. The potential energy barrier increases
from qϕbi to qϕbi + qVR . The reasoning con-
cerning the junction electrostatics in the regional
approach remains essentially the same. In par-
ticular, as the voltage drop across the junction
increases, the depletion region width increases to
accomodate the larger voltage. Therefore:
s s
2εs (ϕbi + VR ) 2εs (ϕbi − V )
Wdep = =
qN qN
(3.22)

75
Clearly, also the electric field increases, as shown in Figure:

Figure 3.2: Electric field profile across the junction as a function of position for two different
junction voltages V . The area below the curves is proportional to the total voltage drop.

Since the electric field profile is triangular, and the voltage drop is the line integral of the electric
field (that is, the area under the triangle), the potential drop across the junction is:

Emax Wdep
ϕ = ϕbi + VR = ϕbi − V = (3.23)
s2  
Emax 2ε 1 1
+ (ϕbi − V ) (3.24)
2 q NA ND

and the peak field value is

1 −1
 
2(ϕbi − V ) q 1
Emax = √ + (3.25)
ϕbi − V 2ε NA ND
√
1 −1 p
 
q ϕbi − V 1
= + ∝ ϕbi − V (3.26)
ε NA ND

We observe that the depletion layer depth, as well as the maximum electric field, depend on the
square root of (ϕbi − V ), and when the reverse voltage VR = −V increases both get larger. If
the voltage becomes too large, then the phenomenon of impact ionization kicks-in with serious
consequences on the diode operation as discussed in the following section.

76
3.4.1 Junction Breakdown
The ultimate and most important consequence
of impact ionization in reverse-biased PN junc-
tions is called junction breakdown, a phe-
nomenon that limits the ability to use the junc-
tion as a rectifier. Since junctions are commonly
encountered in many semiconductor devices, and
junction breakdown is so important to junction
operation, it is worth to discuss in great detail
how impact ionization can eventually cause junc-
tion breakdown and how its onset can be engi-
neered.
Junction breakdown occurs when the peak elec-
tric field in the PN junction reaches a critical
value when we are above the maximum reverse
voltage that can be applied. For increasing re-
verse bias voltage the maximum electric field
Figure 3.3: Representation of the break- increases; generation of electron-hole pairs by
down voltage. impact ionization sets on until a positive feed-
back loop between ionization events triggered by
electrons and those triggered by holes gives rise
to an uncontrolled rise of the reverse current.
The Joule effect heats the diode that could be
burned.

There are some types of diode called zener diode that work in this region. A zener diode is
designed to operate in the breakdown mode.

Figure 3.4: Schematic of a zener diode.

So when there is a large field present there will be a continuous process of creation of extra holes
and electrons and we’ll have more and more of them, so there will be an exponential increase of
charge and current due to impact ionization and this is what is called Breakdown effect and the
generation process is shown in the following Figure:

77
 Figure 3.5: Representation of the breakdown effect.

Consider a N + P junction, as shown in Figure, the depletion region is unbalanced on P-side, in

the depletion region the peak of the electric field is given by:
 1
2qN 2
Ep = E(0) = (ϕbi + Vr ) (3.27)
ε

and so the breakdown voltage is:

2
εs Ecrit
VB = − ϕbi (3.28)
2qN

If the electric field increases a lot, the current in-

creases and it could finish in two different mech-
anisms that depend on some factors:

• Band to Band Tunneling;

• Avalanche Breakdown.

Band to Band Tunneling generation

This mechanism is dominant in devices that are heavily doped, with large fields and low |VB |.
The electrons in the valence band cross the energy bandgap(at constant energy) to an empty
state in N-side conduction band by band-to-band tunneling. It’s possible because the energy
barrier is very thin across the space. It leads to a fast increase in the current without a positive
feedback loop. It’s present in the zener diode.
The way it works is through a quantum mechanical phenomenon in which the high field present
in the device affects the valence band electrons in a way in which they don’t need higher energy
to make the jump through the barrier but it can cross it with constant energy and without ever
changing it, given that the gap it needs to cross is thin enough (provided there is an empty state
available in conduction band it can jump to).

78
 Figure 3.6: Reverse bias with electron tunneling from valence band to conduction band.

It becomes relevant for electric field about Ep = Ecrit ≈ 106 V /cm, which is a really high field
but these fields are present in modern devices so they can’t be neglected. The current density is
given by: J = G exp (− EHp ), with G and H material constant. It has an exponential dependence
on the field and is a very fast effect that doesn’t provoke a positive feedback loop effect, but it
still gives a dangerous rise of current for the device.
There are two differences between BTBT (Band to band tunneling) and the Breakdown effect:

1. Holes and electrons are generated in two different places so they are actually spatially
separated.

2. BTBT doesn’t provoke a total loss of current control due to positive feedback loop effect
like in the Breakdown, it happens and it stops there but still gives a big rise in current.

Avalanche Breakdown

With increasing electric field, electrons traversing the depletion layer gain higher and higher
kinetic energy. Some of them will have enough energy to raise an electron from the valence
band into the conduction band, thereby creating an electron–hole pair. This phenomenon is
called impact ionization. The electrons and holes created by impact ionization are themselves
also accelerated by the electric field. Consequently, they and the original carrier can create even
more carriers by impact ionization. The result is similar to a snow avalanche on a mountainside
(Furthermore, holes accelerate to the left and generate electrons upstream, thus providing positive
feedback). When the field EP reaches its critical value Ecrit , the carrier creation rate and the
reverse current rise abruptly, this is called avalanche breakdown.
2
εEcrit
VB = (3.29)
2qN

79
 Figure 3.7: Electron–hole pair generation by impact ionization.

In general, if a larger breakdown voltage is desired it is necessary, and effective, to reduce

the junction doping concentrations. The energy that a carrier must possess to initiate impact
ionization increases (and therefore, Ecrit also increases) with increasing band gap, Eg . Thus, the
breakdown voltage, for given NA and ND , progressively increases from Ge to Si to GaAs diodes,
due to increasing Eg in these materials.

Impact Ionization
Generation by impact ionization starts when the kinetic Energy is much larger than the bandgap,
in fact EK > EG is the necessary condition for energy ionization. Electrons that are in the
conduction band can interact with electrons in the valence band and promote them to the
conduction band. It generates electron and hole pairs in any interaction.
A similar process can be triggered by a hole in the valence band. We can model generation by
impact ionization assuming that the number of pairs that are generated (denoted as ∆N ) in a
volume ∆V in time ∆t is proportional to the number of carriers that enter in ∆V , so:

∆N = αn|⃗v |∆t∆V (3.30)

where n is the electron concentration, |⃗v | is the velocity, ∆V is the volume and the α is the
ionization coefficient. For the continuity equation the U term:

number of pairs
 
U =R−G (3.31)
V ·s

80
The G term, which is the number of generated pairs in unit volume per unit time, for impact
ionization is:
∆N
GII (⃗r) = = αn n|v⃗n | + αp p|v⃗p | (3.32)
∆V ∆t
Remember that |Jn | = n|v⃗n |q, and similarly |Jp | = p|v⃗p |q, the previous formula becomes:

|J⃗n (⃗r)| |J⃗p (⃗r)|

GII (⃗r) = αn + αp (3.33)
q q

where αn and αp are the ionization coefficients of electrons and holes. We write it as |J|
⃗ to
express the impact ionization term in the drift-diffusion model with its unknowns but without
modifying the structure of the equations.
This expression however has its limitations which are that it’s valid only for large fields, while
for small fields it can create problems as there isn’t enough energy to have impact ionization
(this model doesn’t account for the condition EK > EG ).
The α coefficient could be approximated with Chynoweth’s expression:
 
Bn,p
αn,p = An,p exp − (3.34)
F

In this expression α ∝ F,
1
where F expresses the field. The coefficients An,p and Bn,p are fit to
experiments instead, the coefficient αn and αp are respectively denoted also as α and β. We can
plot the two coefficients in the function of F.
1

Figure 3.8: Ionization coefficients graphs.

In general G is larger when α and J are larger, that is a high field region with a large number
of hot carriers has a non-negligible number of carriers injected (for example depletion regions of
reverse biased junctions, such as diodes and transistors).

81
Carrier Multiplication

Consider a region of high field extending between 0 and L, the multiplication coefficient is defined
as the ratio between the current at the exit of the field region and the one injected at the entrance.
In carrier multiplication, we generate one pair from a single charge (1e− → 2e− + 1h+ ), so from
one electron we obtain two electrons and a hole.

Figure 3.9: Carrier Multiplication.

If impact ionization is the only relevant process of generation-recombination, we have that:

∂n 1 ∂Jn 1 ∂Jn
= −U = +G=0 (3.35)
∂t q ∂x q ∂x

For steady state J = Jn′ is constant for all region so the error at L=0 is J − Jn = Jp :

1 ∂Jn
G=− (3.36)
q ∂x
1 ∂Jn Jn Jp
= αn + αp (3.37)
q ∂x q q

Where Jn , Jp are the absolute values of the current density of electrons and holes respectively.
We can demonstrate that the total current density is constant.

Figure 3.10: Total Current Density.

Remember that, for continuity equation, ∂n

∂t = 1 ∂Jn
q ∂x + G = 0 in steady state, then G = − 1q ∂J
∂x .
n

Using the absolute value of the previous equation it becomes:

1 ∂Jn Jn Jp
= G = αn + αp (3.38)
q ∂x q q

There is an increase of Jn across the structure because we inject electrons, so we have an initial
value which increases along the depletion region because of carrier multiplication. Holes are not
∂p ∂p
injected, that is J = Jn + Jp = Jn . In steady state ∇J = ∂J
∂x + ∂t = 0 but ∂t = 0, then J is
solenoidal because ∇J = 0 and does not depend of x. At the interface J = Jn , Jp = 0, in the

82
other part Jp = J − Jn , these are the holes that are generated inside the region. It operates as
a current amplifier. We remain with the same assumption:

∇J = 0 (3.39)
J = Jn + Jp = constant (3.40)

In equation 3.40 we substitute the relation Jp = J − Jn and simplify the q, it becomes:

∂Jn
= (αn − αp )Jn + αp J (3.41)
∂x

Assume that the field variation is very slow, then α = α(F (⃗r)), which means that the ionization
coefficient is dependent on the field F , which is also not constant but dependent on the distance
⃗r so F (⃗r). At low field αn >> αp and Jp << Jn ≃ J. This assumption allows to neglect αp Jn
and αp J. Then:
Z L 
Jn (L) ≃ Jn (0) exp αn (F (ξ))dξ (3.42)
0
Z x 
Jn (x)
Mn = ≃ exp αn (F (ξ))dξ (3.43)
Jn (0) 0

where ξ denotes the distance and Mn expresses the multiplication coefficient, also called electron
current gain. The second equation comes out from:

dJn
= αn Jn (3.44)
dx
dJn
= αn dx (3.45)
Jn

If we integrate this we obtain:

Z x 
ln(Jn ) = αn dx (3.46)
Z 0x 
Jn = exp αn dx (3.47)
0

If F(x) is known, we can compute Mn , and, if the voltage between 0 and L increases, then F
Jn (L)
and M increase. The definition of Mn is Mn = Jn (0) ≃ J
Jn (0) and we compute:

RL Rx
Jn (L) Mn−1 + 0 αp exp − 0 (αn − αp )dξdx
≃1= RL (3.48)
J exp − 0 (αn − αp )dx
Z L Z x
1
=1− αn exp − (αn − αp )dx = 1 − In (3.49)
Mn 0 0

Then Mn = 1−In ,
1
then when In = 1 the Mn → ∞, these are the condition of the breakdown
voltage. Avalanche breakdown occurs when a positive feedback process involves electrons and
hole ionization because the contribution must come from both carriers, although this model
neglects the breakdown because we are neglecting every effect of the holes.

83
3.4.2 Zener Tunneling vs. Impact Ionization

• Band-to-band tunneling (BTBT): it’s also called zener tunneling because this type of
diode uses this mechanism to conduct. Zener tunneling has more differences than Impact
ionization and in some cases, they have different effects on the charge. If the temperature
increases, for a given electric field, the two mechanisms act in different ways.
In zener tunneling, the generation increases because the carriers have higher velocity and
kinetic energy, therefore they can break the bond more easily and move from the valence
band to the conduction band. Thus, the absolute value of the reverse current in zener
tunneling increases if the dominant mechanism is BTBT. The absolute value of reverse
voltage at which the current starts to increase rapidly, in zener tunneling, decreases. The
temperature sensitivity ( dVdTBR ) is negative in zener tunneling.

• Impact Ionization: in this case, the generation decreases because the carrier-free flight
length and duration become shorter to increase the scattering with phonons. As a result,
the kinetic energy gained is less and the number of impact ionization events is reduced.
The absolute value of reverse current in impact ionization decreases and therefore the
absolute value of reverse voltage at which the current starts to increase rapidly with voltage
in impact ionization increases. The temperature sensitivity ( dVdTBR ) of Voltage breakdown
is positive in Impact ionization.

Figure 3.11: Band to Band Tunneling vs Avalanche Breakdown thermal and voltage character-
istics.

As we can see from the figure 3.11 the diodes with VBR > 6 V are affected more by impact
ionization, VBR < 6 V are affected by Band-to-band tunneling.
A special case is represented by diodes with VBR ≈ 6 V that have almost zero temperature
coefficient and can be used as a reference voltage generators due to their great stability with
changing temperature.
In general, the zener tunneling (or Band to Band tunneling) is dominant in devices that have a
large doping concentration and the voltage breakdown is smaller than 6V as said earlier.

84
In order to control and design the breakdown voltage of the diode there are many solutions:
1. Reduce the doping: space charge density
in depletion region decreases and the depletion
layer widens. The electric field is reduced and
impact ionization is weakened. So we need to
keep low Emax and the voltage under control.
Decreasing the Emax , to have the same area be-
low (so same voltage) we obtain a widened region
by reducing the doping because dE
dx depends on
doping.

dE ρ qND −qNA
= = = (3.50)
dx ε ε ε
2. Leave enough semiconductor space around the junctions to allow the depletion
layer to expand before breakdown occurs;

3. Avoid putting high-doped regions or contacts too close to the junction;

4. Avoid corner regions: where E, electric field,
is intensified due to the junction curvature. At
the edges there is a curvature, so the electric field
is higher and the depletion region is thinner than
in the other parts of the device, so breakdown
can happen more easily at the edges due to the
high charge density ρ present here. To avoid it
Edge of Junction
we can start with a P-type and dope a region as
P + . Then add a large layer with a N + doping.
So at the corner still remains a breakdown cur-
rent, but the new junction is between n+ and
p so the depletion region is larger and the elec- Solution: Avoiding corner region
tric field peak is smaller. So the breakdown is
controlled only from the uniform flat junction.
5. Expand the depletion region with non-
doped (intrinsic) silicon. Introducing a re-
gion with zero doping (as intrinsic silicon) reduce
the Emax and introduce a region with constant
field, so:
dE
=0 (3.51)
dx

85
3.4.3 p-i-n diodes

High reverse bias voltages are necessary to avoid the existence of peaks in the field distribution,
because the ionization coefficient is proportional to the exponential of the field. In Figure 3.12
we can see the result of increasing the reverse bias voltage. When the triangle arrives to the
metal junction of the diode it increases faster because the electric field in a conductive material
is always equal to zero. Adding an intrinsic layer between the two doped regions permits to
control the depletion layer far enough from the metal contact.

Figure 3.12: Electric Field distribution around a PN junction.

In mathematical approach:

∂2ϕ qND
− = f or d ≤ x ≤ xn (3.52)
∂x2 εSi
∂2ϕ
− = 0 f or 0 ≤ x ≤ d (3.53)
∂x2
∂2ϕ qNA
− 2
=− f or − xp ≤ x ≤ 0 (3.54)
∂x εSi

To obtain the electric field we can integrate the previous functions and obtain:

qNA xp qNA (xn − d)

Emax = = (3.55)
εSi εSi

Where d is the width of the intrinsic material. If integrated another time, we obtain that the
potential ϕm is:
Emax (Wd + d)
ϕm = (3.56)
2
To obtain the width of the depletion layer:
s
2εSi (NA + ND )ϕm
Wd = + d2 (3.57)
qNA ND

86
The ratio between the Wdep,0 (without intrinsic layer) and the Wdep , for the same ϕm is:
s
Wdep d2
= 1+ 2 (3.58)
Wdep,0 Wdep,0
s !−1
Emax d2 d
= 1+ 2 + (3.59)
Emax,0 Wd,0 Wd,0

Cd Wd,0 1
= =r (3.60)
Cd,0 Wd 2
1 + Wd2
d,0

3.5 Forward Biased Junction

In the previous chapter, we discussed about reverse bias and now we pass to talk about the
forward bias of a junction. Forward bias refers to the application of a voltage across the device
such that the electric field at the junction is reduced. By applying a positive voltage V to the
P-type material and a negative voltage to the N-type material, an electric field with the opposite
direction to that in the depletion region is applied across the device. The voltage applied reduces
the gap between the conduction band and the valence band on the two sides by a factor of qV .
Given that the electric field in the depletion region is reduced, we won’t have BTBT or impact
ionization anymore, but this introduces a minority carrier injection that increases the diffusion
component, which is now larger than the drift component.
Electrons and holes move from the side where they are the majority carriers to the opposite
side, thus becoming minority carriers in that opposite region (Holes move to the N-region and
electrons move to the P-region). That means both electrons and holes contribute to the total
current.
As shown in Figure 3.13, the two Fermi levels Ef N and Ef P aren’t aligned anymore to form a
unique level, as it’s a concept valid for equilibrium, but they stay flat in their regions and also
in their depletion region, the gap between those two levels is, as said earlier, qV so is dependent
on the voltage applied.

Figure 3.13: Forward Biased PN Junction.

87
Electrons and holes are distributed according to the Fermi-Dirac function as shown in the follow-
ing Figure 3.15. As the voltage modulates the barrier, it means sweeping the Fermi distribution
of the reservoir of carriers of the region. That allows to new carriers to diffuse over the barrier
as it becomes much lower. As the barrier is reduced, a larger portion of the “Boltzmann tail” of
the electrons on the N-side can move into the P-side. More electrons are now present at xP and
more holes appear at −xN than when the barrier was higher.

Figure 3.14: Carrier concentration in forward bias.

N-side P-side
n2i
n ≈ ND n= (3.61)
NA
n2i
p= p ≈ NA (3.62)
ND

However, due to diffusion we expect that the minority carriers will be larger but due to the
recombination process the minority carrier’s density will have not a constant profile; it will be
higher near the junction and then it will decay along the region.

88
 Figure 3.15: Electron concentration distribution in a junction.

The Quasi Fermi level describes the population of electrons separately in the conduction band
and valence band when their populations are displaced from equilibrium. This displacement
could be caused by the application of an external voltage or by exposure to light energy, which
alters the populations of electrons in the conduction band and valence band.
When a semiconductor is in thermal equilibrium, there is no need to distinguish between con-
duction band quasi-Fermi level and valence band quasi-Fermi level as they are simply equal to
the Fermi level.
However, when a disturbance from a thermal equilibrium situation occurs, the populations of the
electrons in the conduction band and valence band change. In this case, it is possible to describe
it using the concept of separate quasi-Fermi levels for each band.
With the assumption of Quasi Fermi levels with the two levels Ef N and Ef P , we justify the use,
out of equilibrium, of electrons concentration equation, as a function of x.
 
Ec − Ef
At equilibrium n(x) = Nc exp − (3.63)
kT
 
Ef − Ev
p(x) = Nv exp − (3.64)
kT

 
Ec − Ef N (x)
Out equilibrium n(x) = Nc exp − (3.65)
kT
 
Ef P (x) − Ev
p(x) = Nv exp − (3.66)
kT

Far from the junction Ef N ≈ Ef , so in the junction it’s possible to demonstrate that the quasi-
Fermi level keeps a constant value in the depletion region. The difference between the two Fermi
levels is qV . The quasi-Fermi levels are defined as the energy levels that allow us to generalize
to the quasi-equilibrium conditions the expressions for the electron (and hole) density valid at
the equilibrium.
 
Ec − Ef N (x)
n(x) = Nc exp − (3.67)
kT
   
Ec − Ef P Ef N − Ef P
= Nc exp − exp (3.68)
kT kT
   
Ef N − Ef P qV
= nP 0 exp = nP 0 exp (3.69)
kT kT

89
By multiplying the first function for eEf P and e−Ef P we obtain the equation shown above. The
first exponential multiplied by Nc is the concentration of the minority carrier inside the P-region,
and it could be indicated as nP 0 . The second exponential at the numerator has the difference
between Ef n and Ef p which could be written as qV . The nP 0 at equilibrium could be obtained
n2i
as nP 0 = NA . This model is valid only if the semiconductor is not degenerate and it tells us that
at the entrance of the P-region at equilibrium the concentration of electrons rises exponentially.
The same reasoning goes also for holes and we obtain that:
 
qV
p(x) = pN 0 exp (3.70)
kT

Current density in forward bias

In steady state condition ∇J(x)+ ∂ρ

∂t = 0 because the total current density is solenoidal, however,
we can write that J(x) = Jn (x) + Jp (x) = constant. Note that only the sum of the terms J(x) is
solenoidal and the singular terms of the sum are not. From the continuity equation, we obtain:

∂n 1 dJn
= −U =0 (3.71)
∂t q dx
dJn
qU = (3.72)
Z xn Zdx xn
qU dx = dJn (3.73)
−xp −xp

At last we obtain the final result in the form of

Z xn Z xn
dJn = Jn (xn ) − Jn (−xp ) = qU dx = JGR (3.74)
−xp −xp

The result obtained, so JGR , is the generation-recombination current density. Jp (xn ) and
Jn (−xp ) are the minority carrier current densities evaluated at the edge of the depletion re-
gion. It can be shown that they are mostly due to diffusion, i.e. the drift component of the
current density is negligible for the minority carriers in a quasi-neutral region. To summarize,
the diffusion current is proportional to the derivative of carrier concentration, which we need to
know how minority carriers decay, this result comes out from the continuity equation as follows:

Ef N −Ef P n2i ( qV )
qV
n(xp ) = nP 0 e kT = nP 0 e( kT ) = e kT (3.75)
NA
Ef N −Ef P qV n2 qV
p(xn ) = pN 0 e kT = pN 0 e( kT ) = i e( kT ) (3.76)
ND

where nP 0 and pN 0 are the minority carrier at equilibrium respectively of electron concentra-
tion in the quasi-neutral P-region and hole concentration in the quasi-neutral N-region. The
concentration in the forward bias condition becomes:
qV
n′ (xp ) = n(xp ) − nP 0 = nP 0 (e kT − 1) (3.77)
qV
p′ (xn ) = p(xn ) − pN 0 = pN 0 (e kT − 1) (3.78)

90
3.5.1 Current Continuity Equation

For holes we have the following expression, from the drift-diffusion model and continuity equation:

⃗ − qDp dp
Jp = qpµp E (3.79)
dx

dp 1 1 p′
= ∇J⃗p − U = − ∇J⃗p − (3.80)
dt q q τp
where p′ = p − p0 . In forward bias, the drift current is negligible in QNR, and then only the drift
component contributes as follows:
dp
Jp = −qDp (3.81)
dx
dp
From continuity equation in steady state dt = 0 so:

dJp p′
− =q (3.82)
dx τp

By substituting the Jp expression we obtain:

p′
 
d dp
− −qDp =q (3.83)
dx dx τp

d2 p p′
qDp = q (3.84)
dx2 τp
p − p0 = p′ p = p0 + p′ (3.85)
dp d(p0 +p′ ) dp′
Dividing by qDp and substituting the p = p0 + p′ we obtain that dx = dx = dx because p0
is a constant and it disappears when derived. So the expression then becomes

d2 p′ p′ p′
= = (3.86)
dx2 Dp τp Lp 2

Therefore the same reasoning applies also to electrons, and its expression is

d2 n′ n′ n′
= = (3.87)
dx2 Dn τn Ln 2

Where Ln and Lp are the diffusion lengths that are defined, for holes and electrons, as

Lp ∼ Ln ∼
p
(3.88)
p
= Dp τp = Dn τn

d2 p′ p′
In Quasi-Neutral region dx2
= Lp 2
, for boundary condition, far from the junction assume that
p′ (∞) = 0 because there are some recombination processes. Consider that the region of the semi-
qV
conductor acts like a parasitic resistor. From Schokley boundary condition p′ (xn ) = pn0 (e kT −1).
The result came from a second-order homogeneous constant coefficient equation 3.86 that gives:
x
− Lx
p′ (x) = Ae Lp + Be p (3.89)

91
Using the boundary conditions we can find A and B and we could graph the carrier’s concen-
tration in function of the diffusion length without considering the depletion region (or actually
considering it as the Y axis, so without any depth).

Figure 3.16: Carrier’s concentration as a function of diffusion length.

So the carrier concentrations, when we consider the diffusion lengths, assume the following form:
qV x−xP
n′ (x) = np0 (e kT − 1)e Ln x < xp (3.90)
x−x
qV − L N
p′ (x) = pn0 (e kT − 1)e p x > xn (3.91)

3.6 PN diode I-V characteristics

In a diode, the current density is given by two terms, JpN (X) which is the current density of the
holes in the N-region, and JnP (X) is the current density of the electrons in the P-region of the
junction, so:
Jtotal = JpN + JnP (3.92)

Figure 3.17: Total current densities.

If we extend the equations proved previously then we can write them as:

dp′ (x) Dp qV (x−x )

− L N
JpN (x) = −qDp =q pN 0 (e kT − 1)e p (3.93)
dx Lp
dn′ (x) Dn qV (x−xP )
JnP (x) = qDn =q nP 0 (e kT − 1)e Ln (3.94)
dx Ln

92
Then the total current density is given by:
  
Dp Dn qV
  qV 
Jtotal = JpN (xn ) + JnP (xp ) = q pN 0 + q nP 0 · e kT − 1 = Js e kT − 1 (3.95)
Lp Ln

Also JGR is negligible in this sum and this whole term regarding the diffusion coefficients and
n2i
lengths, expresses the Js . At last, we can also quantify the concentrations as nP 0 = NA and
n2i
pN 0 = ND .

3.7 PN Junction as Temperature Sensor

Consider the previous equation (3.95). If we integrate it with respect to the cross-section of the
diode then we obtain the current formula, that is:

qV Dp Dn qV
I = I0 (e kT − 1) = Aqn2i ( + )(e kT − 1) (3.96)
Lp Nd Ln Na

Where:
EG
n2i = Nc Nv e− kT (3.97)
p
(3.98)
p
Lp = Dp τp Ln = Dn τn
EG
− kT
Dp = D0 e (3.99)

In these formulas, there is always a proportionality between the voltage in the diode and the
temperature dependence. The derivative of voltage with respect to the temperature gives that
the sensibility of a diode is approximately dV
dT ≈ −2 mV
K for a given constant I.
The dependence on the temperature is an inverse proportionality for Eg because it decreases with
an increase in temperature, while others such as NC and NV are weakly but directly proportional
to T as an increase in temperature gives rise to these parameters. So if we measure how the
voltage is affected by the temperature variations, given a fixed current level I, then we can
extract the temperature measurement thus making our junction into a temperature sensor.

Figure 3.18: I-V characteristic of a PN junction at different temperatures.

93
3.8 Contribution from Depletion Regions
In the depletion region to obtain the same result as in generation-recombination current in other
regions of the diode we need 2kT instead of kT to change the exponential term by one step
because the equation becomes as follows:

qV
n ≈ p ≈ ni e 2kT (3.100)

With a net recombination (generation) rate equal to:

ni qV
(e 2kT − 1) (3.101)
τdep
The total current in the diode then is given by:

qV qni Wdep qV
I = I0 (e kT − 1) + A (e 2kT − 1) (3.102)
τdep
The second part of this equation is given by the generation-recombination mechanism and an
extra current with a 120 mV /dec slope (which is shown in Figure 3.19 with a red dotted line)
which is called Space-Charge Region (SCR) current. Therefore the I-V curve becomes:

Figure 3.19: I-V characteristic of a PN junction.

As shown in Figure 3.19, some diodes for negative voltage do not have I = −I0 but a little
more due to image force barrier lowering, in fact, the total leakage current in these cases is
qni Wdep
Ileakage = I0 + A τdep .
For high voltage, it is possible to see that the current doesn’t follow the traditional I-V model:
qV
I = I0 (e kT − 1), this is due to the parasitic resistance behavior which is unavoidable and so the
curve bends for high voltages and the model does not work properly.
These parasitic resistances are due to the N and P regions and can be called R′ and R” and put
in series to the junction, so the diode, as shown in Figure 3.20.

94
 − VM +
R’ R”
− +
V
Figure 3.20: Schematic of a diode with a parasitic resistance.

So a total voltage VM can be calculated which includes the voltage across the diode and the
potential drops across (R′ + R′′ ) in the following way:

VM = V + (R′ + R′′ )I (3.103)

where VM is the measured voltage in practice, so if V and I are given it is possible to determine
(R′ + R′′ ) which is the parasitic resistance of the junction.

3.9 Capacitance-Voltage Characteristics

Figure 3.21: Charge in a PN junction.

Imagine connecting the diode represented above to a reverse bias voltage. The charge accumu-
lated on one side is equal and opposite to the charge accumulated on the other side, then we
could approximate this situation as a parallel plate capacitor where Q = CV . In a PN junction,
the charge is given by:
Q = qND |xN | = qNA xP (3.104)
√
and the xN , xP factors are proportional to ϕbi − V , so charge is non linear. Then the capac-
dQ
itance is a differential capacitance given by C(V ) = dV calculated in V = V0 , so in our chosen
bias point.
To define it we are interested in a change of charge ∆Q for a certain change in voltage ∆V . So
imagine now to change the applied reverse voltage of a ∆V , so our voltage is now V0 + ∆V . If
∆V > 0, we have less reverse voltage on the depletion layer, so the edges of the depletion region
shift inward.

95
It means that the holes from the positive region arrive to neutralize some electrons that come
from the depletion region and shrink the depletion region, thus creating a charge ∆Q > 0, and
similarly, at the opposite edge the electrons neutralize some charge and shrink the depletion
region, thus creating a charge ∆Q < 0.
So now we have a ∆Q > 0 for the P side and a ∆Q < 0 for the N side (for the charge neutrality
principle). The external circuit shows a charging flow of ∆Q and using Gauss theorem we can
demonstrate that the diode acts like a parallel plate capacitor with the following expression:

εs
Cdep = A (3.105)
Wdep

where the distance between the plates is Wdep = |xN | + xP and A is the section area. This is
called Depletion-layer capacitance which is a function of the bias point V0 which determines
Wdep . The proportionality between the capacitance and the voltage applied is inverse because:
r
2ε 1 1
Wdep = ( + )(ϕbi − V ) (3.106)
q NA ND

Then we could obtain by substituting Wdep expression into the capacitance equation that:

2
Wdep
1 2(ϕbi − V )
2 = 2 2
= (3.107)
Cdep A ε qN εS A2
 
1
N is defined as 1
N = 1
NA + 1
ND = NA ·ND .
NA +ND
We can plot the 1
2
Cdep
as a function of Vr and we
could see a linear increment of inverse capacitance as shown below.

Figure 3.22: C-V characteristic of a PN junction.

If we know the cross-section area A, then we can measure the capacitance using a LCR meter,
and therefore we can measure the built-in potential ϕbi , by finding the Vr where 1
2
Cdep
= 0.

96
3.9.1 Charge in PN Junction

Imagine now to connect the diode in forward bias. In this connection, there is an excess of
electrons and holes, that are minority carriers, near to the junction. This excess is removed by
R∞
recombination charge defined as −Qn = q xp n′ dx = ID τs where τs is the charge storage time
independent by V , in fact, τs expresses the recombination lifetime of minority carriers in a region,
where charge injection and recombination take place (so holes in N-type region and electrons in
P-type region).
In general, τs is an average of the recombination lifetimes on the N side and the P side. In
any event, I and Q are simply linked through a charge-storage time constant τs . |Qn | is also
V
proportional to |e Vth −1| because it’s the integral of the concentration n′ which is also proportional
to this term. We can build a dynamic diode’s current model which can be written as:

Q dQ
ID = + (3.108)
τS dt

Where the first term is a static charge component and the second term is a dynamic component,
called displacement current, due to the variations of minority carrier accumulation, and so due
to diffusion. At last, we can also add the dynamic current term due to the depletion region which
can be expressed as:
dQdep dQdep dV dV
= = Cdep (3.109)
dt dV dt dt
So the final expression of the current ID becomes the following:

Q dQ dQdep Q dQ dV
ID = + + = + + Cdep (3.110)
τS dt dt τS dt dt

Figure 3.23: Charge in a PN junction.

So in a PN junction we have two contributions to differential capacitance, one dominant in

forward bias, which is the one due to diffusion Cdif f , and in reverse bias the dominant one is the
depletion region Cdep instead.

97
Figure 3.24: Variation of Capacitance in function of Voltage.

98
4 Metal-Semiconductor Junction
Differently from a normal PN junction, the metal-semiconsductor (MS) junction is made by
bringing into contact two different materials: a metal, and a semiconductor. There are two very
different electrical behaviors and devices we can obtain out of metal-semiconductor junctions:
Schottky diodes, made by metal on lightly doped silicon and featuring a strongly asymmetric,
rectifying behavior between forward and reverse bias, and low resistance ohmic contacts, usually
made by metal on a heavily doped semiconductor and featuring a symmetrical, low resistance
behavior with very modest difference between forward and reverse bias.

4.1 Band diagram of the metal-semiconductor junction

In order to construct the band diagram of an hetergeneous junction made out of different ma-
terials we need to find a common reference for the energy of the two systems when they are
separate, so that the relative alignment of the conduction and valence band states can be found.
This common reference is provided by the vacuum level. Fig.4.1 shows the energy band diagram
of the MS system at flat band, when the materials are separate, and the reference vacuum level.
The figure also defines the most important quantities to properly align the energy levels.

Figure 4.1: Energy band diagram of the MS system assuming each region is at flat band and the
two materials are not interacting (a).

• E0 : Energy level at vacuum [J]

• EF M : Fermi level of the metal [J]

• EF S : Fermi level of the semiconductor [J]

• EF I : Intrinsic Fermi level [J]

• ΦM : Metal work function [V]

99
 • χS : Electron affinity of the semiconductor [V]

• EC : Conduction band [J]

• EV : Valence band [J]

• EG : Energy band gap [J]

For the avoidance of doubts we emphaisze teh measurement units of the different quantities
adopted in this figure. Since a few of them are usually given in Volts, they need to be multiplied
by q prior to comparing them to energies in Joule. However, if the energies are reported in
Electronvolts, then this multiplcation is not needed and the number extressing the energy in
electronvolts can be combined in the same expression with the number expressing the metal
workfunction or the affinity in Volts in spite of the two quantities having different measurement
units. Also note that in the adopted notation ΨM and χS denote the absolute value of the
distance between the energy levels, that is the length of the doubly arrowed segment. This is
important to define the signes in the expressions without errors.
Figure 4.1 shows that in general the Fermi levels of the two materials are misaligned. To measure
the Fermi level of a metal we use the Photoemission experiment in which we shine light, so
photons, with increasing frequency ν, hence energy Eph = hν, and measure at which frequency
and energy the metal starts to emit electrons into vacuum. Since the highest energy electrons
that will exit the metal first are those at the highest occupied energy level, that is the Fermi
level of the metal, the frequency at which emission starts will give us a measure of the distance
between the vacuum level E0 and the Fermi level EF M . This energy difference is called Metal
work function, denoted as ΦM [V] (sometimes also denoted as ψM ), and, if measured in Joules,
can be expressed as follows:
qΦM = E0 − EF M (4.1)

A photoemission experiment conducted on an N-type semiconductor cannot extract electrons

from the Fermi level EF S because this level lies in the band gap, which is a forbidden energy
range for electrons. The highest energy electrons available in the system are at the bottom of
the conduction band. Therefore, the photoemission experiment will measure the position of the
conduction band edge with respect to vacuum, a quantity denoted electron affinity. In the
semiconductor, which in our example is N-type doped (as can be seen from EF S approaching
the conduction band EC and considering that (EF S − EF I ) = kT ln ( NnD
2 )), the energy difference
i
between the Fermi level and the vacuum energy can be calculated as:

EG
q χS + − (EF S − EF I ) (4.2)
2

where we neglect the small difference between the midgap (EC + EV )/2 and the intrinsic Fermi
level due to the small difference between the effective density of states in the conduction and the
valence band of silicon. Now we join the two materials thus granting continuity to their Fermi
levels as shown in Figure 4.2.

100
Figure 4.2: Band diagram of the MS system at equilibrium, i.e. with aligned Fermi levels (b).

As before we analyze the band diagram after imposing a constant Fermi level EF =EF M =EF S
across the two materials, as appropriate for the equilibrium state. This implies that upon creation
of the contact between the two materials, one of the two charged up with respect to the other in
order to change the reative energy of the two systems until equilibrium is reached. On the metal
side, we have the same qualitative situation as before, with all filled states beneath EF M =EF and
completely empty above it. We note that because the electric field inside a perfect conductor is
always zero and any meal charge lies at the surface, the energy bands of the metal are flat. Indeed,
not visible in the figure is the fact that, because some charge transfer has occurred between the
materials, the metal must have a thin sheet of charge at the surface with the semiconductor.
In the semiconductor part of the device, however, we argue that, out of the interface region
where the junction with the metal has perturbed the semiconductor, the bands must be flat and
the relative position of the semiconductor energy levels EC and EF S =EF must be the typical
ones for N-doped silicon (so a quasi-neutral region). At the interface with the metal instead, the
bands are bent upward, due to the fact that in our example EF S prior to junction formation is
higher than EF M , As can be deduced by the slope of the bands, some negative electric field has
built up on the semiconductor side of the interfacial region.
In the region with this negative field, there is also a depletion region because the negative electric
field pushes the free electrons away from the interface with the metal. Obviously, at equilibrium
the current must be zero. Therefore, the drift current caused by the electric field is balanced by
a diffusion current of electrons moving from the quasi neutral N-type region toward the depleted
surface region having a depthW .
We observe that the electrons in the metal, most of which occupy states below the Fermi energy,
cannot moe into the semiconductor because the Fermi energy in the semiconductor lies in the
band gap. At last, we can introduce a quantity ΦB called Schottky Barrier energy which
represents the energy needed by electrons at the Fermi energy in the metal to reach the energy

101
level of the semiconductor conduction band, where electron states are available and can be
occupied, thus making possible the electron transfer from the metal to the semiconductor.

qΦB = qΦM − q χS [J] (4.3)

ΦB = ΦM − χS [V ] (4.4)

From this equation we can see that the barrier energy is a function of the work function of the
metal. Since we focused on electrons, we adopt a more precise symbolϕBn for this Barrier energy
for the electrons.

Figure 4.3: Band diagram of the MS (Schottky) junction.

We can then note from Figure 4.3 that qϕBn = qψM − q χSi or equivalently in volts
ϕBn = ψM − χSi which means that the barrier energy ϕBn is a function of metal material due to
the ψM presence. Another important relation is that the sum of the barrier energies for electrons
and holes are exactly the same as the energy gap of the semiconductor, which technically means
that
qϕBn + qϕBp = EG (4.5)

At last, we can also see from Figure 4.3 that at the metal-semiconductor interface, there are
some localized states that act as traps because the difference in the crystalline structure of the
materials unavoidably leads to the presenece of numerous broken (so called dangling) or distorted
bonds at the interface, which generate electron states having energy outside the bands. These
states are localized n proximity of the contact surface and they can accumulate charge as they
trap electrons. To calculate the built-in voltage drop (that, differently from the pn junction,
here develops only across the semiconductor material) we need to quantify the difference in
Fermi levels prior to junction formation. This is given by the metal and the semiconductor

102
work-functions, ψM and ψS in Figure 4.3, and we can write it as follows:

qψM = E0 − EF M (4.6)

while for ψS we have that

 
ND
qψS = E0 − EF S we can express EF S = EF i + kB T ln (4.7)
ni
   
ND Eg kB T NV
= E0 − EF i − kB T ln and E0 − EF i = qχSi + − ln (4.8)
ni 2 2 NC
   
Eg kB T NV ND
= qχSi + − ln − kB T ln (4.9)
2 2 NC ni
 
the minus in − kB2T ln NV
NC is due to the fact that the logarithm term is a negative number (NV
is smaller than NC in silicon) thus leading to a positive contribution term. After calculating
both ψM and ψS we can finally express the built-in potential ψ0 =ϕbi as follows

qψ0 = q(ψM − ψS ) (4.10)

which also quantifies the band bending as it is due to the difference between the two Fermi levels
in the first place.
Note also that in a Schottky junction to change in an important manner the built-in potential it
is sufficient to modify the metal used for the junction, thus changing ψM , and with appropriate
metals, the built-in potential can be much smaller (or can even be negative) with respect to the
typical built in voltages of PN junctions (around 0.6 ∼ 1 V).

103
4.2 Fermi Level Pinning
Since we have two materials with different crystal structure, at the interface there are numerous
distorted or broken bonds that do not form as if they were in the bulk of the respective crystal.
These conformation defects and imperfections generate a high density of states with energy in
the band gap which behave as traps for the carriers. Traps are localized states that can be
charged upon capture or emission of an electron or a hole.

Figure 4.4: Representation of acceptor and donor type interface (surface) states.

Typically but not exclusively, the trap states at the semiconductor surface can be classified into
two groups, as shown in Fig. 4.4.

• Donor states: are typically situated at energies below the midgap. These states are
neutral if the state is occupied by an electron and otherwise positively charged (+) if the
state is empty.

• Acceptor states: are typically situated at energies above midgap. These states are
negatively charged (-) if the state is occupied and neutral if it is empty.

We can now distinguish two cases in which this phenomenon modifies the band diagram at the
surface, in the case of a large band bending and a small band bending.

Large band bending

In this case without the surface states (traps) the intrinsic Fermi level at the surface EF I is above
the constant Fermi level EF , but the states below EF I and also above EF are of donor nature
and empty, so they are positively charged (+).
This positive charge forms a dipole and because of this charge, the potential at the surface is
going up thus bringing the bands slightly down instead of letting the band go up even more. So

104
the more we try to push the bands up the more they’ll try to go down because they try to stay
closer to EF level instead of being bent upward. So because of Fermi level pinning the Fermi
level at the interface gets closer to the midgap than it would without the presence of interface
states.

Figure 4.5: Fermi level pinning in case of large band bending.

Small band bending

In this case without the surface states the intrinsic Fermi level at the surface EF I is below the
constant Fermi level EF , but the states above EF I and also below EF are of acceptor nature and
are filled, so they are negatively charged (-). This negative charge forms a dipole and because
of the charge the potential at the surface is pulled down thus bringing the bands up instead of
letting the band flatten even more. So the more we try to flatten the bands the more they’ll bend
upward. So also in this case because of the Fermi level pinning the Fermi level at the interface
tries to get closer to the midgap than it would without the interface states.

Figure 4.6: Fermi level pinning in case of small band bending.

105
4.3 MS junction electrostatics

Figure 4.7: Band diagram of the MS junction in forward and reverse bias.

Figure 4.7 shows the band diagram of a metal-semiconductor junction at equilibrium (in black)
and with positive applied bias voltage V (in green). Due to the Fermi level difference in the
separate materials, a built-in band bending and a negative electric field appear. If the band
bending is large enough compared to kT , then a depletion layer forms at the surface at equilibrium
where n ≃ 0. The width of the depletion layer in this N-type semiconductor can be calculated
with Eq.3.22.
In this equilibrium condition, electrons from the semiconductor quasi-neutral region can dif-
fuse toward the metal, but only those at energy above the top of the barrier can reach the
interface and pass into the metal due to the existence of a built-in potential drop in the semi-
conductor. Conversely, electrons from the metal are blocked by the barrier and only those above
the top of the barrier ϕBn can diffuse into the semiconductor. Since the Fermi level is the same
on both sides of the junction, and both fluxes are due to diffusion, the electron concentration
and the thermal velocity, hence also the current density, are the same for the forward and the
backward flows, which results in a zero net current density as expected in equilibrium. The
positive charge per unit area in the depletion layer is easily quantified as +qND Wdep (similarly

106
to the PN junction case, Eq. ??). This charge is compensated by an equal and opposite negative
charge at the surface of the metal facing the semiconductor.

If we apply a positive voltage V > 0, then the bands become less bent, as shown by the
green line; the depletion region width shrinks, and the built-in energy barrier decreases as a
function of q(ϕbi − V ). The flux of those electrons diffusing from the semiconductor to the
p

interface and then continuing their motion in the metal is now larger than at equilibrium. The
electron flow from the metal to the semiconductor, instead, remains the same, since the surface
barrier height ϕB is unchanged. Indeed, only those few carriers in the high energy tail of the
Fermi-Dirac distribution above ϕBn from the metal Fermi level can actually reach the N-type
region. These are overwhelmed by the diffusion flux from the semiconductor to the metal. As
a result of the unbalanced fluxes, a positive current flows due to electrons with negative charge
exiting the positively biased metal terminal.

If we apply a V < 0 instead, the diode is in reverse bias, i.e. in the off state. We observe a
small and negative current I, because the conduction band energy level on the semiconductor side
is pushed downward with respect to the metal Fermi level, so the semiconductor band bending
and the width of the depletion region, Wdep , increase. The diffusion flux from the semiconductor
to the metal is essentially suppressed by the high barrier height ϕbi − V , while the electron flux
from the metal to the semiconductor, limited by the barrier ϕB , remains the same.
Notice that the junction behavior is fully explained by the unbalance between electron fluxes
only, no role being played by the holes. We can say that the Schottky barrier in Fig.?? is an
unipolar junction, where current is only due to electrons. This observation has important
physical implications for the junction switching speed, as explained in more detail in the follow-
ing sections.

The built-in voltage in the semiconductor is expressed as follows (in Joule):

qϕBi = qϕBn − (EC − EF ) (4.11)

 
which can be rewritten considering that according to eq.?? EC − EF = kT ln NC
ND as
 
NC
qϕBi = qϕBn − kT ln (4.12)
ND

and equivalently in Volts as  

kT NC
ϕBi = ϕBn − ln (4.13)
q ND
For the depletion layer instead, we can calculate its width with the usual formula, but considering
we have a V < 0 we can write the V term in the formula as +|V | instead of −(−V ), this is also
the reason why the depletion layer grows larger.
s
2εs (ϕBi + |V |)
Wdep = (4.14)
qND

107
We can now calculate the differential capacitance due to the depletion layer using the same
formula for the parallel plate capacitor derived for the PN junction; that is:

εs A
C= . (4.15)
Wdep

Now we have all the necessary equations to calculate the ϕBi , as we can algebraically manipulate
the capacitance formula and express it as 1
C2
to obtain the following equation and then plot it
as a function of the voltage V .
1 2(ϕBi + |V |)
2
= (4.16)
C qND εs A2

Figure 4.8: Plot of the inverse squared junction capacitance versus voltage, useful to extract the
built-in voltage.

If we consider Eq. 4.16 and its graphical representation in Figure 4.8, then we clearly see that
the intercept with V axis corresponds to the condition V = −ϕBi ; that is how we extract the ϕBi
parameter from capacitance measurements. Once the built-in voltage ϕBi has been extracted,
and provided the semiconductor doping ND is known, we can extract also the barrier energy ϕB
(in this case ϕBn ) using  
NC
qϕBi = qc − kT ln (4.17)
ND
and equivalently in volts as  
kT NC
ϕBi = ϕBn − ln . (4.18)
q ND
An alternative mean to extract ϕBn from the inverse saturation current density will be discussed
in the following sections.

4.4 Thermionic Emission Theory of MS junction current

Several physical models exist to predict the IV characteristics of MS junctions. In the following,
we describe the simplest of them, which relies on a classical view of electrostatics and transport

108
in semiconductors and metals as the one expressed by the drift-diffusion model. The theory
neglects additional contributions to the current, which may become important for instance in
the reverse bias condition. Namely: interband tunneling through the Schottky barrier which can
become important at high doping and/or high reverse bias.

Figure 4.9: Device and band diagram considered for the calculations.

We consider a Schottky junction in forward bias as illustrated in Fig. 4.9; therefore, the
band bending is smaller than in equilibrium conditions. Based on the results of the previous
section, we know that generation/recombination processes are negligible, i.e., U = 0 everywhere.
Furthermore, there are almost no holes, because there is no P-type region. Therefore Jtot ≈ Jn
as the only free carriers in the metal are electrons) and most of the electrons come from the
semiconductor to the metal as the metal has a high barrier energy. Therefore, in steady state,
the continuity equation for the electron current density predicts that Jn is solenoidal:

∂ρ ∂ρ
∇ · J⃗n + = 0 with = 0 so ∇ · J⃗n = 0 . (4.19)
∂t ∂t

Then, we know that in one dimension the current density and the electron current density are
constant everywhere along the structure; thus, similarly to the PN junction case, we can compute
J⃗n at any abscissa we deem useful. In the following, we work out the calculation at an abscissa
on the semiconductor side of the junction and infinitely close to it of the junction as the location
of the calculation x=0+ . To proceed, we first remind that in general J⃗n = ρ⃗v and ρ is the density
of the charges moving in from the semiconductor to the metal and ⃗v is the average x-component
of the velocity. Since most electrons reach the x=0+ point by diffusion from the semiconductor
to the interface, we calculate the electron concentration n as follows,
(EC −EF )
n = NC e − kT with EC − EF n = qϕB − qV so (4.20)
(ϕB −V )
= NC e−q kT and it can be expressed also as (4.21)
 3
2πmn kT 2 −q (ϕB −V )
=2 e kT (4.22)
h2

The velocity distribution of these carriers will be essentially isotropic in all three spatial dimen-
sions so that only half of them have negative vx < 0 and is actually able to cross the barrier.

109
The average modulus of the velocity vector ⃗v (in all three dimensions) of a quasi-equilibrium
distribution of carriers is the so called thermal velocity introduced in chapter 1 and copied here
for convenience:

3 1
Ek = kT = mn vth 2
solving for vth (4.23)
2 2
r
3kT
vth = (4.24)
mn

In this case, however, the y− and z− velocity components do not contribute current, since
they are parallel to the interface. We should instead consider only the average velocity in the
x-component, which can be expressed as:
r
2kT
vthx = − (4.25)
πmn

vthx has negative sign (-) because the electrons that enter the metal are moving in the opposite
direction with respect to the x axis. We are now fully equipped to calculate the current density
going from the semiconductor to the metal through diffusion as:

n
JS→M = −q vthx (4.26)
2

which is positive, as expected. Substituting Eqs. 4.20 and 4.25 we get:

1
JS→M = − qnvthx (4.27)
2
4πqmn k 2 2 − qϕB qV
 
qϕB
= T e kT e kT and if we consider J0 ≈ 100 exp − (4.28)
h3 kT
 
qV
= J0 exp (4.29)
kT

and similarly to the PN junction we obtain a constant term J0 , dependent on ϕB so on the

chosen metal, and an exponential term which is dependent on the voltage V applied. Once again
we find that the exponential voltage dependence stems from the Boltzmann factor in the energy
distribution of the carriers in near-equilibrium concentrations.

110
4.5 Schottky Diodes
Let us analyze now the current-voltage characteristic of a Schottky diode as sketched in the
following Fig. 4.10:

Figure 4.10: I-V curve of a diode.

We’ll discuss three different bias conditions:

• V = 0, Equilibrium State.

• V < 0, Reverse Bias.

• V > 0, Forward Bias.

Equilibrium state

Figure 4.11: Band diagram of a Schottky junction in equilibrium.

At equilibrium the junction is unperturbed. We have an energy barrier E − EF = qϕB and some
band bending on the semiconductor side of the junction. Also, we know that Jtot = 0 due to the
equilibrium state.
From previous arguments and calculations, we know that the current from the semiconductor to

111
the metal is IS→M = I0 = J0 A where A is the cross-sectional area of the junction. We also know
that the sum of all contributions to the current should satisfy the condition Itot = AJtot = 0.
Besides IS→M , at equilibrium we also have the additional current IM →S , which is the electron
diffusion current flowing from the metal to the semiconductor (there is no electric field, hence
no drift current in the metal). This means that Itot = IM →S + IS→M = 0; hence, IM →S = −I0
to satisfy the equilibrium condition.

Reverse Bias

Figure 4.12: Band diagram of a Schottky junction in reverse bias.

In this case we apply a voltage V < 0 V to the metal with respect to the semiconductor, which
means that the energy bands on the semiconductor side will shift downward by a quantity q|V |,
thus increasing the total band bending on the semiconductor side to increase above the barrier
energy qϕB needed for the electrons to transfer from the metal to the semiconductor, see Fig.
4.12. In fact, the current IS→M is now strongly reduced, because there are many less electrons
with enough energy to overcome the barrier and diffuse into the metal. If |V | ≫ kT /q, we can
assume
IS→M ≈ 0

, whereas the current from the metal to the semiconductor remains essentially the same as before,
i.e. IM →S = −I0 due to the unchanged energy barrier qϕB . This means that

Itot,rev = IM →S + IS→M = −I0 . (4.30)

because only the flux from the metal to the semiconductor is significant, while the opposite one
is now negligible.

112
Forward Bias

Figure 4.13: Band diagram of a Schottky junction in forward bias.

In this case, a positive voltage is applied, V > 0 V, which means that the semiconductor bands
are less bent, the depletion layer shrinks, and the effective energy barrier for electrons diffusing
from the semiconductor to the metal is smaller than in the previous case. As a result, the
diffusion current from the semiconductor to the metal is much larger, and more electrons can
overcome the barrier and make it into the metal. We can express this current component as
qV
IS→M = I0 e kT . (4.31)

whereas the current from the metal to the semiconductor remains unchanged for the very same
reasons mentioned before. Hence, IM →S = −I0 . The total current through the junction is then
given by

Itot = IM →S + IS→M (4.32)

qV
= I0 e kT − I0 (4.33)
qV
= I0 (e kT − 1) (4.34)

The term I0 is given by Eq.4.27:

4πqmn k 2
 
−qϕB A
I0 = AKT e 2 kT where K = ≈ 100 . (4.35)
h3 cm2 K 2

This term is independent of the applied voltage but highly sensitive to the ϕB = qΨM − qΨS .
By changing the metal, hence the metal workfunction, we can modulate the current by many
orders of magnitude because as ϕB decreases our I0 grows exponentially.

113
4.5.1 Applications of Schottky diodes

Figure 4.14: I-V curves for PN and Schottky junctions, linear scale (left), logarithmic scale
(right).

As discussed in the previous section, metals having a small workfunction will create small barriers
to the semiconductor. In turn, the diode current will be large and likely much larger than for
a conventional PN junction of equal area. The I0 of a Schottky diode can easily be 103 to 108
times larger than that of a PN junction diode. Due to the exponential dependence of the current
upon voltage, for a given threshold current the MS junction will have a smaller diode turn-on
voltage (VON ≈0.2÷0.3 V) than that of PN junctions (VON ≈0.5÷0.6 V). This is illustrated
in Figure 4.14 This property makes Schottky diodes the preferred choice for low voltage/high
current applications such as rectifiers and sampling bridges. At last, the Schottky junctions
are unipolar and so there is no minority carrier injection across the junction; therefore, these
diodes can operate at higher frequencies than the PN junctions, which makes them suitable for
high-frequency applications as well.

4.6 Image force barrier lowering

Questo argomento non è stato discusso nell’anno accademico 2023-2024 ma è di una certa im-
portanza generale e in particolare per le giunzioni MS. Ricordarsi di scriverlo in una versione
estesa della dispensa.

4.7 Quantum Mechanical Tunneling

The MS junction theory discussed above neglects quantum mechanical tunneling through the
energy barrier, which is instead an important factor worth more extensive consideration.

114
Figure 4.15: Tunneling mechanism for an electron through a barrier.

115
Quantum mechanical tunneling is the process that allows particle to penetrate energy barriers
that define classically forbidden regions of space. The process can be visualized by considering
an electron wavepacket representing a single classical particle, or a plane wave representing a
continuous stream of particles with kinetic energy E that travel in space until they impinge a
potential energy barrier VH > E. While a classical particle would be elastically reflected by the
barrier, the electron wave is partly reflected and partly transmitted beyond the barrier, and will
emerge on the other side of the barrier with a finite tunneling probability P .
The tunneling probability P can be calculates with a general method of quantum mechanics
known as the WKB (Wentzel-Kramers-Brillouin) method, which yields:
r !
8π 2 m
P ≈ exp −2T (VH − E) . (4.36)
h2

We observe that P has an exponential dependence on the barrier height (VH − E) which is the
difference between the potential energy level VH and the electron wave energy E. The length
of the tunneling path, that is the thickness of the barrier also plays an important role, since
P decays exponentially as T increases. When the electron wave encounters the barrier, part
of the wave is reflected back (thus giving rise to stationary waves). The transmitted part will
travel through the barrier and undergo an exponential decay through the whole thickness of the
barrier T . Therefore, the wave surpassing the barrier will have only a fraction of the initial
wave amplitude. The ration of the squared amplitudes defines the transmission coefficient of the
barrier.

4.8 Ohmic Contacts

Semiconductor devices are connected to each other in an integrated circuit through metal lines
ideally acting as short circuits; in practice as low resistance interconnects. Those semiconductor-
to-metal contacts should not create asymmetrical barriers to current flow, nor strongly voltage-
or current- dependent potential drops. They should instead have very low resistance and, if any,
constant voltage drops irrespective of the current or voltage. If this is the case, then the contacts
do not degrade the device’s performance too much. Contacts with constant potential drop (if
any) and zero resistance are ideal ohmic contacts.
In the previous paragraphs we have seen that a Schottky junction to a moderatly doped semicon-
ductor has good chances to behave as a diode wth highly asymmetrical IV curves. The question
is, then, how to make sure that, if needed, the rectifying behavior can be suppressed and the
behavior of a good ohmic contact can be obtained. One way to achieve this result would be
to increase bilateral electron tunneling through the barrier; clearly, this can happen only if the
depth of the depletion layer (which is part of the tunneling path) is reduced to negligible val-
ues such that it can be bidirectionally penetrated in both directions. Since the depletion layer
thickness is given by s
2εs ϕBn
Wdep = , (4.37)
qNd

116
by increasing the doping Nd we can reduce W : dep thus increasing the tunneling probability.
Thanks to this change, the device can conduct both ways of the thin barrier, so it becomes a
symmetric device, as n ohmic contact should be.
Hϕ
r
− √ Bn 4π εs mn
P ≈e Nd
with H = (4.38)
h q

Eq. 4.38 expresses the tunneling probability at V = 0. The depletion layer of the heavily doped
Si is only tens of Å thin because of the high dopant concentration and when the potential barrier
is very thin, the electrons can pass through the barrier by tunneling with a large probability.
The tunneling barrier height ϕB instead is much more difficult to control, due to surface dipoles
and traps; this is why it is preferable to act on the doping Nd .

Figure 4.16: Band diagram at V = 0.

Now we apply some positive

q voltage V > 0, and if we substitute into Eq, 4.38 the thickness of
Wdep
the barrier T = 2 = ε2qN s ϕBn
d
and the doping dependency, then we obtain the expression for
the current density from the semiconductor to the metal:
r −V )
1 kT − H(ϕ√Bn
JS→M ≈ qNd vthx P = qNd e Nd
(4.39)
2 2πmn
By applying a positive voltage, we are lowering the barrier and therefore increasing the tunneling
probability, as was said previously, so also the current density reasonably is dependent on the
(ϕBn − V ) term.

117
 Figure 4.17: Band diagram at V > 0.

Let us now define the contact resistance, which will contribute to the specific contact resistance
as follows (using the definition of conductance and then taking the inverse)
HϕBn
 −1 √
HϕBn
dJS→M 2e Nd
√
Rc = = √ which is ∝e Nd
(4.40)
dV V =0 qvthx H Nd

so also the resistance has an exponential dependence on ϕ : Bn.

As said earlier the specific contact resistance should be very low in ohmic contacts; typical values
are now around 10−7 -10−10 cm
Ω
2 with doping around Nd = 10
20 , see Fig. 4.18. Achieving this

high doping is complex because of solubility limits. In fact, depending on the semiconductor
but typically above a few units times 1019 dopants per centimeter cube, interactions between
ionized impurities, aggregations, and sedimentation/condensation can occur that limit the dopant
activation in the crystal.

Figure 4.18: Resistivity as a function of doping.

118
The high doping is necessary also to guarantee a linear behavior in the I-V curve, as with high
doping the exponential dependence is no longer visible and instead we have a linear current-
voltage dependence, as in a resistor (that’s because high doping implies also a thin Wdep and
a large tunneling probability P as said earlier). This behavior is shown in the following Figure
4.19 and is essential for a good quality ohmic contacts.

Figure 4.19: I-V curve with high doping (and low doping situation in red).

119
4.9 Dielectric Relaxation Time
As explained in the previous sections, the switching of a PN junction from forward to reverse
bias entails substantial recombinations of the excess minority carriers accumulated in the quasi-
neutral regions. The time scale of this process is set by the carrier lifetimes, which are inversely
proportional to the doping, and range from the ns to the ms. The current flow through a
Schottky junction, instead is essentially due to majority carriers in both forward and reverse
bias conditions. The Schottky junction switching between the on and off states entails a spatial
redistribution of the majority carriers on the semiconductor side and the widening or narrowing
of the depletion layer. The relaxation of excess majority carriers within or at the edges of a
quasi-neutral region occurs on a time scale which is not that of the carrier lifetimes as in PN
junctions, but is set by the so-called dielectric relaxation time td . It is the purpose of this
paragraph to derive a simple analytical model to estimate td in order to compare the order-of-
magnitude switching speed of these two junctions. We start considering a uniformly N-doped
semiconductor slab with a negligible concentration of minority carriers. Since we want to solve
a transient, i.e. a time depedent problem, we have to start with the continuity equation for the
majority carriers; we do it neglecting the generation-recombination processes (i.e. with U = 0)
due to the negligible hole concentration level:

∂n 1 ∂Jn 1 ∂Jn
= +U = (4.41)
∂t q ∂x q ∂x

To evaluate Jn , we start from the drift-diffusion model

dn
Jn = qµn nE + qDn . (4.42)
dx

If the doping and the perturbation of n are uniform in space, then the diffusion term can be
neglected as dn
dx = 0; in other words, we express the current density as mostly due to the
drift component, as already hypothesized when introducing the main properties of quasi-neutral
regions in section ??. Furthermore, the conductivity is mostly due to the majority carriers and
can be written as σn = qµn n. We then have:

Jn = qµn nE = σn E (4.43)

Now substituting Jn into the continuity equation we obtain that:

∂n σn ∂E
= (4.44)
∂t q ∂x

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The spatial derivative of the electric field can be obtained from the Poisson equation for the
electrostatics, that is:

∂E ρ
= then we write ρ using Poisson equation so ρ = q(Nd − n) (4.45)
∂x εSi
q(Nd − n)
= taking the minus sign out (4.46)
εSi
−q(n − Nd )
= (4.47)
εSi

Upon substitution of this result into the continuity equation we obtain

∂n σn −q(n − N − d) (n − Nd )
=− = −σn (4.48)
∂t q εSi εSi

Since the doping is constant, we can substitute dn = d(n−Nd ) and write the differential equation
in the variable n − ND as follows

d(n − Nd ) σn
=− (n − Nd ) (4.49)
dt εSi

The equation states that the derivative of the charge unbalance between the excess free carrier
concentration is proportional to the unbalance itself. It is a first-order linear differential equation
with the following solution

d(n − Nd ) σn εSi
=− dt then we write td = (4.50)
(n − Nd ) εSi σn
d(n − Nd ) dt
=− and by solving we obtain (4.51)
(n − Nd ) td
− tt
n − Nd = [n(0) − Nd ] e d (4.52)

The characteristic time scale of the process is denoted Dielectric relaxation time td and has
the following expression
εSi εSi
td = = . (4.53)
σn qµn Nd
It expresses the majority carrier’s response time to a perturbation. Usually, it’s much smaller
than the minority carrier lifetime which is set by generation-recombination processes. As a
consequence, Schottky junction typically switches on/off much quicker than a PN junction
(τP N ≈ 10−3 ∼ 10−9 s while τSch. = 10−9 ∼ 10−12 s). This means that the current response to
an abrupt chage of the diode voltage from forward to reverse mode leads to an almost immedi-
ate zeroing of the current in a Schottky barrier, whereas in the PN junction we often observe
an anomalously high reverse current. This current is due to the recombination current of the
minority carriers and lasts for a so called storage time of the same order of magnitude as the
carrier lifetime.

121
 Figure 4.20: Switching of Schottky and PN diode for a voltage step.

The inverse of the dielectric relaxation time is called Dielectric relaxation frequency

1 σn
fd = = (4.54)
td εSi

and it provides an order-of-magnitude estimate of the maximum working frequency of the Schot-
tky junction.

122
4.10 MESFETs and HEMTs
Let us now analyze some of the advanced solutions to improve the performance of the transistors.
In particular, this section examines MESFETs (Metal semiconductor field effect transistors) and
HEMTs (High electron mobility transistors). These devices provide cost competitive advantages
in terms of drive current and maximum operating frequency only if fabricated with semiconductor
materials alternative to silicon, most often belonging to the family of binary or ternary III-V
compounds. The most relevant fields of application are in the RF and millimeter wave electronics
domains.

MESFET
MESFETs, Metal Semiconductor Field Effect Transistors, are an evolution of the old silicon
JFET concept where the junction that controlles the current through the transistor is a Schottky
junction instead of a conventional PN junction.
Most often, but not exclusively, the MESFET is a normally on, depletion mode device, meaning
that the threshold voltage of the n-FET is negative. Therefore, the transistor conducts current
at VGS =0 V and can be switched off only upon application of a negative bias to the gate. This is
clearly a complication, since MESFET circuits require two separate power supplies. Furthermore,
because hole mobility in III-V materials is much poorer than electron mobility, p-type transistors
are not worth the complications of the fabrication process. Consequently, CMOS circuits are not
available in MESFETs, nor the advantages that the CMOS architecture brings about for digital
electronics in terms of logic swing, noise margins, power dissipation, etc. MESFETs are therefore
most often used in analog circuits, although ratioed-logic is possible and sometimes used as well.
The MESFET (Figure 4.21) is made of a thin conductive layer of thickness a, obtained via N-type
doping of the semiconductor. The conductivity of the material is set by engineering the doping
Nd , usually chosen in the 1017 ÷ 1018 cm−3 range.
th in which we modulate the conductivity to control the current, which we call n channel,
with
The film lies on a semi-insulating substrate, typically a III-V semiconductor featuring
a very low intrinsic carrier concentration (for instance: GaAs, with ni = 106 cm−3 ) at room
temperature. In between the channel and the substrate, we can also find a buffer layer, which
is typically not doped at all, as shown in Figure 4.21.
Above the n channel we find a highly doped N + cap layer, epitaxially grown to fabricate the
heavily doped source and drain (ND ≈ 1019 -1020 cm−3 ) and the ohmic contacts. The metal gate
is directly connected to the n channel through a Schottky junction.

123
 Figure 4.21: MESFET structure.

The Schottky junction creates a depletion layer (shown in green in Figure 4.21) extending some
distance inside the channel layer. The width of the depletion region is modulated with a reverse
gate-source bias voltage (VGS < 0) which pinches part of the thickness of the layer, thereby
preventing current flow therein. A high enough gate voltage widens the depletion layer into the
channel until the thin conductive layer is fully depleted of the free carriers; thus, unable to conduct
current. (this situation is drawn in red in the Figure 4.21). In other words, the widening of the
depletion layer constricts the current flow in a narrower cross-sectional area, thereby increasing
the channel resistance. This observation suggests to model the channel region as a resistor where
current transport is mostly ohmic (i.e., by drift), and where the current modulation occurs mostly
as a consequence of geometrical changes in the current flow. Neglecting the voltage drop in the
source and drain access regions, the Channel Resistance Rch = Vds
ID can be written as:

1 L
Rch = (4.55)
σ (a − Wdep )W

where σ=1/(qµn ND ) is the channel conductivity, L and W are the channel length and the width,
respectively, Wdep is the width of the depletion layer and it is a function of VGS , and finally a
is the thickness of the n channel layer. It makes sense that the current ID is proportional to W
L
since the resistance proportional to the geometrical length of the current paths (L) and inversly
proportional to the cross section; hence to the device width (W ).
If we want to increase the performance of our device while reducing its dimensions, then we need
to have a small L and a small a which are the physical dimensions of the device. At last, we
need also a small Wdep which is trickier to obtain, because reducing the depletion depth demands
increasing the doping Nd ; however, the higher doping would degrade the mobility (see Fig. ??)
and ultimately the conductivity σ.
If we now consider the band diagram of a MESFET shown in Figure 4.22 we can notice that the
depletion layer can be modulated until covering the whole n channel, as previously said. The

124
depletion layer of the Schottky junction is represented in green and the circles drawn are the
number of the carriers that travel in the channel, and we can notice that at the equilibrium there
are many carriers in the channel.
If we instead increase the reverse bias to a higher voltage then the bands will rise up and thus
they will be more distant from the Fermi level EF n , so the channel is going to have fewer carriers
until their number finally reaches zero with the condition Wdep = a, so when Rch → ∞ from the
previous definition of channel resistance.

Figure 4.22: Band diagram of a MESFET.

Figure 4.23 shows a qualitative sketch of the ID -VGS characteristic of the MESFET over a VGS
ranging from negative values below Vt < 0 V to slightly positive ones. Represented in green we
have the voltage at which the reverse bias isn’t high enough (in absolute value) deplete the whole
channel; hence, the current starts increasing as carriers travel through an increasingly large and
undepleted portion of the channel. As VGS becomes positive, instead, the depletion width keeps
shrinking and the channel resistance keeps decreasing. However, the Schottky barrier enters the
forward bias mode and a positive current enters the gate and exits from the source and possibly
the drain (at low VDS ). This last current component subtracts to the drain current due to channel
conduction. If sufficiently large, it causes the ID to reach a maximum and then start decreasing.
Clearly, this is an unwanted condition, corresponding to a negative static transconductance gm .

125
Figure 4.23: ID -VGS curve of a MESFET.

126
HEMTs
High Electron Mobility Transistors, (HEMTs), are obtained from heterostructures of III-V semi-
conductor materials having similar lattice constant a0 but different bandgap (Eg ). In general,
both the conduction and the valence band edge at the heterointerface exhibit abrupt discontinu-
ities (so-called band offsets ∆EC and ∆EV ). Especially interesting for nFETs is the possibility
to exploit the ∆EC to confine the free electrons in a thin layer rich of free charges even in the
absence of doping. An example of these structures, corresponding to a HEMT, is shown in Fig.
4.24. As for the MESFET, the HEMT is built on a semi-insulating GaAs substrate with
a buffer layer on top. Then, a layer of undoped GaAs is put in contact with a layer of
Aluminum Gallium Arsenide having larger bandgap. A thin layer with doping is placed slightly
above the AlGaAs/GaAs heterointerface during the AlGaAs epitaxial growth. The doped layer
inflects the bands, that eventually reach the Schottky barrier at the gate metal/semiconductor
channel interface. The conduction band offset forms a narrow and deep potential well where
free electrons are confined in the vertical direction and can only flow in the plane parallel to the
wafer surface. This free charge layer is often named two-dimensional electron gas, to underline
that the electrons are free to move in the plane but also forced to stay inside the well. Since
the well is located in the undoped GaAs, the mobility of the 2D electron gas is extremely high
and unspoiled by the doping. At last we have, as in the MESFET, a n+ cap layer used for the
source and drain ohmic contacts to the AlGaAs. The gate metal forming the Schottky barrier is
instead placed in a narrow trench directly on top of the channel.

Figure 4.24: Structure of an HEMT.

Key to the performance of this transistor is the fact that the GaAs and AlGaAs form a high qual-
ity interface with few defects and interface states, thanks to the combination of materials with
the same lattice constant, a0 .Due to this, we will have almost no defects in the crystalline struc-
ture when combining them (such as traps and undesired generation/recombination processes).
The ternary compound created by replacing part of the Gallium with Aluminum atoms has a
band gap with a value somewhere in between those of the AlAs and GaAs band gaps. We can

127
modulate then engineer the value of the band gap and of the band offsetsby tuning the molar
fraction of the Aluminum during the epitaxial growth either gradually or abruptly.
For example, if we consider GaAs then its lattice constant is a0 = 5.6 and its bandgap is
Eg,GaAs = 1.4 eV , then we consider also AlAs which has the same lattice constant as shown
in the Figure 4.25 so also a0 = 5.6 but with a bandgap Eg,AlAs = 2.2 eV . If we want now to
grow some alloy using these two materials, then we will have a high quality interface with few
defects or traps, and the value of the band gap will be an average of those of the two materials,
so Eg,alloy ≈ 1.4+2.2
2 ≈ 1.8 eV , so the value of the bandgap will be around 1.8 eV .

Figure 4.25: Materials sorted by lattice constant and bandgap energy.

Let us now consider the band diagram at the equilibrium of a HEMT and discuss the transport
mechanism of the carriers in the channel.

128
 At first, we can see a Schottky junction (in
green) and the AlGaAs bands, as usual, but then
we see the change in the material to GaAs with
the bands offset discussed earlier. The band off-
set at the GaAs-AlGaAs interface is engineered
to generate a narrow potential well where elec-
trons can accumulate under appropriate gate
bias, thus forming a two-dimensional (2D) elec-
tron gas (similar to the inversion layer in the
MOSFETs).
The generation of the well is due to the step of
the energy gap, and it’s called 2D because this
well is very thin and the electrons can’t move in
the vertical direction which means that they are
quantized and can only move in two dimensions.
Because of this layer/well of electrons, we do not
need to dope the n channel and the only doped
parts are the n+ caps for the contacts. This
highly conductive layer has also a high mobility
because carrier flow occurs far from the ionized
impurity scattering centers.
The transistor then can be turned off only in one way due to the presence of the well of electrons,
and it’s by decreasing the gate potential until the potential well energy rises above the Fermi
level in the semiconductor.

129
5 Junction-based Optoelectronic Devices
5.1 Photo-generation and photon absorption
Consider a PN junction shone by a flux of photons [#photons/m2 sJ] with energy between
hν = c
λ and [hν + d(hν)] impinging on a semiconductor, it penetrates inside the material and
generates electron-hole pairs along the path. The flux is progressively absorbed. The variation
of the photon flux on a distance ∆x is proportional to the flux and the distance ∆x. Let h be
the Planck constant; then we have:

dΦ(x, hν) = −α(x, hν)Φ(x, hν)dx (5.1)

Where:

• dΦ: Flux variation, it’s decreasing so it has a minus sign. Positive dx equals negative dΦ;

• (x, hν): Function of distance and photon energy;

• α: Absorption coefficient;

Absorption is proportional to the amount of photons that hit the surface. If we denote Φ(0, hν)
the incident flux, and assume α independent of x, we get:

Φ(x, hν) = Φ(0, hν)e−α(hν)x (5.2)

This differential equation will lead to an exponential decay.

About light absorption, the sunlight spans a range of wavelengths or photon energy mostly from
infrared to violet. The photon energy and the wavelength, λ, are related by

hc 1.24
Photon energy(eV ) = = (µm) (5.3)
λ λ

As shown in Figure 5.1, the absorption coefficient is zero until the energy reaches the band-
gap energy. Photons with energy larger than Eg are absorbed but some photons may travel a
considerable distance in the semiconductor before being absorbed. The light intensity decreases
exponentially with the travel distance x

Light intensity(x) ∝ e−αx (5.4)

and α is called the absorption coefficient. It’s a strong function of energy and it represents the
probability of a photon being absorbed in the length of α1 , which is called the light penetration
depth. A solar cell must have a thickness significantly larger than the light penetration depth
in order to capture nearly all the photons.

130
 Figure 5.1: Light absorption coefficient as a function of photon energy.

5.2 Carriers Photo-generation

The generation rate [#pairs/m2 s] can be expressed as
Z
Gph (x) = (1 − R(hν))α(hν)Φ(0, hν) exp (−α(hν)x)d(hν) (5.5)
ν

Where:

• R(hν): Represents the optical impedance mismatch (reflection at the top surface);

• (1 − R(hν)): Reflection coefficient;

• α(hν): Absorption probability;

• Φ(0, hν) exp (−α(hν)x): Photon flux;

• d(hν): Energy difference;

The function is integrated for all the frequencies of the spectrum.

If the quantity of absorbed photons is high and the semiconductor is lowly doped, then high
injection conditions may be set on, resulting in a dependence of the absorption coefficient on the
free carrier concentrations. In many instances, the surface of the cell is partly obscured by the
contact metallizations. Thus Gph,ef f = (1 − s)Gph where s is the shadowing factor.

131
 Figure 5.2: Example of generation rate for a large light span.

The violet and blue are absorbed first so they won’t penetrate far so our device has to be built
on the surface of the semiconductor to function. The red color or after that (infrared) are
less absorbed and they penetrate further. It means that our device can be built deep in the
semiconductor as the waves penetrate far enough. (refer to Figure 5.2).

5.3 Avalanche Photo Diodes

These are p-i-n diodes fabricated in such a way as to achieve a very uniform breakdown voltage
VBR across the whole junction area, and with the purpose of separating the electron-hole (e-h)
pairs generated.
These diodes must have a very small inverse saturation current, in fact, the only current present
should be due to photons electron-hole pair generation, so it should be a very high-quality
junction, otherwise, it would measure that current and not the one due to photons which will
lead to incorrect readings.
The absorption of a photon in the diode depletion region leads to the creation of an e-h pair and
this diode separates the generated pair.
There are two possible operating modes for these diodes:

• Linear mode: the diode is reverse biased at |V | < VBR (close to breakdown but still less
than VBR) . The photons generate e-h pairs in proportion to the photon energy. Impact
ionization multiplies the carrier pairs but the current pulse is of finite intensity, so the
current is proportional to the photon flux (more photons = more current).
Due to the diode working condition near breakdown, the high field in the depletion region
separates the e-h pairs. It is commonly used for spectroscopy (determination of the photon’s
energy) and optical fiber transceivers;

132
 • Geiger mode: it switches the diode very
quickly, the diode is reverse biased at |V | > VBR
so it is operating in the breakdown zone. As
soon as a photon arrives it triggers avalanche
breakdown, which will increase the current in
the diode.
A threshold detector senses the current increase
until it reaches Ith , which is the threshold cur-
rent, and then a quenching circuit immediately
reduces the voltage across the junction, thus
damping the avalanche breakdown process. This
process takes some time, called dead-time, in
which we need to compare the current and then
cut off the voltage supply. This is done cyclically
every time we reach the threshold current.
As a result, an intense current pulse is obtained
for each photon absorbed in the junction. The
signal generated by the photon is amplified by
the regenerative mechanism of avalanche multi-
plication. The signal-to-noise ratio is very high.
It is used for single photon counting. e-h pairs
can be generated by other phenomena that inter-
fere with the measure, so it is important to have
a very small inverse current (so a high-quality
junction).

5.4 Solar Cells

Commonly made of silicon, Solar Cells are also known as photovoltaic cells. They convert sun-
light to electricity with a 10-30 % conversion efficiency, that because solar energy is dispersive.
Each square meter of solar cells can produce about 25 W of continuous power (day, night and
sunny/cloudy days averaged conditions). For instance, if all the electricity is to be provided by
solar cells, the cells need to cover a huge 200 Km2 area. Therefore, low cost and high conversion
efficiency are important.
Solar cells can be made of amorphous or poly-crystalline as well as single-crystalline semicon-
ductors. A solar cell’s structure is identical to a PN junction diode but with finger-shaped or
transparent electrodes so that light can strike the semiconductor.
Figure 5.3 shows that when light shines on the PN junction, the minority carriers that are gener-
ated by light within a diffusion length (more or less) from the junction can diffuse to the junction,
and cause a current to flow out of the P terminal through the external short circuit and back
into the N-terminal. This current is called the short-circuit current, Isc , which is proportional to
the light intensity and to the cell area. For positive voltage applied, we will generate a negative
current.

133
 Figure 5.3: Light can produce a current in PN junction at V = 0.

The short circuit is needed so the current can actually circulate when generated. There is an
applied potential so the bands are bent, also due to electrons going to the right, the current will
go from the N side to the P side. Therefore, the current will be negative from the user definition.
The total diode (solar cell) current is the sum of the current generated by the voltage and that
generated by light.
I = I0 (eqV /kT − 1) − Isc (5.6)

The negative sign indicates that the direction of Isc is opposite to that of the voltage-generated
current. Isc is defined as
Isc ≈ qAGph (Ln + Wdep + Lp ) (5.7)

where:

• A: Junction area;

• Ln , Lp : Carrier diffusion lengths;

• Gph : Generation rate due to photons;

Given the generation rate, qGph is the generated charge. To calculate the current we need to
integrate it over the volume, but it is just our cross-section A times the distance in which this
charge happens to be, which is the depletion region, but also the recombination distance in PN
regions (diffusion lengths), so the total volume is V = Ad = A(Ln + Wdep + Lp ).
√
The current Isc has a weak dependence on voltage as the only term is Wdep ∝ ϕbi − V . This is
why we can consider it as a rigid shift without changing the shape of the curve.
The Figure 5.4 represents the solar cell I-V curve. The solar cell operates in the fourth quadrant
of the I-V plot and since I and V have opposite signs, the solar cell generates power. Each silicon
solar cell produces about 0.6 V . Many cells are connected in series to obtain the desired voltage.
Many such series strings are connected in parallel into a solar cell panel.

134
 Figure 5.4: Solar cell I-V curve.

Without light the junction will behave just a regular diode so its I-V curve won’t be any different.
When there is light we generate a negative −Isc so the I-V curve is shifted rigidly downward but
still retains its shape. Note that with light this means that:

1. We can get negative current with 0 voltage;

2. We can get positive voltage with 0 current;

A solar cell is meant to be a generator so the graph is actually reversed as we consider the current
positive instead of negative, as we do in components.
Solar cells are influenced by a lot of factors, so it is important to set the I-V work point to
optimize the power generated. For every cell, we may have a different power point because of
shadowing, changes in light, and photo-flux, so we need also electronics that control biases every
time.

Figure 5.5: Maximum Power.

The generated power is P = IV so they will be hyperbolas for constant power. As soon as it’s
tangent to our curve we find our maximum power point (see Figure 5.5).

135
5.4.1 Short-Circuit Current and Open-Circuit Voltage

This subsection refers to the calculations for −Isc and VOC assuming only Lp is present, so there
is no Ln and Wdep in the formulas.
If light shines on the N-type semiconductor and generates holes (and electrons) at the rate of
G s−1 cm−3 then we can write
d2 p′ p′ G
= − (5.8)
dx2 L2p Dp
If the sample doping is uniform (no PN junction but only one type)

d2 p′ ′
GL2p
= 0 → p = = Gτp (5.9)
dx2 Dp

Assume a very thin P+ layer (refer to Figure 5.6) and carrier generation in N region only (it
means no Wdep and no Ln in the formulas).

Figure 5.6: (a) A P+ N solar cell under the short-circuit condition and (b) the excess carrier
concentration profile. Effectively only the carriers generated within x < Lp can diffuse to the
junction and contribute to the short-circuit current.

Under the short-circuit condition (V = 0), the boundary condition at x = 0 is

p′ (0) = 0 (5.10)

At x = ∞, p′ should reach a constant value and therefore the left-hand side of Eq. 5.8 should
be zero.
G
p′ (∞) = L2p = Gτp (5.11)
Dp
The solution of the differential equation 5.8 is

p′ (x) = τp G(1 − e−x/Lp ) (5.12)

136
The equation 5.12 can be easily verified by substitution and it satisfies Eqs. 5.8, 5.10 and 5.11.

dp′ (x) Dp
Jp = −qDp = 1 τp Ge−x/Lp (5.13)
dx Lp

Isc = AJp (0) = AqLp G (5.14)

Only the holes generated within a distance Lp from the junction are collected by the PN junction
and contribute to the short-circuit current. The carriers generated further from the junction are
lost to recombination. The conclusion is that a large minority carrier diffusion length is good
for the solar cell current. This is always true, although the relationship between Isc and the
diffusion length is more complex in a realistic solar cell structure than the simple proportionality
as in equation 5.14. G is really not uniform and Lp needs to be larger than the light penetration
depth to collect most of the generated carriers.
The total current is Isc plus the PV diode (dark) current:

n2i Dp qV /kT
I = Aq (e − 1) − AqLp G (5.15)
Nd Lp

where the first term expresses the current of the diode when it’s not hit by the light (so normal
diode behavior) and the second the Isc . By setting I = 0, we can solve for the open-circuit
voltage Voc (assuming eqVoc /kT >> 1 for simplicity).

n2i Dp qVoc /kT

0= e − Lp G (5.16)
Nd Lp
 
kT τp GNd
Voc = ln (5.17)
q n2i
The terms τp and G can change to raise Voc , but we don’t have much margin for increasing Voc
as it is a logarithmic dependence, so even a big change in τp or G will have a small effect on Voc .

137
5.4.2 Output Power

There is a particular operating point on the solar cell I-V curve that maximizes the output power,
|I × V |. The Maximum Output Power is defined as

Pmax = Isc × Voc × F F (5.18)

where F F is the Field factor, which is a number always < 1 and its value is typically around
0.75 in real applications.

Figure 5.7: Maximum Power Output.

The field factor (FF) compensates the difference between the Isc · Voc (theoretical maximum
power) area and the actual one of the diode as it has an exponential behavior and the area is
not the same, so the difference in power is just scaled with F F due to these different areas.
Solar cells should have very low parasitic resistance as it will decrease their maximum power
output as shown in Figure 5.7. Considering the parasitic resistances the I-V hyperbola tends to
become linear and will reduce the maximum output.
It is important to optimize the materials used for collecting the current, usually the one used is
aluminum. Especially it’s possible to use an ITO material, which is a special class of materials
used for highly efficient solar cells.
The Si solar cells have usually 15-20 % efficiency. The best solar cell efficiency (∼24 %) is
obtained with Eg values between 1.2 and 1.9 eV . Larger Eg leads to too low Isc so a low light
absorption, and also a smaller Eg leads to too low Voc .
Tandem solar cells get 35% efficiency using large and small Eg materials tailored to the short
and long wavelengths of solar light.

138
5.4.3 Spectral response and efficiency

The spectral response is limited by several factors as the wavelength of the absorbed light changes:

• At high wavelength value, so a low photon energy Eph = hν by the energy gap Eg ;

• At short wavelength values by absorption and reduction in the number of photons (for a
given optical power);

Figure 5.8: Spectral response of a Si PN junc- Figure 5.9: Efficiency of a solar cell as a func-
tion photo-diode. tion of Eg .

The Shockley-Queisser limit is the maximum theoretical efficiency of a single PN junction

when the only loss mechanism is radiative recombination in the solar cell. It is approximately
30 % at 1.1 eV for a 6000 K black-body spectrum. 33.7 % for a solar cell with a bandgap of
1.34 eV operating with sun spectrum. The value expressed is the theoretical maximum value
but with shadowing and reflections at the interface, it reduces the efficiency to smaller values
(around ∼20 %).

5.4.4 Multi-Junction solar cells

In order to increase the efficiency of solar

cells, it is possible to use Multi-Junction
solar cells. They are optimized to capture
and convert most of the available light spec-
trum. Each layer is optimized to absorb
a certain wavelength and let penetrate fur-
ther other wavelengths. The shorter wave-
lengths are captured first by the blue layer,
which is optimized for large energy (so short
wavelengths). Then the longer wavelengths
are captured as last by the red layer, which
is optimized for small energy (so large wave-
lengths). In this way, we can absorb a big
part of the whole spectrum. Therefore, we
unify the junction by sorting it by wave-
Figure 5.10: Layers of a multi-junction solar cell
length and so we obtain a multi-junction (the Ge Substrate has a bandgap of 0.7 eV .)
solar cell.

139
 Figure 5.11: Spectrum of the sun, represents a black body radiation.

The key of this technology is to use firstly the junction with a large bandgap so it absorbs only
high energy photons and let pass the others, then with every junction we decrease the energy
gap so smaller energy photons are absorbed and so on until we absorb every photon we want to
use.

• Advantages: Their efficiency can go up to ∼40% as shown in Figure 5.12;

• Disadvantages: They are very expensive and need to be made of really good quality
materials (good junctions to avoid generation-recombination processes).

Figure 5.12: Best Research-Cell Efficiencies

140
5.5 Light Emitting Diodes
LEDs or light-emitting diodes of various colors are used for such applications as traffic lights,
indicator lights, and video billboards. Light is emitted from an exposed PN junction when
electrons and holes undergo radiative recombination. The electrons and holes recombine by
emitting photons (light) with hv ≈ Eg .

Figure 5.13: Radiative recombination.

The photon generation process, called radiative recombination, is straightforward and fast in
direct-gap semiconductors with a few nanoseconds lifetime. Therefore, radiative recombination
is the dominant recombination process in direct-gap semiconductors, i.e., a high percentage of
the injected carriers generate photons. This percentage is known as the quantum efficiency.
The quantum efficiency of photon generation is much lower in indirect-gap semiconductors
because the radiative recombination is slow with a few milliseconds lifetime. As a result,
the recombination-through-traps process, so non-radiative, (see Figure 5.13), which generates
phonons rather than photons, is the faster and dominant process of recombination in the case of
the indirect-gap semiconductor.

5.5.1 LED Materials and Structure

By adjusting the composition of the semiconductor, Eg can be altered to control the wavelength
of the emitted light in order to make blue, green, yellow, red, infrared, and UV LEDs possible.
LEDs are made of compound semiconductors such as InP and GaN . Direct-gap semiconductors,
such as GaN , are much better for LED applications than indirect-gap semiconductors, such as
pure silicon Si.

Figure 5.14: Schematic drawing of an LED. Photons are generated when the electrons and holes
injected by the PN junction recombine.

141
Figure 5.14 shows a basic LED. A PN junction is made of an appropriate semiconductor that is
forward-biased to inject minority carriers (in the opposite region). When the injected minority
carriers recombine with the majority carriers, photons are emitted and the light is emitted in all
directions. To reduce the reflection of light at the semiconductor and air interface (back into the
semiconductor) and therefore project more light into the forward direction, the semiconductor
surface may be textured or a dome-shaped lens may be provided.
The LED wavelength is defined as follows:

1.24 1.24
LED wavelength(µm) = ≈ = λLED (5.19)
photon energy Eg (eV )

It is possible to use different compound semiconductors in order to change the LED structure:

• Binary semiconductors: used as an efficient emitter (e.g. GaAs);

• Ternary semiconductors: used to tune Eg to vary the colors (e.g. GaAs1−x Px );

• Quaternary semiconductors: used to tune Eg and lattice constant for growing high
quality epitaxial films on inexpensive substrates (e.g. AlInGaP ).

Figure 5.15: LED Structure and Eg variation.

As shown in Figure 5.15 we have an N-type GaAs substrate (contacted at the bottom) which
is followed then by an N-type GaAs1−x Px alloy, with 0 < x < 0.4 in this layer, and as the
quantity of As decreases, P should increase because they are proportional in this alloy. This is
done gradually to have a smooth interface without many defects (traps) and to widen the Eg so
photons can’t be re-absorbed by the substrate, because they are not provided by enough energy
to generate e-h pairs.
Then we are going to change the ratio between As and P in the next step, in fact in this case
we’ll grow uniformly an alloy GaAs1−x Px with 0.4 < x < 0.6, which is a good ratio for having
a bandgap Eg for red light emission. At last, we have a p+ layer and as insulator, we use the
silicon nitrate Si3 N4 .
By doing this change in materials and ratios we’re modulating the energy gap to generate pho-
tons of a chosen wavelength and avoid the re-absorption of the photons by the substrate (shown
in blue in Figure 5.15) while emitting them (shown in red in the same Figure).

142
Both Eg and the lattice constant can be independently tuned by mixing GaP , InP , and AlP
in varying proportions. In other words, quaternary semiconductors, which contain four chem-
ical elements such as AlInGaP , can provide a range of Eg (wavelengths) while meeting the
requirement of matching the lattice constant of the substrate material.

Figure 5.16: Red LED with sloped sides for better light extraction.

Figure 5.16 shows a red LED with its substrate shaped into a truncated pyramid to collect light
with a reflector on the back and total internal reflection from the sides. The GaP substrate is a
thin layer of a semiconductor and is transparent to red light.
In order to increase efficiency, the aluminum is used to reflect photons (like a mirror) to send
them in the other direction so they are not re-absorbed by the substrate. But this widens the
bandgap toward the substrate so there will be less e-h pair generation also in this case.

Figure 5.17: Energy band diagram showing the quantum well.

Figure 5.17 illustrates the concept of energy well or quantum well. Because the AlInGaP film
has a smaller band gap than GaP , it forms a well, called a quantum well, between the GaP
on both sides. The concentrations of both electrons and holes are high in the well, a condition
favorable for recombination and light emission, and if this layer is thin enough then the carriers

143
inside the well will also be quantized. So most of the light is due to these quantum wells because
of quantization and lower Eg .
Often multiple quantum wells (periodic quantum wells) are used with several repeated alternat-
ing layers of different semiconductors with different energy gaps. In this case, it’s called a super
lattice.

The following Figures refer to LED material choice.

Figure 5.18: Room temperature bandgap energy versus lattice constant of common elemental
and binary compound semiconductor.

Figure 5.19: LED materials and applications.

144
5.5.2 LED forward (turn-on) voltage

The forward voltage of a LED, VF , is the voltage that must be applied across the leads of the
LED, from anode to cathode, in order to turn on the LED and as we can see in Figure 5.20 with
and increasing Eg we need also a higher VF to turn on the diode.

Figure 5.20: Room-temperature current-voltage characteristics of PN junction made from differ-

ent semiconductors.

Figure 5.21: Bias voltages and materials needed for different LEDs colors.

As we can see in Figure 5.21 to have different colors LEDs we need to use different materials,
which implies having different energy gaps Eg and so different bias voltages.

145
5.5.3 Light transmission efficiency

The transmission of light from a high to a low refractive index material (e.g., from a semiconduc-
tor with n = n1 ≈ 3 − 4) to a semiconductor with n = n2 entails partial or total reflection of the
incident light depending on the incident angle. For the normal incidence case (so nr = n1 /n2 )
we have that the transmission efficiency has the following expression:

4nr
Tn = (5.20)
(1 + nr )2

The total reflection of light occurs for a critical angle that can be calculated as

n2
sin θc = (5.21)
n1

Assuming a uniform angular distribution and random polarization of the emitted light, overall
we have that the transmission efficiency assumes a different form by considering reflections:

(sin θc )2 2
T ≈ Tn = (5.22)
2 nr (1 + nr )2

To avoid too many reflections one method is to

cover the LED by an epoxy dome, which in-
creases the amount of light extracted from the
LED and it’s shown in Figure 5.22. The refrac-
tion index of the epoxy should be in between of
those of the air and the semiconductor to have
better optical impedance matching and so have
a more gradual change in the refraction index.
The dome should be curved to have larger angles
in which light is emitted but there will be still Figure 5.22: Refractive index of an epoxy
some total reflection. dome.
In order to maximize light emission it is also possible to texture the surface, in fact texturing
the epoxy’s surface roughly implies that even in total reflection conditions the texture will act
as a "waveguide" and set free the light by many internal reflections.

Figure 5.23: Schematic illustration of a wave-guide with different textures.

Figure 5.23 represents the schematic illustration of a wave-guide with different textures: (a) no
surface texture, (b) weak surface texture, and (c) strong surface texture, resulting in secular
reflection, mixed reflection and scattering, and strong scattering respectively.

146
5.5.4 White light generation for lightning

In order to create a white source, it is possible to use a combination of colors which are perceived
as white light. The different LED-base approaches for white sources are shown in Figure 5.24.

Figure 5.24: Different LED-base approaches for white sources.

Commonly, there are two methods in order to create a white source: by using Phosphors and
Multi-Junctions. The first one uses phosphorus to emit different wavelengths.

Figure 5.25: Phosphor-based LED for white color generation.

The Multi-Junction one, considers singular color junctions and by mixing those two (or more)
spectra gives, when combined, white light.

Figure 5.26: Spectra mixing for white color generation.

147
6 MOS capacitance
An MOS capacitor is made of a semiconductor body or substrate, an insulator film, such as
SiO2 , and a metal electrode that is called gate. The oxide film can be as thin as 1.5-2 nm. One
nanometer is equal to 10 Å, or the size of a few oxide molecules. An MOS transistor is an MOS
capacitor with two PN junctions that are placed on the sides of the capacitor.

Figure 6.1: MOS capacitor and transistor structure.

6.1 Band structure

To study the band diagram of a MOS capacitor, we proceed by creating a non-interactive model:
Regarding Figure 6.2, E0 is taken as the energy reference and it expresses the vacuum energy
level, which is the energy state of electrons outside the material.

Figure 6.2: Flat band diagram.

148
The capacitor substrate is a crystalline silicon, in this case, a P-type doped silicon, so the Fermi
level is positioned near the valence band. The difference between the conduction band Ec and
the vacuum level E0 is denoted by the potential qχ, where χ is the affinity of the material. To
obtain the position of the Fermi level in the substrate EF , with respect to the vacuum level, we
need also to consider the difference in energy between the conduction band and the Fermi level,
so Ec − EF and so the final expression for the substrate work function ψs is the following:

ψs = qχSi + (Ec − EF ) (6.1)

The insulator is SiO2 , and its conduction band is related to the vacuum level as previously by
affinity χSiO2 , which is much smaller and with a very high band gap.
The gate is made by a grower layer, which is usually made of polysilicon or metal, and in this
case, the gate is N + -type highly doped. Due to high doping the Fermi level on the gate side has
collapsed to the conduction band edge, which signifies that Ec = EF in our case. Also, due to
the higher doping on the gate side, there should be also some band gap narrowing (BGN), but
as can be seen in Figure 6.2 the bands on both sides are exactly the same, which means that we
are neglecting BGN in our analysis.
After these considerations, we can evaluate the distance between the vacuum level and the
conduction band of the gate as the gate work function ψg . We can now define a quantity of
energy that expresses the difference between the two Fermi levels, obtained previously, as qVf b ,
where Vf b is the voltage needed to be applied at the gate of the capacitor to have a flat band (so
zero field) and is therefore called flat band voltage, which has the following expression:

Vf b = ψg − ψs (6.2)

In this case, concerning Figure 6.3, with an N-

type gate and a P-type substrate, the Vf b is neg-
ative because we need to increase the energy of
the substrate bands (because U = −qV ). Now,
we consider the interaction between the two ma-
terials: firstly, we must align the Fermi levels and
shift the energy levels taking care of the conti-
nuity of the vacuum level. The energy on the
gate side decreases by a quantity equal to the
difference between the two Fermi levels, that is
the qVf b introduced.
Then the vacuum level must be continuous, far
from the junction we have the unperturbed sili-
con so the vacuum level will be qχSi above the
conduction band in the substrate side and simi-
larly near the junction with the insulator. That
means, as shown in Figure 6.3, that we will have
Figure 6.3: Band diagram of a MOS capacitor.
nonlinear conduction/valence bands.

149
So we expect that Ec − Ef grows with increasing distance by insulator while Ef − Ev decreases,
so at the interface we will have fewer holes and more electrons, according to the equation:
Ec −EF
n = Nc e− kT (6.3)

so we expect to have a high electron concentration near the junction because the electrons tend
to occupy first the lower energy layer, the so-called potential well.

6.2 Surface accumulation

Suppose to apply a more negative gate voltage Vg < Vf b < 0 with respect to the bulk. This
excess potential is distributed between the insulator and the substrate.
As shown in Figure 6.4, the band diagram
on the gate side is pushed upward with
respect to the substrate side. So we have
some electric field in the insulator and in
the semiconductor (supposing the gate is a
perfect semiconductor). We can then denote
as Vox the voltage applied to the oxide, and
this is the portion of the potential, or voltage
drop, given to the oxide. In the same way,
we can denote the voltage drop portion in
the semiconductor as ϕs and we can call it
surface voltage or surface potential.
At this point, we consider the quantity qϕs ,
which represents the bending of the substrate
bands, and because the substrate is the
voltage reference, ϕs is negative if Ec bends
Figure 6.4: Band diagram at accumulation upward toward the surface, and it’s positive
condition.
instead if Ec bends downward.

Regarding the oxide we have that Vox is negative if the SiO2 energy band increases as we go
toward the gate, and it’s positive if it decreases when we approach the gate. From Figure 6.4 we
can then express the following equality:

Vg − Vf b = Vox + ϕs (6.4)

Now the electrons in the substrate will see a potential barrier (not anymore a potential well), and
so they are pushed away from the junction, but the holes see instead a potential well so there
will be an extra hole concentration, close to the junction, in addition to those already present
due to the doping, and this forms a hole well. Because Ev is closer to Ef on the surface than it
is in the bulk, the surface hole concentration, ps , is higher than the bulk hole concentration and
so there is a larger number of holes at or near the surface due to the well.
Due to this hole accumulation at the interface, they form an accumulation region where there

150
is a positive charge, and so they are called the accumulation-layer holes, and their charge is
called the accumulation charge Qacc . To balance this positive charge, the corresponding negative
charge piles up on the other side of the oxide, in particular on the surface of the gate, and
because the gate is metallic there is no band bending phenomenon and this is the reason for a
flat conduction band.
That means, it behaves as a parallel plane capacitor, in which the capacitance is given by:

A
C=ε (6.5)
d

where d is the thickness of dielectric tox , A is the surface area and ε is the dielectric constant
of the material. Take into account that Vox is not equal to the total voltage drop, due to the
surface voltage drop ψs present. But, by decreasing Vg , and thus increasing the energy and
the hole charge Qp , it pulls up the potential ψs that becomes negligible when the surface is in
accumulation, that’s because any decrease of the surface potential leads to accumulate a large
hole density, which in turn increases the potential. So ψs will be so small that we can neglect it,
and therefore Vox ≈ Vg − Vf b .

Vox ≈ Vg − Vf b < 0 (6.6)

Qacc = −Vox Cox = −Cox (Vg − Vf b ) note that Vg − Vf b < 0 and so Qacc > 0 (6.7)

The minus sign is due to convention of Vox , as Vg − Vs . So we will get the charge in the gate but
we are interested in the substrate charge that, for a P-type, is positive. Using Gauss’s Law:

−Qacc
Eox = (6.8)
εox
Qacc Qacc
Vox = −Eox tox =− tox = − (6.9)
εox Cox

The equation is the usual capacitor relationship,

V = Q/C except for the negative sign. In
V = Q/C, the capacitor voltage and charge are
both taken from the same electrode, while in the
MOS capacitor theory, the voltage is the gate
voltage, but the charge is the substrate charge
(thus it’s of the opposite sign, Qacc = −Qg ) be-
cause interesting things happen in the substrate
and this unusual choice leads to a negative sign.
Therefore, the MOS capacitor in accumulation
behaves like a capacitor with Q = CV but with
a shift in V by Vf b , and this shift is easily un-
derstandable because Qacc = 0 when Vg = Vf b .

151
6.3 Surface Depletion
Suppose to apply a more positive gate voltage Vg > Vf b (not too much, with respect to the
bulk). Assume zero charge in the oxide, so a linear profile. As shown in Figure 6.5, the band
diagram on the gate side will be pulled downward, so the electric field will be positive. On the
substrate junction side, the holes will be pushed away from the junction and the electrons will
see a potential well, but it is a P-type so there will be a few electrons so:

n2i
np0 = (6.10)
NA
ρ = q(p
− 
n − NA ) = −qNa (6.11)

and as can be seen, we neglect n because there are only a few electrons present (even with the
well) and also we neglect p because the holes are pushed away, as said earlier.

Figure 6.5: Surface depletion of a MOS capacitor and its band diagram.

Clearly, there is now a depletion region because EF at the surface is far from both Ec and Ev ,
and electron and hole densities are both small. This condition is called surface depletion and the
depletion region has a width, Wdep :
r
2εs
Wdep = · φs (6.12)
qNa

In this case, the potential drop across the depletion region is (φs − Vb ), where Vb is the bulk
reference potential, which is null. The charge will be negative because of acceptor ions, with a
density charge of −qNa . The total charge will be then:
Z
Qdep = −qNa dWdep = −qNa Wdep [C/m2 ] (6.13)

√
Qdep qNa Wdep qNa 2εs φs
Vox =− = = (6.14)
Cox Cox Cox

152
Having a positive oxide potential is correct according with reference to the bulk. We can define
the gate voltage as a function of the surface potential:

Vg − Vf b = Vox + φs (6.15)
√
qNa 2εs φs
Vg = Vf b + φs + (6.16)
Cox
It’s possible to study the behavior of φs when we vary the Vg :

• For Vg < Vf b , called accumulation regime, φs is very small and we can approximate it as
null, so below Vf b we consider φs = 0 always;

• For Vf b < Vg < VT , so depletion regime, φs is proportional to Vg with a little bending of

the curve due to the non-linear square root term;

• Over a certain Vt , denoted as inversion regime, φs is increasing very slowly, so we can

approximate it to a constant value φs = 2φf , which needs to be calculated;

Figure 6.6: Surface potential in function of the gate voltage.

Differently from a normal capacitor, the charge is distributed in the depletion region, not only
on the surface. We can now examine the charge distribution for every regime we have discussed
so far:

Figure 6.7: Charge distribution in the accumulation and depletion region.

153
As reported in Figure 6.7 for an N-type capacitor with a P-type substrate, in the accumulation
region, holes pile up at the interface while most of the semiconductor is neutral and ρ = 0.
In the depletion regime, we can divide the charge distribution into a depletion region, with a
high negative charge density and a quasi-neutral region far from the surface. The charge comes
from few free electrons and most of the depleted region carriers.

Figure 6.8: Charge distribution at the threshold voltage and in the inversion region.

If we keep increasing the gate voltage we enter the threshold regime, where the electric field
will be much stronger and the electron density will increase until it is comparable to the dopant
density. So the charge density does not go flat but will pile up near to the surface creating an
inversion region, which means the P-type surface acts as an N-type in this region and so we
revert from a P-type to a Silicon that acts like an N-type. At the threshold voltage:

ρ = q(p − n − Na ) (6.17)
= −qn − qNa (6.18)
= −2qNa at surface (6.19)

where a −qNa term is given by doping and the other −qNa from the electron density at the
surface. Lastly, in the inversion regime, there is a huge peak of negative charge at the surface,
which also prevents any change in surface potential, in fact, if we continue increasing Vg there is
a screening effect at the surface and so ϕs won’t change that much.

6.4 Threshold Voltage

If the gate voltage Vg is increasing and becomes more positive, this bends the energy band down
even further. At some value of Vg , EF will be close enough to Ec at the Si − SiO2 interface that
the surface is no longer in depletion regime but at the threshold of inversion. The term inversion
means that the surface is inverted from P-type to N-type, thus becoming rich of electrons. The
threshold is often defined as the condition when the surface electron concentration, ns , is equal
to the bulk doping concentration, Na .
That means [A] (Ec − EF )surf ace = (EF − Ev )bulk [B], or A = B in Figure 6.9. We can also say

154
that [C] (EF − EF i )surf ace = (EF i − EF )bulk [D] and it’s like saying that C = D if seen from
Figure. At last the Ei is a curve drawn at mid gap, which is halfway between Ec and Ev . Let
the surface potential (band bending) at the threshold condition be ϕst . So at the threshold, due
to Fermi level shifting, we obtain the following condition:

ns = Na or equivalently ns = pbulk with ρ = q(p
− n − Na ) (6.20)

Figure 6.9: Band diagram at threshold voltage condition.

Remember the electron concentration expression (and equivalently also for holes):
(Ec −Ef )
n(x) = Nc e− kT (6.21)
(Ef −Ef i )
= ni e kT (6.22)
(E −Ev )
− fkT
p(x) = Nv e (6.23)
(Ef i −Ef )
= ni e kT (6.24)
Eg
ni = Nc Nv e− 2kT
p
(6.25)

and at threshold condition, we assume that NC = NV . From Figure 6.9 and the analysis done
so far, we can now evaluate the surface potential at the threshold, denoted as ϕst , by considering
firstly the shift of the Fermi level with respect to its intrinsic position, which we denote as ϕF :

qϕst = C + D = 2C (6.26)
Eg
qϕF = − (Ef − Ev )|bulk (6.27)
2    
Nv Nv
= kT ln − kT ln (6.28)
ni Na
 
Na
= kT ln (6.29)
ni

155
So at the threshold condition, the surface potential has the following expression:
 
kT Na
ϕst = 2ϕF = 2 ln (6.30)
q ni

The threshold voltage Vt is the gate-bulk voltage Vgb , with reference to the bulk that is grounded,
which can then be considered as only Vg at threshold condition as follows:

Vg = Vf b + φs + Vox (6.31)

Qs
Using the Gauss theorem, Es = εs , over a volume that includes the oxide substrate surface, and
neglecting the electron peak as it’s pretty small with respect to the depletion region as shown in
Figure 6.10 we obtain that Qs = Es εs (where s indicates the region with Si).

Figure 6.10: Electron peak compared to the depletion region.

If we assume the field in the oxide Eox constant, then we can calculate Vox as:
Z
Vox = Eox dx = Eox tox (6.32)

To calculate Eox , we consider the fact that at the junction the field is continuous, which means
we assume no residual charge in the oxide and we consider the conservation of the displacement
vector all over the surface between the two materials, so:

⃗ ox = εox E
D ⃗ ox ⃗ s = εSi E
D ⃗ Si (6.33)
they must be equal for conservation theorem
⃗ ox = D
D ⃗ Si → εox E
⃗ ox = εsi E
⃗ Si (6.34)
⃗
⃗ ox = ESi εSi
E (6.35)
εox

To apply the Gauss theorem we keep the volume on the right side of the interface (semiconductor
part):
⃗ s = QA = Qs A
Flux: AE (6.36)
εs εs

156
So by substituting the expression of Qs , and subsequently also the Wdep one, and E
⃗ ox we obtain
that:
r r
2εs 2εs
ESi εSi = Qs = qNa Wdep = qNa ϕs = qNa 2ϕF (6.37)
qNa qNa
ESi εSi tox ESi εSi Qs
Vox = Eox tox = = = (6.38)
εox Cox Cox
(6.39)

considering that in those equations ϕs = 2ϕF because of threshold condition and using this result
we can at last calculate Vox as follows:

kT Na
ϕst = 2ϕf = 2 ln (6.40)
q ni
√
qNa 2εs 2ϕF
Vox = (6.41)
Cox
Substituting the result found in the expression of Vg at the beginning, we obtain the Threshold
Voltage equation: √
qNa 2εs 2ϕF
Vt = Vg = Vf b + 2ϕf + (6.42)
Cox
In the last result, we have that the first term Vf b depends on the material, and the second, so
ϕF , is a weak function of temperature and doping.
The last one, which expresses the Vox result, shows a square root dependence on doping and
potential, but it’s also dependent on tox due to the Cox term at the denominator.
It’s a really important formula that separates the inversion from all other regimes, in fact, this
region allows MOSFETs to create the channel of electrons.

Figure 6.11: Theoretical threshold voltage vs body doping concentration.

157
6.5 Strong inversion

Figure 6.12: An MOS capacitor biased into inversion. (a) Types of charge present; (b) Energy
band diagram with an arrow indicating the sense of positive Vg .

The depletion layer grows until we enter the inversion regime, where ϕs does not increase more
than 2ϕF , which means that the depletion region has a maximum width
s
2εs 2ϕF
Wdep,max = (6.43)
qNa

From this point, and for Vg >> Vt , we are deep into the inversion zone and so the inversion charge
at the interface can’t be neglected anymore in Vox calculations, and therefore the Vg expression
becomes

Qdep Qinv
Vg = Vf b + 2ϕF − − (6.44)
C Cox
√ ox
qNa 2εs 2ϕF Qinv
= Vf b + 2ϕF + − (6.45)
Cox Cox
Qinv
= Vt − (6.46)
Cox

so, by inverting the formula, we obtain the following expression for Qinv at the interface, which
is the dominant charge in the inversion regime

Qinv
Vg = Vt − → Qinv = −Cox (Vg − Vt ) (6.47)
Cox

Note:
The threshold voltage Vt is generally set at a small positive value so that at Vg = 0 the tran-
sistor doesn’t have an inversion layer and current does not flow between the two N + regions
(enhancement mode FETs), so generally we have a P-body paired with N + -gate to achieve a
small positive Vt . In the same way, an N-body is paired with an P + -gate to achieve a small
negative Vt .

158
Figure 6.13: (a) The surface inversion behavior is best studied with a PN junction colliding the
MOS capacitor to supply the inversion charge. (b) The inversion layer may be thought of as a
thin N-type layer.

6.6 Review
About MOS capacitor theory, concepts, common approximations, and simple relationships asso-
ciated with it has been shown in this chapter, starting with Figure 6.14.
In this Figure, we can see that the surface poten-
tial ϕs is zero at Vf b and approximately zero in
the whole accumulation region. As Vg increases
from Vf b to the depletion regime, ϕs increases
from zero toward 2ϕF , which is the value at which
it pretty much stops increasing.
When ϕs = 2ϕF , surface electrons concentration
becomes so large that the surface is considered
Figure 6.14: Surface potential as inverted and the Vg at that point is called Vt , the
a function of Vg . threshold voltage.
The Figure 6.15 uses the Wdep to review the MOS capacitor. There is no depletion region when
the MOS interface is in accumulation, and as in PN junctions, Wdep in the MOS capacitor is
√
∝ ϕs (ϕs is the surface potential and it expresses the band bending in MOS case). The value
of Wdep saturates at Wdmax when Vg ≥ Vt , because ϕs saturates at 2ϕF .

Figure 6.15: Depletion region width of a MOS capacitor as a function of Vg .

159
The three next figures (Figure 6.16) show the charge components in the substrate.
Figure 6.16a shows the depletion layer charge, where Qdep is going from zero, in the accumulation
regime, to a constant value in the inversion region because Wdep is constant there. In fact, the
value of Qdep is given by:
Qdep = −qNa Wdep (6.48)
The Figure 6.16b shows the inversion-layer charge, which in mathematical approach is described
by Qinv = −Cox (Vg − Vt ).
Finally, in Figure 6.16c, Qacc is present in the accumulation region and it decreases to zero in the
other two regimes. Note also that in Figures 6.16b and 6.16c, the slope of the curves is −Cox .

Figure 6.16: Components of charge (C/cm2 ) in the MOS capacitor substrate: (a) depletion-layer
charge; (b) inversion-layer charge; and (c) accumulation-layer charge.

160
The Figure 6.17 shows the total substrate charge, Qs , which is the superposition of the three
curves shown previously, in fact, the charge is due to accumulation charges in the accumulation
region, while in the depletion region, Qs is made of depletion charges.
At last, in the inversion region, it’s made of two components, Qdep that has a constant value and
Qinv that is equal to −Cox (Vg − Vt ).

Figure 6.17: The total substrate charge, Qsub (C/cm2 ), is the sum of Qacc , Qdep , and Qinv .

In the same figure above, we can see also a QG charge, which is defined as QG = −Qs , so basically
the opposite of the charge Qsub . If it’s linear, then we have a linear capacitance as well and it
goes as Q = CV (its graph is shown with a green line in Figure 6.17).
However, the QG is not linear in depletion, in this case, we need to use differential capacitance
dQ
(its expression is Cd = dV ) because of the non-linearity, as shown with the red line. Qs is
conventionally negative, but, if we want QG , so its positive counterpart, then we could change
the sign of the graph.
In general, the total substrate charge is equal to the sum of the three singular components, as
said earlier, and therefore assumes the following expression:

Qs = Qacc + Qdep + Qinv (6.49)

6.7 MOS C-V characteristics

The C–V curve is usually measured with a C–V meter shown in Figure 6.18, which applies a DC
bias voltage, Vg sets a work point, and a small sinusoidal signal (1 kHz - 10 M Hz) to the MOS
capacitor and measures the capacity current with an AC meter.
We are going to measure the current icap and then integrate it over time, thus obtaining the
charge, so by knowing the charge and the voltage applied we can also evaluate the differential
capacitance.

161
 Figure 6.18: Setup for the C–V measurement.

The capacitance is evaluated in the following manner by setting a Vg bias point:

dQg dQs
C= Vg =Vg0 =− (6.50)
dVg dVg

We are looking at static or quasi-static curves, so the voltage is steady but there are some non-
static effects that modify the curve shape. Measuring CV characteristics at different frequencies
puts in evidence some non-static effects.

Figure 6.19: The quasi-static MOS C–V characteristics.

By analyzing Figure 6.19 we can extract many parameters without the need to evaluate them
analytically:

• We can extract the Cox as the asymptotic value of the C-V characteristics, then from the
formula Cox = tox ,
εox A
if we know εox and A, we can calculate the oxide thickness tox ,
without the need to destroy the capacitor to measure it physically, as follows

εox A
tox = (6.51)
Cox

162
 • We can also extract the flat band voltage Vf b from the point of change of the C-V curve.
We also know that the flat band voltage can be evaluated as

Vf b = ϕg − ϕs (6.52)

and if we know ϕs , because it can be expressed as qχs which is a material property, we can
also extract the gate work function ϕg by inverting the previous formula.

• In addition, in the depletion region the capacitance decreases because Wdep increases, and
so does also the depletion charge, and because Wdep is dependent on the doping density,
we can extract information about doping level from the slope of the curve ;

• We can also extract the threshold voltage Vt by looking for the other point in which the
curve changes and increases again to the Cox value.

In the accumulation/inversion regime the charge of the semiconductor is on the interface while
in the depletion regime, the charge is distributed in the space so we can model the capacitor as:

Vg
Gate

Insulator Cox

Substrate

Cinv Cdep

Bulk

Figure 6.20: Equivalent circuit of an MOS capacitance.

The total capacitance for all the three regimes can be expressed as:

1 1 1
= + (6.53)
C Cox Cdep + Cinv

In the accumulation, we can only see the capacitance between the gate and insulator, thus Cox
which is the only term present. As we go deeper into the depletion regime there will be another
capacitance Cdep = εsi
Wdep which will contribute to the total capacitance measured, thus decreasing
the curve value as the widening of Wdep causes the Cdep to decrease.
At last, in the inversion regime, we see that the value returns near Cox , and this is because of
the inversion capacitance term which is in parallel to Cdep and shortens it, thus bringing back
the C value near to Cox .

163
6.8 Non-idealities of the MOS capacitor
Oxide charge

The basic MOS theory ignores the possible presence of electric charges in the gate dielectric.
There are several types of oxide charge. Fixed positive oxide charge is attributed to silicon
ions present at the Si−SiO2 interface. Mobile oxide charge is believed to be mostly sodium ions.
Mobile oxide charge can be detected by observing the shifts of Vf b and Vt under a gate bias
at a high temperature as a result of the movement of the ions in the oxide, due to imperfections
or contamination.
For example, sodium contamination must be eliminated from the water, chemicals, and containers
used in a MOS fabrication line to prevent instabilities in Vf b and Vt . In addition, significant
interface traps or interface states may be present, neutral, or charged depending on Vg , and
they can trap and release electrons and generate noise and degrade the sub-threshold current of
MOSFETs.

Fixed Positive charge

Assuming surface charge on the interface, it can be demonstrated that if there are some fixed
charges inside the oxide we can calculate an equivalent surface charge, Qox (C/cm2 ), which exists
at the SiO2 −Si interface, and so the band diagram at the flat-band condition would be modified
with some internal potential decrease (or voltage drop) in the oxide.
The flat-band voltage is ideally Vf b = ϕg − ϕs . The oxide charge, assumed to be located at
the oxide–substrate interface for simplicity, induces an electric field in the oxide and a constant
voltage drop in the material, quantified as −Qox /Cox . Clearly, in this case, Vf b is different from
Vf b0 (the ideal one without any oxide charge), so if we want to align the two Fermi levels we’ll
need to change Vf b accordingly to this shift.
The general expression for the flat band voltage then is the following:

Qox Qox
Vf b = Vf b0 − = ϕg − ϕs − (6.54)
Cox Cox

Figure 6.21: Flat-band condition (no band bending at body surface) (a) without any oxide
charge; (b) with Qox at the oxide–substrate interface.

164
To see if some fabrication defects create a fixed charge we can fabricate with the same technology
MOS capacitors with different tox and measure the voltage Vf b of each one of those.
By plotting the curve in Figure 6.22 of Vf b as a function of tox we can determine whether there
are some oxide charges or not, by looking if the curve’s profile is dependent or not by the oxide
thickness tox . If it’s an increasing/decreasing line then the Vf b is dependent on the thickness
and thus Vf b varies, otherwise, if we have a constant line for all the values of tox then the curve
is independent of tox and we have that Vf b = Vf b0 and the capacitor doesn’t present many
imperfections nor fixed charges.
At last, we can extract some parameters from this curve, such as Vf b0 as the intercept of the
curve with the axis tox = 0, and from the slope of the curve we can also quantify the Qox .

Figure 6.22: Measured Vf b of three capacitors with different oxide thicknesses.

Voltage dependent surface charge

We consider in this case the presence of surface charges. The junction is between a crystal silicon
(substrate) and an amorphous silicon (oxide).
This means that at the junction there will be several states at the interface due to the change in
crystal structure, the states below the Fermi level are full, so they carry an evasive charge that
we denote as Qss , while those above are empty.
If we change the gate voltage, the band bending changes, and the voltage drop is distributed
between the silicon and the oxide. The bands shift and also the Fermi level does, so the traps
state changes consequently by increasing/decreasing the trapped charge, and this can be seen in
Figure 6.23 represented in green.
So the charge on the surface is a function of the surface potential and this charge shifts the flat
band potential Vf b .
Qss
V f b = ϕg − ϕs − (6.55)
Cox
from this expression, we can note that as Qss increases the flat band voltage decreases, instead
if Qss decreases we have an increase in Vf b .

165
 Figure 6.23: Flat band potential shift due to the surface charge.

6.9 Consequences of fixed Qox and variable Qss

Figure 6.24: Effects on the inversion charge of the fixed and variable charge.

In Figure 6.24, the graph at the top left shows the log(Qinv ) in the function of Vg has an
exponential growth below the VT and a linear growth afterward, which means that in log scale
the exponential is represented as linear while the linear behavior is logarithmic in the graph.
In the two graphs below we can see the Qinv and ID that have the same function represented.
This is due to the fact that Qinv is actually responsible for the free charges needed for the
channel, so for the current that flows in the device, therefore they are the same. This was done
by neglecting both Qss and Qox .

166
In the centered graphs instead, we consider the presence of only Qox , and so we have a rigid shift
(along Vg axis), which is due to the fixed charges, but it doesn’t modify the shape of the curve.
In the last graphs on the right side, we consider Qss , and we can see that when Vg increases
there are more trapped charges at the interface, so the curve is distorted with respect to the
initial one. If there’s a distortion, which is increasing for higher values of Vg , it’s due to Qss so
a non-ideality of the interface.

6.10 Poly-Silicon Gate Depletion

MOS capacitor’s gate is made with a high doped poly-Si gate (crystalline) and the capacitor is
biased into surface inversion. The continuity of electric flux (displacement vector) requires that
the bands bend in the gate. Due to the fact that the gate is not a perfect conductor, but a
highly doped poly-silicon, it has a limited conductivity, so it must have a potential drop, which
indicates the presence of a thin depletion layer in the gate. So by increasing the gate voltage,
the Fermi level at the metal side goes down and so our potential drop in the gate, denoted as
qVpoly , increases because the bands are bent and the gradient is positive (so the field is positive).
Therefore the electrons are pushed away leaving behind the positive charges (+) and this creates
a depletion region in the poly-silicon.
Depending on the gate doping concentration and the oxide field, the poly-Si gate depletion layer
will have its depth, Wdpoly and so there will be another capacity Cpoly in this case. This is a bad
effect, because this adds another capacitance between the surface and gate, in series to Cox , and
the total capacitance therefore is reduced:

εpoly
Cpoly = (6.56)
Wdpoly

From the continuity of the displacement vector and Gauss’s Law, we have that

εpoly Epoly = εox Eox (6.57)

qNpoly Wpoly
Epoly = (6.58)
εpoly
So the depletion region width in the poly-silicon is:

εox Eox
Wdpoly = (6.59)
qNpoly

and the total capacitance therefore can be evaluated as a series of two capacitances:
−1 
Wdpoly −1
 
1 1 tox
C= + = + (6.60)
Cox Cpoly εox εpoly
εox εpoly
= with ≈3 (6.61)
tox + Wdpoly /3 εox

167
 Figure 6.25: Poly-silicon gate depletion effect.

If we consider the C-V curve we expect to see the depletion layer growth in the poly-silicon from
the graph because as Vg goes up the Cpoly goes down and so it brings down the total capacitance,
as can be seen in purple in Figure 6.26:
 −1
1 1
C= + (6.62)
Cox Cpoly

Without considering the breakdown effect, at some point with increasing Vg , the capacity goes
up again.

Figure 6.26: Effect of Cpoly introduction.

168
6.11 Inversion and accumulation layer and quantum mechanical effect
The solution of Schrodinger’s and Poisson’s equations determines the inversion-charge profile.
The potential well at the surface, can be considered a quantum well and be approximated as a
rectangular well in which the energy levels are quantized, in fact, at the interface the probability
of finding charges is almost zero and it’s more common to find the charges at lower levels of
energy due to the Fermi function.
This phenomenon is often referred to as the quantum mechanical effect in a MOS device and
the average position of the inversion charge beneath the Si − SiO2 interface is known as the
inversion-layer thickness, Tinv . It is reasonable to assume that Tinv is a function of the field in
the inversion layer, and therefore a function of (Vg + Vt )/6Tox . The electron inversion layer is
thinner than the hole inversion layer because the electron’s effective mass is smaller than that of
the holes.

Figure 6.27: Average location of the inversion-layer electrons is about 15 Å below the Si − SiO2
interface. Poly-Si gate depletion is also shown.

So we can think that the bottom electrode of the MOS capacitor is not exactly at the Si − SiO2
interface, but effectively located below the interface set by the distance Tinv , in other words, Tox
is effectively increased by Tinv /3, where 3 is the ratio of εs /εox . This is due to the quantum
behavior of the charges, in fact, if we didn’t have quantum influence then the charges would pile
up almost at the interface and have a different electron density curve (shown in purple in Figure
6.27). In the accumulation region, the situation is analogous as the accumulation layer will have
a similar thickness.
The effect on the C–V characteristics is to decrease the curve values at the onset of inversion
and accumulation. In the depletion region, Cinv is negligible (because there is no inversion
charge) and Cpoly can be neglected because Wdpoly << Wdep . But as Vg increases towards Vt ,
Cinv increases as the inversion charge begins to appear, and thus the total capacitance begins to
increase again.
After that, we’ll have another decrease due to Cpoly , but due to the inversion of the poly-silicon
at even higher values, we can have a shift upward in the total capacitance (this inversion happens
at higher voltage because of the higher doping in poly-silicon).

169
Figure 6.28: The effects of poly-depletion and charge-layer thickness on the C–V curve of an N +
poly-gate, P-substrate device.

The red curves shown in Figure 6.28 are due to the capacitance Css which is in parallel with
Cdep , thus reducing its effect and bringing up the total capacitance value. The configuration of
the capacitances in this region is shown in Figure 6.29.

Vg
Gate

Cox

Insulator

Cdep Css

Substrate

Figure 6.29: Equivalent capacitance in the depletion region.

The capacitance rises smoothly toward Cox because the inversion charge is not located exactly
at the silicon–oxide interface, but at some depth that varies with Vg . At larger values of Vg ,
Cpoly cannot be assumed to be negligible, because Wdpoly increases, and so the total C drops. In
fact, Tinv and Wdpoly used to be negligible when Tox was large but for thinner oxides this isn’t
the case and they can’t be neglected anymore.
Because it is difficult to separate Tox from Tinv and Wdpoly by measurements, an electrical oxide
thickness, Toxe , is often used to characterize the total effective oxide thickness. The thickness Toxe
is deduced from the inversion region capacitance measured at Vg = Vdd , and it’s an effective oxide
thickness that corresponds to an effective gate capacitance, Coxe = εox /Toxe . Those quantities,
so Toxe and Coxe have therefore the following expressions:

Effective thickness at Vg = Vdd Effective charge

Wdpoly Tinv
Toxe = Tox + + Qinv = Coxe (Vg − Vt ) (6.63)
3 3

170
6.12 Equivalent circuit for MOS Capacitor

Vg

Gate Cpoly,dep Cpoly,inv Cacc Css

Insulator Cox

Substrate Cacc Cdep Cinv Css

Figure 6.30: Equivalent circuit for an MOS Capacitor.

In the poly-silicon Css and Cacc can be neglected as they have an irrelevant contribution, but they
are represented anyway, therefore the only important capacitances in poly-silicon are Cpoly,dep
and Cpoly,inv .
The substrate parallel capacitances can be simplified, according to the operating region: in fact,
Cacc becomes relevant in the accumulation region, while Cdep is relevant in the depletion regime,
at last in the inversion region we have the contribution of Cinv and Css , which is due to trapped
charges in the interface, as stated previously.
The inversion capacitance in the gate becomes relevant at high positive voltage because we bring
the holes at the lower part of the gate and we draw electrons at the top of the substrate so we
can have inversion in both the gate and the substrate. This induces an increase in total capacity,
firstly because of the substrate inversion, and then at some point, we will see an extra increase
due to the inversion of the gate. This happens at a large voltage because of:
r  
qND 2εs 2ϕF kT ND
Vt = Vf b + 2ϕF + ϕF = ln (6.64)
Cox q ni

in fact, at large voltage ND is larger than NA of the substrate so also Vt is larger due to the
change in the square root term, and also in ϕF expression, of NA with ND (note that in the
equations above NA was already substituted with ND ).
To observe the Css effect, which is the effect of traps, we study it in the depletion region, where
increasing a bit the Cdep , distorts the C-V curve increasing the minimum capacity.

171
 Figure 6.31: Depletion process in the P-substrate, generating Cdep .

To switch from accumulation to depletion region we must only push away the positive charge
(holes) away from the substrate surface and build them up at the bottom of the gate instead.
As the next step, we need to invert this layer, which will be explained in the next section.

6.13 Supply of inversion charge

This concept is related to majority carrier mobility and to the dielectric relaxation time. If we
want to go into inversion we need to build up a layer of minority carriers. These electrons must
be created by the generation processes, but we don’t have a current here so we can’t have impact
ionization, nor do we have light for radiative generation, and so the only process is thermal
generation. The thermal generation is quite inefficient though, and could take a log time, few
seconds, to generate a strong inversion layer.
This means that if we are measuring capacitance, if we fast step from depletion to inversion we
must wait to measure it correctly, because of slow inversion layer formation we won’t be able to
measure Cinv . If we fast measure the capacitance we get the H-Frequency C-V curve, otherwise
we obtain a quasi-static low-frequency curve.

Figure 6.32: Inversion process in the P-substrate.

For this reason, as shown in Figure 6.32, the measurements of the capacitance are done either
with light, for better generation processes, or with a reservoir of carriers that we need to use for
the inversion layer.
The reservoir is doped N + and it’s connected to the bulk to have the same potential. At the
surface, we’ll have a forward-biased junction so the reservoir can inject the carriers into the

172
substrate to form the inversion layer. When we want to discharge Cinv then we lower the gate
potential so the junction is then reverse-biased and therefore all the carriers go back into the
reservoir.
This is done to measure it faster or at higher frequencies without the need to wait for long
thermal generation, therefore the core concept is introducing other processes for faster generation
of carriers.

6.14 Application of MOS Capacitor

In this section, we are going to talk about the application of the MOS capacitors, in particular
the CCD Imager and the CMOS Imager.
First of all, an Imager is a sensing device that converts an optical image into an electronic
signal. CCD and CMOS imagers are used in digital cameras and video recording devices. The
first one has higher performance but is more expensive, while the second one is newer and less
expensive.

6.14.1 CDD Imager

A CCD (Charge Coupled Device) imager is a pile of capacitors stacked next to each other that
depend on voltage and behaves like a shift register for the charge, it’s used as memory or camera
sensors. CCD arrays are used also to convert an image into packets of electrons stored in a
two-dimensional array of MOS capacitors.

Figure 6.33: Deep depletion. (a) Immediately after a gate voltage Vg > Vt is applied, there are
no electrons at the surface. (b) After exposure to light, photo-generated electrons have been
collected at the surface. The number of electrons is proportional to the light intensity.

Figure 6.33a displays a MOS capacitor that has been biased into deep depletion. A voltage,
Vg > Vt , has been applied to the gate abruptly. Because thermal generation is a slow process, it
takes some time for the bands to bend beyond 2ϕF and for the depletion region to extend to its
maximum value.
However, due to the abrupt change in voltage and the absence of the carriers at that time,

173
because of slow generation, the depletion region will extend more than at its steady state, and
this is referred to as deep depletion (after some time it will, however, go to the steady state
width, as the carriers will be generated through the thermal process).
If light is shone on the MOS capacitor in this state for around ten milliseconds, some photo-
generated electrons will be collected at the interface as shown in Figure 6.33b, and the number
of electrons collected is proportional to the light intensity. The photon-generated holes instead
flow into the substrate and are removed through the substrate contact. Then a CCD array acts
like a shift register, it transfers the collected charge packets to the edge of the array, where they
can be read by a charge-sensing circuit in a serial fashion.
Every three MOS capacitors, or elements, form one sensor pixel. This is done through a string of
gates arranged in groups of three, thus every 3rd gate is biased by the same voltage. Note that the
gates must be close to each other to not lose charge during the transfer from one gate to the next.
To illustrate this charge transfer process,
consider the one-dimensional array in Fig-
ure 6.34a. In the first image, exposure
to a lens-projected image has caused elec-
trons to be generated in the element on the
right, on the left, and in the middle element
in proportion to the light intensity around
those three locations.
Electrons are only collected under these
three elements, not the ones flanking them,
since these three are biased to deeper deple-
tion than their neighbor elements and any
electrons that might appear in the neigh-
bors would flow to these three more positive
locations.
When the gate biases are changed in the
situation of Figure 6.34b, the deepest de-
pletion is created by V2 . As a result, the
charge packets will move to the elements
connected to V2 (shifted to the right by one
element), and the choice of V1 > V3 ensures
that no electrons are transferred to the right
because of the potential barrier. Figure 6.34: CCD charge transfer.

Finally, V1 is reduced to the same value as V3 , thus making the shift of the electron packets to
the right, preparing for the next transfer operation. In this way, the electron packets are shifted
to the right element by element.

174
 Figure 6.35: Architecture of a two-dimensional CCD imager.

Figure 6.36 shows a two-dimensional CCD imager containing four rows and four columns, for a
total of 16 MOS capacitors, plus a reading row at the bottom. The reading row is shielded from
the light by a metal film and the two-dimensional charge packets are read row by row.

6.15 CMOS Imager

CMOS imagers do not shift the charge packets from row to row. In a CMOS imager, the charge
collected in an array element is converted into a voltage by an integrated circuit in that array
element as shown in 6.36. An unconnected N + P junction gathers the light-induced charge.
Photons generating electrons near the PN
junction leads the electrons to diffuse to-
wards the junction and accumulate in the
thin N + region. The PN junction acts as a
capacitor, and the stored electrons alter the
capacitor voltage, namely the N + -region
voltage. This voltage is amplified by a cir-
cuit within each pixel (refer to 6.36). Ad-
ditionally, each pixel includes a MOS tran-
sistor switch regulated by Vr1 , Vr2 , or Vr3
voltages conveyed through lengthy horizon-
tal metal lines. To read the upper pixel
row, for example, we raise Vr1 that acti-
vates (closes) all switches in the row, trans-
mitting signals from these pixels downward,
Figure 6.36: Architecture of a CMOS imager. through vertical metal lines, to the shifter
circuit below, shown in Figure on the left.

175
 Figure 7.1: Images from Early patents on the MOSFET concept.

7 MOSFET
Transistor and IC technologies owe their success to numerous technologists efforts since the
mid-1900s. Early FET patents by J. E. Lilienfeld in 1930 and Oskar Heil in 1935 showcase
early FET concepts. Lilienfeld’s patent introduced a glass substrate, an aluminum foil gate,
and a semiconductor film without an oxide layer between the gate and the semiconductor. He
utilized a unique method, lacking modern photolithography, to create the gate by breaking and
reassembling the glass substrate with an aluminum foil inserted as the gate’s edge. Heil’s 1935
British patent described a MOSFET, illustrating metal electrodes separated by a semiconductor
layer where varying the charge on an electrode alters the layer’s electrical resistance and current
strength through it. While historically significant, these patents required further innovations and
engineering efforts to shape MOSFETs into their current state.

CMOS Technology
Modern MOSFET technology has continuously evolved since its origin in the 1950s. Well-
established but still largely exploited MOSFET technologies have poly-Si gates and a single-
crystalline Si body, visible with individual Si atoms, separated by a 1.2 nm amorphous SiO2
film, equivalent to about 4-5 atomic layers in thickness, and even less SiO2 molecules.
The CMOS fabrication process integrates in a unique process flow the fabrication of two different
types of transistors: the nMOSFET and the pMOSFET. A typical CMOS process flow involves
numerous key steps, which are listed and explained in the chapter ??.

Figure 7.2: Schematic drawing of an NFET and PFET.

176
A N-channel MOSFET, or more simply NFET, is called in this way because the conductive
channel is rich of electron (N-type) and the controlled current is due to electron transport. Vg
and Vd swing between 0V and Vdd , the power-supply voltage. The body of an NFET is P-type
doped and is connected to the lowest voltage in the circuit, 0V . Consequently, the PN junctions
are always reverse-biased or at most in equilibrium; hence,they do not conduct forward diode
current.
When Vg = Vdd , which implies a high input voltage (logical 1), an inversion layer is present in
the P-type region in-between the source and the drain N+ diffusions (the so-called channel), and
the NFET is turned on, while the PFET is turned off. When body and source are connected to
Vdd , the PFET responds to Vg in exactly the opposite manner.
When Vg = 0, so this is the case with low voltage input (logical 0), the PFET is on, while the
NFET is off. The complementary nature of NFETs and PFETs makes it possible to design low-
power circuits called CMOS or complementary MOS circuits. We can distinguish PFET from
NFET thanks to a circle attached to the gate in the circuit symbols.
The following figure is an example of a CMOS
inverter. It charges and discharges the output
node which is a load with a capacitance, C, to
either Vdd or 0 V depending by Vin . A CMOS
inverter is made of a PFET pull-up device and
an NFET pull-down device. So, when Vin =
Vdd , the NFET is on and the PFET is off, and
the output node is pulled down to the ground
(Vout = 0), otherwise with Vin = 0 the output is
pulled up, that means Vout = Vdd .
Figure 7.3: CMOS inverter circuit.

dVc
C· = Ic = IM OS (7.1)
dt

dVc Ic
so = (7.2)
dt C
Considering the Vout as the capacitor potential Vc we can express the current as in the previous
equations. So the speed at which we charge and discharge the capacitor, so the voltage level is
dependent on IM OS , in fact for charging from 0 to 1 logical level we can evaluate the time as
follows: Z t Z VDD
C
dt = dVc (7.3)
0 0 IM OS (V )
Vdd · C
τ= (7.4)
< IM OS >
where < IM OS > expresses the average current over the transient, while τ is the average time to
switch from one logical state to the other.
In either case, one of the two transistors is off and there is no current flowing directly from Vdd
through the two transistors to the ground. Therefore, CMOS circuits consume much less power
than other types of circuits.

177
NFET and PFET can be fabricated on the same chip, in fact, portions of the P-type substrate
are converted into N-type wells by donor implantation and diffusion. Contacts to the P-substrate
and N wells are included in the figure.

Figure 7.4: View and layout of a CMOS inverter.

7.1 MOSFET structure

The two PN junctions are the source and the drain; they supply the electrons or holes to the
transistor channel, or drain them out of the channel, respectively. The name field-effect transistor,
FET, refers to the fact that the gate turns the transistor (inversion layer) on and off with a charge
induction process enforced by the electric field across the gate insulator. The dashed regions,
which encircle the transistor in all directions, represent shallow trenches filled with insulating
oxide. They separate and electrically isolate the transistors from each other. The area inside the
shallow trench isolation (STI) is denoted active area.

Figure 7.5: Cross section along the lateral (source-drain) direction of a MOSFET structure.

178
 The most relevant dimensions for the discussion to follow are:

• W : width of the transistor in the direction perpendicular to the cross section.

• Lg : physical length of the gate electrode at the interface with the gate dielectric. It is
usually measured at the Secondary Electron Microscope (SEM) or Transmission Electron
Microscope (TEM) after cutting a section or slice of the device.

• Lmet : metallurgical channel length. It is the lateral distance between the source and drain
to channel junctions, measured at the interface. It is usually but not necessarily smaller
than Lg due to short regions of vertical overlap or underlap with the gate electrode. It
is extremely difficult to measure directly due to the lack of high resolution doping profile
imaging techniques in two dimensions.

• L: electrical length of the channel, which is the channel extension where the gate is able to
electrically modulate the channel charge. It is an effective length, sometimes also denoted
Lef f , whose value can appreciably change as a function of gate bias. It is drawn equal to
Lmet in Fig.7.5. Usually L≃Lg at low gate voltages.

In a long channel device L≃Lmet ≃LG , whereas in short channel transistor of the most advanced
technology generations (usually denoted technology nodes) these values can be quite different
from each other, and often not uniquely defined.

Figure 7.6: Static Id -Vgs current in linear and logarithmic scales.

179
 Figure 7.7: Typical static I-V curves of a MOSFET.

The most important MOSFET’s static I-V characteristics are those of the drain current Id s
as a function of the gate voltage Vg (usually plotted in both linear and semilog scales, Fig. 7.6),
and those as a function of Vds , Fig. 7.7. Depending on the Vgs , the MOSFET can be at an off-
state (conducting only a very small off-state leakage current, Iof f ) or at the on-state (conducting
a large on-state current, Ion ). For digital applications we would like to achieve a large current in
the on state, Ion , and a fast transient for switching from the off- to the on-state and vice-versa.

180
MOSFET figures of merit: static, digital
The most relevant and commonly used MOSFET’s figures of merit are:

• On-current: Ion = Ids (Vgs = Vds = Vdd ). It is the drain current Ids measured when the
transistor has the largest possible Vgs and Vds for a given power supply voltage Vdd .

• Off-current: Iof f = Ids (Vgs = 0 V, Vds = Vdd ). It is the residual drain current Ids mea-
sured when the transistor should act as an open switch, that is when the lowest Vgs = 0 V
is applied in a single power supply voltage system operated at Vdd .

• Threshold voltage: Vt = Vgs @ Ids = It where It = 0.1µA per µm of device width.

It is the Vgs voltage at a bias conventionally defined as the turning point between the off-
and the on-state. In long channel transistors it depends on the Vsb (body effect). In short
channel transistors it also depends on Vds and L, see section ??.
dVgs
• Subthreshold Swing: SS = d(log10 (Ids )) @Vgs < Vt . It is the inverse logarithmic slope
of the Ids -Vgs curve in the subthreshold region. It expresses the change of Vgs needed to
change the drain current Ids by one decade (10x).
Vt (Vds,lin )−Vt (Vds,sat )
• Drain induced barrier lowering: DIBL = ∆Vt
∆Vds = Vds,sat −Vds,lin is a metric
to quantify the so-called short-channel effects in MOSFETs. It refersg to the observed
reduction of the Vt at higher drain voltages. It will be discussed better in Chapter ??.

7.2 MOSFET drain current

In the following, using the regional approach, we will derive from the drift-diffusion equations
a number of analytical expressions and models for the MOSFET drain current as a function of
bias voltages. To this end, we assume an N-type device, a uniformly doped silicon substrate,
and uniform structure of width W in the Z direction. Therefore, we expect to find a linear
proportionality of the drain current to the channel width W . We also assume valid the so called
Gradual channel approximation:
We start with a long-channel device, so that the edge effects at the source- and drain-to channel
junctions, and the uncertainties on the value of L, are negligible. If we consider a small Vds , then
the lateral component of the electric field, Ex , will be small compared to the vertical one, Ey .
Therefore, at all x positions along the channel, we can use the 1-D model developed for MOS
capacitors and neglect the lateral field Ex . In other words, according to the GCA we can cut the
channel in infinitely short slices of length dx, and then calculate x-dependent, 1-D solution of the
drift-diffusion model along the y direction, and finally connect with continuity the solutions of
all slices inthe x direction. This procedure holds only when Vds is small; otherwise, the solution
is inaccurate and the approximation breaks down above some bias voltages.
We introduce also the so-called Charge sheet approximation. When excess free carriers are
attracted to the interface they form a thin layer of charge (in the order of few nanometers. For
approximate analytical calculations, the layer can be treated as a Dirac’s delta, i.e., an infinitely
thin distribution of charge (a charge sheet), which is then subjected only to the surface potential
ϕs because a null thickness is considered. This approximation greatly simplifies the calculations

181
to derive an analytical expression of the MOSFET drain current, Ids as a function of applied
voltages, as exemplified below.

Figure 7.8: Current in the MOS transistor.

We start from the continuity equation for the total current density, observing that, at steady
∂ρ
state, partialt = 0; that means the current density J (which flows in the infinitely thin inversion
layer) is solenoidal ( partialx
∂J
= 0). Therefore, the current density is the same in each section of
the channel; hence, independent of x.
Due to the fact that only electrons move in the channel J ≈ Jn , while Jp is negligible; thus, the
MOSFET is a uni-polar device and we can express J as

dϕ dn
J = Jn + Jp ≈ Jn = −qµn n + qDn (7.5)
dx dx

where −qµn n dϕ dϕ
dx is the drift current density component in which E = − dx , and qDn dx is the
dn

diffusion component.
To calculate the channel current I we have to integrate J over the cross-sectional area in the
y-z plane, so in dy (substrate depth) and dz (device width, dz), this because dz is uniform so it
gives us W as a constant, in fact:
Z W Z ∞ Z ∞
I= J(y)dydz = W J(y)dy (7.6)
0 0 0

where the y axis has its origin at the silicon/gate dielectric interface and points toward the
substrate. Note that since from the physics standpoint, electrons are moving in the positive
direction of the x-axis, then Jn < 0 and I as given by Eq. 7.6 is negative. However, the
convention for lumped elements is that the terminal currents are defined as positive if entering
into the terminal. Therefore the drain terminal current Ids entering the drain has the same
direction of the negative I; that is Ids = −I where I is given by Eq. 7.6.
To move forward, we can substitute J from Eq. 7.5 into the integral, and because Vds is small and

182
near equilibrium conditions hold, we can apply the Einstein relation Dn = Vth µn , thus obtaining
Z ∞ 
dϕ dn
Ids = −W −qµn n + qDn dy (7.7)
0 dx dx
Z ∞ Z ∞
dϕ dn
= qW µn n dy − qW Vth µn dy (7.8)
0 dx 0 dx

where − dϕ
dx is the lateral electric field while n is the electron concentration that depends a lot on
y.
dϕ dϕs
If we embrace the charge sheet approximation, then we can substitute dx with dx , where ϕs is
the surface potential, that is the potential at the location of the infinitely thin inversion layer
dϕs
where charges move alongx. Therefore, we can take out of the integral the term dx because it
is independent of y.
We can also replace the x and y-dependent mobility µn with an effective, average, and position-
independent value hereafter denoted µns , that we can then bring out of the integral.
Then, in the second term representing the diffusion component of the current, we can exchange
R∞
the derivative and integral operators, thus obtaining dx
d
0 −qn dy . Remembering that the

total inversion charge per unit area in a thin slice of length dx at position x is expressed as:
Z ∞  
C
−q n dy = Qn (7.9)
0 m2

we obtain Qn , which is actually the same as the inversion charge Qinv < 0 Following these
approximations, we can substitute them into the previous expression and obtain:

dϕs (x) dQn (x)

Ids = −W µns Qn (x) + W Vth µns (7.10)
dx dx
dQn (x)
If we now consider the term dx then, because Vds is relatively small, the gradient along the
lateral dimension will be negligible and we can assume a slowly changing inversion charge Qinv
dQn dQinv
along the x-axis which means that dx = dx ≈ 0.
Therefore we can neglect the diffusion component of the current density, include only the drift
current component, and obtain the following equation:

dϕs
Ids = −W µns Qinv (7.11)
dx
dϕs
we can write: dx = −E so the equation 7.11 assumes the following form:

Ids = W Qinv µns E , (7.12)

since −E can be approximated as −E ≃ Vds

L so Eq. 7.12 becomes:

Vds
Ids = −W Qinv µns (7.13)
L

183
remembering that vn,drif t = −µns E = −µns VLds we can also write it as:

Ids = −W Qinv vn,drif t (7.14)

where vdrif t is the drift velocity, and that means that also the structure of the MOSFET current
is very similar to the current density J = ρ · v from Ohm’s law.
The drift velocity is positive, which means that the electrons go from the source to the drain,while
the J is negative and the drain current enters the drain. If we assume a positive x-axis from the
source to the drain then the current will be negative.
From equation 6.7 we remember the inversion charge Qinv expression

Qinv = −Coxe (Vgs − Vt0 ) (7.15)

So the equation for Ids when we substitute the Qinv becomes

Vds
Ids = W Coxe (Vgs − Vt0 )µns (7.16)
L

It’s important to note that the threshold voltage Vt0 determined according to the capacitor theory
is referenced to the bulk, because the capacitor has neither source nor drain, and therefore an
ideal Coxe = toxe ,
εox
but due to the presence of the source and the drain, the MOSFET Vt0 has to
be recomputed shifting the reference to the source terminal.

184
7.3 MOS threshold Voltage
For an ideal gate insulator with zero space charge density inside, we have that the gate-bulk
voltage VGB has the following expression:

QB (ϕs ) Qn (ϕs )
VGB = VF B + ϕs − − (7.17)
Cox Cox

where Qdep =QB denotes the depletion charge per unit area (the two symbols representing nothing
more than two different ways to refer to the same quantity), whereas Qinv =Qn is the inversion
charge per unit area. The two charge terms represent the expression of the voltage drop in the
oxide computed according to Gauss theorem. For gate voltages below the threshold voltage,
Qn ≈ 0 (see Fig. ??) in chapter 6; therefore, as shown in Fig. ??, we can neglect Qinv compared
to QB and write the VGB at threshold, hereafter denoted VGB
T ,as:

QB (ϕTs ) qNA
T
VGB = VF B + ϕTs − = VF B + ϕTs + yd (ϕTs ) (7.18)
Cox Cox

where ϕTs is the surface potential at threshold, which is equal to 2ϕF for VSB =0 V, while yd (ϕTs )
is the depletion layer width at value ϕTs .
Note that the quantities Cox and Coxe are used equivalently here, but we should always use the
equivalent oxide capacitance, therefore Coxe , since it captures physical phenomena that might
be important in the examined technology. If the MOSFET is biased at a non-zero source-bulk
potential VSB , as the source isn’t connected to the reference zero potential in the bulk anymore,
we have to derive a new expression of ϕTs .
Consider a semiconductor at equilibrium:

dϕ dn
Jn = −qµn n + qDn =0 (7.19)
dx dx
dn dϕ
Dn = µn n (7.20)
dx dx
dn dϕ
= (7.21)
n Vth
 
ϕ1 − ϕ2 n1
= log (7.22)
Vth n2
 
ϕ1 − ϕ2
n1 = n2 exp (7.23)
Vth

185
 Figure 7.9: Threshold voltage.

Using the last equation for a transistor at threshold (Figure 7.9), and choosing point (1) in
the channel, so that ϕ1 = ϕTs , and point (2) in the quasi-neutral region of the source, we have
ϕ2 = ϕbi +VSB which is the potential at the source-bulk junction with a VSB applied and the bulk
is taken at zero potential. In fact, considering that for positive VSB > 0 the junction is reverse
biased, the total voltage drop across the junction is: ϕbi +VR =ϕbi −V =ϕbi −(−VSB ) = ϕbi +VSB .
Regarding the carrier concentrations, we see that n1 = NA (from the definition of threshold
voltage condition) and n2 = ND . Substitution of these expressions in Eq. 7.23 yields:

ϕTS − (ϕbi + VSB )

 
NA = ND exp (7.24)
Vth

Now we can define the built-in potential as the following expression:

 
ND NA
ϕbi = Vth ln (7.25)
n2i

and then we substitute it into 7.24, therefore the expression becomes:

    
ϕTS − Vth ln NDnN
2
A
+ VSB
NA = ND exp  i  (7.26)
Vth

From the last equation we can derive the surface potential at the threshold as follows:
   
ND NA

NA

ϕTS Vth ln n2i
+ VSB
ln = − (7.27)
ND Vth Vth

186
     
NA ND NA
ϕTS = Vth ln + ln + VSB (7.28)
ND n2i
 
NA
= 2Vth ln + VSB (7.29)
ni
= 2ϕF + VSB (7.30)

Using the initial expression (equation 7.18) we have that:

QB (ϕTs ) qNA
T
VGB = VF B + ϕTs − = VF B + ϕTs − yd (ϕTs ) (7.31)
Cox Cox

and by remembering that:

Qdep (ϕs ) = QB (ϕs ) = −qNA Wdep (ϕ) (7.32)

r r
2εSi 2εSi
Wdep (ϕ) = ϕ → at ϕ = ϕTs = 2ϕF + VSB → ydT = (2ϕF + VSB ) (7.33)
qNA qNA
so by substituting the ydT value into the equation 7.18 we obtain that:
r
qNA 2εSi
T
VGB = VF B + 2ϕF + VSB − (2ϕF + VSB ) = (7.34)
Cox qNA
(7.35)
p
= VF B + 2ϕF + VSB + γ 2ϕF + VSB

where γ is the so-called Body-Effect parameter and it has the following expression
√
2εqNA
γ= (7.36)
Cox

So now we consider VGS = VGB − VSB and therefore we obtain the following expression

we add and subtract γ 2ϕF (7.37)

T
p p
VGS = Vt = VF B + 2ϕF + γ 2ϕF + VSB
(7.38)
p p p
= VF B + 2ϕF + γ 2ϕF + VSB + γ 2ϕF − γ 2ϕF
(7.39)
p p p
= (VF B + 2ϕF + γ 2ϕF ) + γ 2ϕF + VSB − γ 2ϕF
p 
(7.40)
p
= VT 0 + γ 2ϕF + VSB − 2ϕF

with VT 0 (7.41)
p
= VF B + 2ϕF + γ 2ϕF

We can now derive a model for larger values of Vds , where we also consider the source and
drain effects. The presence of lateral potential will change the distribution of the electrons in
the channel. From source to drain, the potential increases, and, also, the surface potential with
respect to the bulk increases along the channel.
Therefore, the depletion charge will not be constant along the channel but it will increase toward
the drain, as shown in Figure 7.9, while the gate potential is the same at all points.If we take a
vertical slice of the channel next to the drain, it will be wider and host more depletion charge
than the ones taken next to the source. In order to compensate the wider depletion layer we
will have less electron density per unit area at the drain end of the channel than at the source.

187
A gradient of electron concentration along the channel is then expected to exist at large drain
voltages.

7.4 Body Effect

The previous section assumes a uniform substrate doping and equilibrium state, which is not
always valid, strictly speaking. When the source/body junction is reverse-biased, there are two
quasi-Fermi levels (Ef n and Ef p ) which are separated by qVsb . An NMOSFET reaches the
threshold of inversion when EF n is close to EC , not EF p . This requires the band-bending to be
2ϕF + Vsb , not 2ϕF . The expression of the threshold voltage will then be:
√
qNa 2εs p 
(7.42)
p
Vt = Vt0 + 2ϕF + Vsb − 2ϕF
Coxe
p 
(7.43)
p
= Vt0 + γ 2ϕF + Vsb − 2ϕF

where γ is the Body-Effect parameter. This model contains a square root dependence of the
VT on VSB which is accurate but not very handy to manage for simple back of the envelope
calculations. In the following, we adopt a linearized capacitance model to derive a simpler
expression for the body effect on the threshold voltage. We start from the observation that the
threshold voltage condition is defined by the amount of free charge in the channel, which is in
turn set by the value of the surface potential. The surface is capacitively coupled to the substrate
and the gate terminals, via two voltage dependent capacitances: Cdep , which is the capacitance
of the depletion region in the substrate, and Coxe which is the effective gate dielectric capacitance
discussed in Chapter 6.
When a voltage is applied to the gate terminal, a charge accumulates on the gate which generates
a vertical electric field across the gate dielectric that controls the concentration of free electrons
(or holes) eventually responsible for the source to drain current. This field is not fully screened
by the channel charges; therefore, it extends into the substrate where the field flowlines close on
the ionized acceptor charges inside the depletion layer.
Coxe is the effective gate to channel capacitance and is primarily associated with the gate dielectric
of the MOSFET (between the gate terminal and the semiconductor substrate) as discussed in
chapter 6. As the gate voltage is modulated, the electric field in the dielectric is also modulated,
an effect represented by the lumped Coxe . The inversion charge is the combination of the channel
charge on the plates of Coxe , determined by the excess Vgs with respect to the VT 0 value, and
the depletion charge on the plates of Cdep , determined by the Vsb . Reminding the expressions of
the differential junction capacitance in inversion, chapter 3, and accounting for the sign of the
charges and voltages, we can write

εs
Cdep = [F/m2 ] (7.44)
Wdmax
Qinv = −Coxe (Vgs − Vt0 ) + Cdep Vsb (7.45)
  
Cdep
= −Coxe Vgs − Vt0 + Vsb (7.46)
Coxe

188
where Qinv is the inversion charge that is due to Coxe but also to Cdep . This is why Cdep Vsb term
is positive, as the depletion contribution is made of the opposite charge and therefore it has an
opposite sign with respect to the Coxe term.
Notice that, in principle, Cdep has an inverse square root dependence on Vsb . Only upon Taylor
series expansion at Vsb = 0 we get the linear expression in Eq. 7.44. We can then write:

Cdep
Vt (Vsb ) = Vt0 + Vsb = Vt0 + αVsb (7.47)
Coxe

So we linearize the model with a linear coefficient dependence denoted as α and that is called
the body-effect coefficient, which has the following expression:

Cdep 3Toxe
α= = (7.48)
Coxe Wdep

In order to decrease α and reduce the body effect we need

qto increase Wdep , therefore we need a
low substrate doping NA since Cdep = Wdep and Wdep = qN
εs 2εs
A
ϕs .

Figure 7.10: Body effect in an MOSFET.

To summarize, the body effect makes Vt dependent by Vsb . When the source-body junction is
reverse-biased, as it should be to avoid parasitic source/drain junction forward currents flowing
in the substrate, |Vt | increases (for both n- and p-MOSFETs) as can be seen in Figure 7.11.
Normally, the source-body junction are never forward-biased, so there is no forward diode current.
Furthermore, in the CMOS inverter, the source terminals of the pull-up and pull-down transistors
are directly connected to ground and VDD , therefore VSB = 0. However, when multiple NFETs
(or PFETs) are connected in series in a circuit, they share a common body (the silicon substrate
or the N-well potential) but their sources are not all at the ground potential. So, some transistor’s
source-body junctions will be reverse-biased, and this raises their Vt and reduces the Ids and the
circuit speed. In these instances, it is best if Vt is insensitive to Vsb , so the body effect should

189
be minimized, and this can be accomplished by minimizing the Toxe or increasing Wdep (i.e.
decreasing the doping level NA ) to decrease α.

Figure 7.11: Threshold voltage as a function of Vsb due to the Body Effect.

7.5 Inversion charge for MOSFET

In MOSFETs, Qinv refers to the inversion charge in the channel region. The inversion charge
is the charge carriers (electrons or holes) that accumulate in the semiconductor channel when
the MOSFET is in the inversion mode, allowing current to flow between the source and drain
terminals. This inversion process occurs when a voltage is applied to the gate terminal.
For an N-type MOSFET (NMOS), a positive voltage applied to the gate induces an electric field
that attracts electrons to the surface of the semiconductor, forming an e− channel between the
source and the drain.
For a P-type MOSFET (PMOS), a negative voltage applied to the gate attracts holes to the
surface, forming a h+ channel. In general, we have that:

Qdep (ϕs ) Qinv (ϕs )

VGB = VF B + ϕs − − (7.49)
Coxe Coxe

where VGB is the gate voltage with respect to the bulk, VF B is the flat band voltage, ϕs is the
Qdep (ϕs ) Qinv (ϕs )
surface potential, while the terms − Coxe − Coxe expresses the oxide voltage Vox .
While above the threshold we can express Qinv by inverting the formula as:
 
Qdep (VSB )
Qinv = −Coxe VGS − VF B − 2ϕF + (7.50)
Coxe
= −Coxe (VGS − VT (VSB )) (7.51)

190
 Figure 7.12: Inversion charge in an MOSFET.

We can now introduce a parameter called VCS , which is the voltage of the channel at the surface,
and actually, it’s VCS (x) as a function of the distance.
The channel voltage spans from Vc = Vs at x = 0 to Vc = Vd at x = L, and therefore we have
that Vc (x) ∈ [Vs , Vd ]. At a given point x in the channel where the potential is Vc we have:

Qinv = −Coxe (Vgs − Vcs − Vt0 − α(Vsb + Vcs )) (7.52)

= −Coxe (Vgs − Vcs − (Vt0 + αVsb ) − αVcs ) (7.53)
= −Coxe (Vgs − mVcs − Vt (Vsb )) (7.54)

where m is called the Body-Effect factor or Bulk-Charge factor ,it’s values are around 1,
and the most common is m ≈ 1.3, and it has the following expression:

Cdep 3Toxe
m=1+α=1+ =1+ (7.55)
Coxe Wdep

191
Basic MOSFET I-V Model

Ids = −W Qinv v = W Qinv µns E (7.56)

 
dVcs
= W Coxe (Vgs − mVcs − Vt )µns (7.57)
dx

with v = µns E, Qinv = Coxe (Vgs − mVcs − Vt ) and E = dx .

dVcs
So by separating the variables, the
equation above becomes a differential equation in dx and dVcs .
Z L Z Vds
Ids dx = W Coxe µns (Vgs − mVcs − Vt )dVcs (7.58)
0 0

The parameters Ids , Vgs and Vt are constants so by integrating the function we obtain the
following expression:
 m 
Ids L = W Coxe µns Vgs − Vt − Vds Vds (7.59)
2
W  m 
Ids = Coxe µs Vgs − Vt − Vds Vds (7.60)
L 2

7.6 Channel length Modulation

By saturating the expression 7.60, then it becomes equal to
 
W L
ID = · Id,sat (7.61)
L − ∆L W

where Vds = Vd,sat in Id,sat expression, and because of the saturation also the channel length
varies, therefore we needed to add the term L+∆L .
W

Now if we consider ∆L
L << 1, we obtain the following expression

L 1
= (7.62)
L − ∆L 1 − ∆L
L

and by using Taylor’s series expansion we obtain

1 ∆L
≈ 1 + x so in our case we have 1 + (7.63)
1−x L

So now we have
 
∆L(Vds )
ID = Id,sat 1 + where ∆L have a dependence from VDS (7.64)
L

so actually the channel modulation is defined as:

∆L
ID = Id,sat (1 + λVds ) where λ = (7.65)
L

In saturation, Vd,sat can be approximately defined as the voltage at which the term (1 + λVds )
becomes significant, leading to a flattening of the drain current. As the drain voltage Vds in-
creases, the effective length of the channel is effectively shortened due to the modulation effect.

192
If Vgs < Vt + 2 Vds then
m
we will have a negative current. If we want ID = 0 then we need to
have Vgs = Vt + m2 Vds by nullifying the term (Vgs − Vt − m
2 Vds ).
If we know m and Vds then we can extract the value of Vt as shown in Figure 7.13.

Figure 7.13: Vt extraction.

With ID = 0 we have
1
Id,sat λVds = −Id,sat so Vds = − (7.66)
λ
This is a method to extract the value of λ without doing complex calculations and it’s quite
accurate.

Figure 7.14: Drain saturation voltage.

193
As shown in Figure 7.14 when Vds increases, the average Qinv decreases and dIds
dVds decreases. To
find the maximum of the parabolas, so the saturation value, we can differentiate Ids with respect
to Vds , and it can be shown that dIds
dVds becomes zero at a certain value of Vds that is

dIds W
=0= Coxe µns (Vgs − Vt − mVds ) at Vds = Vd,sat (7.67)
dVds L

In particular we should have that Vgs = Vt + m

2 Vds which expressed in Vds is

Vgs − Vt
Vd,sat = (7.68)
m

The parameter Vd,sat is called the drain saturation voltage, and it refers to the voltage drop across
the drain and source terminals of the MOSFET when it is in saturation mode. In saturation
mode, the MOSFET is fully turned on and the device allows the maximum amount of current
to flow between the source and drain terminals. For each Vgs , there is a different Vd,sat .
Vg −Vt
The problem in this model arises when Vcs = m before reaching the drain, due to the
fact that in dIds
dVds = 0 = W
L Coxe µns (Vgs − Vt − mVds ) we can express the inversion charge as
Qinv = Coxe (Vgs − Vt − mVds ), therefore the model breaks down when we reach the condition
Qinv = 0 and even worse Qinv > 0 which is impossible for electrons, so negative charges, and
this happens exactly for Vgs = Vt + mVds value found before.
The relationship between Vds (drain voltage) and Vd,sat (drain saturation voltage) in a MOS-
FET is important for understanding the transistor’s behavior in different operating regions. In
saturation mode, Vd,sat is the minimum voltage drop between the drain and source terminals to
keep the MOSFET fully turned on. The drain current Ids in saturation is often modeled by the
following equation for NMOS:

1 W
Ids = µn Cox (Vgs − Vt )2 (1 + λVds ) (7.69)
2 L

where

• Ids is the drain current

• µn is the electron mobility

• Cox is the oxide capacitance

• W and L are the width and length of the channel, respectively.

• Vgs is the threshold voltage.

• λ is the channel-length modulation parameter.

In real transistors, the slope is due to the modulation of the channel Id,sat = Id,sat (1 + λVds ) and
the current saturates because of the limited amount of charges provided by the source, even if
the charges are traveling at high velocities.

194
If we now compare the results for different m, we obtain the following considerations, shown also
in Figure ??:

• ID0 is the common quadratic expression of Ids vs Vds with m = 1.

• ID3/2 is the result of the accurate integration of the channel current without Taylor
3
expansion of the depletion charge term, and in the formula, it has x 2 dependence.

• ID0-fit is the same as ID0 where the intrinsic gain term Coxe has been adjusted to an
unphysical, so it’s overestimated as values in order to get the same Idsat as the reference
ID3/2 curve.

• Clearly IDn reproduces accurately the reference ID3/2 without resorting to unphysical
parameter values, its the case when m ̸= 1.

The concepts explained above are represented in the Figure 7.15.

Figure 7.15: Model comparison.

7.7 Carrier mobility in MOSFET

An important factor that determines the MOSFET, and in general the semiconductor, is the
carrier mobility. Carrier mobility is typically expressed in units of centimeters squared per volt-
cm2
second V ·s . It represents the average velocity of charge carriers in response to an electric field.
If we consider the MOSFET there are two types of carrier mobility:

• Electron mobility µn : This refers to the mobility of electrons in an N-type semiconductor.

In an N-type MOSFET, electrons are the majority charge carriers responsible for the flow
of current between the source and drain terminals.

• Hole mobility µp : This refers to the mobility of holes in a P-type semiconductor. In a P-

type MOSFET, holes are the majority charge carriers, and they contribute to the current
flow between the source and drain terminals.

195
From Gauss’s Law, using the depletion layer as the Gaussian box we have

Qdep
Eb = − (7.70)
εs
Qdep
Vt = Vf b + ϕst − (7.71)
Coxe

Therefore

Coxe
Eb = (Vt − Vf b − ϕst ) (7.72)
εs
(Qdep + Qinv )
Et = − (7.73)
εs
Qinv Coxe
= Eb − = Eb + (Vgs − Vt ) (7.74)
εs εs
Coxe
= (Vgs − Vf b − ϕst ) (7.75)
εs

So we obtain the following expression:

1 Coxe
(Eb + Et ) = (Vgs + Vt − 2Vf b − 2ϕst ) (7.76)
2 2εs
Coxe
≃ (Vgs + Vt + 0.2V ) (7.77)
2εs
Vgs + Vt + 0.2V
= (7.78)
6Toxe
Vgs +Vt +0.2V
where the term 6Toxe is called universal mobility curve.
In conclusion we remember the previous result for the equivalent oxide thickness:

Wdpoly Tinv
Toxe = Tox + + (7.79)
3 3

Universal surface mobility (surface roughness)

The mobility of charge carriers (µn and µp ) is a measure of how quickly they can move through
the semiconductor material under the influence of an electric field, and it’s a key concept to
performance as the current ID is proportional to the mobility. If we consider a rough surface the
electron mobility value varies.
So surface roughness in semiconductor materials can have a significant impact on carrier mobility
through several mechanisms like scattering. The roughness of the surface introduces scattering
centers for charge carriers.
As carriers move through the semiconductor, they can scatter off rough surfaces, impurities, or
defects. This scattering process leads to a reduction in the average carrier mobility. Scattering
in stronger (so the mobility is lower) at higher Vg , higher Vt (so higher doping), and thinner Toxe .
Due to the quantum nature of electrons mobility in the inversion layer is best described as a
function of the so-called effective field which is a measure of the average electric field by the free
carriers.

196
In general, we have that the electric field has the following expression

Eef f = (|QB | + η|Qinv |)/εSi (7.80)

with η = 1/2 for electrons and η = 1/3 for holes. The universal mobility curve is shown in Figure
7.16 and it expresses the surface mobility µ as a function of the effective electric field Eef f .

Figure 7.16: Universal surface mobility.

The region in the tails of the curve is where the mobilities are limited by impurities (ionized)
and as the field increases we have more free charges which screen the effect of Coulomb charges,
therefore we can see the effect due to the impurities because we have less free charges and so less
screening effects.

7.8 Velocity saturation

The major weakness of the basic MOSFET I-V model is the way the transition between the linear
and saturation region, When the pinch-off condition sets on, at the drain side of the channel
Qinv = 0; hence, an infinite carrier velocity is needed to explain the non zero saturation current
observed in experiments, which is physically impossible. In order to improve the modelling of
this transition, we remind that at low electric field, the carrier drift velocity is, vdrif ⃗
⃗ t = −µns E.
As E = |E|
⃗ increases, the kinetic energy of the carriers rises and, when the energy of a carrier
exceeds the optical phonon energy, inelastic optical phonon emission increases, causing loss of
kinetic energy and randomization of the particles’ velocity vectors. As a result, the average
velocity of the carrier population tends to saturate, although the individual velocity of individual
electrons keeps increasing. The limiting magnitude of the average carrier velocity at high electric
fields is called the saturation velocity and is denoted as vsat .

197
The phenomenon of velocity saturation is modeled with good precision by the following expression
(where E is absolute value of the field component in the direction of the drift velocity):

µns E µns E
vdrif t =   β 1/β =   β 1/β , (7.81)
1 + EEsat E
1 + µns vsat

where β is a fudge factor used to fit the model to experiments. Typical values are β = 1 for holes
and β = 2 for electrons. Notice that, for electrons in nMOSFETs the lateral field in the channel
is actually negative but here E denotes its absolute value. The general behavior of Eq. 7.81 is
easily understood considering that for:

E << Esat : v = µns E (7.82)

E >> Esat : v = vsat = µns Esat . (7.83)

The β factor has a modest effect, restricted to the transition region between the linear transport
regime where v = µE and the saturation regime where v = vsat . For MOSFET modeling, it
is convenient to assume β=1 also for electrons, since in this case new expressions for the drain
current can be derived that incorporate the velocity saturation effect. To this end, we start again
with the general expression:
Ids = −W Qinv v (7.84)

and substitute Qinv (<0) and v (>0) with the expressions:

Qinv = −Coxe (Vgs − mVcs − Vt ) (7.85)

µn E
v= (7.86)
1 + EEsat
dVcs
E= (7.87)
dx

where Esat = vsat /µns and Vcs is the channel surface potential referred to the source. We then
get:

µns ( dV
dx )
cs
Ids = W Coxe (Vgs − mVcs − Vt ) dVcs
(7.88)
1+ dx /Esat
Z L Z Vds  
Ids
Ids dx = W Coxe µns (Vgs − mVcs − Vt ) − dVcs (7.89)
0 0 Esat
 m 
Ids L = W µns Coxe Vgs − Vt − Vds Vds − Ids Vds /Esat (7.90)
2

W µns Coxe Vgs − Vt − m

2 Vds Vds Ids0
Ids = Vds
= (7.91)
L 1 − Esat L 1 + EVsat
ds
L

where Ids0 is the current we would get without velocity saturation, also called "long-channel
current" as with a long channel device the velocity would not saturate because the applied Vds
would fall over a large distance and the electric field would always be smaller than the critical

198
field. Remember that the term µns should include the corrections studied in section 7.7; there-
fore, we should consider µns as a Vgs -dependent quantity.
If Vds is small, the term at the denominator of Eq. 7.91, Esat L ,
Vds
is negligible, the new equation
coincides with the one without velocity saturation, as expected. Instead, if velocity saturation oc-
curs along the channel because Vds
Esat L >> 1, then we can neglect the +1 term in the denominator
and, by remembering that vsat = µns Esat , we obtain:

W  m  vsat 
L  m 
Ids =  Vgs − Vt − Vds 
µns
Coxe ds ·
V = W Coxe Vgs − Vt − Vds vsat (7.92)
L
 2 V
 µns
ds   2

Eq. 7.92 shows that when velocity saturation is established at all sections in the channel, the
current becomes independent of the channel length L and takes values much smaller than the ones
predicted neglecting velocity saturation. Even if this limit case is not reached, the diminished
sensitivity of the current to the channel length has important implications when comparing scaled
devices belonging to different technology generations, since the performance advantage expected
upon scaling may not be reachable.

199
The drain voltage where saturation of the current is achieved, Vd,sat , can be derived imposing

dIds
=0 . (7.93)
dVds

Lengthy and tedious but straightforward calculations lead to:

2(Vgs − Vt )/m
Vdsat = p , (7.94)
1 + 1 + 2(Vgs − Vt )/(mEsat L)

Substitution of Eq. ?? in Eq. 7.92 gives an explicit analytical expression for Ids,sat with velocity
saturation. A simpler, empirical but still accurate expression for Vdsat is:

1 m 1
= + (7.95)
Vdsat Vgs − Vt Esat L

which represents the drain voltage at pinch-off (that is, the saturation drain voltage) as the
"parallel" combination of two voltages, the smallest gives the larger contribution in saturating
the drain current. Esat = vsat /µns is the field value where the mobility saturates.
The first term is the saturation voltage without velocity saturation, due to the inversion charge
going to zero at the drain side of the channel as usually happens if L is large.
The second term is due to velocity saturation; it is the inverse Vds value at which the velocity
v = vsat , so that velocity saturation limits the current; the situation we expect when L is small.
The two terms compete and which is the dominant one depends on the channel length If L
is large and Vds /L << Esat , then Ids saturates because a pinch-off condition is reached where
the inversion charge goes to zero at the drain end of the channel. Instead, if L is small and
Vds
L >> Esat , the velocity will be limited by vsat ; thus, the |Qinv | reaches a minimum value (still
larger than zero); then both the velocity and the drain current saturate, a situation expected
to occur in modern short channel device or in the drift region of special MOSFETs for power
applications explicitly designed to sustain very large drain voltages in the order of hundreds of
Volts.

Very short channel

If the channel length L is very short, we can assume the field is larger than the critical field
for velocity saturation everywhere in the channel. Therefore, the velocity should everywhere be
constant and equal to vsat , thus the potential Vds,sat is:

Vgs − Vt
Esat L << Vgs − Vt Vds,sat = (7.96)
m

so if we consider the current expression for the saturation region

W
Id = Coxe µns (Vgs − Vt )2 (7.97)
2mL

200
and considering the saturation velocity condition we modify it to be

W (Vgs − Vt )2
Id,sat = Coxe µns (7.98)
2mL 1 + EVdsL
sat

then, by substituting the Vds,sat we obtain the following expression

W (Vgs − Vt )2 long − channel Id,sat

Id,sat = Coxe µns V −V
= Vgs −Vt
(7.99)
2mL gs
1 + mEsat L t
1 + mE sat L

If we consider Esat L << Vgs − Vt , we obtain the modified expression for the current

Ids = W Qinv vsat = W vsat Coxe (Vgs − Vt − mEsat L) (7.100)

But L is very small so it can be neglected, thus the expression becomes as follows:

Ids = W vsat Coxe (Vgs − Vt ) (7.101)

The term Coxe (Vgs − Vt ) is equal to Qinv , also in this equation we lose the linear dependence on
the length L and only 1
L dependence remains, which is less sensitive, and the saturation current
ID is now linearly dependent to Vgs − Vt and not anymore to the quadratic term (Vgs − Vt )2 .
Considering the transconductance gm = dIds
dVgs we observe that for a very short channel, its value
is constant, while in a long channel device, we have that gm ∝ (Vgs − Vt ), where Vgs is the bias
voltage.
Having a constant gm is a good thing for large signal amplification because it removes the
distortion effect introduced by the changing of the bias point and so the gain doesn’t change
when Vgs varies.
For small signals instead, we have that gm ∝ (Vgs − Vt ), but it’s not a problem as in this case,
it’s "almost" constant.

7.9 Subthreshold region

The subthreshold voltage in a MOSFET refers to the gate-source voltage at which the transistor
is just starting to conduct, allowing a small but non-zero current to flow from the source to the
drain.
It defines a critical operational region with unique characteristics, in fact, this region is charac-
terized by the transistor being in a slightly conducting state, holding substantial significance in
low-power circuit design and optimization.
We consider the usual current expression, expressed in the following equation:

W  m 
Ids = Coxe µns Vgs − Vt − Vds Vds (7.102)
L 2

The MOSFET current observed at Vgs < Vt , which is shown in Figure 7.17, is called the Sub-
threshold current. This is the main contributor to the MOSFET off-state current, Iof f , which
is the Id measured at Vgs = 0 and Vds = Vdd .
It is important to keep Iof f very small in order to minimize the static power that a circuit con-

201
sumes when it is in standby mode.
As shown in Figure 7.17, the subthreshold current is plotted in a semi-log Ids vs Vgs graph. When
Vgs is below Vt , Ids has a linear behavior because of an exponential dependence (if considered in
the linear scale).

Figure 7.17: Subthreshold current plot.

At Vgs below Vt , the inversion electron concentration (ns ) is small, but nonetheless can allow
a small leakage current to flow between the source and the drain. From the band diagram in
Figure 7.18 we can express the electron concentration as
 
ϕ1 − ϕ2
ns = n2 exp (7.103)
Vth

n2i
Where n2 = NA and ϕs = φs = ϕ1 − ϕ2 , taken from the points marked in Figure 7.18, and so
after substituting we obtain the following expression:

n2
 
φs
ns = i exp (7.104)
NA Vth

Figure 7.18: Subthreshold current band diagram.

202
In this situation the equivalent model of capacitance is composed of the capacitance between
the gate and the surface Coxe and the depletion capacitance Cdep between the surface and the
substrate as shown in Figure 7.19.

Vg

Coxe

φs

Cdep

Figure 7.19: Equivalent capacitance circuit.

So we can derive that φs varies with Vg through a capacitance network in the following way:

dφs Coxe 1
= = ≤1 (7.105)
dVg Coxe + Cdep η

and by taking the inverse we can express η as

Cdep
η =1+ >1 (7.106)
Coxe
Vg
So in the subthreshold regime φs = constant + η . Consequently, we can say that:
   
 qφ 
s q(constant + Vgs /η) qVgs
Ids ∝ ns ∝ exp ∝ exp ∝ exp (7.107)
kT kT ηkT

So Ids is exponentially proportional to Vgs , and therefore on a logarithmic scale it will be linear,
as shown before in Figure 7.17.

Figure 7.20: Subthreshold leakage current.

203
With this model we neglect the velocity saturation effect and so the current will depend on Vg .
If Vg = VF B , where Vf b is the flat band voltage, the potential drop from surface to bulk φs = 0,
therefore the source-channel voltage drop is equal to ϕbi , the built-in voltage of the junction.
If we increase Vg , and obtain the condition Vg > VF B , also φs increases and becomes positive.
Therefore with a φs > 0 we lower the energy bands, so also the conduction band goes down of a
quantity φS , and so the barrier goes down and allows the electrons to form the channel, because
they can move with lower energy now and be injected into the junction from the N-reservoir
(which is shown in red in Figure 7.20).
At room temperature, so Vth ≈ 25 mV the Ids function changes by a decade, so 10x, for every
η60mV changes in Vg :  
qVgs Vgs
log (Ids ) ∝ = (7.108)
ηkT ηVth
Subthreshold swing = SS = η ln (10)Vth ≈ η ln (10)25mV ≈ η · 60mV (7.109)

This parameter sets the value of ∆Vgs needed to switch from the off state to the on state. It’s
important because this value of ∆Vgs must be less than the maximum power supply Vdd . In
addition, this changes also the value of Iof f .
For example, if we want a difference between Ion and Iof f , of 5 decades we will need a range of
∆Vgs = 5 · η · 60mV and that value must be under the maximum Vdd .
The Iof f can be expressed as follows

W Vt
Iof f (nA) = 100 · · 10− SS (7.110)
L

and as can be seen, it’s determined only by Vt and SS, so the subthreshold swing.
For a given set of W and L values, minimizing Iof f , as depicted in Figure 7.21, can be approached
in two primary ways.
One method involves opting for a larger Vt , yet this isn’t ideal since a higher Vt diminishes Ion ,
consequently impacting the circuit’s speed negatively.
The more favorable approach entails reducing the subthreshold swing SS, as can be seen in
purple in Figure 7.21, in fact, if we lower SS then 1
SS will become larger and therefore we need
less ∆Vgs to turn on the device, and so we can reduce also the maximum voltage supply Vdd .
Achieving this involves decreasing SS, which can be obtained by reducing η. This reduction can
be facilitated either by increasing Coxe or by decreasing Cdep , which expressions we remind in
the following equation

εox εs
Coxe = Cdep = (7.111)
Tox + Tinv + Wd,poly Wdep

Regarding the increase of Coxe we can either utilize a thinner oxide, thus reducing Tox or by
removing completely the Wd,poly term by changing the material to a metal gate, hence avoiding
the depletion in this case.
For the decrease of Cdep instead, we have only one way, which is augmenting Wdep , this can be
achieved with a smaller doping.
However, we must be careful in doing so as, in case of Coxe , having a thinner Tox raises the

204
field in the oxide (which is E = Tox )
V
and therefore it makes the oxide less reliable due to big-
ger breakdown probability (due to high fields), and also it can cause bigger oxide leakage currents.

At last, regarding Cdep , lowering the substrate doping is not that easy as it’s not a free parame-
ter, but it’s set by Vt . So as we can see we have some limitations in lowering the SS, and even
if we could lower it in an ideal way (so making for example Cdep ≈ 0) we’ll obtain an η = 1 at
best, so it can’t be changed too much anyway.
Additionally, an alternative method to diminish SS, and thereby reduce Iof f , involves operat-
ing transistors at significantly lower temperatures than room temperature. While theoretically
valid, this strategy is seldom employed due to the substantial added cost associated with cooling
measures.

Figure 7.21: Subthreshold swing.

Regarding the CMOS usage for digital applications, in particular switching, we can consider the
power formula for switching:
2
Pdyn = f CL Vdd (7.112)

where f is the frequency, CL is the load capacitance and Vdd is the supply voltage. This formula
expresses the dynamic power dissipated to switch from one logical state to another (for example
from 0 to 1) in a CMOS used for digital applications.
Ideally, to achieve the minimum power consumption, we might think to decrease the Vdd , but
we can’t do this too much, because we are limited by the range of ∆Vgs introduced with the
subthreshold swing concept.
In fact, reducing Vdd means having less range to set Vgs < Vdd , so the switch doesn’t close totally
and there is some leakage current, which means lost standby power. Also, if Vdd is small we’ll
have a smaller Id,on and so our circuit will be slower as we charge/discharge the capacitor CL
more slowly, therefore power consumption is inversely proportional to speed and performance
(in fact with larger Vdd we have more Pdyn , so more leakage currents and dissipations, but the
device is much faster).

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7.10 Parasitic source-drain Resistance
The source and drain terminals have a fundamental role in the operation of the device. However,
these terminals are not ideal conductors; they are doped semiconductors that have low, but not
negligible, resistance:
1 1
ρ= = (7.113)
qµn n + qµp p σ
Parasitic resistance emerges due to the physical properties of the materials and the structure of
the MOSFET. Separating the channel from S/D series resistance entails the identification of two
nodes at the end of intrinsic channel.
If Id,sat0 ∝ Vg − Vt , then we can express it with the following expression

Id,sat0
Id,sat = Idsat0 Rs
(7.114)
1+ (Vgs −Vt )

and because of the parasitic resistance Id,sat can be reduced by about 15% in a 0.1µm MOSFET
and the effect is greater in shorter MOSFETs (in fact, it can reach up to 30-40% reduction in
current). Due to the presence of the parasitic resistances also the voltage expression changes and
it becomes of the following form:

Vd,sat = Vd,sat0 + Id,sat (Rs + Rd ) (7.115)

Thus, the two series resistances contribute to the channel, which is not described by the previous
models. These resistors introduce voltage drops before and after the channel, causing an internal
′ that differs from the external V . Consequently, the voltage at the beginning of the
voltage Vds ds
channel (x = 0) may not be equal to the source and the voltage at the end of the channel (x = L)
will not be equal to Vds . In the following Figure 7.22 the parasitic resistances are represented
and below also the equations for the voltage at source and drain, both in the ideal case and with
parasitic resistances effects:

G
RS RD
S D

Figure 7.22: Equivalent circuit of MOSFET with Source and Drain resistance.

With Rs and Rd : Ideal case:

V (0) = ID Rs V (0) = 0 (7.116)
V (L) = Vds − ID Rd V (L) = Vds (7.117)

206
As shown in Figure 7.23, the S/D series resistances have three components, and it’s defined as

Rs = Rd = Rc + Rsh + Rsp (7.118)

where the terms express:

• Contact resistance (Rc ): Resistance between the metal-semiconductor junction.

• Sheet resistance (Rsh ): It’s the channel resistance and is approximately equal to

LS/D
Rsh ≈ ρsh · (7.119)
(W · xj )

where ρsh is the resistivity of the channel, xj is the depth of the junction, and L and W
are the length and the width, respectively.

• Spreading resistance (Rsp ): Also called access resistance, it’s due to the portion of the
source/drain facing the channel where all of the current’s flowlines converge to the channel
in a strict space. This constriction of flow lines generates some extra resistance, which is
represented as Rsp .
Another effect considered in this resistance is the gate’s effect, in fact, the gate creates the
inversion layer to form the channel, so it modulates the carrier density at the interface. By
doing this, as can be seen in Figure 7.23, it creates some lateral fields and this changes the
carrier concentration in the region adjacent to the gate, which consequently changes the
resistivity and the resistance in those regions.

Figure 7.23: Parasitic resistances inside the device.

Identifying the exact impact of the resistance at the parasitic site remains challenging, even with
an equivalent model. If the channel is very long, then Rsh dominates, because it’s larger with
respect to the other terms, therefore we can neglect Rc and Rsp .
On the other hand, if the channel is short then we need to consider Rc and Rsp and their effects.

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7.10.1 Extraction of the series Resistance and Effective channel length

Figure 7.24: Channel length representation.

Figure 7.24 illustrates the different lengths that are present in the circuit layout, referred to as:

• Drawn gate length, Ldrawn , is the length of the gate as drawn in the lithography masks.

• Physical gate length, Lg , is the physical gate length after fabrication. It may not be
equal to Ldrawn due to dimensional changes that can occur during the pattern transfer
process.

• Metallurgical channel length, Lmet , is the distance between the Source-channel and
Drain-channel junctions.

• Effective channel length, Lef f , or electrical channel length Le , or simply L,

is defined as the portion of the channel where modulation of the inversion charge occurs
according to a defined criterion. It is particularly important to know the difference between
Lg and L, which is called ∆L, and therefore, assuming that Ldrawn = Lg we have that
∆L = Lg − L = L − Ldrawn .

To extract the effective channel length we proceed as follows, we consider a MOSFET with a
small Vds , in this case, we are in the linear region, so the current is defined as:

W
Ids = Cox µns (Vgs − Vt )Vds (7.120)
L

Using Ohm’s law and substituting Ids equation the channel resistance can be expressed as:

Vds L 1
Rch = = (7.121)
Ids W Cox µns (Vgs − Vt )

208
But L in this expression is the effective length, and so it’s equivalent to L = Ldrawn − ∆L with
the assumption that Ldrawn = Lg .
Remember that the source and the drain have parasitic resistances, which are called respectively
Rs and Rd , with some different contributions, as discussed in Section 7.10.
Assume that the drops in potential due to the parasitic resistances are

Rs Ids << Vds and Rs Ids << Vgs − Vt (7.122)

Rd Ids << Vds and Rd Ids << Vgs − Vt (7.123)

Due to these assumptions, we can neglect those drops and so we can say that Vgs ≈ Vgs
′ and

′ , therefore the expression of I

Vds ≈ Vds ds becomes

W Coxe µs Vds (Vgs − Vt )

Ids = (7.124)
Ldrawn − ∆L
Ids (Ldrawn − ∆L)
Vds = (7.125)
W Coxe µs (Vgs − Vt )

where Vds is obtained by inverting the formula of the current. The total resistance measured
between the two terminals (source and drain) is equal to:

Rtot = RS + Rch + RD = Rds + Rch (7.126)

By definition, we can obtain the same result with a physical approach given below:

Vds Ldrawn − ∆L
Rtot = = Rds + = Rds + Rch (7.127)
Ids W Cox µs (Vgs − Vt )

The total resistance is a function of Ldrawn .

So, if we take different devices that have iden-
tical specifications and were fabricated on the
same test chip, except for their Ldrawns , and
we suppose them to have Vds and Vgs constant
and equal in the two devices, we can plot the
measured Vds
Ids against Ldrawn (as shown in Fig-
ure 7.25).
We can observe that Vds
Ids is a linear function
of Ldrawn . The two straight lines intercept in
a common point where Vds
Ids is independent of
Vgs −Vt according to the equation 7.127, where
Figure 7.25: Method of extracting Rds and ∆L.
Ldrawn = ∆L and Vds
Ids = Rds . Once ∆L is
known, L can be calculated using Ldrawn .
Therefore from this graph we can extract both ∆L and Rds simultaneously. Detailed measure-
ments indicate that Rds tends to decrease with an increasing Vg . This is because the gate voltage
induces more (accumulation) electrons in the source–drain diffusion region and therefore reduces
Rds . It is also observed that ∆L decreases (or L increases) with increasing Vg .

209
8 Advanced MOSFET Concepts
In this chapter, we’ll discuss about difficulties encountered while trying to improve the perfor-
mance and scale the dimensions of the MOSFETs, such as Short Channel Effects and conse-
quently Vt roll-off, and how to mitigate their effects. Then we’ll proceed to analyze the advanced
MOSFET technologies, both planar and vertical, developed to have further improvements.

8.1 Short Channel Effects (SCE): Threshold voltage roll-off

While trying to reduce the physical dimensions of the MOSFET one key parameter subject to
change is the gate length LG and so also the channel length. The parameter mostly affected by
this change is the threshold voltage Vt which is found to decrease with decreasing Lg . This is
the most prominent manifestation of the so-called Short Channel Effects (SCE) that appear
when, as the name says, the channel becomes too short with decreasing LG , thus modifying the
normal behavior of the device and jeopardizing its functionality and performance.
It is really important to not let the Vt decrease too much and not set it too low, as Vt sets the
value of the Iof f , which is the leakage current we have when the transistor is turned off. Having
a too small Vt means having a very large Iof f , which must be avoided. In fact, for a given
supply voltage VDD the Iof f determines the parasitic power dissipation when the transistor is
in the off-state mode, a detrimental contribution to the total power consumption which must be
avoided or kept under strict control.
As a reminder the threshold voltage, Vt , (not to be confused with the thermal voltage Vth =kT /q)
has been derived in section 7.37 using a one-dimensional model. Accordingly, it has the following
expression: √
2εs qNA
(8.1)
p
Vt = VF B + 2ϕF + γ 2ϕB + VSB with γ =
Coxe
where there is no dependence of LG , but actually the threshold voltage is dependent both on LG
and the drain-source voltage VDS even if those parameters don’t appear explicitly in the formula.
This means that we can consider the threshold voltage as a function of those parameters and
then analyze it as Vt = f (Lg , Vds ) as can be seen in Figure 8.1.

Figure 8.1: Threshold voltage as a function of gate length and drain-source voltage.

210
We note that the Vt roll-off, so the variation of the threshold voltage, is much more apparent
when the Vds is large (curve in red). Also, the data is plotted against Lg instead of L because
the latter is difficult to measure, whereas Lg is actually a quantity that manufacturing engineers
can control directly.
In order to explain the Vt roll-off we look at the energy band diagram along the semiconductor-
insulator interface of a long channel device at both Vgs = 0 and Vgs = Vt . Curves are drawn at
Vds = 0 (in red) and high Vds =Vdd (in black).

Figure 8.2: Band diagram of a long-channel device.

At Vgs = 0 we can observe that the conduction band edge increases when moving from the N+
source and drain toward the P-type channel, and as expected, the transition develops over a
small distance compared to the channel length, so the central portion of the device has a flat
potential and we can neglect the source/drain edge effects. In these conditions, the 1-D model
describing carrier concentrations in the vertical direction developed to calculate the Vt expression
7.37 is valid.
At Vgs = Vt , the energy barrier between the source and channel which regulates how many
electrons can flow out of the source reservoir is pulled down. As Vgs increases, capacitive coupling
through the gate insulator increases the surface potential and decreases the EC in the channel.
Then, the energy barrier decreases for Vgs > 0, thus allowing the electrons with higher energy
to enter the channel and form the inversion layer. At the threshold, such as in this case, due to
the condition Vgs = Vt , the concentration is ns = NA .

211
 Figure 8.3: Band diagrams for long and short channel devices.

Let us now also consider the band diagram of a device with a shorter gate length but otherwise
identical structure, as depicted in Figure 8.3. We see that if Lg becomes small enough, the
transition regions where the barriers from the S/D to the channel build-up start to interact with
each other and cooperate in reducing the injection barrier from source to channel. Consequently,
for the same Vgs a larger concentration of electrons is achieved in the channel or, alternatively, a
lower Vgs suffices to reach the threshold condition ns =NA . This means that the Vt of the short
device is smaller than that of the long one; i.e. a Vt roll-off has affected the short channel device.
In other words, by lowering the barrier we also lowered the Vt .
As regards the Vds dependence, we see that the more we increase the drain-source voltage, the
more the transition region on the drain side expands toward the source, until it starts lowering
the source/channel barrier. This means that also a higher Vds can noticeably contribute to change
the injection barrier on the source side.
So, both the decreasing of Lg and the increasing of Vds cause a lowering of the source barrier
and of the Vt . The drain voltage dependence of Vt is obviously unpredictable by any pure
one-dimensional model of the MOS system electrostatics, since it is entirely due to the lateral
expansion of the drain depletion region toward the source. The consequent reduction of Vt is
called Drain Induced Barrier Lowering (DIBL), and it is a more relevant phenomenon
at short channel lengths. For long channel transistors, instead, avalanche multiplication at the
drain junction kicks-in well before DIBL can be appreciated.
We can visualize the DIBL as the shift of the threshold voltage shown in the following IV curve:

212
 Figure 8.4: Lowering of the threshold voltage with increasing drain-source voltage.

The threshold voltage roll-off for increasing Vds can be explained and modeled in terms of a
capacitive divider between the gate to channel capacitance, denominated as usual Coxe , and a
capacitance between the channel and the drain, denoted Cd in Figure 8.5. Those two capacitances
compete with each other to set the potential of the channel by using the drain-source voltage
Vds which helps Vgs to invert the surface.

Figure 8.5: Capacitances responsible of threshold voltage roll-off.

Based on the simple model above, we can express the threshold voltage with the following
simple equation, to be interpreted as a 1st order (linearized) model of a much more complex
two-dimensional spatial distribution of the electric field surrounding the junction:

Cd
Vt = Vt−long − VDS (8.2)
Coxe

where Vt−long denotes the Lg and Vds independent threshold voltage of a long channel device.
This equation, however, can be improved by reminding that the total reverse voltage drop across
the drain junction and the Cd is larger than Vds due to the built-in potential between the n-
channel and N + drain, which can be empirically estimated in the order of 0.4 V. A more accurate

213
expression of Vt including DIBL is then:

Cd
Vt = Vt−long − (VDS + 0.4) (8.3)
Coxe

From this equation, if we solve it using a 2-D Poisson equation we obtain a solution that shows
that Cd is actually an exponential function of the length L through a scaling factor Ld , thus
adding the missing length dependence and providing an expression containing both Vds and L
dependencies for the threshold voltage.
The final result then becomes:

− LL
with Ld = (8.4)
p
Vt = Vt−long − (VDS + 0.4)e d 3
Tox Wdep Xj

Note also that Ld , which expresses the distance scale by which the drain potential decays into the
channel is a function of the oxide thickness Tox , the depletion region width Wdep , and the junction
depth Xj . This means that if we want to shrink L without modifying Vt then we should change
also the Ld accordingly, so as to maintain constant the exponential term. We can achieve this
result by decreasing the oxide thickness Tox , decreasing Wdep (which means increasing the doping
NA ), and finally by making a thinner junction. In applying all these structural changes to the
transistor architecture, an appropriate balance should be implemented to preserve the device’s
functionality and performance. The key concept though is that the vertical dimensions must
be scaled together with the lateral dimensions to not modify too much the exponential
term of the equation, hence reducing the Vt roll-off.

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8.2 MOSFET scaling
The concept of MOSFET scaling was first introduced by R.Dennard as guidelines to develop
new technologies with smaller dimensions, in order to have smaller device, and lower supply
voltages, to have constant field scaling for constant reliability. This was in principle possible for
MOSFETs because I ∝ W
L which means that if we scale accordingly by the same quantity α both
W and L we’ll obtain the same current in the device as the bigger transistor, considering that the
only parameters we modify are the physical dimensions, which means that with a W ′ = W
α and
W′
L′ = L
α we’ll obtain that I′ ∝ L′ which means that I′ = I. Note also that not all technologies
are scalable in dimensions or supply voltage, but MOSFETs are.
So the key concept is scaling all physical dimensions and/or the supply voltage by some quantity
α, which is the scaling factor by which all physical dimensions are shrunk, and some λ which
is the voltage scaling factor. Initially we’ll assume that λ = α but we’ll see that some scaling
methods can actually have, λ ̸= α, so different scaling factors.

Figure 8.6: Representation of the initial MOSFET (left) and the scaled MOSFET (right).

While scaling the technology there are some important parameters that we need to take into
account apart from the current I, as with the scaling also those ones will change by some
proportionality factor, and those parameters are shown in the Figure 8.7.
During the scaling process there are some rules to follow for a different scenario we need at the
moment, these ones are divided in: Constant Field scenario, Constant Voltage scenario
and at last Mixed scenario.
We will now analyze separately every situation:

• Constant Field scenario: in this case we are scaling the voltage supply alongside the
physical dimensions by the same scaling factor. This is done in order to preserve the same
electric field in the device after scaling, thus making the device more stable and reliable.

• Constant Voltage scenario: this configuration is used when we don’t want to change the
whole power supply unit but only the component, thus scaling only the physical dimensions
of the device without changing the voltages and instead keeping them constant. In this

215
 case we’ll have less reliability of the device but also less costs as we don’t need to replace
the supply units.

• Mixed scenario: in this case we will scale both the physical dimensions and the supply
voltages but for a different quantity, in fact the physical dimensions will be scaled with a
scaling factor α while the voltages with λ and typically λ ̸= α as said earlier.

Figure 8.7: Scaling rules for every scenario discussed.

Let us now make some examples of calculating some different parameters for the Constant Field
scenario after the scaling process to see their change:
Capacitance C:

εox
C= W L then we scale by α so (8.5)
tox
εox W L
= tox which means that (8.6)
α
α α
1
C′ = C (8.7)
α
Doping NA :

r
2ε ′ Wdep
Wdep = ϕ then we scale by α so Wdep = (8.8)
qNA α
s
′ Wdep 2ε ϕ
Wdep = = so we need another α in the square root (8.9)
α qNA α
s
′ Wdep 2ε ϕ
Wdep = = ans so we obtain that the doping should change as (8.10)
α qNA α α
′
NA = αNA (8.11)

216
Current IDS :

W
IDS = µns Coxe (Vgs − Vt )Vds then we scale by α so (8.12)
L
W
′ (Vgs − Vt )Vds
IDS = Lα
µns αCoxe which means that (8.13)
α
α2
′ 1
IDS = IDS (8.14)
α
Power Area-Density (power dissipated per unit area) PAD :

VI
PAD = then we scale by α so (8.15)
WL
V I
′
PAD = α
W
α
L
which means that (8.16)
α α
′
PAD = PAD so scaling factor is 1 (8.17)

Switching delay τ :

CV
τ= then we scale by α so (8.18)
I
CV
τ′ = α α
I
which means that (8.19)
α
1
τ′ = τ (8.20)
α
Interconnect delay τID :

L
τID = RC with R = ρ so (8.21)
WH
L
=ρ C then we scale by α so (8.22)
WH
L
′ C 1
τID = ρ WαH note that C ′ = C so we have that (8.23)
α α
α α
′
τID = τID so scaling factor is 1 (8.24)

In fact, the interconnect delay between the transistors is a bottleneck for the whole device as it
remains constant with scaling, so we can reduce the Switching delay as much as we want but the
Interconnect delay will remain always the same, thus slowing down the whole device.
Other than scaling there are some more sophisticated processes to enhance the performance of
the devices, those processes are shown in Table 8.8.

217
 Figure 8.8: Technological development roadmap for semiconductors.

We can note from this table that the supply Vdd is reduced at each node to contain power con-
sumption in spite of rising transistor density and frequency, while Tox (EOT in the Figure 8.8)
is reduced to raise the current Ion and retain good transistor behaviors.

8.3 Mitigation of Short Channel Effects (SCE)

We will now discuss some strategies to contain the Short Channel Effects (SCE), the first of
which is Ground Plane MOSFET.
As we’ve seen previously one consequence of scaling the MOS transistor is the increasing doping
in the device, so the main idea to contain SCE here is to have a highly doped substrate and a
low doped surface at the interface grown by epitaxy.
This method has many advantages in fact, first of all, it limits the depletion region extension and
so we can control the maximum depth of the depletion layer Wdep (and in this case, it doesn’t
vary with VSB ).
It also decouples the threshold voltage Vt from the depletion layer width, as now we can control
it. At last, with this method we reduce the vertical field at the surface, thus increasing the
mobility at the surface (remember that the mobility decreases with high fields due to surface
roughness).
So the basic idea to mitigate the SCE is to create a non-uniform substrate doping, with a low
doping at the surface of depth yR , and a higher doping at the depth yd , as shown in Figure 8.9.

218
 Figure 8.9: Ground plane MOSFET structure.

So if we now consider the doping as a function of the depth we will see an abrupt change in doping
from the surface to the deep part of the substrate (which has a higher doping), represented as
an upward step in Figure 8.10.
This also means that, due to this non-uniform doping, the potential ϕ as a function of distance
doesn’t have anymore a quadratic behaviour and instead presents a linear decay, which means
that the electric field at the surface is constant.

Figure 8.10: Doping profile (left) and potential (right) as a function of depth (distance).

Due to the change in doping we also have that the depletion layer can expand up to the point
with the higher doping and then it stops, which means that it’s confined in the low-doping region
and Wdep,max = yR . This is the case of Retrograde Body Doping shown in the Figure 8.11.

Figure 8.11: Depletion layer depth for uniform and retrograde body doping.

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Halos or p-pockets
Another method to mitigate SCE is using Halos (also called P-Pockets) in the device. In a
normally designed MOS, there will typically be only a source and a drain. However, in a short-
channel MOSFET, there will be an interaction between the source and drain junction potential,
due to SCE, and to counteract this effect, we generate P-pockets/Halos by introducing a P +
region on the edges of the source and drain (with comparable doping to the ground plane).
These pockets are made through an ion implantation which is not done in a vertical direction
as usual but with a tilted direction of around θ ≈ 30-40°, and this is done before the gate
implantation, so they can penetrate more laterally and thus achieve the halo shape. Then this
process is repeated to form a pocket also in the other direction by rotating the wafer by 90° to
generate the other halo. The angle is chosen carefully to implant the pocket only where we want
it to be and the rest of the device is covered by the gate so it prevents the ions going everywhere
and/or in the channel.

Figure 8.12: MOSFET with halos around source and drain.

The introduction of the pockets with higher doping generates two junctions at the surface, leading
to a smaller depletion region and a faster and steeper decay of potential, thus preventing major
interactions between the source and the drain with short channel length, and this allows for even
more channel shrinkage without experiencing short-channel effects as they are reduced by the
halos as shown in the Figure 8.13.

Figure 8.13: Surface potential decay as a function of distance for different doping levels.

220
We can then discuss about threshold voltage Vt and how it’s affected by the introduction of halos,
as the SCE now are reduced. As shown in Figure 8.14 with halos/pockets added we have a more
stable and almost constant threshold voltage Vt for lower channel lengths (in green, ≈ 0.15µm)
as opposed to the device without halos (in red, ≈ 0.27µm) before it starts changing.

Figure 8.14: Threshold voltage with and without halos as a function of channel length.

We can also note from the graph that the threshold voltage for the shorter channels, before
decreasing, has also an increase until it reaches a maximum peak. This is due to the fact that
the doping has increased around the source and the drain because of the pockets and so with
shorter lengths there will be some overlap between the pockets.
The doping in the overlapping region becomes higher thus countering the interaction effects be-
tween the source and the drain, which sets a theoretical limit to the gate length, hence increasing
the threshold voltage. This increase is called Reverse Short Channel Effect, as it increases
the Vt instead of decreasing it. Eventually, as the channel length continues to shrink, the SCE
emerges again and brings down the Vt as it should be.

Figure 8.15: Overlap region between the pockets.

Due to the Reverse Short Channel Effect we can also engineer the threshold voltage to make it
as stable as possible to the fluctuations of the length L, by considering the maximum value of
Vt , which we denote as Vt,max , for the minimum value of the length that we can achieve through
lithography, which we denote Lmin .
By doing this we are taking the point in which the derivative is zero (because we are choosing

221
the maximum of the function) and if there are some fluctuations in the channel length those
won’t cause any major instability as we will be close to the maximum.

Figure 8.16: Threshold voltage as a function of channel length.

Reducing Gate-Insulator Thickness and Tunneling Leakage

Another way to contain SCE is to reduce the gate-insulator thickness denoted as tox which over
the years has been continuously reduced (from around 300 nm to 1.2 nm nowadays) because
it gives many important advantages to the device. First of all, reducing the thickness gives us
better control over the Vt roll-off, because having a higher gate capacitance means that the gate
has more control over the device and this is why it’s one of the strategies for mitigating SCEs.
It also increases the oxide capacitance Cox = εox
tox with thinner oxide thickness, which is respon-
sible for the current of the device Ion because Ion ∝ Coxe . However, we also must be careful in
increasing the capacitance as it’s also responsible for the delay τ = I,
C
so increasing it too much
may also slow down the device.
At last, we are reducing tox to reduce the Subthreshold Swing (SS) and make it more "ideal",
in fact by defining it as following
 
Cdep
SS = ln (10)Vth 1 + (8.25)
Coxe

we can observe that with a large Coxe the second term of the parenthesis will be more negligible
and the SS will become smaller overall.
There are however also some disadvantages if we thin down the oxide too much, the first of which
is the Breakdown effect due to the high field generated. In fact, long-term operation at high
field, especially at elevated chip operating temperatures, breaks the weaker chemical bonds at
the Si − SiO2 interface thus creating oxide charge and Vt shifts that cause circuit behaviors to
change and raise reliability issues.
Another big problem is the leakage current as with thin oxides there’s a higher tunneling prob-
ability which can generate a leakage current and so we won’t have zero current in the gate
anymore. This is because with a thin tox the electrons in the potential well, due to inversion,
are capable of tunneling and thus creating a current in the gate, which is an undesirable effect
because it interferes with the gate controlling the device but also degrades faster the whole device
(so provoking, also in this case, a reliability issue).

222
Considering the Figure 8.17 we can quantify the tunneling mechanism and the current generated
as follows:
R −tox
−2 K(x)dx
JG,tun = Ge 0 (8.26)
where G is a constant term and the function K(x) is defined as:
r
2m
K(x) = (Ec (x) − E) (8.27)
h̄

so the distance dependence comes from Ec (x) which is the conduction band function, while E is
the electron energy as can be also seen in Figure 8.17.

Figure 8.17: Representation of tunneling for thinner oxides.

So if we want to reduce the leakage current we need to reduce the tunneling probability, so we
need the integral to be large (because it’s at the exponent) by either making a thicker tox or by
making the energy difference (EC (x) − E) larger, thus decreasing the current density JG,tun .
The gate currents due to leakage reach quite high values as the length of the channel is reduced,
in fact as can be seen in Figure 8.18 reducing even by a small amount the length of the device
(shown by different colored curves) causes the current to increase by some orders of magnitude,
as every tick on the y axis, so gate current, correspond to one order of magnitude.

Figure 8.18: Gate current (leakage current) as a function of Gate voltage.

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8.4 Alternative gate dielectrics and High K materials
The conventional dielectric used in CMOS devices is SiO2 , which has excellent interface quality,
thus having a low level of interface states and few defects in the oxide (such as traps and charges).
Also, it has excellent control of the process, so we can manipulate it very well, such as thickness
control, uniformity on the wafer, and roughness of the material. At last, because of all these
qualities, it’s fully suitable for CMOS integration.
However, with the evolution of MOSFETs, we need to increase Cox = εox
tox by reducing the
thickness of the oxide, and so a limitation of such dielectric was discovered, in fact, it has many
major problems for very thin oxides (tox < 1.5 nm), such as Boron penetration in the P + gate,
and very high levels of tunneling currents, which causes consequently also reliability problems.
Therefore, because of these disadvantages at low thicknesses, the solution proposed was to use
some alternative gate dielectrics such as Oxynitride films and High K materials.

Oxynitride films

Oxynitrides are a class of alloys made of nitrogen, N , doped silicon dioxide, SiO2 , and their
general chemical formula is SiOx Ny and one of the most used is the Silicon Nitride, Si3 N4 .
The nitride alloy films were used because as the presence of nitrogen N increased in the alloy, it
also increased the dielectric constant of the material, as shown in Figure 8.19 below.

Figure 8.19: Dielectric constant as a function of nitrogen presence in the alloy.

In fact, if we consider for example Si3 N4 we have that, with respect to the SiO2 with εSiO2 = 3.9
its dielectric constant is much greater and is equal to εSi3 N4 = 7. However, by increasing the
dielectric constant, we have also reduced, in proportion to N presence, the band offset (measured
in eV ) and generated more traps due to the nitrogen.
In general, the use of oxynitrides has many advantages for the different concentrations of nitrogen
utilized, and we can differentiate between low N concentration and high N concentration.
At low nitrogen concentrations (so around N ≈ 1 %) we have an improvement in the reliability
of the devices.
At high concentrations of nitrogen instead, we achieve a reduction in Boron penetration in the
gate, and also a higher dielectric constant ε (also denoted frequently as K).

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However, the use of nitrogen in these films has also some non-negligible drawbacks.
In fact, it has almost no impact on boron penetration, and also, it generates some positive
charges in the oxide, thus degrading the interface properties and also the mobility of the carriers.
Other drawbacks regard also the band diagram, in fact, we have a large flat band shift, and
also a threshold shift. At last, we have a low reduction in the tunneling current, as introducing
nitrogen lowers the barrier of the oxide layer. In general, whatever the technique or material
we use, if we try to increase the dielectric constant, we will also receive a lowering in the oxide
barrier.

High K Materials

This is another class of materials that are utilized as alternative gate dielectrics in MOSFET
production. They are called "High-K" due to their elevated dielectric constant, in fact, K is
equivalent to εr in some states. The following Figure 8.20 represents a table of these materials,
their dielectric constant, band gap, and the conduction band offset.

Figure 8.20: Table of High-K materials used for MOSFETs.

Some of these materials are used more than others, for example, the highlighted ones, and this
is because some of them are stable on silicon, Si, while others are unstable. This means that
when we try to put some of these on the silicon, such as tantalum pentoxide, T a2 O5 , or titanium
dioxide, T iO2 , they can be incompatible or generate a lot of interface defects and traps, which
means that the mobility will be limited and the whole device will be somewhat slower.
So the key concept of High K materials is to reduce the tunneling by using an equivalent thickness
oxide, composed of the actual oxide thickness and the dielectric thickness, instead of the actual
physical thickness.
The High K material must satisfy the following properties in order to be an efficient solution:

• Have a barrier height of the same order of magnitude as Si, in fact, in most cases an
increase of εr induces also a band gap energy Eg lowering;

• Not be chemically active with Si or Poly-Si to avoid any formation of silicides;

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 • Have a deposition controlled at the atomic level, like the oxidation in Si, so we can have
better control over thickness, uniformity of the wafer, roughness, and avoid any parasitic
oxidation of the silicon;

• Should be compatible with CMOS integration, in general thermally stable, and in particular
compatible with the polysilicon gate process;

• Have a low level of defects, such as traps and fixed charges, in the volume and at the
surface, to keep good mobility and flat band;

• As last, have a good reliability.

Figure 8.21: MOSFET structure with High K materials.

The following Figure 8.21 shows the MOSFET structure while using High K materials, as we
can see here our insulator isn’t anymore the SiO2 but a stack of a thin layer of SiO2 and on
top of it a thicker layer of some High K material, due to this change the gate is made of metal
instead of polysilicon (the metal used is not aluminum, Al, maybe titanium nitrate, T iN ).
Regarding the thickness, we can introduce the concept of Equivalent Oxide Thickness, EOT,
which expresses the thickness of an SiO2 layer having the same capacitance as the actual gate-
stack capacitance, due to the series of CHK and CIT L . Therefore we can express the gate
capacitance, CG , as the series capacitance:

1 1 1 ε
= + with C = (8.28)
CG CIT L CHK t
tIT L tHK
= + divide and multiply by εox (8.29)
εIT L εHK
tIT L tHK εox 1
= + we take out the term (8.30)
εox εHK εox εox
 
1 εox
= tIT L + tHK (8.31)
εox εHK
EOT εox
= where EOT = tIT L + tHK (8.32)
εox εHK

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Note that EOT can’t be smaller than tIT L , in other terms we’ll always have that EOT ≥ tIT L .
Consider now applying these concepts to a practical case, in which we are going to use hafnium
oxide, Hf O2 , on top of the silicon oxide, SiO2 , then the band diagram becomes that of the
following Figure 8.22.

Figure 8.22: Band diagram of Hf O2 stacked on top of SiO2 .

As we can see by using the stacked Hf O2 on top of a thin layer of SiO2 we obtain that our
device has a smaller bandgap in the Hf O2 . Also, because the Hf O2 has a very thick layer our
device will have a reduced probability of tunneling for the same EOT . Note also that the Hf O2
has a far higher dielectric constant than that of the SiO2 , in fact, it’s εHf O2 ≈ 24, which is six
times greater than εSiO2 = 3.9.

Figure 8.23: Tunneling current J as a function of EOT .

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Figure 8.23 represents the effect of the High K material on the tunneling current J, for only the
SiO2 in blue, and for the stack of SiO2 with High K material in black.
As we can see, using the stack of the oxide with High K material stacked on top gives us very
good results, in fact, for a given EOT we’ll have a tunneling current that is smaller by many
orders of magnitude with respect to the one with only SiO2 utilized of the same thickness.
Note, however, that at some point the blue and the black curves will intercept if we reduce the
thickness enough, therefore we’ll need to find another solution to improve further the device.
At last, we can notice that the curve with High K material is steeper, and this means that for
a small EOT increase we’ll have a great decrease in current (but also a great increase, when
decreasing EOT , which is what we must be careful about).

8.5 Main issues in conventional Bulk MOSFET

The major problems that we come across in a scaling planar MOSFET are to control the short-
channel effect that requires a high doping level, but this degrades the mobility and variability of
the carriers. The strained silicon is a solution, but in general it’s not sufficient.
The International Technology Roadmap for Semiconductor, which occurred in 2005, states that
the problem of scaling planar bulk MOSFETs requires undesirably increasing high levels in order
to adequately control the short-channel effect and to set properly the threshold voltage.
In these years many solutions have been adopted to resolve the issues related to the MOSFET
but not all of them are solved yet. The main issues are:

• Thin SiO2 gate dielectric: it reduces the tunnel currents by thicker High-K materials
and a low-quality material reduces the mobility of carriers;

• Series Resistance: Gate, Source, and Drain could be made of Silicon material that gives
a typical high series resistance to the MOSFET circuit. Introducing silicidation technology
(which means silicon-containing material such as Germanium to the surface of the junction)
could reduce these resistances;

• Polysilicon Gate: The gate capacitance could be improved by introducing a metal-gate

junction. It is mandatory for High-K materials, but it will cause an increase of VF B ;

• Low Channel Mobility: It could be improved by using strained silicon (s − Si). It gives
better performance on short channels MOS;

• Doping fluctuation: The small number of dopants induce Vt , Ion and Iof f fluctuations.

8.6 Strained-Silicon technology

Strain represents the deformation of a crystal that changes the interatomic distances, hence the
band structure of a material. The strain is defined as:

∆L
ε= (8.33)
L

which quantifies how much the crystal has deformed.

The strain and its impacts are in general, anisotropic (whether it’s uniaxial or biaxial). The band

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structure modulation affects electrostatic and transport characteristics represented respectively
by the C-V and I-V curves. It also affects interfaces and thermal properties, with possible
consequences in reliability as well.
The tensile strain in the channel direction is beneficial to transport properties in Si NMOS, while
the compressive strain has benefits in Si PMOS. Strained Silicon could be obtained in both bulk
and SOI wafers with various fabrication techniques (global, i.e. wafer level; local, i.e. device
level). Local strain technologies have Lg and W dependent impacts.
The stress of the Silicon σ is measured in Pascal [P a], and it’s defined as the pressure applied
to deform the crystal. Remember that, the mobility is given by:

qτ
µ= (8.34)
mef f

where mef f introduces the concept of improving the mobility and this is possible by modulating
the effective mass of the crystal, which means changing its structure. The strain technology used
this idea.

Figure 8.24: Graph of Alloy material in Energy Gap/wavelength to Lattice constant.

In figure 8.24 we can see the relation between the energy gap (Eg [eV ]), or the wavelength of the
alloy/material expressed in µm, with the lattice constant of them expressed in Å.
We could see that silicon (Si) and germanium (Ge) have similar lattice constants (5.43 Å for Si
and about 5.65 Å for Ge) and an energy gap respectively over 1 or about 0.6 eV . This indicates
that they are completely miscible elements, also because both have diamond-shaped crystal so
they are compatible, they have a large mismatch, above 4%. If we consider an alloy of these two
materials and want to recover the lattice constant, we must consider the framework of elastic
theory where:

a0 (Si(1−y) Gey ) = a0 (y) = (1 − y)a0 (Si) + ya0 (Ge) = (1 − y)5.43 + y 5.658 Å (8.35)

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This equation describes a curve that connects the two points and the lattice constant is the result
of this, where y is the concentration of germanium referred to the concentration of the solution,
because y must be positive but <1.
Assume to place a strained Si(1−x) Gex over a relaxed Si(1−y) Gey with a lattice parameter a0 (y)
and interface in the x − y plane. The layer with different molar fractions grows very slowly to
create strained silicon and to limit the mismatches and prevent defects in the structure.

Figure 8.25: Layer of SiGe with an interface layer.

||
|| af −a0 (x)
Consider that af (x) = a0 (y), ε|| = a0 (x) and εxx = εyy = ε|| where εxy = 0. Then:
 
||
a (x) − a (x)
 
⊥ c12 (x) f 0 c12 (x)
af (x) = a0 (x) 1 − 2 = a0 (x) 1 − 2 ε (8.36)
c11 (x) ||
 
c11 (x) a0 (x)

a⊥
f − a0 (x) ε||
ε⊥ = =− (8.37)
a0 (x) ν

The parameter a0 indicates the distance between atoms in SiGe alloy. Thick relaxed layer, so
it’s not strained, and Si1−y Gey where y stays for its molar fraction, so y ∈ [0; 1].
f (x) has a different alloy of SiGe, so the distance will be different. In fact, it’ll be strained
The a⊥
and a⊥
f (x) > a0 , but this strain has a critical thickness and beyond this, the crystal will relax
again and create defects.
This idea is used in HBT (Heterojunction Bipolar Transistor) technology, but it has a limit where
the layer doesn’t relax and does not create defects.
af −a0
Film mismatch factor is given by f = a0 where af is the lattice constant of relaxed film
material and a0 is the lattice constant of the relaxed substrate. We have two limiting cases:

• Pseudomorphic (commensurate) growth:

Figure 8.26: Pseudomorphic growth.

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 The bandgap of strained SiGe has a smaller bandgap, which is contained on the silicon one,
this is called broken bandgap situation. The values of the valence band and the conduction
band of strained silicon are lower than the two bands of the relaxed silicon, this is also
called compressive strain because the SiGe is compressed. The electrons and the holes
in a steady state are collected in the strained SiGe valence and in its conduction band,
because they are at a lower level than in relaxed silicon, therefore we’ll have potential wells
generation.

• Fully strained:

Figure 8.27: Fully strained.

It’s the case where the valence band and the conduction band are misaligned with respect
to each other. The electrons and the holes in a steady state are collected in their respective
lower band. In this type of structure, the interface between the relaxed SiGe and Si
layer (shown in red) must be done carefully to not create defects or other problems in the
structure.

8.6.1 Issues with strained-SiGe technology

Some issues in strained-SiGe technology are non-negligible. When we adopt this technology to
develop a device we must take into account about:

• Critical thickness;

• Strain relaxation;

• Surface roughness;

• Diffusion of impurities;

• Diffusion of Ge in the sSi;

• Interface state generation due to Ge;

• Capacitance and self-heating.

A solution to some of these problems is Selective Epi Growth (SEG) in S/D. This technology
allows control of the parasitic series resistance of the ohmic junctions. The silicon is etched

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away, and in small devices, it creates uniaxial compression in the channel. In process flow, SiGe
is introduced at a late stage, to reduce the number of issues. There are different strains for
different types of MOSFET. In this section, we’ll illustrate two types of possible strains, which
are examples of uniaxial strains.

Figure 8.28: P-MOS SEG.

Figure 8.29: Linear strained layer.

The first type is a P-channel MOSFET, which uses compressive strain, and that has a SiGe
source and drain in which we will first etch away the silicon. Then we do the epitaxial growth
process of SiGe to create the crystal structure at the interface.
Because SiGe has a lattice constant larger than Si, to adapt to the silicon interface it will
compress towards the channel, therefore a compressive strain is induced (local to the device).
In Figure 8.29 we have individuated a "wall", and having a high "wall" allows us to reduce
parasitic S/D resistance as the current is more distributed, but we could have some extra parasitic
capacitance that we don’t want.

Figure 8.30: N-MOS Selective Epi-Growth.

Differently from what we have seen in the previous transistor, in an N-channel MOSFET we
have tensile strain instead, so we could change the source and drain material to obtain a similar
transistor, in fact, we substitute the SiGe with SiC which has a similar crystal structure and
band numbers but has a smaller lattice constant than Si.
Therefore in order to adapt to this material the Si is pulled towards the source and the drain,
hence causing a tensile strain.

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8.7 CESL concept
This is another technology that consists in depositing a strained layer that induces stress on the
substrate of silicon, without the need to use epitaxial growth, and we could use SiN (Silicon
Nitride) as the material in this case, which has an amorphous structure.
So what we do is deposit already strained SiN , so when we attach it to the Si substrate it will
try to return to its equilibrium position by applying a repulsive force, opposite to the one of the
strain applied. Therefore the substrate will be compressed toward the opposite direction of the
SiN strain and so we’ll create a tension zone in the middle.

Figure 8.31: Linear strained layer.

In MOSFET, we deposit it into the source and the drain over the gate edges, hence creating a
biaxial strain to develop a tension region.
Therefore as shown in Figure 8.32 we’ll have a change in angle during the strain, which will
cause the strain to occur in a biaxial mode, so in both lateral and vertical directions, but we
are interested more in the lateral strain. Because of both strains, there will be a tension zone
between the gate and the substrate.

Figure 8.32: Angular strained.

It is also important to consider that the stress of the Strained Silicon on the channel is not
uniform as a function of the length, for example, long-channel devices have a low level of stress
at the center of the channel, as shown in Figure 8.33, for the case of a long transistor with
Lg = 2 µm, and so not all of the channel will be strained uniformly if we consider long devices.
This affects the charge mobility, and therefore also the current due to its dependence on µ. The
same considerations apply to the compression case, where long channels are subjected to low
compressions, while shorter devices are more impacted by the stress applied.

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 Figure 8.33: CESL concept.

The impact on the mobility (µ) of the transistor changes with their gate length, in fact, with
the short channel we have a µ ≈ constant, while in long-channel transistors µ is a function of
length. The functions that describe the improvement of electron/hole mobility with the strain
are illustrated below in Figure 8.34, where the mobility enhancement for electrons is expressed
∆µ µstrain −µrelaxed
as µ = µrelaxed , so a difference between the case before and after the strain. For holes
µstrain
instead, it’s expressed as just µrelaxed and this is why the plot starts from a value equal to 1, so
relaxed case.

Figure 8.34: Impact of strain in channel mobility.

The image above shows that, at low strains (so at maximum 1% strain), the uniaxial strain is
effective because the improvement of the mobility can go up to 300 % for holes, and up to 60%
for electrons, which is quite good with small strains (max ≈ 1 %). Differently from the uniaxial
strain, the biaxial strain is not so effective because the curves for electrons and holes are rather
flat even with a whole 1 % strain.

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8.8 Fully Depleted MOSFETs
This is a technique used to improve control over SCE and DIBL, and it’s achieved by introducing
ultra-thin body substrates. Such a device will typically have a lightly doped channel and therefore
the threshold voltage will be controlled by the metal gate electrode’s work function.
The most critical challenge is to control the body thickness and planar bulk structures, and set
the metal gate electrode work function to its desired value. As a planar bulk MOSFET, it will
be highly challenging to reduce the parasitic series resistance to a tolerable value.

Figure 8.35: Bulk MOSFET and SOI MOSFET

In a classic bulk MOSFET, shown on the left, the source and the drain are not fully depleted and
so they have some parasitic capacitance between the source/drain and the bulk that contributes
to the load capacitance.
In FD-SOI transistors, shown on the right side, which are faster and have a lower QB , that is
equivalent to the depletion charge Qdep , we introduce into the bulk a thin layer of an insulator and
in this case the depletion is full, in fact, FD-SOI stands for Fully Depleted-Silicon On Insulator.
From the previous chapter
 we can remember that:
QB √
Vt = VF B + 2ϕF + − Cox , where QB ∝ NA , therefore because of low QB contribution we can
avoid doping the channel too much and by doing this we can increase the mobility of the carriers.
Also in this case, the source and the drain have the same parasitic capacitances but with a lower
value than in Bulk MOSFETs, so they charge much faster. At last, regarding the thickness of
the junction, we can note that it’s much smaller than in a traditional bulk MOSFET and it is
around 10-8 nm.

8.8.1 Ultra-Thin-Body SOI

Ultra-Thin-Body SOI, by reducing Tox , gives the gate excellent control of Si surface potential.
The problem is that the drain could still have more control than the gate along sub-surface
leakage current paths. Each of these devices are sensitive to high energy packets, in fact, when
some α or β particles, or γ rays hit the surface of a transistor they penetrate into the substrate
and interact with the atoms of the structure by generating electron-hole pairs, which generate
noise and could induce errors in bits, circuits, and memory.

235
 Figure 8.36: MOSFET without an insulator layer.

In UTB SOI Technology, an insulator layer is used to protect the substrate, so the electron-hole
pairs can’t hit the above part as in the previous case.
That’s because most of the generated pairs won’t go to the surface and they will be stopped by
the insulator, thus avoiding the noise.

Figure 8.37: MOSFET with an insulator layer.

The insulator layer is made of a silicon dioxide film (SiO2 ) and its thickness is less than 10 nm,
thus reducing the distance between the leakage path and the gate, in fact SOI are used to cut
out those leakage paths.
Due to the deeper junctions, we have reduced coupling in the depth of the substrate due to the
depletion capacitance, and therefore it will be closer to the interface, so the gate influence will
be strong there.

Figure 8.38: MOSFET leakage path.

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The subthreshold leakage current is reduced as the silicon film is made thinner, this is clearly
visible in the thermal graph below in Figure 8.39.

Figure 8.39: Leakage current graph.

Instead, in Figure 8.40 we are shown a comparison between leakage currents of two transistors
with different distances between the BOX, which is an acronym for the buried oxide in the
substrate, and the channel.

Figure 8.40: The BOX is pushed upward to reduce the leakage current.

237
As we can see on the left, the current of the channel is suppressed due to the depletion (shown in
green) but there is a large leakage current at the depth (shown in red) which indicates a strong
leakage path.
On the right, instead, we can see that if the BOX is pushed upward, therefore making thinner
the distance between the BOX and the channel, then we avoid major leakage currents, which
can be seen in the Figure due to the absence of red/orange zones that indicate strong leakage.

8.8.2 Producing Silicon-on-Insulator (SOI) Substrates

To produce an SOI substrate we can use wafer bonding technology. This procedure starts with
two different silicon wafers that we call for simplicity A and B. At the beginning we oxidize A,
to grow an SiO2 layer all around it. Then we proceed with an ion implantation of hydrogen
ions (H + ), which are very light atoms, above the wafer A. The implantation breaks the existing
bonds and creates bonds between silicon and hydrogen instead.
The implanted side of the wafer is rotated and gets in touch with the second wafer as shown
in Figure 8.41, and they are attached together with force, by pressing them together,which
damages the surface. Then a low-temperature annealing causes the two wafers to fuse together
permanently, and after that, we apply another annealing step to form H2 bubbles and split the
two wafers.
In fact, because of the damage the wafer A cracks and leaves behind a layer of oxide and active
silicon layer. So we have high-quality oxide (in red) and silicon (in green) but a damaged surface,
which then must be polished to become of good quality as well. At the end, we polish the surface
and then the SOI wafer is ready to be used, while the remaining wafer A can be reused in a new
process.

Figure 8.41: Production of Silicon-on-Insulator (SOI) Substrates.

238
Due to the high cost of SOI wafers, only some microprocessors have embraced this technology.
These devices compete, with other manufacturers, on speed and command high prices. In order
Lg
to benefit from the UTB concept, Silicon film thickness must be aggressively reduced to ∼ 4 .

Figure 8.42: Cross Section of SOI Circuits.

If we consider a fully depleted oxide layer, we can envision using the substrate as a second gate,
with the only precaution being that the substrate becomes a common gate for all transistors, as
depicted in Figure 8.42. The main advantage is the ability to control the drain current from two
different points (like an OR logic gate). However, the introduction of two gates brings about
several issues: the gate capacitance is doubled, and the second gate is unique for all transistors
on the chip. The primary limitation concerns the thickness of the oxide layer; if it’s too thick, it
will increase the threshold voltage according to:
p
2εq Na 2ϕf 1
Vt = Vf b + 2ϕF + with Cox ∝ (8.38)
Cox tox

The advantage of a double gate arises when both in-

version regions are active, allowing a double current
flow from the gate. To distinguish the second gate for
each transistor, various solutions can be considered.
One is shown in Figure 8.43, where the bottom gate
is inserted inside the substrate by etching it before
and then proceeding by growing the different layers
that make up the two gates/oxide and the channel
layer. However, the biggest challenge lies in align-
ing the two gates one over the other. Additionally,
this setup introduces a significant amount of para-
sitic capacitances. The first inversion layer creates
uncontrollable carriers with the substrate junction, Figure 8.43: Double Gate SOI or SON.
and the second inversion layer converts these
uncontrollable carriers into a second channel on the left and right sides, thus reducing the leakage
current. Therefore, the idea is to build the gate around the silicon to achieve a Gate-All-
Around or FINFET.

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8.9 Advantages of FD (SOI) MOSFET architectures
The main advantages of FD (SOI) MOSFETs architecture are the following:
• Improved electrostatics control: We obtain reduced Subthreshold Slope (SS), in fact,
FD SOI MOSFETs exhibit improved subthreshold characteristics, leading to lower off-state
leakage currents and better control over the device’s behavior in the subthreshold region;

• Enhanced Short Channel Effects (SCE) and DIBL Reduction: FD SOI MOSFETs
effectively mitigate short-channel effects, such as SCE and Drain-Induced Barrier Lowering
(DIBL), resulting in improved device performance and reliability at smaller technology
nodes;

• Reduced junction capacitance: The isolation provided by the insulating buried oxide
(BOX) layer in FD SOI reduces parasitic capacitances, including junction capacitance.
This contributes to faster switching speeds and improved overall circuit performance;

• Higher carrier mobility: Reduced vertical electric field in FD SOI MOSFETs leads to
higher carrier mobility, enhancing electron and hole transport properties. This contributes
to higher electron and hole velocities and, consequently, faster transistor operations;

• Vt control through back-bias voltage: FD SOI MOSFETs offer the ability to control
the threshold voltage through back-biasing. This provides flexibility in optimizing power,
performance, and leakage characteristics for different operational scenarios;

• Reduced random dopant fluctuation of the Vt : The thin silicon film in FD SOI
MOSFETs minimizes the impact of random dopant fluctuations, leading to improved con-
sistency and predictability in threshold voltage values, which is crucial for manufacturing
reliable devices;

• Increased radiation hardness: FD SOI MOSFETs demonstrate improved radiation

tolerance compared to bulk CMOS devices. The insulating BOX layer provides a natural
barrier that helps reduce the impact of ionizing radiation on the device, making it suitable
for space and high-radiation environments;

• Reduced Single-Event Upsets (SEU) in SRAM: FD SOI technology is known for

its robustness against single-event upsets in static random-access memory (SRAM) cells,
making it suitable for applications where radiation-induced errors need to be minimized;

• Elimination of latch-up: The absence of a substrate in FD SOI MOSFETs eliminates

latch-up, leading to a low-resistance path between the power supply rails. This enhances
the reliability of the devices in high-voltage and mixed-signal applications.

• Potential for low power operations: FD SOI MOSFETs allow for efficient power
management and low-power design due to their ability to control threshold voltage and
reduce leakage currents, making them suitable for battery-powered devices and energy-
efficient applications;
These advantages collectively make SOI MOSFETs a compelling choice for advanced semiconduc-
tor technologies, offering improved performance, reliability, and flexibility in various applications.

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8.10 Multi-gate Devices
A multi-gate device, multi-gate MOSFET or Multi Gate Field Effect Transistor (MuGFET),
refers to a metal–oxide–semiconductor field-effect transistor (MOSFET) that has more than one
gate on a single transistor.
Using more gates means that we have more carrier channels, this leads to a transformation of
all the leakage paths into the channel, first with 2 gates, then up to 4 in order to avoid lateral
leakage on the edges.
The multiple gates may be controlled by a single gate electrode, where the multiple gate surfaces
act electrically as a single gate, or by independent gate electrodes.
A multigate device employing independent gate electrodes is sometimes called a Multiple In-
dependent Gate Field Effect Transistor (MIGFET).
The most widely used multi-gate devices are the Fin Field Effect Transistor (FinFET) and
the Gate All Around Field Effect Transistor (GAAFET) , which are non-planar transistors,
or 3-D transistors. In particular, GAA devices have gates on all the 4 sides wrapped around,
this means we have 4 gates and this implies quadrupled current and capacitance. On the other
hand, FinFET has 3 gates, therefore, current and capacitance is tripled.

Figure 8.44: GAA and FinFET devices.

The main advantage of multi-gate devices is the control of SCE and DIBL which is achieved by
using ultra-thin body substrates and increasing the number of gates.

8.10.1 FinFET

As said before, a Fin Field Effect Transistor (FinFET) is a multi-gate device, a MOSFET
(Metal Oxide Semiconductor Field Effect Transistor) built on a substrate where the gate is placed
on two, three, or four sides of the channel or wrapped around the channel, forming a double or
even multi-gate structure. Usually, the channel consists of two vertical surfaces and the top
surface of the Fin, as shown in Figure 8.45.

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 Figure 8.45: FinFET device structure.

The curvature of the gate is called "Fin", this is the reason its called FinFET. The channel width
and length of the FinFET are respectively defined as

WF inF ET = 2hF in + WF in (8.39)

LF inF ET = Lg (8.40)

FinFETs are easy to fabricate, just by etching away the whole line instead of every single tran-
sistor thus making a long trench, in fact, Fins are fabricated throughout the whole wafer. The
only flaws are the discrete W values, which means that we have limited degrees of freedom, and
if we want larger currents then we need to have FinFETs in parallel, so we can increase W with
discrete steps matching a number of FinFETs used. To create a real multi-gate, it is possible to
grow the Fin’s Gate, then etch all the top parts, which wraps the Si, away in order to have two
separate gates G1 and G2 .
We saw two types of FinFET:
• SOI FinFET

• Bulk FinFET
In an SOI FinFET, a buried oxide (BOX) is used to suppress the leakage paths (see Figure 8.46).

Figure 8.46: SOI FinFET device structure.

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In a Bulk FinFET, instead, a Silicon oxide STI is placed at the bottom to stop leakage current
as shown in Figure 8.47.

Figure 8.47: Bulk FinFET device structure.

In both cases, the inversion layer is formed all around the Fin structure.
Talking about custom specification, there are three variations of FinFETs (see Figure 8.48):

• Tall FinFET: it has the advantage of providing a large W and therefore large Ion while
occupying a small footprint. This technology is very expensive and it is very difficult to
have uniform fields but it’s less sensitive to short channel effects (SCE), in fact, it has only
one short channel at the top of the device;

• Short FinFET: it has the advantage of less challenging lithography and etching. This
variation though, is sensitive to SCE because it is made from three channels, which are
all short so they are subjected to short channel effects. Short FinFET is also wider and
shorter in height than the tall one;

• Nanowire FinFET: it gives the gate even more control over the silicon wire by surround-
ing it. The gate wraps all around the silicon and suppresses almost all SCE, but it has a
limitation on the current carrying capability;

Figure 8.48: Variations of FinFET.

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The following Figures represent the I-V of a Nanowire multi-gate MOSFET.

Figure 8.49: Simulated I–V curves of a Nanowire MOSFET.

As shown in Figure 8.49, the subthreshold region is very linear and also there is no channel
length modulation. Overall, the Drain current is quite small even for a high Gate voltage.
This is due to the fact that, as said before, Nanowire FinFETs have limited current-carrying
capability, in fact, in a very thin nanowire, the carriers can move only in one direction out of the
three dimensions.
So, by limiting the possible direction of electrons to only one, it means that the carriers are
quantized and therefore can only move back and forth along that direction, which limits the
current carrying capability.

8.11 Device and Process Simulation

• Device Simulation: There are commercially available computer simulation tools that
solve all the equations presented in this notes with few or no approximations. Device simu-
lation provides quick feedback about device behavior and design before long and expensive
fabrication;

• Process Simulation: The input that a user provides to the process simulation program
are the lithography mask pattern, implantation dose and energy, temperatures and times
for oxide growth, and annealing steps.
The process simulator then generates a 2-D or 3-D structures with all the deposited or
grown and etched thin films and doped regions.
This output may be fed into a device simulator together with the applied voltages and the
operating temperature as the input to the device simulator.

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 Figure 8.50: Example of Process Simulation.

8.12 Future Innovations

• High mobility and wide bandgap semiconductor channel materials (GaAs,
GaN );

• Graphene channel FETs (GFETs): this technology is hard to use due to the leakage
currents, because graphene has an Eg = 0. This technology also uses a 2-D material (such
as M oS2 );

• Stacked nanosheet MOSFETs (3D structures);

• III-V vertical nanowire Tunnel FETs: in this technology, we obtain an SS < 60 mV

dec ,
which is below the theoretical limit. This is possible because we use tunneling instead of
emission by surpassing the barrier which is what sets the SS limit, at 60 mV ;

• Negative capacitance FETs: we exploit ferro-electrical materials to have SS < 60 mV

dec
and to fabricate transistors with defects due to these materials to exploit them for different
purposes (like neural fields).

Another important technological evolution is that of enhancing the performance of CMOS devices
beyond FinFETs, in fact, as we can see in Figure 8.51 there are some future implementations
such as nanosheets and forksheets.

Figure 8.51: CMOS implementations beyond FinFETs.

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• Nanosheets: in this case, we have sheets in parallel and stacked one on top of the other,
this solution has a high current and excellent SCE because it’s like a nanowire in behavior.
We slice the fin horizontally and then it’s done by alternating Si and SiGe, and then etching
away only one of them. At last, they oxidize it and pour the metal for the contacts.

• Forksheet: this solution is interesting because we can do NMOS and PMOS very close in
this case, and with a common gate for both types of transistors. This is done by connecting
the drains of N-type and P-type regions with a fork in between, so they are built together
but separated in the middle.

Figure 8.52: Process flow.

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References

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