Computer Engineering (CPE305)- Course notes [Jan-March 2023] CPE FUOYE

CPE305: Computer Engineering [DIGITAL ELECTRONICS] (3 Units)

Contents

1. Circuits
a. Basic circuits
i. Gates and Flip-flops
ii. Counters and Registers.
b. General requirements/ circuit parameters
i. Fan in, Fan out
ii. Gate delay, wire delay, Skew
iii. Logic Levels, Noise margin and Power dissipation
c. Circuit families
i. TTL: Transistor-Transistor Logic
ii. ECL: Emitter Coupled Logic
iii. CMOS: Complementary Metal Oxide Semi-conductor
iv. DTL: Diode Transistor Logic
v. I2L: Integrated Injection Logic
d. Special circuits
i. Pulse shaping
ii. Driving,
iii. Addressing
iv. Tuning – Delays, Strobing
v. Interconnection, Back winding, interfacing
vi. Peripheral equipment circuitry.
2. Reliability
a. Component selection
i. Sampled testing
ii. Mean Time Between Failure
b. Redundancy
i. Component level repetitive operation
ii. System level repetitive operation
c. Error detection and correction
i. Parity
ii. Grey codes
iii. Processing Errors
iv. Fail safe/soft.

Assessment
o Coursework: 40% : format to be decided- written test, term paper, group work etc
o Written Examination: 60% : 3hrs paper, Answer 5 of 7 questions

References
1. Roger L. Tokheim (1994): Schuam's outline of Theory and Problems of Digital Principles, McGrawHill
2. Tony R. Kuphaldt (2008): Introduction Lessons in Electric Circuits, Volume IV – Digital, Fourth Edition,
available freely from www.ibiblio.org/obp/electricCircuits [assessed February 2013].
3. Deepak K. Tala (2013): Tutorial on Digital Electronics, www.asic-world.com [assessed March 2013].

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1. RELATED BOOKS AVAILABLE IN FUOYE IKOLE ENGINEERING LIBRARY

A Textbook of Electronics Engineering J.B. Gupta 2015 2
Design for Electrical and Computer
Ralph M. Ford, 2
Engineers-Theory, Concepts and TA174.F66 2008
Chris S. Coulston
Practices
Digital Electronics-Principles &
Applications-Seventh Edition Roger Tokheim TK7868.D5 .T65

M. Senthil
Fundamentals of Digital Design 2014
Sivakumar
Amit Kumar
Basic Computer Engineering 2012
Mishra
Electronic Circuits Analysis and Design-
Donald A Neamen TK.7867N41 2008
Third Edition
M. Morris Mano,
Digital Design-Fourth Edition 2007
Michael D. Ciletti
An Introduction to Digital Computer V. Rajaraman, T. TK7888.3 .R32
Design-Fifth Edition Radhakrishnan 2009
Circuits, Devices and Systems-Fifth Ralph J. Smith,
1992
Edition Richard C. Dofr
Microelectronics Circuit Analysis and TK7867.N412
Donald A. Neamen 2
Design-Third Edition 2007
Introduction to Electronics A.I. Menkiti, et al TK7860.M46 2010
R. Ananda
Digital Design 2015
Natarajan
An Introduction to Semiconductor
Donald Neamen 2006
devices
Ian A. Glover, TK5103.7.G58
Digital communication-Second Edition 2
Peter M. Grant 2004
S. Salivahanan, S.
Digital Circuits and Design-Third Edition 2008
Arivazhagan

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2. Basic Digital Concepts

Digitization is the process of converting continuous analog signals into a finite number of discrete states to
the extent that the states are sufficiently well separated so that noise does create errors. Some information is
intrinsically digital, so it is natural to process and manipulate it using purely digital techniques. Examples
are numbers and words. The drawback to digitization is that a single analog signal (e.g. a voltage which is a
function of time, like a stereo signal) needs many discrete states, or bits, in order to give a satisfactory
reproduction. For example, it requires a minimum of 10 bits to determine a voltage at any given time to an
accuracy of ≈ 0.1%. For transmission, one now requires 10 lines instead of the one original analog line.

The explosion in digital techniques and technology has been made possible by the incredible increase in the
density of digital circuitry, its robust performance, its relatively low cost, and its speed. The requirement of
using many bits in reproduction is no longer an issue: The more the better. This circuitry is based upon the
transistor, which can be operated as a switch with two states. Hence, the digital information is intrinsically
binary. So in practice, the terms digital and binary are used interchangeably. In the following sections, we
summarize some conventions for defining the binary states and for doing binary arithmetic.

2.1 Binary Logic States

Table 2.1 attempts to make correspondences between conventions for defining binary logic states. In the
case of the TTL, Transistor-Transistor Logic, gates (to be discussed fully later), the Low voltage state is
roughly 0–1 Volt and the High state is roughly 2.5–5 Volts.

Table 2.1: Binary Logic states

Boolean Logic Boolean Algebra Voltage State Voltage State
(positive true) (negative true )
True (T) 1 High (H) Low (L)
False (F) 0 L H

The convention for naming these states is illustrated in Fig. 1. The “positive true” case is illustrated. The
relationship between the logic state and label (in this case “switch open”) at some point in the circuit can be
summarized with the following:

The labelled voltage is High (Low) when the label’s stated function is True (False).

In the figure, the stated function is certainly true (switch open), and this does correspond to a high voltage at
the labelled point. (Recall that with the switch open, Ohm’s Law implies that with zero current, the voltage
difference across the “pull up” resistor is zero, so that the labelled point is at +5 Volts. With a closed switch,
the labelled point is connected to ground, with a 5 Volt drop across the resistor and a current of I = V /R = 5
mA through it.)

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Figure 2.1: Illustration for labelling logic states (“positive true”).

With the convention known as “negative true”, the label would be changed to “switch closed” with a bar
over it: switch closed. Our statement becomes:
The labelled voltage is Low (High) when the label’s stated function is True (False).

So in the figure, the stated function (switch closed) is true when the voltage is low. The bar is meant to
invoke the Boolean inversion operation: T=F, F=T and T=T.

2.2 Binary Arithmetic

Each digit in binary is a 0 or a 1 and is called a bit, which is an abbreviation of binary digit. There are
several common conventions for representation of numbers in binary. The most familiar is unsigned binary.
An example of a 8-bit number in this case is

010011112 = 0 × 27 +1 × 26 + ··· +1 × 20 = 64+8+4+2+1 = 7910

Generally the subscripts will be omitted, since it will be clear from the context. To convert from base 10 to
binary, one can use a decomposition like above, or use the following algorithm illustrated by 79: 79/2 = 39,
remainder 1, then 39/2 = 19 r 1, and so forth. Then assemble all the remainders in reverse order. The largest
number which can be represented by n bits is 2n − 1. For example, with 4 bits the largest number is 11112 =
15. The most significant bit (MSB) is the bit representing the highest power of 2, and the LSB represents the
lowest power of 2.

Arithmetic with unsigned binary is analogous to decimal. For example 1-bit addition and multiplication are
as follows: 0 + 0 = 0, 0 + 1 = 1, 1 + 1 = 0, 0 × 0 = 0, 0 × 1 = 0, and 1 × 1 = 1. Note that this is different from
Boolean algebra, as we shall see later, where 1+1 = 1.

Another convention is called BCD (“binary coded decimal”) and is a type of weighted binary code. In this
case each decimal digit is separately converted to binary. Therefore, since 7 = 01112 and 9 = 10012, then 79
= 01111001 (BCD). Note that this is different than our previous result. BCD is quite often used in digital
electronics. It is quite convenient, for example, when decimal numerical displays are used. Weighted BCD
4-bit codes include 8421 BCD, 5421 BCD and 2421 BCD. Some binary codes are non-weighted. Each bit
therefore has no special weighting. Two such non-weighted codes are the excess-3 and Gray codes.

The excess-3 (XS3) code is related to the 8421 BCD code because of its binary-coded-decimal nature. In
other words, each 4-bit group in the XS3 code equals a specific decimal digit. Table 2.2 shows the XS3 code
along with its 8421 BCD and decimal equivalents. Note that the XS3 number is always 3 more than the 8421
BCD number. To convert from XS3 code to decimal, the XS3 number is divided into 4-bit groups starting at
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the binary point. 3 (binary 0011) is subtracted from each 4-bit group to give an 8421 BCD number results
which can be translated into its decimal equivalent. The XS3 code has significant value in arithmetic
circuits. The value of the code lies in its ease of complementing. If each bit is complemented (0s to 1s and
1s to 0s), the resulting 4-bit word will be the 9s complement of the number. Adders can use 9s complement
numbers to perform subtraction.

Table 2.2: The excess 3 (XS3) code

The Gray code is another non-weighted binary code. The Gray code is not a BCD-type code. Table 2.3
compares the Gray code with equivalent binary and decimal numbers. Look carefully at the Gray code. Note
that each increase in count (increment) is accompanied by only 1bit changing state. Look at the change from
the decimal 7 line to the decimal 8 line. In binary all four bits change state (from 0111 to 1000). In this same
line the Gray code has only the left bit changing state (0100 to 1100). This change of a single bit in the code
group per increment characteristic is important in some applications in digital electronics.

Table 2.3: The Gray Code

Consider converting a binary number to its Gray code equivalent. Figure 2.2 shows the binary number 0010
being translated into its Gray code equivalent. The rules for converting from any binary number to its
equivalent Gray code number are as follows:
1. The left bit is the same in the Gray code as in the binary number.
2. Add the MSB to the bit on its immediate right and record the sum (neglect any carry) below in the
Gray code line.
3. Continue adding bits to the bits on their right and recording sums until the LSB is reached.
4. The Gray code number will always have the same number of bits as the binary number.

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Figure 2.2: Binary to Gray code conversion

2.3 Representation of Negative Numbers

There are two commonly used conventions for representing negative numbers. With sign magnitude, the
MSB is used to flag a negative number. So for example with 4-bit numbers we would have 0011 = 3 and
1011 = −3. This is simple to see, but is not good for doing arithmetic. With 2’s complement, negative
numbers are designed so that the sum of a number and its 2’s complement is zero. To form 2’s complement,
make the transformation 0 → 1 and 1 → 0, then add 1. Using a 4-bit example again, we have 0101 = 5 and
its 2’s complement, −5 = 1011. Adding (remember to carry) gives 10000 = 0. (The 5th bit doesn’t count!)
Both addition and multiplication work as you would expect using 2’s complement.

2.4 Hexadecimal Representation and Alphanumeric codes

It is very often quite useful to represent blocks of 4 bits by a single digit. Thus in base 16 there is a
convention for using one digit for the numbers 0,1,2,.. .,15 which is called hexadecimal. It follows decimal
for 0–9, then uses letters A–F. Bits can also be coded to represent letters of the alphabet, numbers, and
punctuation marks. One such 7-bit code is the American Standard Code for Information Interchange (ASCII,
pronounced “ask-ee”), shown in Figure 2.3. Note that the letter A is represented by 1000001, whereas B in
the ASCII code is 1000010. The ASCII code is used extensively in small computer systems to translate
from the keyboard characters to computer language. The chart in Fig. 2.3 is not a complete list of all the
combinations in the ASCII code. Codes that can represent both letters and numbers are called alphanumeric
codes. Another alphanumeric code that is widely used is the Extended Binary-Coded Decimal Interchange
Code (EBCDIC, pronounced “eb-si-dik”). Part of the EBCDIC code is shown in Fig. 2.3. Note that the
EBCDIC code is an 8-bit code and therefore can have more variations and characters than the ASCII code
can have. The EBCDIC code is used in many larger computer systems. The alphanumeric ASCII code is the
modern code for getting information into and out of microcomputers. ASCII is used when interfacing
computer keyboards, printers, and video displays. ASCII has become the standard input/output code for
microcomputers. Other alphanumeric codes are:

1. 7-bit BCDIC ( Binary-Coded Decimal Interchange Code).

2. 8-bit EBCDIC (Extended Binary-Coded Decimal Interchange Code). Used on some IBM
equipment.
3. 7-bit Selectric. Used to control the spinning ball on IBM Selectric typewriters.
4. 12-bit Hollerith. Used on punched paper cards.

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Figure 2.3: Alphanumeric codes

2.5 Tutorial Questions

1. Convert the following 8421 BCD numbers to their decimal equivalents:
(a) 1010 (b) 00010111 (c) 10000110 (d) 010101000011 (e) 00110010.10010100
2. Convert the following decimal numbers to their 8421 BCD equivalents:
(a) 6 (b) 13 (c) 99.9 (d) 872.8 (e) 145.6 (f) 21.001
3. List three weighted BCD codes.
4. Convert the following decimal numbers to their XS3 code equivalents:
(a) 9 (b) 18 (c) 37 (d) 42
5. Convert the following 8421 BCD numbers to their XS3 code equivalents:
(a) 0001 (b) 0111 (c) 01100000 (d) 00101001 (e) 10000100
6. Convert the following XS3 numbers to their decimal equivalents:
(a) 0011 (b) 01100100 (c) 11001011 (d) 10011010 (e) 10000101
7. Convert the following straight binary numbers to their Gray code equivalents:
(a) 1010 (b) 10000 (c) 10001 (d) 10010 (e) 10011
8. Convert the following Gray code numbers to their straight binary equivalents:
(a) 0100 (b) 11111 (c) 10101 (d) 110011 (e) 011100
9. The following are abbreviations for what?
(a) ASCII (b) EBCDIC
10. Refer to Fig. 2.3. The ASCII keyboard-encoder output would be _______ if the K on the
typewriter-like keyboard were pressed.

Figure 2.4: ASCII Keyboard encoder system

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3. Logic Gates

The binary numeration system is an interesting mathematical abstraction has practical application to
electronics. What makes binary numeration so important to the application of digital electronics is the ease
in which bits may be represented in physical terms. Because a binary bit can only have one of two different
values, either 0 or 1, any physical medium capable of switching between two saturated states may be used to
represent a bit. Consequently, any physical system capable of representing binary bits is able to represent
numerical quantities, and potentially has the ability to manipulate those numbers. This is the basic concept
underlying digital computing.

Electronic circuits are physical systems that lend themselves well to the representation of binary numbers.
Transistors, when operated at their bias limits, may be in one of two different states: either cut-off (no
controlled current) or saturation (maximum controlled current). If a transistor circuit is designed to
maximize the probability of falling into either one of these states (and not operating in the linear, or active,
mode), it can serve as a physical representation of a binary bit. A voltage signal measured at the output of
such a circuit may also serve as a representation of a single bit, a low voltage representing a binary ”0” and a
(relatively) high voltage representing a binary ”1.” Note the transistor circuit in Fig. 3.1.

Figure 3.1: Transistor in saturation

In this circuit, the transistor is in a state of saturation by virtue of the applied input voltage (5 volts) through
the two-position switch. Because its saturated, the transistor drops very little voltage between collector and
emitter, resulting in an output voltage of (practically) 0 volts. If we were using this circuit to represent
binary bits, we would say that the input signal is a binary ”1” and that the output signal is a binary ”0.” Any
voltage close to full supply voltage (measured in reference to ground, of course) is considered a ”1” and a
lack of voltage is considered a ”0.” Alternative terms for these voltage levels are high (same as a binary ”1”)
and low (same as a binary ”0”). A general term for the representation of a binary bit by a circuit voltage is
logic level. Moving the switch to the other position, we apply a binary ”0” to the input and receive a binary
”1” at the output as shown in Fig. 3.2.

Figure 3.1: Transistor in cut-off

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What we’ve created here with a single transistor is a circuit generally known as a logic gate, or simply gate.
A gate is a special type of amplifier circuit designed to accept and generate voltage signals corresponding to
binary 1’s and 0’s. As such, gates are not intended to be used for amplifying analog signals (voltage signals
between 0 and full voltage). Used together, multiple gates may be applied to the task of binary number
storage (memory circuits) or manipulation (computing circuits), each gate’s output representing one bit of a
multi-bit binary number. The gate shown in Figures 3.1 & 3.2 with the single transistor is known as an
inverter, or NOT gate, because it outputs the exact opposite digital signal as what is input. For convenience,
gate circuits are generally represented by their own symbols rather than by their constituent transistors and
resistors.

3.1 The NOT gate

The NOT gate performs the basic logical function called inversion or complementation. NOT gate is also
called inverter. The purpose of this gate is to convert one logic level into the opposite logic level. It has one
input and one output. When a HIGH level is applied to an inverter, a LOW level appears on its output and
vice versa.

If X is the input, then output F can be represented mathematically as F = X', Here apostrophe (') denotes the
NOT (inversion) operation. There are a couple of other ways to represent inversion, F= !X, here ! represents
inversion. Truth table and NOT gate symbol is shown in the figure below.

Truth Table
X F= X'
0 1
1 0

NOT gate using "transistor-resistor" logic is shown in the figure below, where X is the input and F is the
output.

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When X = 1, The transistor input pin 1 is HIGH, this produces the forward bias across the emitter base
junction and so the transistor conducts. As the collector current flows, the voltage drop across RL increases
and hence F is LOW. When X = 0, the transistor input pin 2 is LOW: this produces no bias voltage across
the transistor base emitter junction. Thus, Voltage at F is HIGH.

The single-transistor inverter circuit illustrated In Fig. 3.1 is actually too crude to be of practical use as a
gate. Real inverter circuits contain more than one transistor to maximize voltage gain (so as to ensure that
the final output transistor is either in full cut-off or full saturation), and other components designed to reduce
the chance of accidental damage. Figure below shows a schematic diagram for a real inverter circuit,
complete with all necessary components for efficient and reliable operation. This circuit is composed
exclusively of resistors and bipolar transistors. Bear in mind that other circuit designs are capable of
performing the NOT gate function, including designs substituting field-effect transistors for bipolar.

Figure 3.3 A practical Inverter (NOT) circuit

Let’s analyze this circuit for the condition where the input is ”high,” or in a binary ”1” state. We can
simulate this by showing the input terminal connected to Vcc through a switch:

In this case, diode D1 will be reverse-biased, and therefore not conduct any current. In fact, the only purpose
for having D1 in the circuit is to prevent transistor damage in the case of a negative voltage being impressed
on the input (a voltage that is negative, rather than positive, with respect to ground). With no voltage
between the base and emitter of transistor Q1 , we would expect no current through it, either. However, as
strange as it may seem, transistor Q1 is not being used as is customary for a transistor. In reality , Q1 is being
used in this circuit as nothing more than a back-to-back pair of diodes. The following schematic shows the
real function of Q1:

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The purpose of these diodes is to ”steer” current to or away from the base of transistor Q2, depending on the
logic level of the input. Exactly how these two diodes are able to ”steer” current isn’t exactly obvious at first
inspection, so a short example may be necessary for understanding. Suppose we had the following
diode/resistor circuit, representing the base-emitter junctions of transistors Q2 and Q4 as single diodes,
stripping away all other portions of the circuit so that we can concentrate on the current ”steered” through
the two back-to-back diodes:

With the input switch in the ”up” position (connected to Vcc), it should be obvious that there will be no
current through the left steering diode of Q1, because there isn’t any voltage in the switch-diode-R1 switch
loop to motivate electrons to flow. However, there will be current through the right steering diode of Q1, as
well as through Q2’s base-emitter diode junction and Q4’s base-emitter diode junction:

This tells us that in the real gate circuit, transistors Q2 and Q4 will have base current, which will turn them
on to conduct collector current. The total voltage dropped between the base of Q1 (the node joining the two
back-to-back steering diodes) and ground will be about 2.1 volts, equal to the combined voltage drops of
three PN junctions: the right steering diode, Q2’s base-emitter diode, and Q4’s base-emitter diode.

Now, let’s move the input switch to the ”down” position and see what happens:

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If we were to measure current in this circuit, we would find that all of the current goes through the left
steering diode of Q1 and none of it through the right diode. Why is this? It still appears as though there is a
complete path for current through Q4’s diode, Q2 ’s diode, the right diode of the pair, and R1, so why will
there be no current through that path?

Remember that PN junction diodes are very nonlinear devices: they do not even begin to conduct current
until the forward voltage applied across them reaches a certain minimum quantity, approximately 0.7 volts
for silicon and 0.3 volts for germanium. And then when they begin to conduct current, they will not drop
substantially more than 0.7 volts. When the switch in this circuit is in the ”down” position, the left diode of
the steering diode pair is fully conducting, and so it drops about 0.7 volts across it and no more.

Recall that with the switch in the ”up” position (transistors Q2 and Q4 conducting), there was about 2.1 volts
dropped between those same two points (Q1’s base and ground), which also happens to be the minimum
voltage necessary to forward-bias three series-connected silicon PN junctions into a state of conduction. The
0.7 volts provided by the left diode’s forward voltage drop is simply insufficient to allow any electron flow
through the series string of the right diode, Q2’s diode, and the R3//Q4 diode parallel sub-circuit, and so no
electrons flow through that path. With no current through the bases of either transistor Q2 or Q4 , neither one
will be able to conduct collector current: transistors Q2 and Q4 will both be in a state of cut-off.
Consequently, this circuit configuration allows 100 percent switching of Q2 base current (and therefore
control over the rest of the gate circuit, including voltage at the output) by diversion of current through the
left steering diode.

In the case of our example gate circuit, the input is held ”high” by the switch (connected to Vcc), making the
left steering diode (zero voltage dropped across it). However, the right steering diode is conducting current
through the base of Q2, through resistor R1:

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With base current provided, transistor Q2 will be turned ”on.” More specifically, it will be saturated by
virtue of the more-than-adequate current allowed by R1 through the base. With Q2 saturated, resistor R3 will
be dropping enough voltage to forward-bias the base-emitter junction of transistor Q4, thus saturating it as
well:

With Q4 saturated, the output terminal will be almost directly shorted to ground, leaving the output terminal
at a voltage (in reference to ground) of almost 0volts, or a binary ”0” (”low”) logic level. Due to the
presence of diode D2, there will not be enough voltage between the base of Q3 and its emitter to turn it on, so
it remains in cut-off.

Let’s see now what happens if we reverse the input’s logic level to a binary ”0” by actuating the input
switch:

Now there will be current through the left steering diode of Q1 and no current through the right steering
diode. This eliminates current through the base of Q2, thus turning it off. With Q2 off, there is no longer a
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path for Q4 base current, so Q4 goes into cut-off as well. Q3, on the other hand, now has sufficient voltage
dropped between its base and ground to forward-bias its base-emitter junction and saturate it, thus raising
the output terminal voltage to a ”high” state. In actuality, the output voltage will be somewhere around 4
volts depending on the degree of saturation and any load current, but still high enough to be considered a
”high” (1) logic level. With this, our simulation of the inverter circuit is complete: a ”1” in gives a ”0” out,
and vice versa.

The astute observer will note that this inverter circuit’s input will assume a ”high” state of left floating (not
connected to either Vcc or ground). With the input terminal left unconnected, there will be no current through
the left steering diode of Q1, leaving all of R1’s current to go through Q2’s base, thus saturating Q2 and
driving the circuit output to a ”low” state:

The tendency for such a circuit to assume a high input state if left floating is one shared by all gate circuits
based on this type of design, known as Transistor-to-Transistor Logic, or TTL. This characteristic may be
taken advantage of in simplifying the design of a gate’s output circuitry, knowing that the outputs of gates
typically drive the inputs of other gates. If the input of a TTL gate circuit assumes a high state when floating,
then the output of any gate driving a TTL input need only provide a path to ground for a low state and be
floating for a high state. This concept may require further elaboration for full understanding, so it will be
explored in detail here.

A gate circuit as we have just analyzed has the ability to handle output current in two directions: in and out.
Technically, this is known as sourcing and sinking current, respectively. When the gate output is high, there
is continuity from the output terminal to Vcc through the top output transistor (Q3), allowing electrons to
flow from ground, through a load, into the gate’s output terminal, through the emitter of Q3, and eventually
up to the Vcc power terminal (positive side of the DC power supply):

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To simplify this concept, we may show the output of a gate circuit as being a double-throw switch, capable
of connecting the output terminal either to Vcc or ground, depending on its state. For a gate outputting a
”high” logic level, the combination of Q3 saturated and Q4 cut-off is analogous to a double-throw switch in
the ”Vcc” position, providing a path for current through a grounded load:

Please note that this two-position switch shown inside the gate symbol is representative of transistors Q3 and
Q4 alternately connecting the output terminal to Vcc or ground, not of the switch previously shown sending
an input signal to the gate! Conversely, when a gate circuit is outputting a ”low” logic level to a load, it is
analogous to the double-throw switch being set in the ”ground” position. Current will then be going the
other way if the load resistance connects to Vcc: from ground, through the emitter of Q4, out the output
terminal, through the load resistance, and back to Vcc. In this condition, the gate is said to be sinking current:

The combination of Q3 and Q4 working as a ”push-pull” transistor pair (otherwise known as a totem pole
output) has the ability to either source current (draw in current to Vcc ) or sink current (output current from
ground) to a load. However, a standard TTL gate input never needs current to be sourced, only sunk. That is,
since a TTL gate input naturally assumes a high state if left floating, any gate output driving a TTL input
need only sink current to provide a ”0” or ”low” input, and need not source current to provide a ”1” or a
”high” logic level at the input of the receiving gate:

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This means we have the option of simplifying the output stage of a gate circuit so as to eliminate Q3
altogether. The result is known as an open-collector output:

To designate open-collector output circuitry within a standard gate symbol, a special marker is used. Shown
here is the symbol for an inverter gate with open-collector output:

Please keep in mind that the ”high” default condition of a floating gate input is only true for TTL circuitry,
and not necessarily for other types, especially for logic gates constructed of field-effect transistors.

For simplification, we shall skip the internal details of other logic gates and focus more on their
functionalities. This is because in practice, such gates will be realised with the use of integrated circuits
(ICs). For each gate, it is important to know the symbol(s), truth table and Boolean expression. Truth tables
show all combinations of input conditions in terms of logic level states (either ”high” or ”low,” ”1” or ”0,”
for each input terminal of the gate), along with the corresponding output logic level, either ”high” or ”low".
The number of truth table rows needed for a gate is equal to 2 raised to the power of the number of input
terminals (2n).

3.2 The Buffer gate

If we were to connect two inverter gates together so that the output of one fed into the input of another, the
two inversion functions would ”cancel” each other out so that there would be no inversion from input to
final output:

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While this may seem like a pointless thing to do, it does have practical application. Remember that gate
circuits are signal amplifiers, regardless of what logic function they may perform. A weak signal source (one
that is not capable of sourcing or sinking very much current to a load) may be boosted by means of two
inverters like the pair shown in the previous illustration. The logic level is unchanged, but the full current-
sourcing or -sinking capabilities of the final inverter are available to drive a load resistance if needed. For
this purpose, a special logic gate called a buffer is manufactured to perform the same function as two
inverters. Its symbol is simply a triangle, with no inverting ”bubble” on the output terminal

Buffer or BUF is also a gate with the exception that it does not perform any logical operation on its input.
Buffers just pass input to output. Buffers are used to increase the drive strength or sometime just to
introduce delay. If X is the input, then output F can be represented mathematically as F = X. Truth table and
symbol of the Buffer gate is shown in the figure below.

Truth Table
X F= X
0 0
1 1
3.3 Multiple Input Gates
Given commutative and associative laws, many logic gates can be implemented with more than two inputs,
and for reasons of space in circuits, usually multiple input, complex gates are made. You will encounter such
gates in real world.

3.3.1 AND Gate

The AND gate performs logical multiplication, commonly known as AND function. The AND gate has two
or more inputs and single output. The output of AND gate is HIGH only when all its inputs are HIGH (i.e.
even if one input is LOW, Output will be LOW). If X and Y are two inputs, then output F can be represented
mathematically as

F = X.Y

Here dot (.) denotes the AND operation. Symbol of the AND gate is shown in the figure below followed by
its Truth table.

Truth Table
X Y F= X.Y
0 0 0
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0 1 0
1 0 0
1 1 1

Two input AND gate using "diode-resistor" logic circuit is shown in the figure below, where X, Y are inputs
and F is the output.

If X = 0 and Y = 0, then both diodes D1 and D2 are forward biased and thus both diodes conduct and pull F
low. If X = 0 and Y = 1, D2 is reverse biased, thus does not conduct. But D1 is forward biased, thus
conducts and thus pulls Flow. If X = 1 and Y = 0, D1 is reverse biased, thus does not conduct. But D2 is
forward biased, thus conducts and thus pulls Flow. If X = 1 and Y = 1, then both diodes D1 and D2 are
reverse biased and thus both the diodes are in cut-off and thus there is no drop in voltage at F. Thus F is
HIGH.

3.3.1.1 Switch Representation of AND Gate

In the figure below, X and Y are two switches which have been connected in series (or just cascaded) with
the load LED and source battery. When both switches are closed, current flows to LED.

3.3.1.2 Multiple Input AND gate

The AND gate can take 2 or more inputs. Here, the logic diagram and truth table of a three-input AND gate
is shown.

Truth Table
X Y Z F= X.Y.Z
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0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
3.3.2 OR Gate
The OR gate performs logical addition, commonly known as OR function. The OR gate has two or more
inputs and single output. The output of OR gate is HIGH only when any one of its inputs are HIGH (i.e.
even if one input is HIGH, Output will be HIGH). If X and Y are two inputs, then output F can be
represented mathematically as F = X+Y. Here plus sign (+) denotes the OR operation. Truth table and
symbol of the OR gate is shown in the figure below.

Truth Table
X Y F= X+Y
0 0 0
0 1 1
1 0 1
1 1 1

Two input OR gate using "diode-resistor" logic is shown in figure below, where X, Y are inputs and F is the
output.

If X = 0 and Y = 0, then both diodes D1 and D2 are reverse biased and thus both the diodes are in cut-off
and thus F is low. If X = 0 and Y = 1, D1 is reverse biased, thus does not conduct. But D2 is forward biased,
thus conducts and thus pulling F to HIGH. If X = 1 and Y = 0, D2 is reverse biased, thus does not conduct.
But D1 is forward biased, thus conducts and thus pulling F to HIGH. If X = 1 and Y = 1, then both diodes
D1 and D2 are forward biased and thus both the diodes conduct and thus F is HIGH.

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3.3.2.1 Switch Representation of OR Gate

In the figure below, X and Y are two switches which have been connected in parallel, and this is connected
in series with the load LED and source battery. When both switches are open, current does not flow to LED,
but when any switch is closed then current flows.

3.3.2.2 Multiple Input OR gate

The OR gate can also take 2 or more inputs. Here, the truth table of a three-input OR gate is shown.

Truth Table
X Y Z F= X+Y+Z
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
3.3.3 NAND Gate
NAND gate is a cascade of AND gate and NOT gate, as shown in the figure below. It has two or more
inputs and only one output. The output of NAND gate is HIGH when any one of its input is LOW (i.e. even
if one input is LOW, Output will be HIGH).

If X and Y are two inputs, then output F can be represented mathematically as F = (X.Y)', Here dot (.)
denotes the AND operation and (') denotes inversion. Truth table and symbol of the NAND gate is shown in
the figure below.

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Truth Table
X Y F= (X.Y)'
0 0 1
0 1 1
1 0 1
1 1 0
3.3.4 NOR Gate
NOR gate is a cascade of OR gate and NOT gate, as shown in the figure below. It has two or more inputs
and only one output. The output of NOR gate is HIGH when any all its inputs are LOW (i.e. even if one
input is HIGH, output will be LOW).

If X and Y are two inputs, then output F can be represented mathematically as F = (X+Y)'; here plus (+)
denotes the OR operation and (') denotes inversion. Truth table of the NOR gate is shown below.

Truth Table
X Y F= (X+Y)'
0 0 1
0 1 0
1 0 0
1 1 0
3.3.5 XOR Gate
An Exclusive-OR (XOR) gate is gate with two or three or more inputs and one output. The output of a two-
input XOR gate assumes a HIGH state if one and only one input assumes a HIGH state. This is equivalent to
saying that the output is HIGH if either input X or input Y is HIGH exclusively, and LOW when both are 1
or 0 simultaneously. If X and Y are two inputs, then output F can be represented mathematically as F = X Y.
Here denotes the XOR operation. This is equivalent to X.Y' + X'.Y. Truth table and symbol of the XOR
gate is shown in the figure below.

XOR From Simple gates

XOR logic Symbol

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Truth Table
X Y F= X+Y
0 0 0
0 1 1
1 0 1
1 1 0
3.3.6 XNOR Gate
An Exclusive-NOR (XNOR) gate is gate with two or three or more inputs and one output. The output of a
two-input XNOR gate assumes a HIGH state if all the inputs assumes same state. This is equivalent to
saying that the output is HIGH if both input X and input Y is HIGH exclusively or same as input X and
input Y is LOW exclusively, and LOW when both are not same. If X and Y are two inputs, then output F
can be represented mathematically as F = (X Y)' which denotes the XNOR operation. (X Y)' and is
equivalent to X.Y + X'.Y'. Truth table and symbol of the XNOR gate is shown in the figure below.

Truth Table
X Y F= (X Y)'
0 0 1
0 1 0
1 0 0
1 1 1
3.4 Universal Gates
Universal gates are the ones which can be used for implementing any gate like AND, OR and NOT, or any
combination of these basic gates; NAND and NOR gates are universal gates. But there are some rules that
need to be followed when implementing NAND or NOR based gates. To facilitate the conversion to NAND
and NOR logic, we have two new logic symbols for these gates.

NOR Gate

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3.4.1 NAND AS UNIVERSAL GATES

3.4.1.1 Realization of Logic Function Using NAND Gates
Any logic function can be implemented using NAND gates. To achieve this, first the logic function has to be
written in Sum of Product (SOP) form. Once logic function is converted to SOP, then is very easy to
implement using NAND gate. In other words any logic circuit with AND gates in first level and OR gates in
second level can be converted into a NAND-NAND gate circuit. Consider the following SOP expression:

F = W.X.Y + X.Y.Z + Y.Z.W

The above expression can be implemented with three AND gates in first stage and one OR gate in second
stage as shown in figure below.

If bubbles are introduced at AND gates output and OR gates inputs (the same for NOR gates), the above
circuit becomes as shown in figure.

Now replace OR gate with input bubble with the NAND gate. Now we have circuit which is fully
implemented with just NAND gates.

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3.4.1.2 Realization of Logic Gates Using NAND Gates

3.4.1.2.1 Implementing an inverter using NAND gate
Input Output Rule: (X.X)' = X' [Idempotent]

3.4.1.2.2 Implementing AND using NAND gates

Input Output Rule: ((XY)'(XY)')' = ((XY)')' [Idempotent]= (XY) [Involution]

3.4.1.2.3 Implementing OR using NAND gates

Input Output Rule: ((XX)'(YY)')' = (X'Y')' [Idempotent]= X''+Y'' [DeMorgan]= X+Y [Involution]

3.4.1.2.4 Implementing NOR using NAND gates

Input Output Rule: ((XX)'(YY)')' =(X'Y')' [Idempotent]= (X+Y)' [DeMorgan]

3.4.2 NOR AS UNIVERSAL GATES

3.4.2.1 Realization of Logic Function Using NOR Gates
Any logic function can be implemented using NOR gates. To achieve this, first the logic function has to be
written in Product of Sum (POS) form. Once it is converted to POS, then it's very easy to implement using

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NOR gate. In other words any logic circuit with OR gates in first level and AND gates in second level can
be converted into a NOR-NOR gate circuit. Consider the following POS expression: F = (X+Y) . (Y+Z).
This expression can be implemented with three OR gates in first stage and one AND gate in second stage as
shown in figure below

If bubble are introduced at the output of the OR gates and the inputs of AND gate, the above circuit becomes
as shown in figure below.

Now replace AND gate with input bubble with the NOR gate. Now we have circuit which is fully
implemented with just NOR gates.

3.4.2.2 Realization of Logic Gates Using NOR Gates

3.4.2.2.1 Implementing an inverter using NOR gate
Input Output Rule: (X+X)' = X' [Idempotent]

3.4.2.2.2 Implementing AND using NOR gates

Input Output Rule: ((X+X)'+(Y+Y)')'= (X'+Y')'[Idempotent]= X''.Y''[DeMorgan]= (X.Y)[Involution]

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3.4.2.2.3 Implementing OR using NOR gates

Input Output Rule: ((X+Y)'+(X+Y)')' = ((X+Y)')' [Idempotent]= X+Y Involution

3.4.2.2.4 Implementing NAND using NOR gates

Rule: ((X+Y)'+(X+Y)')'= ((X+Y)')'[Idempotent]= X+Y[Involution]= (X+Y)'[Idempotent]

Tutorial Questions
A. From Section 2
1. Discuss the concept of Digitization. What are its advantages and disadvantages?
2. Explain briefly how the following conventions are used to represent unsigned numbers on Computer
systems. a) Binary Coded Decimal b) Excess 3 c) Gray codes
3. Elucidate on the ways in which signed numbers can be represented on a Computer system.
4. Differentiate between ASCII and EBCDIC alpha-numeric codes for representing alphabet, numbers,
punctuation marks and other special characters in binary.

B. From Section 3
1. If a transistor circuit is designed to maximize the probability of falling into either one of cut-off or
saturated states (and not operating in the linear or active mode), it can serve as a physical representation of
binary digits essential to digital Computer system design. Discuss.
2. Show a schematic diagram for a real inverter circuit, complete with all necessary components for efficient
and reliable operation and explain how it works.
3. With the aid of the electronic circuits (transistor, diodes and resistors), ladder logic (switches), logic
symbol/ diagram, boolean algebra and truth table, explain the functions of the following gates:
a) NOT b) AND c) OR d) NAND e) NOR f) XOR

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4. The NAND and NOR are universal gates. Discuss this statement with suitable examples of converting the
three basic logic symbols (NOT, AND, and OR) to these universal gates.

4. Simplification of Boolean Functions

4.1 Introduction
Simplification of Boolean functions is mainly used to reduce the gate count of a design. Less number of
gates means less power consumption, sometimes the circuit works faster and also when number of gates is
reduced, cost also comes down. There are many ways to simplify a logic design, some of them are given
below. We will be looking at each of these in detail in the next few pages.

➢ Algebraic Simplification: Simplify symbolically using theorems/postulates. This requires good

knowledge of Boolean algebra
➢ Karnaugh Maps: Diagrammatic technique using 'Venn-like diagram'. Limited to no more than 6
variables.

4.2 Algebraic Simplification

4.2.1 Symbolic Logic
Boolean algebra derives its name from the mathematician George Boole. Symbolic Logic uses values,
variables and operations :
➢ True is represented by the value 1.
➢ False is represented by the value 0.
Variables are represented by letters and can have one of two values, either 0 or 1. Operations are functions
of one or more variables.
➢ AND is represented by X.Y
➢ OR is represented by X + Y
➢ NOT is represented by X' which will be used mostly in this course note.
These basic operations can be combined to give expressions such as W.X'.Y + Z

4.2.2 Precedence
As with any other branch of mathematics, these operators have an order of precedence. NOT operations
have the highest precedence, followed by AND operations, followed by OR operations. Brackets can be
used as with other forms of algebra. E.g. X.Y + Z and X.(Y + Z) are different.
4.2.3 Boolean Algebraic Axioms and Theories
Identity Law
an identity 0 for + such that X + 0 = X
an identity 1 for . such that X . 1 = X
Commutative Laws
X+Y=Y+X X.Y=Y.X
Distributive Laws
X.(Y + Z ) = X.Y + X.Z X + Y.Z = (X + Y) . (X + Z)
Complement
X + X' = 1 X . X' = 0
Idempotent Law
X+X=X X.X=X
DeMorgan's Law
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(X + Y)' = X' . Y' (X.Y) = X' + Y'

Note : DeMorgans Laws are applicable for any number of variables.
Boundedness Law
X+1=1 X.0=0
Absorption Law
X + (X . Y) = X X . (X + Y ) = X
Elimination Law
X + (X' . Y) = X + Y X.(X' + Y) = X.Y
Unique Complement theorem
If X + Y = 1 and X.Y = 0 then X = Y'
Involution theorem
X'' = X
Associative Properties
X + (Y + Z) = (X + Y) + Z X.(Y.Z)=(X.Y).Z
Duality Principle
In Boolean algebras, the duality Principle can be is obtained by interchanging AND and OR operators and
replacing 0's by 1's and 1's by 0's. Compare the identities on the left side with the identities on the right.
Example: X.Y+Z' = (X'+Y').Z
Consensus theorem
X.Y + X'.Z + Y.Z = X.Y + X'.Z
or dual form as (X + Y).(X' + Z).(Y + Z) = (X + Y).(X' + Z)
The term which is left out is called the consensus term. Given a pair of terms for which a variable appears in
one term, and its complement in the other, then the consensus term is formed by ANDing the original terms
together, leaving out the selected variable and its complement.
Example: The consensus of X.Y and X'.Z is Y.Z;
The consensus of X.Y.Z and Y'.Z'.W' is (X.Z).(Z.W')
Simplification theorems
XY + XY' = X (uniting) (X + Y)(X + Y') = X
X + XY = X (absorption) X(X + Y) = X
(X + Y')Y = XY (adsorption) XY' + Y = X + Y
4.2.4 Algebraic Manipulation
4.2.4.1 Minterms and Maxterms
Any boolean expression may be expressed in terms of either minterms or maxterms. To do this we must first
define the concept of a literal. A literal is a single variable within a term which may or may not be
complemented. For an expression with N variables, minterms and maxterms are defined as follows:
A minterm is the product of N distinct literals where each literal occurs exactly once.
A maxterm is the sum of N distinct literals where each literal occurs exactly once.
For two-variable and three-variable expressions , the minterms and maxterms are as follows
X Y Z MinTerm MaxTerm
X Y MinTerm MaxTerm 0 0 0 X'.Y'.Z' X+Y+Z
0 0 X'.Y' X+Y 0 0 1 X'.Y'.Z X+Y+Z'
0 1 X'.Y X+Y' 0 1 0 X'.Y.Z' X+Y'+Z
1 0 X.Y' X'+Y 0 1 1 X'.Y.Z X+Y'+Z'
1 1 X.Y X'+Y' 1 0 0 X.Y'.Z' X'+Y+Z
1 0 1 X.Y'.Z X'+Y+Z'
1 1 0 X.Y.Z' X'+Y'+Z
1 126 1 X.Y.Z X'+Y'+Z'
 Computer Engineering (CPE305)- Course notes [Jan-March 2023] CPE FUOYE

This allows us to represent expressions in either Sum of Products or Product of Sums forms
4.2.4.2 Sum Of Products (SOP)
The Sum of Products form represents an expression as a sum of minterms.
F(X, Y, ...) = Sum (ak.mk) where ak is 0 or 1 and mk is a minterm.
To derive the Sum of Products form from a truth table, OR together all of the minterms which give a value
of 1.
Example: SOP
Consider the truth table
X Y F MinTerm
0 0 0 X'.Y'
0 1 0 X'.Y
1 0 1 X.Y'
1 1 1 X.Y
Here SOP is f(X.Y) = X.Y' + X.Y

4.2.4.3 Product Of Sum (POS)

The Product of Sums form represents an expression as a product of maxterms.
F(X, Y, .......) = Product (bk+ Mk), where bk is 0 or 1 and Mk is a maxterm.
To derive the Product of Sums form from a truth table, AND together all of the maxterms which give a
value of 0.
Example: POS
Consider the truth table from the previous example.
X Y F MaxTerm
0 0 1 X+Y
0 1 0 X+Y'
1 0 1 X'+Y
1 1 1 X'+Y'
Here POS is F(X,Y) = (X+Y')
4.2.4.3 Conversion between POS and SOP
Conversion between the two forms is done by application of DeMorgans Laws.
4.2.5 Simplification
As with any other form of algebra you have encountered, simplification of expressions can be performed
with Boolean algebra.
Example 1
Simplify X.Y.Z' + X'.Y.Z' + Y.Z
X.Y.Z' + X'.Y.Z' + Y.Z = Y.Z' (X+X')+ Y.Z = Y(Z'+Z)= Y [Recall X+X'=Z+Z'=1]
Example 2
Simplify (X.Y' + Z).(X + Y).Z = X.Z + Y.Z
(X.Y' + Z).(X + Y).Z
=(X.X.Y'+X.Y'.Y+Z.X+Y.Z).Z [Recall X.X=X, Y'.Y=0]
= (X.Y' + Z.X + Y.Z).Z
= X.Y'.Z + Z.X + Y.Z [Z.Z=Z]
= Z.(X.Y' + X + Y) [XY'+X= X(Y'+1)= X]
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= Z.(X+Y)= X.Z+ Y.Z

4.3 Karnaugh Maps (k-maps)

Karnaugh maps provide a systematic method to obtain simplified sum-of-products (SOPs) Boolean
expressions. This is a compact way of representing a truth table and is a technique that is used to simplify
logic expressions. It is ideally suited for four or less variables, becoming cumbersome for five or more
variables. Each square represents either a minterm or maxterm. A K-map of n variables will have 2n squares.
For a Boolean expression, product terms are denoted by 1's, while sum terms are denoted by 0's - but 0's are
often left blank.

A K-map consists of a grid of squares, each square representing one canonical minterm combination of the
variables or their inverse. The map is arranged so that squares representing minterms which differ by only
one variable are adjacent both vertically and horizontally. Therefore XY'Z' would be adjacent to X'Y'Z' and
would also adjacent to XY'Z and XYZ'.

4.3.1 Minimization Technique

This is based on the Unifying Theorem: X + X' = 1. The expression to be minimized should generally be in
sum-of-product form (If necessary, the conversion process is applied to create the sum-of-product form).
The function is mapped onto the K-map by marking a 1 in those squares corresponding to the terms in the
expression to be simplified (The other squares may be filled with 0's). Pairs of 1's on the map which are
adjacent are combined using the theorem Y(X+X') = Y where Y is any Boolean expression (If two pairs are
also adjacent, then these can also be combined using the same theorem). The minimization procedure
consists of recognizing those pairs and multiple pairs. These are circled indicating reduced terms. Groups
which can be circled are those which have two (21) 1's, four (22) 1's, eight (23) 1's, and so on. Note that
because squares on one edge of the map are considered adjacent to those on the opposite edge, group can be
formed with these squares. Groups are allowed to overlap.

The objective is to cover all the 1's on the map in the fewest number of groups and to create the largest
groups to do this. Once all possible groups have been formed, the corresponding terms are identified. A
group of two 1's eliminates one variable from the original minterm. A group of four 1's eliminates two
variables from the original minterm. A group of eight 1's eliminates three variables from the original
minterm, and so on. The variables eliminated are those which are different in the original minterms of the
group.

4.3.2 2-Variable K-Map

In any K-Map, each square represents a minterm. Adjacent squares always differ by just one literal (So that
the unifying theorem may apply: X + X' = 1). For the 2-variable case (e.g.: variables X, Y), the map can be
drawn as below. Two variable map is the one which has got only two variables as input.

4.3.3 Equivalent labelling

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K-map needs not follow the ordering as shown in the figure above. What this means is that we can change
the position of m0, m1, m2, m3 of the above figure as shown in the two figures below. Position assignment
is the same as the default k-maps positions. This is the one which we will be using throughout this course
notes. The K-map for a function is specified by putting a '1' in the square corresponding to a minterm, a '0'
otherwise.

4.3.4 Example- Carry and Sum of a half adder

In this example we have the truth table as input, and we have two output functions. Generally we may have
n output functions for m input variables. Since we have two output functions, we need to draw two k-maps
(i.e. one for each function). Truth table and k-map of 1 bit half-adder (with Carry and Sum) is shown below.

X Y SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

4.3.5 Grouping/Circling K-maps

The power of K-maps is in minimizing the terms, K-maps can be minimized with the help of grouping the
terms to form single terms. When forming groups of squares, observe/consider the following:
➢ Every square containing 1 must be considered at least once.
➢ A square containing 1 can be included in as many groups as desired.
➢ A group must be as large as possible.

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If a square containing 1 cannot be placed in a group, then leave it out to include in final expression. The
number of squares in a group must be equal to 2 , i.e. 2,4,8 etc. The map is considered to be folded or
spherical, therefore squares at the end of a row or column are treated as adjacent squares. The simplified
logic expression obtained from a K-map is not always unique. Groupings can be made in different ways.
Before drawing a K-map the logic expression must be in canonical form.

Example of invalid groups

4.3.5.1 Example - X'Y+XY

In this example we have the equation as input, and we have one output function. Draw the k-map for
function F with marking 1 for X'Y and XY position. Now combine two 1's as shown in figure to form the
single term. As you can see X and X' get cancelled and only Y remains.

F=Y

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4.3.5.2 Example - X'Y+XY+XY'

In this example we have the equation as input, and we have one output function. Draw the k-map for
function F with marking 1 for X'Y, XY and XY position. Now combine two 1's as shown in figure to form
the two single terms.

F=X+Y

4.3.6 3-Variable K-Map

There are 8 minterms for 3 variables (X, Y, Z). Therefore, there are 8 cells in a 3-variable K-map. One
important thing to note is that K-maps follow the gray code sequence, not the binary one.

Using gray code arrangement ensures that minterms of adjacent cells differ by only ONE literal. (Other
arrangements which satisfy this criterion may also be used). Each cell in a 3-variable K-map has 3 adjacent
neighbours. In general, each cell in an n-variable K-map has n adjacent neighbours.

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There are wrap-a-rounds in the K-map:

➢ X'Y'Z' (m0) is adjacent to X'YZ' (m2)
➢ XY'Z' (m4) is adjacent to XYZ' (m6)

4.3.6.1 Example
F = XYZ'+XYZ+X'YZ

F = XY + YZ

4.3.6.2 Example
F(X,Y,Z) =Summation (1,3,4,5,6,7)

F=X+Z

4.3.7 4-Variable K-Map

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There are 16 cells in a 4-variable (W, X, Y, Z); K-map as shown in the figure below

There are 2 wrap-a-rounds: a horizontal wrap-around and a vertical wrap-around. Every cell thus has 4
neighbours. For example, the cell corresponding to minterm m0 has neighbours m1, m2, m4 and m8.

4.3.7.1 Example
F(W,X,Y,Z) = (1,5,12,13)

F = WY'Z + W'Y'Z

4.3.7.2 Example
F(W,X,Y,Z) = (4, 5, 10, 11, 14, 15)

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F = W'XY' + WY

4.3.8 5-Variable K-Map

There are 32 cells in a 5-variable (V, W, X, Y, Z); K-map as shown in the figure below.

4.3.9 Inverse Function

The 0's on a K-map indicate when the function is 0. We can minimize the inverse function by grouping the
0's(and any suitable don't cares) instead of the 1's. This technique leads to an expression which is not
logically equivalent to that obtained by grouping the 1's (i.e., the inverse of X != X'). Minimizing for the
inverse function may be particularly advantageous if there are many more 0's than 1's on the map. We can
also apply De Morgan's theorem to obtain a product-of-sum expression.

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5. Digital Combinational Logic

5.1 Introduction
Combinatorial Circuits are circuits which can be considered to have the following generic structure.

Whenever the same set of inputs is fed in to a combinatorial circuit, the same outputs will be generated.
Such circuits are said to be stateless. Some simple combinational logic elements that we have seen in
previous sections are "Gates".

All the gates in the above figure have 2 inputs and one output; combinational elements simplest form are
"not" gate and "buffer" as shown in the figure below. They have only one input and one output.

5.2 Decoders
A decoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs,
where the input and output codes are different; e.g. n-to-2n, BCD decoders. Enable inputs must be on for the
decoder to function, otherwise its outputs assume a single "disabled" output code word. Decoding is
necessary in applications such as data multiplexing, 7-segment display and memory address decoding.
Figure below shows the pseudo block of a decoder.

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5.2.1 Basic Binary Decoder

An AND gate can be used as the basic decoding element, because its output is HIGH only when all its inputs
are HIGH. For example, if the input binary number is 0110, then, to make all the inputs to the AND gate
HIGH, the two outer bits must be inverted using two inverters as shown in figure below.

5.2.2 Binary n-to-2n Decoders

A binary decoder has n inputs and 2n outputs. Only one output is active at any one time, corresponding to the
input value. Figure below shows a representation of Binary n-to-2n decoder.

5.2.2.1 Example: 2-to-4 Binary Decoder

A 2 to 4 decoder consists of two inputs and four outputs, truth table and symbols of which is shown below.
Truth Table
X Y F0 F1 F2 F3
0 0 1 0 0 0
0 1 0 1 0 0
1 1 0 0 1 0
1 1 0 0 0 1

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To minimize the above truth table we may use k-map, but doing that you will realize that it is a waste of
time. One can directly write down the function for each of the outputs. Thus we can draw the circuit as
shown in figure below. Note that each output is a 2-variable minterm (X'Y', X'Y, XY',XY).

5.2.2.2 Example: 3-to-8 Binary Decoder

A 3 to 8 decoder consists of three inputs and eight outputs, truth table and symbols of which is shown below.

Truth Table
X Y Z F0 F1 F2 F3 F4 F5 F6 F7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

From the truth table we can draw the circuit diagram as shown in figure below.

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5.3 Implementing Functions Using Decoders

Any n-variable logic function, in canonical sum-of-minterms form can be implemented using a single n-to-
2n decoder to generate the minterms, and an OR gate to form the sum. The output lines of the decoder
corresponding to the minterms of the function are used as inputs to the or gate. Any combinational circuit
with n inputs and m outputs can be implemented with an n-to-2n decoder with m OR gates. Suitable when a
circuit has many outputs, and each output function is expressed with few minterms.

5.3.1 Example: Full adder

S(x, y, z) = sum(1,2,4,7)
C(x, y, z) = sum(3,5,6,7)

X Y Z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

From the truth table we know the values for which the sum (S) is active and also the carry (C) is active.
Thus we have the equation as shown above and a circuit can be drawn as shown below from the equation
derived.

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5.4 Encoders
An encoder is a combinational circuit that performs the inverse operation of a decoder. If a device output
code has fewer bits than the input code has, the device is usually called an encoder. e.g. 2n-to-n, priority
encoders. The simplest encoder is a 2n-to-n binary encoder, where it has only one of 2n inputs and the output
is the n-bit binary number corresponding to the active input.

5.4.1 Example: Octal-to-Binary Encoder

Octal-to-Binary take 8 inputs and provides 3 outputs, thus doing the opposite of what the 3-to-8 decoder
does. At any one time, only one input line has a value of 1. The figure below shows the truth table of an
Octal-to-binary encoder.
Truth Table
I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

For an 8-to-3 binary encoder with inputs I0-I7 the logic expressions of the outputs Y0-Y2 are:
Y0 = I1 + I3 + I5 + I7
Y1= I2 + I3 + I6 + I7
Y2 = I4 + I5 + I6 +I7

Based on the above equations, we can draw the circuit as shown below.

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5.4.2 Example: Decimal-to-Binary Encoder

Decimal-to-Binary take 10 inputs and provides 4 outputs, thus doing the opposite of what the 4-to-10
decoder does. At any one time, only one input line has a value of 1. The figure below shows the truth table
of a Decimal-to-binary encoder.
Truth Table
I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 Y3 Y2 Y1 Y0
1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 0 0 0 1 0 0
0 0 0 0 0 1 0 0 0 0 0 1 0 1
0 0 0 0 0 0 1 0 0 0 0 1 1 0
0 0 0 0 0 0 0 1 0 0 0 1 1 1
0 0 0 0 0 0 0 0 1 0 1 0 0 0
0 0 0 0 0 0 0 0 0 1 1 0 0 1

From the above truth table , we can derive the functions Y3, Y2, Y1 and Y0 as given below.
Y3 = I8 + I9
Y2 = I4 + I5 + I6 + I7
Y1 = I2 + I3 + I6 + I7
Y0 = I1 + I3 + I5 + I7 + I9

5.4.3 Priority Encoder

If we look carefully at the Encoder circuits that we got, we see that if more than two inputs are active
simultaneously, the output is unpredictable or rather it is not what we expect it to be. This ambiguity is
resolved if priority is established so that only one input is encoded, no matter how many inputs are active at
a given point of time. The priority encoder includes a priority function. The operation of the priority encoder
is such that if two or more inputs are active at the same time, the input having the highest priority will take
precedence.

5.4.3.1 Example: 4 to 3 Priority Encoder

The truth table of a 4-input priority encoder is as shown below. The input D3 has the highest priority, D2 has
next highest priority, D0 has the lowest priority. This means output Y2 and Y1 are 0 only when none of the
inputs D1, D2, D3 are high and only D0 is high. A 4 to 3 encoder consists of four inputs and three outputs,
truth table and symbols of which is shown below.

Truth Table
D3 D2 D1 D0 Y2 Y1 Y0
0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 X 0 1 0
0 1 X X 0 1 1
1 X X X 1 0 0

Now that we have the truth table, we can draw the K-maps as shown below.

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From the K-map we can draw the circuit as shown below. For Y2, we connect directly to D3.

We can apply the same logic to get higher order priority encoders.

5.5 Multiplexer
A multiplexer (MUX) is a digital switch which connects data from one of n sources to the output. A number
of select inputs determine which data source is connected to the output. The block diagram of MUX with n
data sources of b bits wide and s bits wide select line is shown in below figure.

MUX acts like a digitally controlled multi-position switch where the binary code applied to the select inputs
controls the input source that will be switched on to the output as shown in the figure below. At any given
point of time only one input gets selected and is connected to output, based on the select input signal.

5.5.1 Mechanical Switch Equivalent (Ladder logic) of a Multiplexer

The operation of a multiplexer can be better explained using a mechanical switch as shown in the figure
below. This rotary switch can touch any of the inputs, which is connected to the output. As you can see at
any given point of time only one input gets transferred to output.

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5.5.2 Example: 2x1 MUX

A 2 to 1 line multiplexer is shown in figure below, each 2 input lines A to B is applied to one input of an
AND gate. Selection lines S are decoded to select a particular AND gate. The truth table for the 2:1 MUX is
given in the table below.

Truth Table
S Y
0 A
1 B

5.5.2.1 Design of a 2:1 Mux

To derive the gate level implementation of 2:1 MUX, we need to have truth table as shown in figure. And
once we have the truth table, we can draw the K-map as shown in figure for all the cases when Y is equal to
'1'. Combining the two 1' as shown in figure, we can drive the output Y: Y = A.S' + B.S
Truth Table
B A S Y
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

5.5.3 Example: 4:1 MUX

A 4 to 1 line multiplexer is shown in figure below, each of 4 input lines I0 to I3 is applied to one input of an
AND gate. Selection lines S0 and S1 are decoded to select a particular AND gate. The truth table for the 4:1
MUX is given in the table below.
Truth Table
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3

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5.5.4 Larger Multiplexers

Larger multiplexers can be constructed from smaller ones. An 8-to-1 multiplexer can be constructed from
smaller multiplexers as shown below.

5.5.4.1 Example: 8-to-1 multiplexer from Smaller MUX

Truth Table
S2 S1 S0 F
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7

5.5.4.2 Example: 16-to-1 multiplexer from 4:1 mux

5.6 De-multiplexers
They are digital switches which connect data from one input source to one of n outputs. Usually
implemented by using n-to-2n binary decoders where the decoder enable line is used for data input of the de-

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multiplexer. The figure below shows a de-multiplexer block diagram which has got s-bits-wide select input,
one b-bits-wide data input and n b-bits-wide outputs.

5.6.1 Mechanical Switch Equivalent (Ladder logic) of a De-Multiplexer

The operation of a de-multiplexer can be better explained using a mechanical switch as shown in the figure
below. This rotary switch can touch any of the outputs, which is connected to the input. As you can see at
any given point of time only one output gets connected to input.

5.6.2 Example: 1-to-4 De-multiplexer

1-bit 4-output de-multiplexer using a 2x4 binary decoder

Truth Table
S1 S0 F0 F1 F2 F3
0 0 D 0 0 0
0 1 0 D 0 0
1 0 0 0 D 0
1 1 0 0 0 D
5.6.3 Boolean Function Implementation
Earlier we had seen that it is possible to implement Boolean functions using decoders. In the same way it is
also possible to implement Boolean functions using MUXers and DEMUXers.

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5.7 Mux-Demux Application Example

This enables sharing a single communication line among a number of devices. At any time, only one source
and one destination can use the communication line.

5.8 Tutorial Questions

A. From Section 4
1. Discuss the two ways in which boolean functions can be simplified. Hence simplify the following
functions using both ways.
a) XYZ'+XYZ+X'YZ b) (X+Y' + Z).(X + Y+Z) c) X'Y+XY+XY'
2. Write short notes on the following:
a) Minterms b) Maxterms c) Sum of Product d) Product of Sum
3. The binary labels on each cell in a Karnaugh map follows the gray code sequence across rows or columns.
Explain with the aid of an hypothetical k-map with 3-bit labels across each row and column. How many
cells will be in this map? (Note: This question does not require drawing the k-map but just the row or
column cell labels).

B. From Section 5
1. What are Decoders? Hence, design a n-to-2n decoder when n=2; show the truth table, simplification and
logic diagram.
2. What are Encoders? Hence, design a decimal-to-binary encoder having 10 inputs and 4 outputs; showing
the truth table and logic diagram.
3. Differentiate between Standard Encoders and Priority Encoders. Hence, design two 3-to-2 encoders, one
apiece for standard and priority.
4. What is a Multiplexer? Illustrate with a schematic diagram and explain how it might be useful on a
computer circuit board.
5. Design a 2:1 Multiplexer and illustrate how this might be used to construct larger multiplexers such as an
8:1 multiplexer.
6. Design a 1:4 de-multiplexer, show its block diagram, truth table, logic symbol as well as logic
combinational circuit from gates.

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6. Combinational Arithmetic Circuits

6.1 Introduction
Arithmetic circuits are the ones which perform arithmetic operations like addition, subtraction,
multiplication, division, parity calculation. Most of the time, designing these circuits is the same as
designing MUXers, encoders and decoders. In the next few pages we will see few of these circuits in detail.

6.2 Adders
Adders are the basic building blocks of all arithmetic circuits; adders add two binary numbers and give out
sum and carry as output. Basically we have two types of adders: Half Adder and Full Adder.

6.2.1 Half Adder

Adding two single-bit binary values X, Y produces a sum S bit and a carry out C-out bit. This operation is
called half addition and the circuit to realize it is called a half adder.
Truth Table
Symbol
X Y SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

S (X,Y) = ∑(1,2) = X'Y + XY'= X Y

CARRY(X,Y) = ∑ (3)= XY

6.2.2 Full Adder

Full adder takes a three-bits input. Adding two single-bit binary values X, Y with a carry input bit C-in
produces a sum bit S and a carry out C-out bit.
K-map for SUM K-map for CARRY
X Y Z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

SUM (X,Y,Z) = ∑(1,2,4,7) SUM = X'Y'Z + XY'Z' + X'YZ' CARRY = XY + XZ + YZ

CARRY (X,Y,Z) = ∑(3,5,6,7) =X Y Z

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6.2.2.1 Full Adder using AND-OR

The below implementation shows implementing the full adder with AND-OR gates, instead of using XOR
gates. The basis of the circuit below is from the above Kmap.

6.2.3 n-bit Carry Ripple Adder

An n-bit adder used to add two n-bit binary numbers can be built by connecting n full adders in series. Each
full adder represents a bit position j (from 0 to n-1). Each carry out C-out from a full adder at position j is
connected to the carry in C-in of the full adder at higher position j+1. The output of a full adder at position j
is given by:
Sj = Xj Yj Zj
Cj+1 = Xj . Yj + Xj . Cj + Yj . Cj
In the expression of the sum, Cj must be generated by the full adder at lower position j. The propagation
delay in each full adder to produce the carry is equal to two gate delays = 2 D Since the generation of the
sum requires the propagation of the carry from the lowest position to the highest position, the total
propagation delay of the adder is approximately equals to 2nD.

6.2.3.1 4-bit Carry Ripple Adder

Adds two 4-bit numbers:

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X = X3 X2 X1 X0
Y = Y3 Y2 Y1 Y0
producing the sum S = S3 S2 S1 S0 , C-out = C4 from the most significant position j=3.

Total Propagation delay = 2nD = 8D or 8 gate delays

6.2.4 Larger Adders

Example: 16-bit adder using four 4-bit adders. Adds two 16-bit inputs X (bits X0 to X15), Y (bits Y0 to
Y15) producing a 16-bit Sum S (bits S0 to S15) and a carry out C16 from the most significant position.

Propagation delay for 16-bit adder = 4 x propagation delay of 4-bit adder

= 4 x 2 nD = 4 x 8D = 32 D or 32 gate delays

6.2.5 Carry Look-Ahead Adder [READ UP!]

6.2.6 BCD Adder [READ MORE!]

BCD addition is the same as binary addition with a bit of variation: whenever a sum is greater than 1001, it
is not a valid BCD number, so we add 0110 to it, to do the correction. This will produce a carry , which is
added to the next BCD position. The basic steps are:
➢ Add the two 4-bit BCD code inputs.
➢ Determine if the sum of this addition is greater than 1001;
o if yes, then add 0110 to this sum and generate a carry to the next decimal position.

6.3 Subtracter
Subtracter circuits take two binary numbers as input and subtract one binary number input from the other
binary number input. Similar to adders, it gives out two outputs, difference and borrow (carry-in the case of
Adder). There are two types of subtracters: Half Subtracter and Full Subtracter.
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6.3.1 Half Subtracter

The half-subtracter is a combinational circuit which is used to perform subtraction of two bits. It has two
inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow). The logic symbol
and truth table are shown below.
Truth Table
X Y D Bout
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

From the above table we can draw the K-map as shown below for "difference" and "borrow". The boolean
expression for the difference and Borrow can be written. From the equation we can draw the half-subtracter
as shown in the figure below.

6.3.2 Full Subtracter

A full subtracter is a combinational circuit that performs subtraction involving three bits, namely minuend,
subtrahend, and borrow-in. The logic symbol and truth table are shown below.
X Y Bin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

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From above table we can draw the K-map as shown below for "difference" and "borrow". The boolean
expression for difference and borrow can be written.

D = X'Y'Bin + X'YBin' + XY'Bin' + XYBin

= (X'Y' + XY)Bin + (X'Y + XY')Bin'
= (X Y)'Bin + (X Y)Bin'
= X Y Bin

Bout = X'.Y + X'.Bin + Y.Bin

From the above expression, we can draw the circuit below. If you look carefully, you will see that a full-
subtracter circuit is more or less same as a full-adder with slight modification.

6.3.3 Parallel Binary Subtracter

Parallel binary subtracter can be implemented by cascading several full-subtracters. Implementation and
associated problems are like those of a parallel binary adder. Below is the block level representation of a 4-
bit parallel binary subtracter, which subtracts 4-bit Y3Y2Y1Y0 from 4-bit X3X2X1X0. It has 4-bit
difference output D3D2D1D0 with borrow output, Bout.

D3

6.3.4 Serial Binary Subtracter

A serial subtracter can be obtained by converting the serial adder using the 2's complement system. The
subtrahend is stored in the Y register and must be 2's complemented before it is added to the minuend stored
in the X register. The circuit for a 4-bit serial subtracter using full-adder is shown in the figure below.

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6.4 Comparators [READ MORE!]

Comparators can compare either a variable number X (xn xn-1 ... x3 x2 x1) with a predefined constant C (cn cn-
1 ... c3 c2 c1) or two variable numbers X and Y. In the first case the implementation reduces to a series of
cascaded AND and OR logic gates. If the comparator answers the question 'X>C?' then
its hardware implementation is designed according to the following rules:

➢ The number X has two types of binary figures: bits corresponding to '1' in the predefined constant
and bits corresponding to '0'in the predefined constant.
➢ The bits of the number X corresponding to '1' are supplied to AND gates
➢ The bits corresponding to '0' are supplied to OR logic gates
➢ If the least significant bits of the predefined constant are '10' then bit X0 is supplied to the same
AND gate as bit X1.

If the least significant bits of the constant are all '1' then the corresponding bits of the number X are not
included in the hardware implementation. All other relations between X and C can be transformed in
equivalent ones that use the operator '>' and the NOT logic operator as shown in the table below.

Initial relationship to be tested Equivalent relationship to be implemented

X<C NOT (X>C-1)
X<= C NOT (X>C)
X >= C X>C-1

The comparison process of two positive numbers X and Y is performed in a bit-by-bit manner starting with
the most significant bit:

➢ If the most significant bits are Xn='1' and Yn='0' then number X is larger than Y.
➢ If Xn='0' and Yn='1' then number X is smaller than Y.
➢ If Xn=Yn then no decision can be taken about X and Y based only on these two bits.
➢ If the most significant bits are equal then the result of the comparison is determined by the less
significant bits Xn-1 and Yn-1. If these bits are equal as well, the process continues with the next
pair of bits. If all bits are equal then the two numbers are equal.

6.5 Multipliers
Multiplication is achieved by adding a list of shifted multiplicands according to the digits of the multiplier.
An n-bit X n-bit multiplier can be realized in combinational circuitry by using an array of n-1 n-bit adders
where each adder is shifted by one position. For each adder one input is the shifted multiplicand multiplied
by 0 or 1 (using AND gates) depending on the multiplier bit, the other input is n partial product bits.

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6.6 Dividers
The binary divisions are performed in a very similar manner to the decimal divisions, as shown in the
diagrams below. Thus, the second number is repeatedly subtracted from the figures of the first number after
being multiplied either with '1' or with '0'. The multiplication bit ('1' or '0') is selected for each subtraction
step in such a manner that the subtraction result is not negative. The division result is composed from all the
successive multiplication bits while the remainder is the result of the last subtraction step.

This algorithm can be implemented by a series of subtracters composed of modified elementary cells. Each
subtracter calculates the difference between two input numbers, but if the result is negative the operation is
cancelled and replaced with a subtraction by zero. Thus, each divider cell has the normal inputs of a
subtracter unit as in the figure below but a supplementary input ('div_bit') is also present. This input is
connected to the b_req_out signal generated by the most significant cell of the subtracter. If this signal is '1',
the initial subtraction result is negative and it has to be replaced with a subtraction by zero. Inside each
divider cell the div_bit signal controls an equivalent 2:1 multiplexer that selects between bit 'x' and the bit
included in the subtraction result X-Y. The complete division can therefore by implemented by a matrix of
divider cells connected on rows and columns as shown in figure below. Each row performs one
multiplication-and-subtraction cycle where the multiplication bit is supplied by the NOT logic gate at the
end of each row . Therefore, the NOT logic gates generate the bits of the division result.

6.7 Parity Circuit [READ UP!]

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7. Sequential Circuits
Digital electronics is classified into combinational logic and sequential logic. Combinational logic output
depends on the inputs levels, whereas sequential logic output depends on stored levels and also the input
levels.

The memory elements are devices capable of storing binary info. The binary info stored in the memory
elements at any given time defines the state of the sequential circuit. The input and the present state of the
memory element determines the output. Memory elements next state is also a function of external inputs
and present state. A sequential circuit is specified by a time sequence of inputs, outputs, and internal states.
There are two types of sequential circuits. Their classification depends on the timing of their signals:
➢ Synchronous sequential circuits
➢ Asynchronous sequential circuits

7.1 Asynchronous sequential circuit

This is a system whose outputs depend upon the order in which its input variables change and can be
affected at any instant of time. Gate-type asynchronous systems are basically combinational circuits with
feedback paths. Because of the feedback among logic gates, the system may, at times, become unstable.
Consequently they are not often used.

7.2 Synchronous sequential circuits

This type of system uses storage elements called flip-flops that are employed to change their binary value
only at discrete instants of time. Synchronous sequential circuits use logic gates and flip-flop storage
devices. Sequential circuits have a clock signal as one of their inputs. All state transitions in such circuits
occur only when the clock value is either 0 or 1 or happen at the rising or falling edges of the clock
depending on the type of memory elements used in the circuit. Synchronization is achieved by a timing
device called a clock pulse generator. Clock pulses are distributed throughout the system in such a way that
the flip-flops are affected only with the arrival of the synchronization pulse. Synchronous sequential circuits
that use clock pulses in the inputs are called clocked-sequential circuits. They are stable and their timing can
easily be broken down into independent discrete steps, each of which is considered separately.

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A clock signal is a periodic square wave that indefinitely switches from 0 to 1 and from 1 to 0 at fixed
intervals. Clock cycle time or clock period: the time interval between two consecutive rising or falling edges
of the clock. Clock Frequency is the inverse of clock cycle time and measured in cycles per second or
Hertz). For example, if Clock cycle time = 10ns then, clock frequency = 100MHz.

7.3 Concept of Sequential Logic

A sequential circuit is combinational logic with some feedback to maintain its current value, like a memory
cell. To understand the basics let's consider the basic feedback logic circuit below, which is a simple NOT
gate whose output is connected to its input. The effect is that output oscillates between HIGH and LOW
(i.e. 1 and 0). Oscillation frequency depends on gate delay and wire delay as discussed later under the
"Logic Families" Section. Assuming a wire delay of 0 and a gate delay of 10ns, then oscillation frequency
would be 50MHz (on time + off time = 20ns).

The basic idea of having the feedback is to store the value or hold the value, but in the above circuit, output
keeps toggling. We can overcome this problem with the circuit below, which is basically cascading two
inverters, so that the feedback is in-phase, thus avoids toggling. The equivalent circuit is the same as having
a buffer with its output connected to its input.

But there is a problem here too: each gate output value is stable, but what will it be? Or in other words,
buffer output cannot be known. There is no way to tell. If we could know or set the value we would have a
simple 1-bit storage/memory element.

The circuit below is the same as the inverters connected back to back with provision to set the state of each
gate (NOR gate with both inputs shorted is like a inverter). The operation is clear from the truth table. S is
called set and R is called Reset.

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S R Q Q+
0 0 0 0
0 0 1 1
0 1 X 0
1 0 X 1
1 1 X 0

There still seems to be some problem with the above configuration, we cannot control when the input should
be sampled. In other words, there is no enable signal to control when the input is sampled. Normally input
enable signals can be of two types:
➢ Level Sensitive or ( LATCH)
➢ Edge Sensitive or (Flip-Flop)

Level Sensitive: The circuit below is a modification of the above one to have level sensitive enable input.
Enable, when LOW, masks the input S and R. When HIGH, presents S and R to the sequential logic input
(the above circuit two NOR Gates). Thus Enable, when HIGH, transfers input S and R to the sequential cell
transparently, so this kind of sequential circuits are called transparent Latch. The memory element we get is
an RS Latch with active high Enable.

Edge Sensitive: The circuit below is a cascade of two level sensitive memory elements, with a phase shift in
the enable input between first memory element and second memory element. The first RS latch (i.e. the first
memory element) will be enabled when CLK input is HIGH and the second RS latch will be enabled when
CLK is LOW. The net effect is input RS is moved to Q and Q' when CLK changes state from HIGH to
LOW, this HIGH to LOW transition is called falling edge. So the Edge sensitive element we get is called
negative edge RS flip-flop.

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7.4 Latches and Flip-Flops

There are two types of sequential circuits:
➢ Asynchronous Circuits.
➢ Synchronous Circuits.

As seen in last section, Latches and Flip-flops are one and the same with a slight variation: Latches have
level sensitive control signal input and Flip-flops have edge sensitive control signal input. Flip-flops and
latches which use this control signals are called synchronous circuits. So if they don't use clock inputs, then
they are called asynchronous circuits.

7.4.1 RS Latch
RS latch have two inputs, S and R. S is called set and R is called reset. The S input is used to produce HIGH
on Q ( i.e. store binary 1 in flip-flop). The R input is used to produce LOW on Q (i.e. store binary 0 in flip-
flop). Q' is Q complementary output, so it always holds the opposite value of Q. The output of the S-R latch
depends on current as well as previous inputs or state, and its state (value stored) can change as soon as its
inputs change. The circuit and the truth table of RS latch is shown below. (This circuit is as we saw
previously, but arranged to look beautiful.

S R Q Q+
0 0 0 0
0 0 1 1
0 1 X 0
1 0 X 1
1 1 X invalid

The operation has to be analyzed with the 4 inputs combinations together with the 2 possible previous states.

When S = 0 and R = 0: If we assume Q = 1 and Q' = 0 as initial condition, then output Q after input is
applied would be Q = (R + Q')' = 1 and Q' = (S + Q)' = 0. Assuming Q =0 and Q' = 1 as initial condition,
then output Q after the input applied would be Q = (R + Q')' = 0 and Q' = (S + Q)' = 1. So it is clear that
when both S and R inputs are LOW, the output is retained as before the application of inputs. (i.e. there is no
state change).

When S = 1 and R = 0: If we assume Q = 1 and Q' = 0 as initial condition, then output Q after input is
applied would be Q = (R + Q')' = 1 and Q' = (S + Q)' = 0. Assuming Q =0 and Q' = 1 as initial condition,
then output Q after the input applied would be Q = (R + Q')' = 1 and Q' = (S + Q)' = 0. So in simple words
when S is HIGH and R is LOW, output Q is HIGH.

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When S = 0 and R = 1:If we assume Q = 1 and Q' = 0 as initial condition, then output Q after input is
applied would be Q = (R + Q')' = 0 and Q' = (S + Q)' = 1. Assuming Q =0 and Q' = 1 as initial condition,
then output Q after the input applied would be Q = (R + Q')' = 0 and Q' = (S + Q)' = 1. So in simple words
when S is LOW and R is HIGH, output Q is LOW.

When S = 1 and R =1 :No matter what state Q and Q' are in, application of 1 at input of NOR gate always
results in 0 at output of NOR gate, which results in both Q and Q' set to LOW (i.e. Q = Q'). LOW in both the
outputs basically is wrong, so this case is invalid.

The waveform below shows the operation of NOR gates based RS Latch.

It is possible to construct the RS latch using NAND gates (of course as seen in Logic gates section). The
only difference is that NAND is NOR gate dual form. So in this case the R = 0 and S = 0 case becomes the
invalid case. The circuit and Truth table of RS latch using NAND is shown below.

S R Q Q+
1 1 0 0
1 1 1 1
0 1 X 0
1 0 X 1
0 0 X invalid

If you look closely, there is no control signal (i.e. no clock and no enable), so this kind of latches or flip-
flops are called asynchronous logic elements. Since all the sequential circuits are built around the RS latch,
we will concentrate on synchronous circuits and not on asynchronous circuits.

7.4.2 RS Latch with Clock

We have seen this circuit earlier with two possible input configurations: one with level sensitive input and
one with edge sensitive input. The circuit below shows the level sensitive RS latch. Control signal "Enable"
E is used to gate the input S and R to the RS Latch. When Enable E is HIGH, both the AND gates act as
buffers and thus R and S appears at the RS latch input and it functions like a normal RS latch. When Enable

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E is LOW, it drives LOW to both inputs of RS latch. As we saw previously, when both inputs of a NOR
latch are low, values are retained (i.e. the output does not change).

Setup and Hold Time

For synchronous flip-flops, we have special requirements for the inputs with respect to clock signal input.
They are
Setup Time: Minimum time period during which data must be stable before the clock makes a valid
transition. For example, for a posedge triggered flip-flop, with a setup time of 2 ns, Input Data (i.e. R and S
in the case of RS flip-flop) should be stable for at least 2 ns before clock makes transition from 0 to 1.
Hold Time: Minimum time period during which data must be stable after the clock has made a valid
transition. For example, for a posedge triggered flip-flop, with a hold time of 1 ns. Input Data (i.e. R and S
in the case of RS flip-flop) should be stable for at least 1 ns after clock has made transition from 0 to 1.

If data makes transition within this setup window and before the hold window, then the flip-flop output is
not predictable, and flip-flop enters what is known as meta stable state. In this state flip-flop output
oscillates between 0 and 1. It takes some time for the flip-flop to settle down. The whole process is called
meta-stability. The waveform below shows input S (R is not shown), and CLK and output Q (Q' is not
shown) for a SR posedge flip-flop.

7.4.3 D Latch
The RS latch seen earlier contains ambiguous state; to eliminate this condition we can ensure that S and R
are never equal. This is done by connecting S and R together with an inverter. Thus we have D Latch: the
same as the RS latch, with the only difference that there is only one input, instead of two (R and S). This
input is called D or Data input. D latch is called D transparent latch for the reasons explained earlier. Delay
flip-flop or delay latch is another name used. Below is the truth table and circuit of D latch. In most real
world designs, only D latches/Flip-Flops are used.

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D Q Q+
1 X 1
0 X 0

Below is the D latch waveform, which is similar to the RS latch one, but with R removed.

7.4.4 JK Latch
The ambiguous state output in the RS latch was eliminated in the D latch by joining the inputs with an
inverter. But the D latch has a single input. JK latch is similar to RS latch in that it has 2 inputs J and K as
shown figure below. The ambiguous state has been eliminated here: when both inputs are high, output
toggles. The only difference we see here is output feedback to inputs, which is not there in the RS latch.

J K Q Q+
1 1 0 1
1 1 1 0
1 0 X 1
0 1 X 0

7.4.5 T Latch
When the two inputs of JK latch are shorted (shunted), a T Latch is formed. It is called T latch as, when
input is held HIGH, output toggles.

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T Q Q+
1 0 1
1 1 0
0 1 1
0 0 0

7.4.6 JK Master Slave Flip-Flop

All sequential circuits that we have seen previously have a problem; all level sensitive sequential circuits
have this problem. Before the enable input changes state from HIGH to LOW (assuming HIGH is ON and
LOW is OFF state), if inputs changes, then another state transition occurs for the same enable pulse. This
sort of multiple transition problem is called racing. If we make the sequential element sensitive to edges,
instead of levels, we can overcome this problem, as input is evaluated only during enable/clock edges.

In the figure above there are two latches, the first latch on the left is called master latch and the one on the
right is called slave latch. Master latch is positively clocked and slave latch is negatively clocked.

7.5 Sequential Circuits Design

We saw in the combinational circuits section how to design a combinational circuit from the given problem.
We convert the problem into a truth table, then draw K-map for the truth table, and then finally draw the

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gate level circuit for the problem. Similarly we have a flow for the sequential circuit design. The steps are
given below.
➢ Draw state diagram.
➢ Draw the state table (excitation table) for each output.
➢ Draw the K-map for each output.
➢ Draw the circuit.

Therefore, sequential circuit design flow is very much the same as for combinational circuit.

7.5.1 State Diagram

The state diagram is constructed using all the states of the sequential circuit in question. It builds up the
relationship between various states and also shows how inputs affect the states. For simplicity, let's consider
designing the 2 bit up counter (Binary counter is one which counts a binary sequence) using the T flip-flop.
Below is the state diagram of the 2-bit binary counter.

7.5.2 State Table

The state table is the same as the excitation table of a flip-flop, i.e. what inputs need to be applied to get the
required output. In other words this table gives the inputs required to produce the specific outputs.
Q1 Q0 Q1+ Q0+ T1 T0
0 0 0 1 0 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 0 1 1

7.5.3 K-map
The K-map is the same as the combinational circuits K-map. Only difference: we draw K-map for the inputs
i.e. T1 and T0 in the above table. From the table we deduct that we don't need to draw K-map for T0, as it is
high for all the state combinations. But for T1 we need to draw the K-map as shown below, using SOP.

7.5.4 Circuit
There is nothing special in drawing the circuit, it is the same as any circuit drawing from K-map output.
Below is the circuit of 2-bit up counter using the T flip-flop.

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7.6 COUNTERS
Counters are important digital electronic circuits. They are sequential logic circuits because timing is
obviously important and because they need a memory characteristic. Digital counters have the following
important characteristics:
1. Maximum number of counts (modulus of counter)
2. Up or down count
3. Asynchronous or synchronous operation
4. Free-running or self-stopping
As with other sequential circuits, flip-flops are used to construct counters. Counters are extremely useful in
digital systems. Counters can be used to count events such as a number of clock pulses in a given time
(measuring frequency). They can be used to divide frequency and store data as in a digital clock, and they
can also be used in sequential addressing and in some arithmetic circuits.

7.6.1 Ripple Counters

Digital counters will count only in binary or in binary codes. The figure below shows the counting sequence
in binary from 0000 to 1111 (0 to 15 in decimal). A digital counter that would count from binary 0000 to
1111 as shown in the table might be called a modulo-16 counter. The modulus of a counter is the number of
counts the counter goes through. The term “modulo” is sometimes shortened to “mod.” This counter might
thus be called a mod-16 counter.

A logic diagram of a mod-16 counter using JK flip-flops is shown in the next Figure. First note that the J
and K data inputs of the flip-flops are tied to logical 1. This means that each flip-flop is in its toggle mode.
Each clock pulse will then cause the flip-flop to toggle to its opposite state. Note also that the Q output of
FF1 (flip-flop 1) is connected directly to the clock (CLK) input to the next unit (FF2), and so forth. Output
indicators (lamps or LEDs), shown at the upper right, monitor the binary output of the counter. Indicator A
is the LSB (least significant bit), D is the MSB.

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7.6.2 Parallel Counters

The asynchronous ripple counter has the limitation of the time lag in triggering all the flip-flops. To cure this
problem, parallel counters can be used. The logic diagram for a 3-bit parallel counter is shown below. Note
that all CLK inputs are tied directly to the input clock. They are wired in parallel. Note also that JK flip-
flops are used. FFl is the 1s place counter and is always in the toggle mode. FF2 has its J and K inputs tied to
the output of FF1 and will be in the hold or toggle mode. The outputs of FF1 and FF2 are fed into an AND
gate. The AND gate controls the mode of operation of FF3. When the AND gate is activated by 1s at A and
B , FF3 will be in its toggle mode. With the AND gate deactivated, FF3 will be in its hold mode. FF2 is the
2s place counter and FF3 the 4s place counter.

The counting sequence for this 3-bit parallel counter is shown above. Note that this is a modulo-8 (mod-8)
counter. The counter will start counting at binary 000 and count up to 111. It will then recycle back to 000 to
start the count again. Hardly any time lag is evident from FF1 to FF3 because all the flip-flops are clocked at
exactly the same time. That is the advantage of the parallel-type counter. Parallel counters are also called
synchronous counters because all flip-flops trigger exactly in time with the clock. Parallel counters are more
complicated (see the added lines and the AND gate), but they are used when the time lag problem with a
ripple counter would cause problems. You should be able to construct a 4-bit parallel counter using the steps
for designing sequential circuits discussed in Section 7.5. Is there a difference from the 4-bit ripple counter?

7.7 SHIFT REGISTERS

Shift registers, like counters, are a form of sequential logic. Sequential logic, unlike combinational logic is
not only affected by the present inputs, but also, by the prior history. In other words, sequential logic
remembers past events. Shift registers produce a discrete delay of a digital signal or waveform. A waveform
synchronized to a clock, a repeating square wave, is delayed by "n" discrete clock times, where "n" is the
number of shift register stages. Thus, a four stage shift register delays ”data in” by four clocks to ”data out”.
The stages in a shift register are delay stages, typically ”D” Flip-Flops or "JK" Flip-flops.

Formerly, very long (several hundred stages) shift registers served as digital memory. This obsolete
application is reminiscent of the acoustic mercury delay lines used as early computer memory. Serial data
transmission, over a distance of meters to kilometres, uses shift registers to convert parallel data to serial

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form. Serial data communications replaces many slow parallel data wires with a single serial high speed
circuit. Serial data over shorter distances of tens of centimetres, uses shift registers to get data into and out of
microprocessors. Numerous peripherals, including analog to digital converters, digital to analog converters,
display drivers, and memory, use shift registers to reduce the amount of wiring in circuit boards. Some
specialized counter circuits actually use shift registers to generate repeating waveforms. Longer shift
registers, with the help of feedback generate patterns so long that they look like random noise, pseudo-noise.
Basic shift registers are classified by structure according to the following types:
➢ Serial-in/serial-out
➢ Parallel-in/serial-out
➢ Serial-in/parallel-out
➢ Universal parallel-in/parallel-out
➢ Ring counter

7.7.1 Serial-in/serial-out

Above we show a block diagram of a serial-in/serial-out shift register, which is 4-stages long. Data at the
input will be delayed by four clock periods from the input to the output of the shift register. Data at ”data
in”, above, will be present at the Stage A output after the first clock pulse. After the second pulse stage A
data is transferred to stage B output, and ”data in” is transferred to stage A output. After the third clock,
stage C is replaced by stage B; stage B is replaced by stage A; and stage A is replaced by ”data in”. After the
fourth clock, the data originally present at ”data in” is at stage D, ”output”. The ”first in” data is ”first out”
as it is shifted from ”data in” to ”data out”.

7.7.2 Parallel-in/serial-out

Data is loaded into all stages at once of a parallel-in/serial-out shift register. The data is then shifted out via
”data out” by clock pulses. Since a 4- stage shift register is shown above, four clock pulses are required to
shift out all of the data. In the diagram above, stage D data will be present at the ”data out” up until the first
clock pulse; stage C data will be present at ”data out” between the first clock and the second clock pulse;
stage B data will be present between the second clock and the third clock; and stage A data will be present
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between the third and the fourth clock. After the fourth clock pulse and thereafter, successive bits of ”data
in” should appear at ”data out” of the shift register after a delay of four clock pulses. If four switches were
connected to DA through DD, the status could be read into a microprocessor using only one data pin and a
clock pin. Since adding more switches would require no additional pins, this approach looks attractive for
many inputs.

7.7.3 Serial-in/parallel-out

Above, four data bits will be shifted in from ”data in” by four clock pulses and be available at QA through
QD for driving external circuitry such as LEDs, lamps, relay drivers, and horns. After the first clock, the data
at ”data in” appears at QA. After the second clock, The old QA data appears at QB; QA receives next data
from ”data in”. After the third clock, QB data is at QC. After the fourth clock, QC data is at QD. This stage
contains the data first present at ”data in”. The shift register should now contain four data bits.

7.7.4 Parallel-in/parallel-out

A parallel-in/parallel-out shift register combines the function of the parallel-in, serial-out shift register with
the function of the serial-in, parallel-out shift register to yields the universal shift register. The ”do anything”
shifter comes at a price– the increased number of I/O (Input/ Output) pins may reduce the number of stages
which can be packaged. Data presented at DA through DD is parallel loaded into the registers. This data at
QA through QD may be shifted by the number of pulses presented at the clock input. The shifted data is
available at QA through QD. The ”mode” input, which may be more than one input, controls parallel loading
of data from DA through DD, shifting of data, and the direction of shifting. There are shift registers which
will shift data either left or right.

7.7.5 Ring counter

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If the serial output of a shift register is connected to the serial input, data can be perpetually shifted around
the ring as long as clock pulses are present. If the output is inverted before being fed back as shown above,
we do not have to worry about loading the initial data into the ”ring counter”.

7.8 Tutorial Questions

A. From Section 6
1. Discuss the function of a Comparator in a digital Computer system. Hence design a 2-bit comparator that
compares any two bit numbers, A & B and outputs whether A>B, A=B or A<B.
2. How do Multiplexer, De-multiplexer and Decoder work?
3. Design a 4-bit full Adder that performs subtraction and explain how it works. Note that only the
schematic diagram is required, no truth tables nor logic gates diagram.
4. Differentiate between a Half-Adder and Full-Adder. Hence, design a 1-bit full adder showing its truth
table, algebraic simplification and logic gates diagram.
5. Compare and contrast parallel binary subtracters with serial binary subtracters. Support your explanation
with schematic diagrams.

B. From Section 7
1. Write short notes on the following:
a) Ripple (asynchronous) counters b) Parallel (synchronous) counters
Hence, design the synchronous and asynchronous versions of a modulo 8 counter.
2. List and state the functions of the various types of Shift registers that you know. Hence, give the detailed
design and practical operation of any three of the listed shift registers.
3. All Computer logic systems are built from Combinational and Sequential logic. Discuss this statement in
relation to the building block of Combinational and Sequential logic. Also, explain the difference between
truth table and state table.
4. Explain the two types of Sequential circuits briefly.
5. Explain the difference between Latches and flip-flops.
6. What is setup and hold time with respect to the operation of flip-flops?
7. List the types of latches/flip-flops that you are aware of and explain the workings of any two of them.
8. List the steps required in design of sequential circuits. Hence, design a 2-bit synchronous down counter.

8. Digital Logic Families.

The digital IC technology has advanced considerably and rapidly over the years. Starting from small scale
integration (SSI) with less than 12 gates per chip, advancing to medium scale integration (MSI) with 12 to
100 gates per chip and then to large scale integration (LSI) with up to 10,000 gates per chip and on to Very
large scale integration (VLSI) with up to 100,000 gates per chip, the digital IC technology has come a long
way. In recent years, it has advanced to ultra large scale integration (ULSI) with more than 100,000 gates
per chip. A group of compatible ICs with similar logic levels and supply voltages fabricated using a specific
circuitry is referred as a logic family. Logic families can be classified broadly according to the technologies
they are built with. In earlier days we had vast number of these technologies, as you can see in the list
below.
i. DL : Diode Logic.
ii. RTL : Resistor Transistor Logic.

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iii. DTL : Diode Transistor Logic.

iv. HTL : High threshold Logic.
v. TTL : Transistor Transistor Logic.
vi. IIL : Integrated Injection Logic.
vii. ECL : Emitter coupled logic.
viii. MOS : Metal Oxide Semiconductor Logic (PMOS and NMOS).
ix. CMOS : Complementary Metal Oxide Semiconductor Logic.

Among these, only CMOS is most widely used by the Chip designers; we will still try to understand a few of
the extinct / less used technologies.

8.1 Basic Characteristics

Before we start looking at the how gates are built using various technologies, we need to understand a few
basic concepts related to the characteristics of a logic family. These concepts are actually the factors to be
considered in the design and fabrication of logic systems and have practical implications.
i. Speed of operation
ii. Operating temperature range
iii. Logic/ Current levels, Rise/Fall times
iv. Fan-in.
v. Fan-out.
vi. Gate Delay.
vii. Wire Delay.
viii. Skew
ix. Noise Margin (Noise immunity)
x. Power Dissipation.

1) Speed of operation: Speed is typically the first parameter at which a designer looks. Usually people
want high speed devices. So it is normally desired to have a shorter propagation delay time. But
increased speed often creates many potential problems such as: increased noise generation, higher
power consumption, increased component and system cost, more difficult board layout, etc.
2) Operating Temperature: The temperature range in which an IC functions properly is a very
important parameter. The accepted temperature ranges are: 0 to +700C for consumer and industrial
applications whereas -550C to +125 0C for military applications.
3) Logic levels: Logic levels are the voltage levels for logic high and logic low. These are
➢ VOHmin: The minimum output voltage in HIGH state (logic '1'). VOHmin is 2.4V for TTL and 4.9V
for CMOS.
➢ VOLmax: The maximum output voltage in LOW state (logic '0'). VOLmax is 0.4V for TTL and 0.1V
for CMOS.
➢ VIHmin: The minimum input voltage guaranteed to be recognised as logic 1. VIHmin is 2 V for TTL
and 3.5 V for CMOS.
➢ VILmax: The maximum input voltage guaranteed to be recognised as logic 0. VILmax is 0.8 V for
TTL and 1.5V for CMOS.
4) Current levels
➢ IOHmin: The maximum current the output can source in HIGH state while still maintaining the
output voltage above VOHmin.

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➢ IOLmax: The maximum current the output can sink in LOW state while still maintaining the output
voltage below VOLmax.
➢ IImax: The maximum current that flows into an input in any state (1µA for CMOS).
5) Rise time (tr): The time required for the output voltage to increase from VILmax to VIHmin.
6) Fall time (tf): The time required for the output voltage to decrease from VIHmin to VILmax.
7) tp (Propagation delay): The time between the logic transition on an input and the corresponding
logic transition on the output of the logic gate. The propagation delay is measured at midpoints.
Propagation delay is the time taken between 50% of peak points on the input and output transistors.
The propagation delay time of a logic gate varies from 1 nano-second to 50 nano-seconds.
8) Fan-in: Fan-in is the number of inputs a gate has. A two input AND gate has fan-in of two, a three
input NAND gate as a fan-in of three. So a NOT gate always has a fan-in of one. Normally gate
delay increases following a quadratic function of fan-in.
9) Fan-out: The number of gates that each gate can drive, while providing voltage levels in the
guaranteed range, is called the standard load or fan-out. The fan-out really depends on the amount of
electric current a gate can source or sink while driving other gates. Normally as in the case of fan-in,
the delay offered by a gate increases with the increase in fan-out. The effects of loading a logic gate
output with more than its rated fan-out has the following effects:
➢ In the LOW state the output voltage VOL may increase above VOLmax
➢ In the HIGH state the output voltage VOH may decrease below VOHmin.
➢ The operating temperature of the device may increase thereby reducing the reliability of the
device and eventually causing the device failure.
➢ Output rise and fall times may increase beyond specifications
➢ The propagation delay may rise above the specified value.
10) Gate Delay: Gate delay is the delay offered by a gate for the signal appearing at its input, before it
reaches the gate output. The figure below shows a NOT gate with a delay of "Delta", where output X'
changes only after a delay of "Delta". Gate delay is also known as propagation delay. Gate delay is
not the same for both transitions, i.e. gate delay will be different for low to high transition, compared
to high to low transition. Low to high transition delay is called turn-on delay and High to low
transition delay is called turn-off delay.

11) Wire Delay: Gates are connected together with wires and these wires do delay the signal they carry,
these delays become very significant when frequency increases, say when the transistor sizes are
sub-micron. Sometimes wire delay is also called flight time (i.e. signal flight time from point A to
B). Wire delay is also known as transport delay.

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12) Skew: The same signal arriving at different parts of the design with different phase is known as
skew. Skew normally refers to clock signals. In the figure below, clock signal CLK reaches flip-flop
FF0 at time t0, so with respect to the clock phase at the source, it has at FF0 input a clock skew of t0
time units. Normally this is expressed in nanoseconds.

The waveform below shows how clock looks at different parts of the design.

13) Noise Margin: Gate circuits are constructed to sustain variations in input and output voltage levels.
Variations are usually the result of several different factors.
➢ Batteries lose their full potential, causing the supply voltage to drop
➢ High operating temperatures may cause a drift in transistor voltage and current characteristics
➢ Spurious pulses may be introduced on signal lines by normal surges of current in neighbouring
supply lines.

All these undesirable voltage variations that are superimposed on normal operating voltage levels are
called noise. All gates are designed to tolerate a certain amount of noise on their input and output
ports. The maximum noise voltage level that is tolerated by a gate is called noise margin. It derives
from I/P-O/P voltage characteristic, measured under different operating conditions. It's normally
supplied from manufacturer in the gate documentation.

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➢ LNM (Low noise margin): The largest noise amplitude that is guaranteed not to change the
output voltage level when superimposed on the input voltage of the logic gate (when this voltage
is in the LOW interval). LNM=VILmax - VOLmax
➢ HNM (High noise margin): The largest noise amplitude that is guaranteed not to change the
output voltage level if superimposed on the input voltage of the logic gate (when this voltage is
in the HIGH interval). HNM=VOHmin - VIHmin
14) Power Dissipation: Each gate is connected to a power supply VCC (VDD in the case of CMOS). It
draws a certain amount of current during its operation. It is defined as the supply power required for
the logic gate to operate with 50% duty cycle at the specified frequency. The power dissipation of a
logic circuit varies from 0.05 mW to 50mW per gate. This is determined by the current drawn by the
chip. Normally there is only one power supply terminal on the chip, which is normally denoted by
Vcc for TTL devices and by VDD for MOS devices. The power is specified in milli-watts.

Since each gate can be in a High, Transition or Low state, there are three different currents drawn
from power supply.

➢ ICCH: Current drawn during HIGH state.

➢ ICCT: Current drawn during HIGH to LOW, LOW to HIGH transition.
➢ ICCL: Current drawn during LOW state.

For TTL, ICCT the transition current is negligible, in comparison to ICCH and ICCL. If we assume
that ICCH and ICCL are equal then,

Average Power Dissipation = Vcc * (ICCH + ICCL)/2

For CMOS, ICCH and ICCL current is negligible, in comparison to ICCT. So the Average power
dissipation is calculated as below.

Average Power Dissipation = Vcc * ICCT.

So for TTL-like logic family, power dissipation does not depend on frequency of operation, and for
CMOS the power dissipation depends on the operation frequency. Power Dissipation is an important
metric for two reasons. The amount of current and power available in a battery is nearly constant.

➢ Power dissipation of a circuit or system defines battery life: the greater the power dissipation, the
shorter the battery life.
➢ Power dissipation is proportional to the heat generated by the chip or system; excessive heat
dissipation may increase operating temperature and cause gate circuitry to drift out of its normal
operating range; will cause gates to generate improper output values. Thus power dissipation of
any gate implementation must be kept as low as possible.

Moreover, power dissipation can be classified into Static power dissipation and Dynamic power dissipation.

➢ Ps (Static Power Dissipation): Power consumed when the output or input is not changing or rather
when clock is turned off. Normally static power dissipation is caused by leakage current. (As we
reduce the transistor size, i.e. below 90nm, leakage current could be as high as 40% of total power
dissipation).
➢ Pd (Dynamic Power Dissipation): Power consumed during output and input transitions. So we can
say Pd is the actual power consumed i.e. the power consumed by transistors + leakage current.
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Thus:
Total power dissipation = static power dissipation + dynamic power dissipation.

8.2 Categories of Digital IC Logic family

The entire range of digital ICs is fabricated using either bipolar devices or MOS devices or a combination of
the two. Some of these technologies are discussed below after the listing.

 Bipolar families:
◦ Diode logic (DL) [obsolete]
◦ Resistor transistor logic (RTL) [obsolete]
◦ Diode transistor logic (DTL) (obsolete)
◦ Transistor Transistor logic (TTL)
◦ Emitter Coupled Logic (ECL), also known as Current Mode Logic(CML).
◦ Integrated Injection logic (I2L)[obsolete]
 MOS families:
◦ PMOS family (using P-channel MOSFETs) [obsolete]
◦ The NMOS family (using N-channel MOSFETs)
◦ The CMOS family (using both N- and P-channel devices).
◦ The Bi-MOS logic family uses both bipolar and MOS devices.
8.2.1 Diode Logic
In DL (diode logic), all the logic is implemented using diodes and resistors. One basic thing about the diode,
is that diode needs to be forward biased to conduct. Below is an example of DL circuit.

When no input is connected or driven, output Z is low, due to resistor R1. When high is applied to either X
or Y, or both X and Y are driven high, the corresponding diode get forward biased and thus conducts. When
any diode conducts, output Z goes high.

Notes on DL:
➢ Diode Logic suffers from voltage degradation from one stage to the next.
➢ Diode Logic only permits OR and AND functions.
➢ Diode Logic is used extensively but not in integrated circuits.

8.2.2 Resistor Transistor Logic

In RTL (resistor transistor logic), all the logic are implemented using resistors and transistors. RTL is a type
of digital circuits built using resistors as the input network and bipolar junction transistors (BJTs) as
switching devices. RTL is the earliest class of transistorized digital logic circuit used commercially. One
basic thing about the transistor (NPN) is that HIGH at input causes output to be LOW (i.e. like a inverter).
Below is an example of a RTL circuit.

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A basic circuit of an RTL NOR gate consists of two transistors Q1 and Q2, connected as shown in the figure
above. When either input X or Y is driven HIGH, the corresponding transistor goes to saturation and output
Z is pulled to LOW.

A simple two input RTL NOR gate is shown below. The circuit consists of four resistors and one transistor
(T). Here the transistor acts as an inverter. When both the inputs are zero (A=0, B=0), the input to the
transistor is zero. So the output of the transistor is HIGH or Logic 1. Similarly, when one of the inputs is
HIGH (logic1), the input to the transistor is HIGH. So the output Q is LOW or logic 0. On the same lines
when both the inputs are HIGH the input to the transistor is HIGH (logic1), so the output of the transistor is
LOW or logic 0. This is the working of two inputs NOR gate which is also shown in the truth table.

____
A B Q= A+B
0 0 1
1 0 0
0 1 0
1 1 0

Notes on RTL:
➢ The basic advantage of RTL technology is that it uses a minimum number of transistors, which was
an important consideration before integrated circuit technology, as transistors were the most
expensive component to produce. Early IC logic production such as Fairchild's in 1961, used the
same RTL approach briefly, but quickly transitioned to higher-performance circuits such as diode–
transistor logic and then transistor–transistor logic, since diodes and transistors were no more
expensive than resistors.
➢ The obvious disadvantage of RTL is its high current dissipation when the transistor conducts to
overdrive the output biasing resistor.
➢ Also another limitation is its limited Fan-In, 3 inputs being the limit for many circuit designs.
➢ RTL circuits are no more in use. They are obsolete

8.2.3 Diode Transistor Logic

It is a class of digital circuits built from bipolar junction transistors (BJT), diodes and resistors. It is called
diode–transistor logic because the logic gating function (e.g., AND) is performed by a diode network and
the amplifying function is performed by a transistor (contrast this with RTL and TTL). A basic circuit in the
DTL logic family is as shown in the figure below. Each input is associated with one diode. The diodes and
the 4.7K resistor form an AND gate. If input X, Y or Z is low, the corresponding diode conducts current,
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through the 4.7K resistor. Thus there is no current through the diodes connected in series to transistor base.
Hence the transistor does not conduct, thus remains in cut-off, and output out is High. If all the inputs X, Y,
Z are driven high, the diodes in series conduct, driving the transistor into saturation. Thus output out is Low.

A simple two input DTL NAND gate circuit is also shown below. It consists of two Diodes, four resistors
and one Transistor and a power supply V+. Here the Transistor acts as an inverter. When the inputs A & B
are at logic 0 (LOW) , the current due to V+ flows through the Diodes to ground and the current through the
resistors R3 is Zero i.e. the input to the Transistor T is zero. And, the Transistor is in off state and the out-
put at Q is High (Logic1). Similarly when one of the inputs is HIGH (Logic1), the other will be at LOW. So
the current due to V+ will pass through one diode and the other diode is in reverse bias i.e. the input to the
transistor is zero or the transistor is in cut-off state. So the output at Q is HIGH or at logic1. Suppose both
the inputs are HIGH (logic 1).The current due to V+ do not pass through the diodes. The input of the
Transistor will be at Logic 1 i.e. the transistor is in conducting state. Hence the output of the Transistor is
LOW or at logic 0. This working of NAND gate is shown in the truth table.

A B Q= A.B
0 0 1
1 0 1
0 1 1
1 1 0

Notes on DTL:
➢ One problem that DTL suffers is its low speed, especially when the transistor is being turned off.
Turning off a saturated transistor in a DTL gate requires it to first pass through the active region
before going into cut-off. Cut-off, however, will not be reached until the stored charge in its base
has been removed. The dissipation of the base charge takes time if there is no available path from the
base to ground. This is why in DTL circuits a base resistor is connected to ground so that it provides
a path for discharge as shown in the figure.
➢ Another problem with turning off the DTL output transistor is the fact that the effective capacitance
of the output needs to charge up through R2 before the output voltage rises to the final logic '1' level,
which also consumes a relatively large amount of time.
➢ But, one advantage of DTL over RTL is its better noise margin and greater fan-outs than RTL, but it
suffers from low speed, especially in comparison to TTL.

8.2.4 Transistor Transistor Logic

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In Transistor Transistor logic or just TTL, logic gates are built only around transistors. TTL was developed
in 1965. Through the years basic TTL has been improved to meet performance requirements. There are
many versions or families of TTL.

Here we will discuss only standard TTL. All TTL families have three configurations for outputs.
➢ Totem - Pole output.
➢ Open Collector Output.
➢ Tristate Output.

Before we discuss the output stage let's look at the input stage, which is used with almost all versions of
TTL. This consists of an input transistor and a phase splitter transistor. Input stage consists of a multi emitter
transistor as shown in the figure below. When any input is driven low, the emitter base junction is forward
biased and input transistor conducts. This in turn drives the phase splitter transistor into cut-off.

8.2.4.1 Totem - Pole Output

Below is the circuit of a totem-pole NAND gate, which has got three stages.
➢ Input Stage
➢ Phase Splitter Stage
➢ Output Stage

Input stage and Phase splitter stage have been briefly discussed earlier. Output stage is called Totem-Pole
because transistor Q3 sits upon Q4. Q2 provides complementary voltages for the output transistors Q3 and
Q4, which stack one above the other in such a way that while one of these conducts, the other is in cut-off.
Q4 is called pull-down transistor, as it pulls the output voltage down, when it saturates and the other is in
cut-off (i.e. Q3 is in cut-off). Q3 is called pull-up transistor, as it pulls the output voltage up, when it
saturates and the other is in cut-off (i.e. Q4 is in cut-off). Diodes in input are protection diodes which
conduct when there is large negative voltage at input, shorting it to the ground.

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8.2.4.2 Tristate Output

Normally when we have to implement shared bus systems inside an ASIC (Application Specific Integrated
Circuit) or externally to the chip, we have two options: either to use a MUX/DEMUX based system or to use
a tri-state base bus system. In the latter when logic is not driving its output, it does not drive LOW neither
HIGH, which means that logic output is floating. Well, one may ask, why not just use an open collector for
shared bus systems? The problem is that open collectors are not so good for implementing wire-ANDs. The
circuit below is a tri-state NAND gate; when Enable En is HIGH, it works like any other NAND gate. But
when Enable En is driven LOW, Q1 Conducts, and the diode connecting Q1 emitter and Q2 collector,
conducts driving Q3 into cut-off. Since Q2 is not conducting, Q4 is also at cut-off. When both pull-up and
pull-down transistors are not conducting, output Z is in high-impedance state.

8.2.5 Emitter coupled logic

ECL was invented in August 1956 at IBM by Hannon S. Yourke. Originally called current-steering logic, it
was used in the Stretch, IBM 7090, and IBM 7094 computers. Emitter coupled logic (ECL) is the fastest of
all logic families and therefore used in applications where very high speed is needed. ECL is fastest because,
the transistors are used in difference amplifier configuration in which they are never driven into saturation
.The transistor is driven between ON and OFF states (cut-off & active) only. Hence propagation delay of
less than 1ns per gate has become possible. In other transistor based logic circuits, switching is between cut-
off and saturation states; hence delay is more. Basically ECL is realized using difference amplifier in which
the emitters of the two transistors are connected and hence it is referred to as emitter-coupled logic.

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Emitter coupled logic (ECL) is a non-saturated logic, which means that transistors are prevented from going
into deep saturation, thus eliminating storage delays. Preventing the transistors from
going into saturation is accomplished by using logic levels whose values are so close to each other that a
transistor is not driven into saturation when its input switches from low to high. In other words, the transistor
is switched on, but not completely on. This logic family is faster than TTL. Voltage level for high is -0.9
Volts and for low is -1.7V; thus biggest problem with ECL is a poor noise margin.

The ECL circuits usually operate with negative power supplies (positive end of the supply is connected to
ground) in contrast to other logic families in which negative end of the supply are grounded. This is done
mainly to minimize the influence of the power supply variations on the logic levels as ECL is more sensitive
to noise on the VCC and relatively immune to noise on VEE. Because ground should be the most stable
voltage in a system, ECL is specified with a positive ground

A typical ECL OR gate is shown below. When any input is HIGH (-0.9v), its connected transistor will
conduct, and hence will make Q3 off, which in turn will make Q4 output HIGH. When both inputs are LOW
(-1.7v), their connected transistors will not conduct, making Q3 on, which in turn will make Q4 output
LOW.

The basic circuit configuration consists of a pair of NPN transistors with their emitters connected together
and fed by a current source IE as shown below.

Emitter coupled logic is basically a combination of differential amplifier with Q1 &Q2 and Emitter
followers with Q3 & Q4.This emitter-follower provides low output impedance typically of the order of 6-8
Ω. In the steady state, either Q1 or Q2 is ON but not both, and the output logic state is determined by the
voltage difference between the bases of Q1 and Q2. If Vb1 – Vb2 > 200 mV, Q1 will be turned ON and Q2
turned OFF, and vice versa.
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The inputs can be driven either differentially or single-ended. In the single-ended mode, the non-driven base
must be connected to a suitable bias voltage, VBB, which is either supplied internally by the device, or
externally. The voltages developed at the collectors of Q1 and Q2 are connected to a pair of emitter
followers, Q3 and Q4. The outputs are taken at the emitters of Q3 and Q4.The two outputs are complements
of each other. So if one is the OR output, the other will be the NOR output. Note that the output emitters are
open, and, unlike TTL/CMOS circuits, there will be no output until a pull-down resistor is connected to the
open emitter. This pull-down resistor plays a very important role in determining the performance of the ECL
circuit.

Notes on ECL:
➢ The power dissipation is of the order of 50mW and Fan-out is typically around 15 to 20.
➢ Due to the disadvantage of high power dissipation and relatively low noise margins ECL family has
limited applications, except in high frequency applications.

8.2.6 Metal Oxide Semiconductor Logic

MOS or Metal Oxide Semiconductor logic uses nmos and pmos to implement logic gates. One needs to
know the operation of FET and MOS transistors to understand the operation of MOS logic circuits. The
basic NMOS inverter is shown below: when input is LOW, NMOS transistor does not conduct, and thus
output is HIGH. But when input is HIGH, NMOS transistor conducts and thus output is LOW.

Normally it is difficult to fabricate resistors inside the chips, so the resistor is replaced with an NMOS gate
as shown above. This new NMOS transistor acts as resistor.

8.2.7 Complementary Metal Oxide Semiconductor Logic

CMOS or Complementary Metal Oxide Semiconductor logic is built using both NMOS and PMOS. Below
is the basic CMOS inverter circuit, which follows these rules:
➢ NMOS conducts when its input is HIGH.
➢ PMOS conducts when its input is LOW.
➢ So when input is HIGH, NMOS conducts, and thus output is LOW
➢ When input is LOW PMOS conducts and thus output is HIGH.

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CMOS Sub families include ICs with the following part numbers
➢ 4000A (obsolete)
➢ 4000B, 4000UB,
➢ 54/74C, 54/74HC, 54/74HCT, 54/74AC and 54/74ACT(TTL pin compatible)

9. DIP GATE PACKAGING

Digital logic gate circuits are manufactured as integrated circuits: all the constituent transistors and resistors
built on a single piece of semiconductor material. The engineer, technician, or hobbyist using small numbers
of gates will likely find what he or she needs enclosed in DIP (Dual Inline Package) housing. DIP-enclosed
integrated circuits are available with even numbers of pins, located at 0.100 inch intervals from each other
for standard circuit board layout compatibility. Pin counts of 8, 14, 16, 18, and 24 are common for DIP
chips. Part numbers given to these DIP packages specify what type of gates are enclosed, and how many.
These part numbers are industry standards, meaning that a ”74LS02” manufactured by Motorola will be
identical in function to a ”74LS02” manufactured by Fairchild or by any other manufacturer. Letter codes
prepended to the part number are unique to the manufacturer, and are not industry-standard codes. For
instance, a SN74LS02 is a quad 2-input TTL NOR gate manufactured by Motorola, while a DM74LS02 is
the exact same circuit manufactured by Fairchild. Logic circuit part numbers beginning with ”74” are
commercial-grade TTL. If the part number begins with the number ”54”, the chip is a military-grade unit:
having a greater operating temperature range, and typically more robust in regard to allowable power supply
and signal voltage levels. The letters ”LS” immediately following the 74/54 prefix indicate ”Low power
Schottky” circuitry, using Schottky-barrier diodes and transistors throughout, to decrease power dissipation.
Non-Schottky gate circuits consume more power, but are able to operate at higher frequencies due to their
faster switching times. A few of the more common TTL ”DIP” circuit packages are shown here for
reference:

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9.1 BASIC GATES IC

Logic functions can be implemented in several ways. In the past, vacuum-tube and relay circuits performed
logic functions. Presently tiny integrated circuits (ICs) perform as logic gates. These ICs contain the
equivalent of miniature resistors, diodes, and transistors.

A popular type of IC is illustrated in the Figure above. This particular IC is called a 14-pin DIP integrated
circuit. Note that immediately counter clockwise from the notch on the IC shown is pin number 1. The pins
are numbered counter clockwise from 1 to 14 when viewed from the top of the IC. Manufacturers of ICs
provide pin diagrams similar to the one above for a 7408 IC. Note that this IC contains four 2-input AND
gates; thus it is called a quadruple 2-input AND gate. Figure below shows the IC pins numbered from 1
through 14 in a counter clockwise direction from the notch. The power connections to the IC are the GND
(pin 7) and Vcc (pin 14) pins. All other pins are the inputs and outputs to the four AND gates. The 7408 IC
is part of TTL family of logic devices. It is one of many the most popular logic devices.

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Given the logic diagram above, how do we wire a circuit using a 7408 IC? A wiring diagram for the circuit
is shown below. A 5-V power supply is used with all TTL devices. The positive (Vcc) and negative (GND)
power connections are made to pins 14 and 7. Input switches (A and B ) are wired to pins 1 and 2 of the
7408 IC. Note that, if a switch is in the up position, a logical 1 (+5V) is applied to the input of the AND
gate. At the right, a light-emitting diode (LED) and 150-ohm limiting resistor are connected to ground. If the
output at pin 3 is HIGH (+5V), current will flow through the LED. Lighting the LED indicates a HIGH, or a
binary 1, at the output of the AND gate. The LED lights only when both input switches (A and B) are at
+5V.

Manufacturers of integrated circuits also produce other logic functions. Figure below illustrates pin diagrams
for two basic TTL ICs. Figure (a) is the pin diagram for a quadruple 2-input OR gate. In other words, the
7432 IC contains four 2-input OR gates. It could be wired and tested in a manner similar to the testing of the
AND gate shown earlier. The 7404 IC shown in Figure (b) is also a TTL device. The 7404 IC contains six
NOT gates, or inverters. The 7404 is described by the manufacturer as a hex inverter IC. Note that each IC
has its power connections (V,, and GND). A 5-V dc power supply is always used with TTL logic circuits.

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Two variations of DIP ICs are illustrated below. The integrated circuit shown in Fig (a) has 16 pins with pin
1 identified by using a dot instead of a notch. The IC shown in Fig (b) is a 24-pin DIP integrated circuit with
pin 1 located immediately counter clockwise (viewed from top) from notch.

The 7408, 7432, and 7404 ICs are all from the TTL logic family. The newer complementary metal oxide
semiconductor (CMOS) family of ICs has been gaining popularity because of its low power requirements.
Logic gates (AND, OR, and NOT) also are available in DIP IC form in the CMOS family. Typical DIP ICs
might be the CMOS 74C08 quad 2-input AND gate, 74C04 hex inverter, or the 74C32 quad 2-input OR
gate. The 74CXX series of CMOS gates is not directly compatible with the TTL 7400 series of integrated
circuits.

9.2 OTHER GATES IC

A pin diagram of the 7400 IC is shown below; it is described by the manufacturer as a quadruple 2-input
NAND gate IC. Note that the 7400 IC does have the customary power connections (Vcc and GND). All
other pins are the inputs and outputs from the four 2-input NAND gates.

Three 3-input NAND gates are housed in the 7410ICwhose pin diagram is shown beside the 7400IC. This
device is described by the manufacturer as a triple 3-input NAND gate IC. NAND gates with more than
three inputs also are available. The 7400 and 7410 ICs were from the common TTL logic family.

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Manufacturers also produce a variety of NAND, NOR, and XOR gates in CMOS-type ICs. Typical NAND
gates might be the CMOS 74COO quad 2-input NAND gate, 74C30 8-input NAND gate, and 4012 dual 4-
input NAND gate DIP ICs. Some CMOS NOR gates in DIP IC form are the 74C02 quad 2-input NOR gate
and the 4002 dual 4-input NOR gate. Several exclusive-OR gates are produced in CMOS; examples are the
74C86 quad 2-input XOR gate and the 4030 quad 2-input XOR gate. Note that CMOS ICs come in both a
74COO series and a 4000 series. It must be remembered that without special interfacing, TTL and CMOS
ICs are not compatible.

9.3 COMBINATIONAL CIRCUITS

9.3.1 Encoders and Decoders
The 74147 encoder is a TTL device, which means that unconnected inputs will float HIGH.

An encoder using the CMOS technology also is available. The 74HC147 10-to-4 Line Priority Encoder is
one of many DIP ICs available from National Semiconductor Corporation in its 74HC00 series. A practical
decoder system is shown below. A BCD number is entered at the left into the 7447A decoder. The decoder
activates the proper outputs and allows the correct decimal to appear on the display. The display is a
common seven segment LED display.

9.3.2 Adders and Subtracters

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The ICs for the 4-bit parallel full adder and subtracter are shown above. Note that the subtracter is
constructed from the adder by complementing the subrahend and making the carry-in HIGH to produce the
twos complement of the subrahend. This is illustrated in the diagram between the adder and subtracter.

9.4 SEQUENTIAL CIRCUITS

7474 is an IC that implements the D-flip flop, the schematic and pin diagrams are shown below.

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9.4.1 Counters
The 74192 IC is described by the manufacturers as a TTL synchronous BCD up/down counter. A block
symbol of the 74192 IC decade counter is shown below. Note the use of dual clock (CLK) inputs. If the
count-up clock input is pulsed, the counter will count upward from 0000 to 1001 (0 to 9 in decimal). If the
count-down clock input is pulsed, the counter will count downward from 1001 to 0000 (9 to 0 in decimal).
The counter toggles on the L-to-H transition of the clock pulse.

A second counter in IC form is detailed below. A block diagram of the TTL 7493 4-bit binary counter is
shown in Fig (a). Note the use of four JK flip-flops each in the toggle mode. Inputs D, and p, are clock
inputs. Note that normal output Q of the left-hand flip-flop in Fig (b) is not connected to the clock input of
the second FF. To form a 4-bit mod-16 ripple counter, an external connection must be made from Q0 to CP1
(pin 12 to pin 1), with Q0 serving as the counter clock input. The 7493 IC has two reset inputs (MR1 and
MR2) as shown in Fig (a). Under normal use, the reset inputs of the 7493 IC must not be left disconnected
(floating). The reset pins float HIGH, which places the IC in the reset mode. While in the reset mode, the
7493 IC cannot count. The reset inputs are asynchronous and override both clocks. The CMOS version
(74HC393) is also shown afterwards.

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9.4.2 Shift Registers

Integrated-circuit manufacturers market many shift registers. The one that has been selected for description
is a universal shift register. A block logic symbol for the commercial TTL 74194 4-bit universal shift
register is shown below. The 74194 register has 10 inputs and 4 outputs. The outputs are connected to the
normal (2) outputs of each flip-flop inside the IC.

A wide variety of CMOS shift registers are available from chip manufacturers. The 74HC164 8-bit serial-in,
parallel-out shift-register IC is shown below. Information from the manufacturer's data manual is also
reproduced.

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9.5 Tutorial Questions

A. From Section 8
1. List ten factors to be considered in the design and fabrication of electronic circuits from gates ICs and
briefly explain the practical implications of any five of them.
2. Explain the design fundamentals of any TTL gate of your choice.
3. Enumerate the logic families known to you.
4. What are logic levels? Explain in relation to a logic family.
5. The digital IC technology has advanced considerably and rapidly over the years. Discuss this statement in
relation to the scale of integration from inception of ICs to the current day.
6. Differentiate between static and dynamic power dissipation as a logic parameter for ICs.
7. Digital IC Logic families can be divided into two broad categories.
a. What are these categories?
b. List three logic families under each category highlighting which ones are obsolete
c. Explain the workings of one IC family that is not currently obsolete from each category.
8. Emitter coupled logic (ECL) is the fastest of all logic families but has limited applications. Discuss this
statement in relation to the configuration of ECL and its merits and de-merits.
9. TTL and CMOS logic families are the most common in the design and fabrication of ICs today.
Compare and contrast these two families in relation to their logic parameters and typical applications.

B. From Section 9
1. What logic function is performed by the circuit illustrated below? (7432 is a Quad 2-input OR IC from the
TTL family)

2. Construct the truth table for the circuit shown below. (7400 is a Quad 2-input NAND IC from the TTL
family)

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 Computer Engineering (CPE305)- Course notes [Jan-March 2023] CPE FUOYE

3. Write the Boolean expression and construct the truth table for the circuit shown below. (7400 and 7410
are Quad 2-input and triple 3-input NAND ICs respectively from the TTL family).

4. Digital logic gate circuits are manufactured as integrated circuits typically in form of Dual-Inline-
Packages. Discuss the pin configuration of any gate IC in relation to the pin count, logic family, commercial/
military grade, other compatible ICs in the same family and non-compatible ICs from other logic families.

5. The 7483 IC is a 4-bit parallel full adder. Discuss how this can be configured to give a 4-bit parallel full
subtracter circuit showing the schematic diagram.

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