Digital System Design: Area Delay Model
Lecture 24
Professor: Neeraj Goel
Department: Computer Science Engineering
Institution: Indian Institute of Technology, Ropar
Date: [Course Module Final Lecture]
Table of Contents
1. Introduction & Course Overview
2. Hardware Implementation Mapping
3. Area Analysis
4. Delay Analysis
5. Propagation Delay Explained
6. Two-Level Logic Delay Analysis
7. Fan-in Optimization Strategy
8. Design Trade-offs & Conclusions
1. Introduction & Course Overview
Objectives of Logic Minimization
Primary Goal: Cost optimization in Boolean expression implementation
Key Question: How to represent Boolean functions with minimal hardware cost?
Challenge: Multiple equivalent expressions exist for the same Boolean function
Optimality Criteria (Previously Established)
For Sum of Products (SOP):
1. Minimize number of product terms
2. For expressions with same number of product terms → minimize literals per product
For Product of Sums (POS):
1. Minimize number of sum terms
2. For expressions with same number of sum terms → minimize literals per sum
Assumption: Inputs available in both original and complemented forms
2. Hardware Implementation Mapping
SOP to Gate Implementation
Product Term → AND Gate
- Number of literals = Number of AND gate inputs
- Number of product terms = Number of OR gate inputs
Example: AB + AC + BC
- 3 AND gates (for AB, AC, BC)
- Each AND gate has 2 inputs
- 1 OR gate with 3 inputs
Cost Metrics in Hardware
Two Primary Metrics:
1. Area: Silicon consumption for implementation
2. Delay: End-to-end propagation time
3. Area Analysis
Area Dependencies
Number of gates (primary factor)
Number of inputs per gate
Interconnections/wires (secondary factor)
General Relationship
Area ∝ (Number of Gates) × (Gate Complexity)
4. Delay Analysis
Key Terminology
Fan-in: Number of inputs to a gate
Fan-out: Number of gates driven by one output
Propagation Delay Formula
Propagation Delay = a₁ × Fan-in + a₂ × (Fan-in)² + a₃ × Fan-out
Where:
Linear dependence on fan-out
Quadratic dependence on fan-in (most critical factor)
a₁, a₂, a₃ are technology-dependent constants
Delay Characteristics
Input Impact: Severe - grows quadratically
Output Impact: Linear growth
Technology Dependence: Constants vary with manufacturing process
5. Propagation Delay Explained
Timing Diagram Concept
Input: ____/‾‾‾‾\____
↓ (propagation delay)
Output: ________/‾‾‾‾\____
Time → [Input Change] → [Output Change]
Physical Basis (CMOS Technology)
Inertial Delay: Physical resistance to state change
Capacitive Effects: Output stored in capacitors
RC Time Constant: Determines charging/discharging time
Voltage Transitions: 0→1 and 1→0 may have different delays
Uncertainty Period
Output may fluctuate during transition
Propagation delay = Maximum time after which output stabilizes
No further changes occur once inputs stabilize
6. Two-Level Logic Delay Analysis
Example Circuit Analysis
Expression: AB + AC + BC
Level 1 (AND Gates): Level 2 (OR Gate):
A ──┐ T₁ ──┐
B ──┘ AND → T₁ T₂ ──┤ OR → F
A ──┐ T₃ ──┘
C ──┘ AND → T₂
B ──┐
C ──┘ AND → T₃
Timing Analysis
Inputs: A,B,C change at t₀
Level 1: T₁,T₂,T₃ available at t₀ + Delay₁
Level 2: F available at t₀ + Delay₁ + Delay₂
Total Delay = Max(Level 1 Delays) + Max(Level 2 Delays)
Glitch Phenomenon
Cause: Different gate delays in same level
Effect: Temporary output fluctuations (spikes)
Resolution: Output stabilizes after total propagation delay
Critical Timing Rule
⚠️ Input must remain stable for entire propagation delay period
Changing inputs before delay completion causes uncertainty
Output may correspond to old or new input values
7. Fan-in Optimization Strategy
Problem: Large Fan-in Gates
4-input AND gate vs. Multi-level Implementation
Single Level (4-input AND):
A ──┐
B ──┤ 4-input AND → Output
C ──┤
D ──┘
Multi-level (2-input ANDs):
A ──┐ ┌── Output
B ──┘ AND ──┐ │
├─┘ AND
C ──┐ │
D ──┘ AND ──┘
Delay Comparison
4-input AND:
Delay = 4a₁ + 16a₂ + a₃
Multi-level (2 stages of 2-input ANDs):
Delay = 2 × (2a₁ + 4a₂ + a₃)
= 4a₁ + 8a₂ + 2a₃
Analysis Result
Multi-level implementation typically faster due to quadratic fan-in effect
Trade-off: Lower delay vs. Higher area
Stage Count: log₂(n) stages for n-input function with 2-input gates
8. Design Trade-offs & Conclusions
Conflicting Requirements
1. Two-level logic: Predictable delay, good for optimization
2. Multi-level logic: Better for high fan-in gates, reduced delay
Practical Implementation Strategy
Small fan-in: Use two-level implementation
Large fan-in: Break into multi-level stages
Threshold-based: Implementation choice depends on input count
Optimization Implications
Our minimization criteria remain valid for most cases
Hardware implementation may use multi-level internally
Appears as two-level logically, implemented as multi-level physically
Key Takeaways
1. Area and delay are fundamental hardware cost metrics
2. Fan-in has quadratic impact on delay - most critical factor
3. Two-level logic provides good baseline for optimization
4. Large fan-in requires multi-level implementation for delay optimization
5. Glitches are inevitable in combinational logic during transitions
6. Input stability is crucial for reliable operation
Note: This represents the final lecture of the logic minimization module, summarizing the relationship
between Boolean optimization and actual hardware implementation costs.
