Chapter 4.

Combinational logic technologies

© Copyright 2004, Gaetano Borriello and

Randy H. Katz 1
 Combinational Logic Technologies
n Standard gates (random logic)
q gate packages
q cell libraries
n Regular logic
q multiplexers
q decoders
n Two-level programmable logic
q PALs
q PLAs

q ROMs
The simplest way to implement logic circuits would be using standard gates. However, as
more complicated and diverse logic systems are getting required, a wealth of
implementation techniques are proposed. There are three major categories in logic
implementation technologies.

2
 Random logic
n Transistors quickly integrated into logic gates (1960s)
n Catalog of common gates (1970s)
q Texas Instruments Logic Data Book – the yellow bible
q all common packages listed and characterized (delays, power)
q typical packages:
n in 14-pin IC: 6-inverters, 4 NAND gates, 4 XOR gates
n Today, very few parts are still in use
n However, parts libraries exist for chip design
q designers reuse already characterized logic gates on chips

Again it is easy and simple to use standard gates such as NAND and AND, called
random logic. Since a single gate is not good to sell and buy, a few or several gates are
packed into a package. Right now, it is not widely used for economical reasons since
there are a lot of IC packages in the catalog.
3
 Regular logic
n Need to make design faster
n Need to make engineering changes easier to make
n MUX and DEMUX

Unlike random logic, regular logic refers to a flexible component that performs a specific
high-level function compared to primitive logic gates. Design becomes easier with these
regular logic components since each component performs a specific function. Sometimes
we can flexibly exploit the regular logic components for other purposes than its original
one.

4
 Making connections
n Direct point-to-point connections between gates
q wires we've seen so far
n Route one of many inputs to a single output - multiplexer (MUX)
n Route a single input to one of many outputs - demultiplexer (DEMUX)
control control

multiplexer demultiplexer 4x4 switch

Two popular regular logic components are MUX and DEMUX. A MUX selects one of its
data inputs to the output by the control inputs; a MUX is also called a selector. The
diagram on the left shows a 4-input MUX. Can you guess the relation between the
number of data inputs and the number of control lines? A DEMUX performs the reverse
function, often called a decoder. We can clearly see that these components perform
higher-level functions compared to logic gates
5
 Mux and demux
n Switch implementation of multiplexers and demultiplexers
q can be composed to make arbitrary size switching networks
q used to implement multiple-source/multiple-destination
interconnections

A Y A Y

B Z B Z

When we combine MUXs and DEMUXs, a switching network can be implemented.

Note that control lines are skipped here.
In this slide, there are 2X2 switching networks. By using control variables (which are
skipped), A and B can be routed to either Y or Z.

6
 Mux and demux (cont'd)
n Uses of multiplexers/demultiplexers in multi-point
connections
A0 A1 B0 B1

Sa Sb
MUX MUX multiple input sources

A B

Sum

Ss DEMUX multiple output destinations

S0 S1
Let’s see how MUX and DEMUX can be used for a logic system design. Here is a 1-bit
adder, a V-shape polygon. There are two sources for each input and two destinations for
the resulting sum. So there are total three control variables. 7
 Multiplexers (MUXs)/selectors
n Multiplexers/selectors: general concept
q 2n data inputs, n control inputs (called "selects"), 1 output
q used to connect 2n points to a single point
q control signal pattern forms binary index of input connected to
output I1 I0 A Z
A Z
0 I0 0 0 0 0
Z = A' I0 + A I1 0 0 1 0
1 I1
0 1 0 1
functional form 0 1 1 0
1 0 0 0
two alternative forms 1 0 1 1
logical form
for a 2:1 Mux truth table 1 1 0 1
1 1 1 1
Let’s look at how a MUX function can be described as a boolean expression or a truth
table. We will start with the simplest one, 2:1 MUX. There are two inputs I0 and I1 and
the control input is A. Then Z will select I0 or I1 depending on A’s value. If we tabulate
all the cases of I0 and I1, the final truth table is the one on the right.

8
 Multiplexers/selectors (cont'd)
n 2:1 mux: Z = A'I0 + AI1
n 4:1 mux: Z = A'B'I0 + A'BI1 + AB'I2 + ABI3
n 8:1 mux: Z = A'B'C'I0 + A'B'CI1 + A'BC'I2 + A'BCI3 +
AB'C'I4 + AB'CI5 + ABC'I6 + ABCI7

2 n -1
n In general: Z = S (mkIk) I0
k=0 I1
I2
q in minterm shorthand form for a 2n:1 Mux I3 8:1 Z
I4 mux
I0 I5
I1 4:1 I6
I0 2:1 I2 Z I7
Z mux
I1 mux I3
A B C
A A B
How can we express the output in a general form, regardless of the # of inputs? First of
all, n is the # of control wires. So there are total 2**n inputs. Here m_k is the k-th
minterm from the control variables.
9
 Gate level implementation of muxes
n 2:1 mux

n 4:1 mux

At the top left, an AND-OR realization of a 2:1 MUX is shown. What are the 2 data
inputs and what is the control input?

10
 Cascading multiplexers
n Large multiplexers can be made by cascading smaller ones
8:1 alternative
I0
I1 4:1 mux implementation
I2 mux
I3 I0 2:1 8:1
2:1 I1
Z mux mux
mux
I4
I5 4:1 I2 2:1
I6 mux I3 mux 4:1 Z
I7 mux
I4 2:1
I5 mux
B C A
I6 2:1
control signals B and C simultaneously choose I7
one of I0, I1, I2, I3 and one of I4, I5, I6, I7 mux

control signal A chooses which of the C A B

upper or lower mux's output to gate to Z

You can build a large scale MUX in two ways. One option is just to use a single
conventional MUX for 2**n inputs and n control lines. Or you can combine small scale
MUXs. This slide shows two cases of building an 8:1 MUX from small scale MUXs.
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 Multiplexers as general-purpose logic
n A 2n:1 multiplexer can implement any function of n variables
q with the variables used as control inputs and
q the data inputs tied to 0 or 1 1 0
q in essence, a lookup table 0 1
1 2
n Example: 0 3
F(A,B,C) = m0 + m2 + m6 + m7 4 8:1 MUX Z
F
q 0
= A'B'C' + A'BC' + ABC' + ABC 0 5
1 6
= A'B'C'(1) + A'B'C(0) 1 7
+ A'BC'(1) + A'BC(0) S2 S1 S0
+ AB'C'(0) + AB'C(0)
+ ABC'(1) + ABC(1) A B C
F = A'B'C'I0 + A'B'CI1 + A'BC'I2 + A'BCI3 + AB'C'I4 + AB'CI5 + ABC'I6 + ABCI7
This slide is very important. Actually a MUX can do more than just selection. Suppose
each input wire (one of 2**n inputs) is fixed to either 0 or 1. Depending on the control
inputs (here A,B,C), the corresponding bit will be popped up to F. This is kind of a
lookup table.
Now look at the system with a different viewpoint. Forget this is a MUX. Suppose A,B,C
are the input variables of a logic function F. When will F be true?
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 Multiplexers as general-purpose logic (cont’d)
n A 2n-1:1 multiplexer can implement any function of n variables
q with n-1 variables used as control inputs and
q the data inputs tied to the last variable or its complement
n Example:
q F(A,B,C) = m0 + m2 + m6 + m7
= A'B'C' + A'BC' + ABC' + ABC
1 0
0 1
= A'B' (C') + A'B (C') + AB' (0) + AB (1)
1 2 A B C F
0 3 0 0 0 1 C' C' 0
0 4 8:1 MUX 0 0 1 0 F
F 0 1 0 1 C' 1 4:1 MUX
0 5 C'
0 1 1 0 0 2
1 6
1 0 0 0 1 3 S1 S0
1 7 0
S2 S1 S0 1 0 1 0
1 1 0 1 1 A B
1 1 1 1
A B C
The reality is that a MUX can implement any function of n variables. Here is another
example of implementing the same logic function in a simplified way. In this variation,
one of the control variable is used as a data input of a 4:1 MUX. Now we have two
control variables A and B. Meanwhile C becomes some of the data inputs. Overall, we
have 4 cases instead 8 cases by considering F as a function of C 13
 Multiplexers as general-purpose logic (cont’d)
I0 I1 . . . In-2 In-1 F four possible
n Generalization configurations
. . . . 0 0 0 1 1 of truth table
n-1 mux control
variables . . . . 1 0 1 0 1 rows can be
expressed as
single mux data a function of In-1
variable
A B C D G 0 In-1 In-1' 1
0 0 0 0 1
1
n Example: 0 0 0 1 1
0 0 1 0 0
G(A,B,C,D) 0 0 1 1 1 D 1 0
can be realized 0 1 0 0 0
0
D 1
0 1 0 1 0 0 2
by an 8:1 MUX 0 1 1 0 1 1 3
1
0 1 1 1 1 D’ 4 8:1 MUX
1 0 0 0 1 D 5
1 0 0 1 0 D' D’ 6
choose A,B,C as 1 0 1 0 0 D’ 7
control variables 1 0 1 1 1 D
S2 S1 S0
1 1 0 0 1
D’
1 1 0 1 0
1 1 1 0 1 A B C
D’
1 1 1 1 0
Here is the generalized n-input logic function by a (n-1)-input MUX.
Depending on the output of two cases of the singled-out variable, a different data input is
attached to each minterm of the (n-1) input MUX. Reducing the MUX size is economical.
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 Demultiplexers (DEMUXs)/decoders
n Decoders/demultiplexers: general concept
q single data input, n control inputs, 2n outputs
q control inputs (called “selects” (S)) represent binary index of output
to which the input is connected
q data input usually called “enable” (G)
1:2 Decoder: 3:8 Decoder:
O0 = G • S’ O0 = G • S2’ • S1’ • S0’
O1 = G • S O1 = G • S2’ • S1’ • S0
O2 = G • S2’ • S1 • S0’
2:4 Decoder: O3 = G • S2’ • S1 • S0
O0 = G • S1’ • S0’ O4 = G • S2 • S1’ • S0’
O1 = G • S1’ • S0 O5 = G • S2 • S1’ • S0
O2 = G • S1 • S0’ O6 = G • S2 • S1 • S0’
O3 = G • S1 • S0 O7 = G • S2 • S1 • S0

There is only one data input in DEMUXs, often denoted by G, which will be carried to
one of the outputs. The control inputs are often denoted by S and the index of the control
wires. Again, for n control inputs, we have 2**n outputs.

15
 Gate level implementation of demultiplexers
n 1:2 decoders active-high active-low
enable enable
G O0 \G O0
S S
O1 O1
n 2:4 decoders
G \G O0
O0
active-high active-low
enable enable
O1 O1

O2 O2

O3 O3

S1 S0 S1 S0
This slide shows a few DEMUXs implemented by logic gates. We can add two bubbles
for each input. The reason for inserting two bubbles is to implement the DEMUX by
NOR gates
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 Cascading decoders
n 5:32 decoder
0 A'B'C'D'E' 0
q 1 x 2:4 decoder 1 1
2 2 A'BC'DE'
q 4 x 3:8 decoders 3:8 DEC3 3:8 DEC 3
4 4
5 5
6 6
7 7
S2 S1 S0 S2 S1 S0
0
F 2:4 DEC 1
2
S1 S0 3
0 0 AB'C'D'E'
A B 1 1
2 2
3:8 DEC3 3:8 DEC 3
4 4
5 5
6 6
7 ABCDE 7 AB'CDE
S2 S1 S0 S2 S1 S0

C D E C D E
By combining small scale decoders or demuxes, we can build a larger-scale demux.
Here, we have 5 control lines (A,B,C,D,E) to route the enable line, F, to one of 32 output
lines
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 Demultiplexers as general-purpose logic
n A n:2n decoder can implement any function of n variables
q with the variables used as control inputs
q the enable input is tied to 1 and
q the appropriate minterms summed to form the function

0 A'B'C'
1 A'B'C
2 A'BC' demultiplexer generates appropriate
3 A'BC minterm based on control signals
“1” 3:8 DEC 4 AB'C' (it "decodes" control signals)
5 AB'C
6 ABC'
7 ABC
S2 S1 S0

A B C
Like a MUX, a DEMUX can also perform a logic function of n variables. Here n
variables are used for the control wires of the DEMUX. Depending on the values of
control wires, a specific minterm will be asserted. Then what we need to do is ORing the
relevant minterms for each output function F.
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 Demultiplexers as general-purpose logic
(cont’d)
n F1 = A'BC'D + A'B'CD + ABCD
n F2 = ABC'D' + ABC 0 A'B'C'D'
n F3 = (A' + B' + C' + D') 1 A'B'C'D
2 A'B'CD' F1
3 A'B'CD
4 A'BC'D'
5 A'BC'D
6 A'BCD'
4:16 7 A'BCD
Enable DEC 8 AB'C'D' F2
9 AB'C'D
10 AB'CD'
DEMUX is a 11 AB'CD
minterm 12 ABC'D'
13 ABC'D
generator! 14 ABCD'
15 ABCD F3

A B C D
By using a single 4:16 DEMUX, we can implement three functions of 4 variables, with a
few more gates. 19
 Programmable logic arrays (PLAs)
n Pre-fabricated building block of many AND/OR gates
q actually NOR or NAND
q "personalized" by making/breaking connections among the gates
q programmable array block diagram for sum of products form
• • •
inputs
Sum of

OR
AND
product array
array
terms

products outputs
• • •

A PLA is a general implementation of sum of products of a logic function. We first

implement each product term (not necessarily minterm). Then the product terms will be
Ored in the next stage. So we have two generic logic arrays. Programming means
configuring connections in two arrays.
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 Enabling concept
n Shared product terms among outputs
F0 = A + B' C'
example: F1 = A C' + AB
F2 = B' C' + AB
F3 = B' C + A
input side:

personality matrix 1 = uncomplemented in term

0 = complemented in term
product inputs outputs – = does not participate
term A B C F0 F1 F2 F3
AB 1 1 – 0 1 1 0 output side:
B'C – 0 1 0 0 0 1 1 = term connected to output
AC' 1 – 0 0 1 0 0 0 = no connection to output
B'C' – 0 0 1 0 1 0
reuse of terms
A 1 – – 1 0 0 1
Let’s take some logic functions for example to illustrate how we can use an PLA for
logic implementation. There are 4 functions of three input variables. To use an PLA
systematically, it is good to write a personality matrix. The middle section indicates how
input variables are combined in the AND array and the right section shows how those
product terms are combined in the OR array.
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 Before programming
n All possible connections are available before "programming"
q in reality, all AND and OR gates are NANDs
A B C

AB

We have to look at two cross-connects: one is between inputs and AND gates and the
other is between AND gates and OR gates. We can make or break connections in those
two cross-connects. 22
 After programming
n Unwanted connections are "blown"
q fuse (normally connected, break unwanted ones)
q anti-fuse (normally disconnected, make wanted connections)
A B C

AB

B'C

AC'

B'C'

F0 F1 F2 F3
Then we have to do programming, which is the process of enabling or disabling each
cross-point. If fuses are used for each cross point, we break unwanted ones. If anti-fuses
are used, we enable the wanted ones.
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 Alternate representation for high fan-in structures
n Short-hand notation so we don't have to draw all the wires
q x signifies a connection is present and perpendicular signal is an
input to gate
notation for implementing
F0 = A B + A' B'
F1 = C D' + C' D
A B C D

AB
A'B'
CD'
C'D

AB+A'B'
CD'+C'D
For simplicity, let’s assume fuses for each crosspoint, denoted by x. Before programming,
the PLA will look like the one on the left. After programming for the required functions,
the PLA will become the one on the right. All the unwanted crosspoints are broken. 24
 PLA example
n Multiple functions of A, B, C full decoder as for memory address
q F1 = A B C bits stored in memory
A B C
q F2 = A + B + C
q F3 = A' B' C' A'B'C'
q F4 = A' + B' + C' A'B'C
q F5 = A xor B xor C A'BC'
q F6 = A xnor B xnor C A'BC
AB'C'
A B C F1 F2 F3 F4 F5 F6
0 0 0 0 0 1 1 0 0 AB'C
0 0 1 0 1 0 1 1 1
ABC'
0 1 0 0 1 0 1 1 1
0 1 1 0 1 0 1 0 0 ABC
1 0 0 0 1 0 1 1 1
1 0 1 0 1 0 1 0 0
1 1 0 0 1 0 1 0 0
1 1 1 1 1 0 0 1 1 F1 F2 F3 F4 F5
F6
Here are the six functions of three variables.
As there are three variables, total 8 minterms exist. Then all the relevant minterms of
each function will be connected to its OR gate.
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 PALs and PLAs
n Programmable logic array (PLA)
q unconstrained fully-general AND and OR arrays
n Programmable array logic (PAL)
q constrained topology of the OR array
q faster and smaller OR plane

a given column of the OR array

has access to only a subset of
the possible product terms

A little bit less programmable but faster version is PAL. In PALs, the cross-connects
between AND gates and OR gates are already fixed; the transistor logic is much simpler.
What we can control is the cross-connects between inputs and AND gates, denoted by x.
So, there is less flexibility in PALs compared to PLAs.
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 PALs and PLAs: design example
n BCD to Gray code converter
A B C D W X Y Z
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0 minimized functions:
0 1 0 0 0 1 1 0
0 1 0 1 1 1 1 0
0 1 1 0 1 0 1 0 W = A + BD + BC
0 1 1 1 1 0 1 1 X = BC'
1 0 0 0 1 0 0 1 Y=B+C
1 0 0 1 1 0 0 0 Z = A'B'C'D + BCD + AD' + B'CD'
1 0 1 – – – – –
1 1 – – – – – –
Suppose we have to design a BCD to GRAY code converter. And simplified functions
are shown in the above. Unfortunately, there are no common product terms among
outputs.

27
 PALs and PLAs: design example (cont’d)
n Code converter: programmed PLA
A B C D minimized functions:

A
W = A + BD + BC
X = B C'
BD Y=B+C
Z = A'B'C'D + BCD + AD' + B'CD'
BC

BC' not a particularly good

candidate for PLA
B
implementation since no terms
C are shared among outputs
A'B'C'D

BCD
however, much more compact
AD' and regular implementation
BCD' when compared with discrete
AND and OR gates

W X Y Z
Here, 4 functions are implemented by a single PLA. Total 10 product terms are needed to
be represented. In this case, there is no common product term that can be shared by
multiple outputs, which means PLA is not an attractive option.
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 PALs and PLAs: (cont’d) A B C D

A
n Code converter: programmed PAL BD
BC
0
BC'
0
0
0
Could be 4 product terms B
a limiting per each OR gate C
factor 0
0
A'B'C'D
BCD
AD'
Let’s consider a PAL where exactly 4 AND gates
B'CD'
are ORed for each function. Note that the maximum
# of product terms of outputs is 4 W X Y Z
As there are 4 functions, total 16 AND gates are required. For some functions, they don’t
need up to 4 product terms. Then, a FALSE term is connected to surplus AND gates. To
make a false term, just leave all the fuses intact.
29
 PALs and PLAs: design example (cont’d)
n Code converter: NAND gate implementation of PAL and
PLA

A
A B
C
B W D
D B
B C
D Z
C
A
B \D
X \B
C C
\D

Y
B

As we have seen before, an AND-OR combination is easily converted to NAND logic.

Just add two bubbles (inverters) in the middle and push them to the opposite directions.
So PALs and PLAs are actually implemented by NAND gates.

30
Activity

n Map the following functions to the PLA below:

q W = AB + A’C’ + BC’ A B C
q X = ABC + AB’ + A’B
q Y = ABC’ + BC + B’C’

W X Y

31
Activity (cont’d)

32
 Activity (cont’d)

n 9 terms won’t fit in a 7 term PLA

q can apply concensus theorem A B C
to W to simplify to: ABC
W = AB + A’C’
ABC’
n 8 terms wont’ fit in a 7 term PLA
q observe that AB = ABC + ABC’ A’C’
q can rewrite W to reuse terms: AB’
W = ABC + ABC’ + A’C’ A’B
n Now it fits BC
q W = ABC + ABC’ + A’C’
B’C’
q X = ABC + AB’ + A’B
q Y = ABC’ + BC + B’C’
n This is called technology mapping
q manipulating logic functions
so that they can use available W X Y
resources

33
 Read-only memories (ROMs)
n Two dimensional array of 1s and 0s word lines (only one
is active – decoder is
q entry (row) is called a "word" just right for this)

q width of row = word-size 1 1 1 1

q index is called an "address"
q address is input n
2 -1
q selected word is output
i word[i] = 0011
decoder
j word[j] = 1010

internal organization 0

0 n-1
Address
bit lines (normally pulled to 1 through
resistor – selectively connected to 0
by word line controlled switches)
Let’s look at the simplified structure of a ROM. A ROM is just like a look-up table
whose structure is similar to that of a DEMUX. Actually, all the minterms are present in
ROMs. Instead of the enable wire, the bits for outputs are programmed. When an address
is coming in, its stored data (bits) should be brought up. An address to retrieve each
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 ROMs and combinational logic
n Combinational logic implementation (two-level canonical
form) using a ROM
F0 = A' B' C + A B' C' + A B' C
F1 = A' B' C + A' B C' + A B C
F2 = A' B' C' + A' B' C + A B' C'
F3 = A' B C + A B' C' + A B C'
A B C F0 F1 F2 F3
0 0 0 0 0 1 0 ROM
0 0 1 1 1 1 0 8 words x 4 bits/word
0 1 0 0 1 0 0
0 1 1 0 0 0 1
1 0 0 1 0 1 1
1 0 1 1 0 0 0
1 1 0 0 0 0 1 A B C F0F1F2F3
1 1 1 0 1 0 0 address outputs
truth table block diagram
So, a number of functions can be implemented together by using a single ROM. Here,
total 32 bits are stored and 4 bits constitute a word. Actually, we don’t need those
boolean expressions. We just need to fill in the ROM by the truth table and that’s it.
35
 ROM structure
n Similar to a PLA structure but with a fully decoded AND array
q completely flexible OR array (unlike PAL)
n address lines
• • •
inputs

memory
decoder 2n word
array
n
(2 words
lines
by m bits)

outputs
• • •

m data lines
A ROM is similar to a PLA, but for n inputs, there are always 2**n AND gates.
Depending on the output values, what we need to do is to control transistors of
crosspoints (or bits)

36
 ROM vs. PLA/PAL
n ROM approach advantageous when
q design time is short (no need to minimize output functions)
q most input combinations are needed (e.g., code converters)
q little sharing of product terms among output functions
n ROM problems
q size doubles for each additional input
q can't exploit don't cares
n PLA approach advantageous when
q design tools are available for multi-output minimization
q there are relatively few unique minterm combinations
q many minterms are shared among the output functions
n PAL problems
q constrained fan-ins on OR plane

By using ROMs, we can implement a number of functions quickly at the cost of large
size (e.g. 2**n AND gates). Also, we cannot utilize DC terms. We can say that if we have
to use many minterms, the ROM approach is the best. If there are many shared product
terms among outputs, PLA may be good. If the number of product terms for each output
is small, PAL may be the best approach
37
 Regular logic structures for two-level logic
n ROM – full AND plane, general OR plane
q cheap (high-volume component)
q can implement any function of n inputs
q medium speed
n PAL – programmable AND plane, fixed OR plane
q intermediate cost
q can implement functions limited by number of terms
q high speed (only one programmable plane that is much smaller than
ROM's decoder)
n PLA – programmable AND and OR planes
q most expensive (most complex in design, need more sophisticated tools)
q can implement any function up to a product term limit
q slow (two programmable planes)

This slide shows a pro-con list of ROM, PAL, PLA technologies. ROMs may be the
cheapest due to mass production. In PALs, the OR array is fixed; it takes less time in the
OR array. However, no shared product terms is supported in PALs. PLA is the most
flexible and expensive option among logic implementation technologies. 38
 Combinational logic technology summary
n Random (fixed) logic
q Single gates or in groups
q conversion to NAND-NAND and NOR-NOR networks
q transition from simple gates to more complex gate building blocks
q reduced gate count, fan-ins, potentially faster
q more levels, harder to design
n Time response in combinational networks
q gate delays and timing waveforms
q hazards/glitches (what they are and why they happen)
n Regular logic
q multiplexers/decoders
q ROMs
q PLAs/PALs
q advantages/disadvantages of each
In chapter 4, we looked at a few programmable structures that facilitate the
implementations of two-level logic functions. Each structure has its own pros and cons.

39