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Digital Logic

This document outlines the examination structure for a Bachelor of Engineering course in Digital Logic at Pokhara University for Fall 2024. It includes various questions covering topics such as digital and analog systems, binary arithmetic, Boolean algebra, combinational and sequential circuits, and counters. The exam consists of multiple sections requiring candidates to demonstrate their understanding and application of digital logic concepts.

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41 views2 pages

Digital Logic

This document outlines the examination structure for a Bachelor of Engineering course in Digital Logic at Pokhara University for Fall 2024. It includes various questions covering topics such as digital and analog systems, binary arithmetic, Boolean algebra, combinational and sequential circuits, and counters. The exam consists of multiple sections requiring candidates to demonstrate their understanding and application of digital logic concepts.

Uploaded by

lalitpal091091
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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P O K H A R A U N IV E R S IT Y

Level: Bachelor Semester: Fall Year : 2024


Programme: BE Full Marks : 100
Course: Digital Logic Pass Marks : 45
Time : 3 hrs.
Candidates are required to give their answers in their own words as far
as practicable.
The figures in the margin indicate full marks.
Attempt all the questions.
1. a) Describe about Digital and Analog System. Differentiate between 5
the Digital and Analog system.
b) Subtract the following using r’s complement: 5
i. (3085)10 – (2040)10
ii. (11011)2 – (1010)2
c) Show your familiarization to weighted and non-weighted code with 5
example. Write excess 3 code for decimal digits and justify it as a
self-complementing code.
2. a) Perform the following conversions: 5
i. (457)8 = (?)BCD
ii. (100101)2 = (?)Gray
iii. (101011.11010)2 = (?)8, (?)16
iv. (1010)excess 3 = (?)84-2-1
b) What is Universal gate? Draw and explain about all the basic gates 5
that can be derived from NAND gate.
c) Simplify the following expression using Boolean algebra. 5
i. A’BC+ABC’+A’B’C’+ABC+A’BC’
ii. (A+B)’.C+(A+BC’)+(A’+B)(A+C’)
3. a) Using k-map simplify the following Boolean function and 8
implement using Universal gate.
𝐹 = ∑(1,2,3,6,7,9,11,14) and 𝑑𝑜𝑛’𝑡 𝑐𝑎𝑟𝑒 (𝑑) = ∑(4,10,15).
b) Design a combinational circuit that converts 2421 code to 84-2-1 7
code.
OR
Construct a Full Adder Circuit using two Half Adder and an OR
Gate.
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4. a) Why De-Multiplexer is used? Implement F(A,B,C,D) = 8
∑(1,2,4,7,8,10,12,14) using 8 to 1 Multiplexer.
OR
Write the logical expression for two bit magnitude comparator and
Design a single bit magnitude comparator with all the logical
diagrams.
b) A combinational circuit is defined by the function, F1 (A, B, C) = ∑ 7
(3, 5, 6, 7), F2 (A, B, C) = ∑ (0, 2, 4, 6) implement by using PLA
with program table.
5. a) From the following state diagram, design a sequential circuit using 8
SR flip flops:

b) Differentiate between Flip-flop and Latch. Explain the operation of 7


clocked T flip-flop with the help of its logic diagram, characteristic
table, characteristic equation and excitation table.
6. a) What is counter? Design a 3 bit asynchronous binary up counter 8
using JK Flip-flop.
b) Design Arithmetic Logic Unit (ALU) that performs eight Arithmetic 7
operations and four different logical operations.
7. Write short notes on: (Any two) 2×5
a) Parity checker
b) Shift Register
c) Processor unit

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