Lecture 2:

Fundamental Concepts

Pangun Park
Chungnam National University
Information Communications Engineering

Some materials from

“Embedded Software Essentials” by Alex Fosdick
“Embedded Systems – Shape the world” by Jonathan Valvano and Ramesh Yerraballi
1
 Contents
§ Embedded System Development Platform
§ Processor and Memory
§ Microcontroller / Architecture
§ Four Types of Memories
§ Programming Embedded Systems
§ I/O Ports
§ Number representation
§ IDE Keil and Launchpad

Pangun Park (CNU) 2

Embedded System Development Platform
Embedded System Development Platform

Print Circuit Board (PCB)

Processor(s)
Power
Host Machine Chapter 1
SPMU296 – April 2013

Programmer Internal External Board Overview

SW Memory External
Code Debugger External
Hardware
Tools The Tiva™ C Series TM4C123G LaunchPad Evaluation Board (EK-TM4C123GXL) is a low-cost

Hardware
evaluation platform for ARM® Cortex™-M4F-based microcontrollers. The Tiva C Series LaunchPad design
highlights the TM4C123GH6PMI microcontroller USB 2.0 device interface, hibernation module, and motion

Hardware
control pulse-width modulator (MC PWM) module. The Tiva C Series LaunchPad also features
programmable user buttons and an RGB LED for custom applications. The stackable headers of the Tiva
C Series TM4C123G LaunchPad BoosterPack XL interface demonstrate how easy it is to expand the
functionality of the Tiva C Series LaunchPad when interfacing to other peripherals on many existing
BoosterPack add-on boards as well as future products. Figure 1-1 shows a photo of the Tiva C Series
LaunchPad.

Figure 1-1. Tiva C Series TM4C123G LaunchPad Evaluation Board

Power Select USB Connector
Switch (Power/ICDI) Green Power LED Tiva
TM4C123GH6PMI
Microcontroller

Software Engineer’s Tools USB Micro-A/-B

Connector
(Device)
Reset Switch

RGB User LED

Tiva C Series

The host machine contains our Build Environment

LaunchPad
BoosterPack XL
Interface (J1, J2, J3,
Tiva C Series
and J4 Connectors)
LaunchPad
BoosterPack XL
Tiva
Interface (J1, J2, J3,
TM4C123GH6PMI
and J4 Connectors)
Microcontroller

MSP430 MSP430
LaunchPad-Compatible LaunchPad-Compatible
BoosterPack Interface BoosterPack Interface

User Switch 1 User Switch 2

Tiva, MSP430, Code Composer Studio are trademarks of Texas Instruments.

Cortex is a trademark of ARM Limited.
ARM, RealView are registered trademarks of ARM Limited.
Microsoft, Windows are registered trademarks of Microsoft Corporation.
All other trademarks are the property of their respective owners.

4 Board Overview SPMU296 – April 2013

Submit Documentation Feedback

Pangun Park (CNU)

Copyright © 2013, Texas Instruments Incorporated

3
Embedded System Development
Embedded PlatformPlatform
System Development

Print Circuit Board (PCB)

Processor(s)
Power
Host Machine Chapter 1
SPMU296 – April 2013

Programmer Internal External

Board Overview
SW Memory External
Code Debugger External
Hardware
Tools The Tiva™ C Series TM4C123G LaunchPad Evaluation Board (EK-TM4C123GXL) is a low-cost

Hardware
evaluation platform for ARM® Cortex™-M4F-based microcontrollers. The Tiva C Series LaunchPad design
highlights the TM4C123GH6PMI microcontroller USB 2.0 device interface, hibernation module, and motion

Hardware
control pulse-width modulator (MC PWM) module. The Tiva C Series LaunchPad also features
programmable user buttons and an RGB LED for custom applications. The stackable headers of the Tiva
C Series TM4C123G LaunchPad BoosterPack XL interface demonstrate how easy it is to expand the
functionality of the Tiva C Series LaunchPad when interfacing to other peripherals on many existing
BoosterPack add-on boards as well as future products. Figure 1-1 shows a photo of the Tiva C Series
LaunchPad.

Figure 1-1. Tiva C Series TM4C123G LaunchPad Evaluation Board

Power Select USB Connector
Switch (Power/ICDI) Green Power LED Tiva
TM4C123GH6PMI
Microcontroller

Software Engineer’s Tools USB Micro-A/-B

Connector
(Device)
Reset Switch

RGB User LED

Tiva C Series
LaunchPad
BoosterPack XL
Interface (J1, J2, J3,
Tiva C Series
and J4 Connectors)
LaunchPad
BoosterPack XL
Tiva
Interface (J1, J2, J3,
TM4C123GH6PMI
and J4 Connectors)
Microcontroller

MSP430 MSP430
LaunchPad-Compatible LaunchPad-Compatible
BoosterPack Interface BoosterPack Interface

User Switch 1 User Switch 2

Tiva, MSP430, Code Composer Studio are trademarks of Texas Instruments.

Cortex is a trademark of ARM Limited.
ARM, RealView are registered trademarks of ARM Limited.
Microsoft, Windows are registered trademarks of Microsoft Corporation.
All other trademarks are the property of their respective owners.

Pangun Park (CNU)

4 Board Overview SPMU296 – April 2013
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
4
 Printed Circuit Board Example

Printed Circuit Board Example

Printed Circuit
Board
Power
System

On-board
Debugger
Programmer
System

Processor
Host Machine

SW
Code Tools

Pangun Park (CNU) 5

 Software Tools

Source Files usually

mostly in High Level
Compiler Toolchain
Languages Architecture Specific
Software Tools Machine Code
*.c
*.c
*.c Compiler Executable
*.h Toolchain File

Version Executable
IDE
Control Loader

Integrated development environment (IDE)

• It is a software application that provides comprehensive facilities to computer
programmers for software development. An IDE normally consists of at least
a source code editor, build automation tools, and a debugger.

Pangun Park (CNU) 6

 Contents
§ Embedded System Development Platform
§ Processor and Memory
§ Microcontroller / Architecture
§ Four Types of Memories
§ Programming Embedded Systems
§ I/O Ports
§ Number representation
§ IDE Keil and Launchpad

Pangun Park (CNU) 7

ntral Processing Unit (CPU)
Processor
PU performs computation work
§ Processor
Ø Incorporating the functions of CPU on a single CPU
integrated circuit
entral Processing Unit contains: Registers
§ Central Processing Unit contains:
RegistersØ Registers
ALU
• Special• Purpose
Special Purpose Interrupt
• General• General
Purpose Purpose Controller
Ø Arithmetic Logic Unit (ALU)
Arithmetic Logic Unit (ALU) Debug
• Combinational digital electronic circuit that performs
Interrupt Controller
arithmetic and bitwise operations on integer binary
numbers
Debug
Ø Interrupt Controller
Ø Debug

Pangun Park (CNU) 8

 Memory
§ Bit – Building Block of Memory
Memories Data
Address

ØStores 1 piece of Boolean information (0 or 1)

0xFF
• Bit– –8 Building
§ Byte Bits Block of Memory 0xFE
• Stores 1 piece of Boolean information (0 or 1) …
Ø Usually minimum unit for access 0x08
• Byte – 8 Bits 256 Bytes
0x07
0x06
• Usually minimum unit for access Of Memory 0x05
0x04
0x03
§ Memory Scale Examples: 0x02
0x01
Memory Scale Examples:
Ø Data• Centers à PetaBytes
Data Centers PetaBytes
0x00

Ø Personal Computers
• Personal à MegaBytes
Computers – TeraBytes
MegaBytes – TeraBytes 1 Byte
1 Bit
• Embedded Systems KiloBytes - MegaBytes
Ø Embedded Systems à KiloBytes - MegaBytes

Pangun Park (CNU) 9

 Memory Models

Memory Models
Memory Models Address
Data Address
Data
Address
Data Address Byte Byte Byte Byte 0x00000000
Data 0 1 2 3
Byte Byte Byte Byte 0x00000000
0xFF 0
Byte 1
Byte 2
Byte 3
Byte 0x00000004
0xFF
0xFE 0
Byte 1
Byte 2
Byte 3
Byte 0x00000004
0xFE 0
Byte 1
Byte 2
Byte 3
Byte
… 0x00000008
0
Byte 1
Byte 2
Byte 3
Byte
…
0x08 0x00000008
0x08
0x07 4 Giga Bytes 0 1 2 3
256 Bytes 0x07 4OfGiga Bytes
Memory
256 Bytes 0x06
Of Memory 0x06
0x05 Of Memory
(232 Bytes) …
Of
(2Memory
8 Bytes) 0x05
0x04 32
(2 Bytes) …
Increments
Increments
by 4 Bytes
(28 Bytes) 0x04
0x03
by 4 Bytes
0x03
0x02
0x02
0x01
0x01
0x00 Byte Byte Byte Byte
0x00 0
Byte 1
Byte 2
Byte 3
Byte 0xFFFFFFFC
1 Byte 0 1 2 3 0xFFFFFFFC
1 Byte 1 Bit 32 bits wide
1 Bit 32 bits wide

Pangun Park (CNU) 10

 Memory Hierarchy
§ Computer systems contain a mixture of memories
§ Memory considerations technology

Memory
Ø Capacity
Hierarchy Expensive, Fast
(low latency),
Power
Ø Small Capacity

• Computer Systems contain a

Ø Speed/Latency
Registers
Used in
Embedded
mixture of memories
Ø Price Cache Systems
(L1/L2/L3)

• Memory considerations RAM

(SRAM/DRAM)
Technology
• Capacity Flash/EEPROM Not Used in
• Power Embedded
• Speed/Latency Systems
HDD (Hard Drives)
• Price
Cheap, Slow
Tape (high latency),
Large Capacity

Pangun Park (CNU) 11

 Memory Sizes
§ Manufacturers release multiple
Memory Sizes
chips from a family with
varying features and memory
• Manufacturers
sizes release multiple chips
from a Øfamily
Flash &with
SRAMvarying features
and §memory sizes different
Accommodates
applications
• Flash & SRAM with a different
chip cost

• Accommodates different applications

with a different chip cost
Different KL2x Chips have:
Different•SRAM
KL2x Chips
Rangeshave:
from 4 KB – 32 KB
• SRAM
•FLASHRanges
Rangesfrom
from432KBKB– –32256
KBKB
• FLASH Ranges from 32 KB – 256 KB

Pangun Park (CNU) 12

Capacity
acity Capacity

Capacity: the amount

§ Capacity: of storage
the amount a memory
of storage cancan
a memory hold
hold
city: the amount of storage a memory can hold
• Embedded Systems Systems
Ø Embedded do NOTdoneed
NOTa need
lot ofa memory, they need
lot of memory, optimized
they need optimized
bedded Systems do NOT need a lot of memory, they need optimized
performance
performance
ormance
Capacity ≠ Performance
Capacity ≠ Performance
ncreasing capacity increases the complexity of design and size
§ Increasing capacity increases the complexity of design and size
sing capacity
• Physical increases
size and the
connection complexity
circuitry of design
(potentially) and size
Ø Physical size and connection circuitry (potentially)
sical sizetoand
You want LIMITconnection circuitry (potentially)
size, power & cost of Capacity = Size = Power = Cost
nt to LIMIT
system
wer & cost of Capacity = Size = Power = Cost
ystem
We want to LIMIT size, power & cost of system

Pangun Park (CNU) 13

 Volatility
Volatility
§ Volatility: The ability for memory to hold data without power
• Volatility:
Ø Volatile The ability
Memory for memory
– Loses data whento holdremoved
power data without power
• Volatile Memory – Loses data when power removed
Ø Non-Volatile – Retains data when power is removed
• Non-Volatile – Retains data when power is removed

Volatility
Volatile Memories:
• SRAM
Non-Volatile Memories:
• ROM/PROM/EPROM/EEPROM
• DRAM • Flash
• Volatility:
• SDRAMThe ability for memory to hold
• Diskdata
1 without power
• Volatile Memory
• Register – Loses data when power
(most) removed
• Tape 1
• Non-Volatile – Retains data when power is removed
1Not used in modern design
Many pros and cons to the
Non-Volatile Memories:different technologies
• ROM/PROM Programmable only once

Exhibits endurance issues,

• EPROM/EEPROM/Flash limited number of write-erase
cycles

Pangun Park (CNU) 14

 Write Endurance
Write
• Endurance: Non-volatile Endurance memories have a limited
semiconductor
number of write-erase cycles before failure
§ Endurance: Non-volatile semiconductor memories have a limited
number of write-erase cycles before failure
Write Endurance
§ Programmable Memory Evolution:
Programmable Memory Evolution:
• Endurance:
ROM Non-volatile
PROM semiconductor
EPROM memories
EEPROM have aFlash
limited
number of write-erase cycles before failure

Programmable ONLY once

Programmable Memory Evolution:
ROM PROM EPROM EEPROM Flash

Erasable (UV exposure)

and Programmable Multiple
times

Pangun Park (CNU) 15

 • Endurance: Non-volatileWrite
semiconductor
Endurance memories have a limited
number of write-erase cycles before failure
§ Endurance: Non-volatile semiconductor memories have a limited
number of write-erase cycles before failure
Write Endurance
§ Programmable Memory Evolution:
Programmable Memory Evolution:
• Endurance:
ROM Non-volatile
PROM semiconductor
EPROM memories have a limited
EEPROM Flash
number of write-erase cycles before failure
Electrically Erasable and
Programmable Many times
Programmable Memory Evolution:
ROM PROM EPROM EEPROM Flash
Flash has an Endurance
lasting 10,000 to 100,000+
Write-Erase Cycles

Pangun Park (CNU) 16

 Memory Access
§ Random Access: Allows for access to any part of memory given
the address of that location
Ø Random Access Memory (RAM) – SRAM/DRAM
§ Access Security: Require credentials to Read/Write parts of
memory
Ø Read-Only Memory (ROM) – No ability to write without extra permissions or
Memory Comparison
process

SRAM Flash (as Read-Only Memory)

• Simple Read/Write Process • Complex Read/Write process
• No Access Security • Secure Write Access
• Byte level read/write • Page level read/write
• Volatile • Non-Volatile
• No write/erase endurance • Endurance issues (Limited
issues Write/erase cycles)

Pangun Park (CNU) 17

 Latency
§ Latency: Time it takes for memory to respond to a read/write
request
§ Code and data need to be read/written to memory
Ø Assembly instructions are read
Ø Instruction operands need to be read
Ø Instruction results need to written
§ Any data read/written interacts with the CPU, bus controller, bus,
memory controller, & memory

Pangun Park (CNU) 18

 Tradeoffs

Tradeoffs
§ Want memory with:
Off-Chip Memories
Ø High Capacity Cheap,
• Want memory with: High latency,
Ø Low Latency Large Capacity
• High Capacity
Ø Low Power
• Low Latency On-Chip Memories
• Low
Ø High Reliability
Power
• High Reliability
§ Usually cannot
Expensive, External Memory
get all of these
…but Low latency, (Disc, Tape)

without high cost!!! Small Capacity,

Flash
Usually cannot
get all of these
without high cost!!! CPU Layer
RAM
Layer 1 2
Registers Cache Cache

Pangun Park (CNU) 19

 Contents
§ Embedded System Development Platform
§ Processor and Memory
§ Microcontroller / Architecture
§ Four Types of Memories
§ Programming Embedded Systems
§ I/O Ports
§ Number representation
§ IDE Keil and Launchpad

Pangun Park (CNU) 20

 Microprocessor (MPU) vs Microcontroller (MCU)

Pangun Park (CNU) 21

 Microcontroller
Microcontroller Components/Architecture
Clocks
Memory
CPU
Registers RAM Flash

Bus Controller
ALU
Interrupt
Controller

Debug Peripherals Ports (I/O)

Power Management

§ Software is an ordered sequence of very specific instructions that are stored in

memory, defining exactly what and when certain tasks are to be performed.
§ Processor executes the software by retrieving and interpreting these instructions
one at a time.
Ø Multipurpose, clock driven, register based, digital-integrated circuit which accepts binary
data as input, processes it according to instructions stored in its memory, and provides
results as output.

Pangun Park (CNU) 22

 Microcontroller /Architecture
§ Memory
Ø Non-Volatile (ROM, EPROM, EEPROM, Flash)
• For storing the software and fixed constant data
Ø Volatile (RAM (DRAM, SRAM))
• For storing temporary information
§ Port is a physical connection between the computer and its outside world.
Ø Ports allow information to enter and exit the system.
Ø Ports are I/O ports, I/O devices, interfaces, or sometimes just devices
Ø Memory-mapped vs. I/O-instructions (I/O-mapped)
Ø Parallel ports, serial ports, timers, digital to analog converters (DAC), and analog to
digital converters (ADC)
Ø Interface is defined as the hardware and software that combine to allow the computer to
communicate with the external hardware.
§ Bus is a collection of wires used to pass information between modules.

Pangun Park (CNU) 23

 General Embedded System Architecture

Computer Bus

Processor
Input Input
ports External Physical signals
RAM circuits devices
Output Output
ports signals
ROM

Address Control
Data

Pangun Park (CNU) 24

 ARM Cortex M4
§ Harvard architecture
Ø Different busses for instructions and data
§ ARM Cortex M4
Ø The Cortex-M instruction set combines the high performance typical of a 32-bit
processor with high code density typical of 8-bit and 16-bit microcontrollers.

Harvard architecture of an
ARM® Cortex-M-based von Neumann architecture
microcontroller.

Pangun Park (CNU) 25

 Harvard Architecture of ARM® Cortex-M-based Microcontroller.

Microcontroller System bus

ARM® CortexTM-M
processor
Input
PPB ports
Internal
Advanced
peripherals High-perf Output
Bus ports
Instructions
Flash ROM Data
ICode bus DCode bus RAM

Pangun Park (CNU) 26

 Contents
§ Embedded System Development Platform
§ Processor and Memory
§ Microcontroller / Architecture
§ Four Types of Memories
§ Programming Embedded Systems
§ I/O Ports
§ Number representation
§ IDE Keil and Launchpad

Pangun Park (CNU) 27

 Memory Interfaces

Memory Interfaces
§ CPU Reads or Writes data to Memory through Bus and Memory
Controllers
Requires or
• CPUØ Reads Address,
WritesData,
dataandto
Read/Write
Memorysignal
through Bus and Memory
Controllers
• Requires Address, Data, and Read/Write signal Memory

____
Read/Write
CPU

Memory Controller
Bus Controller
Registers Data

Address

ALU
Strobe

Enable

Pangun Park (CNU) 28

 Choosing a Platform
Choosing a Platform
§ • Executable
Executable Program
Programconsists
consistsofofprogram
programcode and
code program
and data
program data
compiled for
compiled for aa particular
particulararchitecture
architectureand
andplatform
platform

Flash
Linker CPU
File
SRAM

Command *.c
*.c Compiler &
SRCS Executable
Line Options Linker Peripherals GPIO

*.c
*.c Microcontroller
libs
Build System

Pangun Park (CNU) 29

 Choosing a Platform
Choosing a Platform
§ Executable Program consists of program code and program data
• Executable Program consists of program code and program data
compiled for a particular architecture and platform
compiled for a particular architecture and platform

Flash
CPU
Linker
File SRAM

Command *.c
*.c Compiler &
SRCS Executable Peripherals GPIO
Line Options Linker
Microcontroller
*.c
*.c
libs
Build System

Ø Platform - The underlying Integrated Circuit (IC) and the components

surrounding the CPU (Peripherals)

Pangun Park (CNU) 30

 Choosing a Platform
§ Architecture Families have many different chip sets
Ø ARMv6-M vs ARMv7-M vsARMv8-M
§ These have the same Architecture (ARM) but different memory
tform size and peripheral support
Microcontroller
itecture Families have many CPU Flash
rent chip sets
Registers
L24z vs. KL25z vs KL26z
SRAM

se have the same Architecture

M) but different memory size
Peripherals GPIO
peripheral support
Registers Registers

Platform Dependent
Platform
Pangun Park (CNU) Dependent 31
 Memory
§ Four types of storage needed for a program
Ø Code Memory

mory Ø
Ø
Data Memory
Runtime State of Program (Register Memory – Internal to chip)
Ø External
types of stoage neededMemory
for a(ifprogram
applicable) Microcontroller
de Memory CPU Code
Memory
a Memory Registers
ntime State of Program
Data
Memory

Peripherals GPIO

Registers Registers

Pangun Park (CNU) 32

 Memory
Memory
§ Three types of storage needed for a
program
• Three types of stoage needed for a program Microcontroller
• ØCode
CodeMemory
Memory CPU Flash
• ØData
DataMemory
Memory Registers
• Runtime State of Program
Ø Runtime State of Program (Register
SRAM
Memory – Internal to chip)
• Compilation tracks and maps memory from
Ø External
program code Memory (if applicable)
and program data into
§segments
Compilation tracks and maps Peripherals GPIO
•memory
Code Segment
from(Flash)
program code and Registers Registers
•program
Data Segment
data(SRAM)
into segments >
Specified in the Linker Filein
Specified
Ø the Linker File
Code Segment (Flash)
Ø Data Segment (SRAM)

Pangun Park (CNU) 33

 Memory
§ Three types of storage needed for a program
• Code Memory
• Data Memory
• Runtime State of Program (Register Memory – Internal to chip)

mory§ • External Memory (if applicable)

The CPU and peripherals contain register memory
ypes of stoage needed
Ø CPU for a program
Registers Microcontroller
e Memory • General Purpose CPU Code
Memory
a Memory • Special Purpose
Registers
time State of
Ø Program
Peripheral Registers
Data
Memory
U and peripherals contain register
y
U Registers Peripherals GPIO
General Purpose Registers Registers
Special Purpose
pheral Registers
Pangun Park (CNU) 34
 Memory
§ Flash and SRAM memory require a controller to manage interface
to CPU
§ Internal Bus also has a controller
§ External memory can be added if more memory is needed
Memory
Ø EEPROM
• Flash and SRAM memory

Controller
CPU

Flash
require a controller to Flash
manage interface to CPU

Controller
Bus Controller

SRAM
• Internal Bus also has a SRAM
controller

• External memory can be Peripherals SPI GPIO

Microcontroller
added if more memory is
needed
External EEPROM
• EEPROM
Connected with SPI
EEPROM
controlled GPIO

Pangun Park (CNU) 35

 Contents
§ Embedded System Development Platform
§ Processor and Memory
§ Microcontroller / Architecture
§ Four Types of Memories
§ Programming Embedded Systems
§ I/O Ports
§ Number representation
§ IDE Keil and Launchpad

Pangun Park (CNU) 36

 Programming Embedded Systems
Programing Embedded Systems
§ Executable Program consists of program code and program data
• Executable Program
compiled for consists
a particular of program
architecture code
and and program data
platform
compiled for a particular architecture and platform
Linker
File Flash
CPU

Command *.c
*.c Compiler &
SRCS Executable SRAM
Line Options Linker

*.c Peripherals GPIO

*.c
libs
Build System Microcontroller

Installation and Testing is needed!!!

Pangun Park (CNU) 37

Memory Map Memory Map
MemoryMap:
•§ Memory Map:Provides
Providesa memory
a memory address
address to physical
to physical device
device
mappingwithin
mapping withinananaddress
addressspace
spacefor
foruse
use in
in programming
programming

Mapped Components (Memory, Peripherals, System Config, etc)

Address Space
(Ranges for
each device)

Pangun Park (CNU) 38

 Memory Address Space TM4C123
§ Memory map of the TM4C123.
Ø 32 bits address mode
No use: empty space -> return “error”
0x0000.0000
256k Flash ROM: code, constant, etc
ROM 0x0003.FFFF
0x2000.0000
32k RAM RAM: data, variable, stack, etc
0x2000.7FFF

0x4000.0000 Device register

I/O ports
0x400F.FFFF Memory-mapped I/O
(address, bit) -> (Port, Pin)
0xE000.0000
Internal I/O
PPB 0xE004.1FFF

Each location holds “8 bits” information.

Pangun Park (CNU) 39

 CPU Registers
§ General purpose store operation operands

CPU§ Registers
Ø R0-R12
Special purpose track and control CPU state
General Purpose store
operation operands
• R0-R12

Special Purpose Track and

Control CPU state
General Purpose Registers

General Purpose Registers

Special Purpose Registers
Special Purpose Registers

Pangun Park (CNU) 40

 Register Contents

Register Contents
§ Register data constantly changes
Data is loaded in from memory
Ø
SRAM
CPU
Ø Results are stored back to memory Load into R4
• Register data constantly changes
§ Application Binary Interface (ABI)
• Data is loaded in from memory
provides architecture details to
• Results are stored
Compiler back to
/ Software memory
Programmer
§ Example Assembly relative load:
• Application Bus Interface
ldr Binary
r1, [r7,#8]Interface (ABI)
provides architecture
LDR rn [pc, #offsetdetails topool]
to literal
Compiler / Software Programmer
; load register n with one word
; from the address [pc + offset] Store from R10
Example Assembly relative load/store:
ldr r1, [r7,#8]
str r1, [r7,#8]

Pangun Park (CNU) 41

 Contents
§ Embedded System Development Platform
§ Processor and Memory
§ Microcontroller / Architecture
§ Four Types of Memories
§ Programming Embedded Systems
§ I/O Ports
§ Number representation
§ IDE Keil and Launchpad

Pangun Park (CNU) 42

 Memory I/O Ports and Interfacing
§ Port• types
Three types of stoage needed for a program Microcontroller
• Code
Ø Input portMemory
is hardware on the CPU Code
Memory
• Data Memory
microcontroller that allows information Registers
• Runtime
about Stateworld
the external of Program
to be entered into
Data
the computer. Memory

Ø Output port to send information out to the

external world. Peripherals GPIO
Ø Most of the pins on a microcontroller chip Registers Registers
are input/output ports.

§ Interface is defined as the collection of

the I/O port, external electronics,
physical devices, and the software, which
combine to allow the computer to
communicate with the external world.

Pangun Park (CNU) 43

 I/O Ports and Interfacing

§ I/O interfaces into four categories

Ø Parallel - binary data are available simultaneously on a group of lines
Ø Serial - binary data are available one bit at a time on a single line
Ø Analog - data are encoded as an electrical voltage, current, or power

Ø Time - data are encoded as a period, frequency, pulse width, or phase shift

Pangun Park (CNU) 44

 Ports on the TM4C123

Architecture of
TM4C123
microcontroller.

Pangun Park (CNU) 45

 TM4C123 Architecture
Cortex M4 Systick
System Bus Interface NVIC

GPIO Port A GPIO Port B

PA7 PB7
PA6 Four PB6
PA5/SSI0Tx Eight PB5
PA4/SSI0Rx UARTs I2Cs PB4
PA3/SSI0Fss PB3/I2C0SDA
PA2/SSI0Clk Four PB2/I2C0SCL
PA1/U0Tx CAN 2.0 PB1
SSIs
PA0/U0Rx PB0

PC7 GPIO Port C GPIO Port D PD7

PC6 PD6
PC5 USB 2.0 Twelve PD5
PC4 Timers PD4
PC3/TDO/SWO PD3
PC2/TDI JTAG Six PD2
PC1/TMS/SWDIO 64-bit wide PD1
PC0/TCK/SWCLK PD0

GPIO Port E GPIO Port F

PE5
PE4 ADC Two Analog PF4
PE3 2 channels Comparators PF3
PE2 12 inputs PF2
PE1 12 bits Two PWM PF1
PE0 Modules PF0

Advanced High Performance Bus Advanced Peripheral Bus

Pangun Park (CNU) 46

 Contents
§ Embedded System Development Platform
§ Processor and Memory
§ Microcontroller / Architecture
§ Four Types of Memories
§ Programming Embedded Systems
§ I/O Ports
§ Number representation
§ IDE Keil and Launchpad

Pangun Park (CNU) 47

 C-Data Types
C-Data Types
C-Data Types

1 Byte = 8 Bits
1 Byte = 8 Bits

𝑏7 𝑏6 𝑏5 𝑏4 𝑏3 𝑏2 𝑏1 𝑏0
𝑏7 𝑏6 𝑏5 𝑏4 𝑏3 𝑏2 𝑏1 𝑏0

Most Least
Most Least
Significant Bit Significant Bit
Significant Bit Significant Bit
(MSb) (LSb)
(MSb) (LSb)

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 Binary number of Systems
§ Most of the binary numbers stored in the computer will have 8, 16, or
32 bits
Ø Byte: 8-bit number
Ø Halfword : 16-bit number
Ø Word : 32-bit number

Ø Example : 011010102 = 0•27 + 1•26 + 1•25 + 0•24 + 1•23 + 0•22 + 1•21 +

0•20 = 64+32+8+2 = 106

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 Hexadecimal Notation
§ To simplify working with binary numbers, humans use a related number
system called hexadecimal, which uses base 16.
Ø Often abbreviated as “hex”
Ø Put a 0x or a $ before the number to mean hexadecimal.
Ø ARM Cortex-M 32 bit address mode : 0x2000 001A
Ø Contents of register, memory 32 bits (8 digits in hex)
§ Each hexadecimal digit has a place and a value.
Ø Place is a power of 16
Ø Value is a digit selected from the set {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E,
F}.

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 Hexadecimal to Binary Conversion
§ A nibble is defined as 4 binary bits, or one hexadecimal digit.

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 Hexadecimal to Binary Conversion
§ Convert from binary to hexadecimal we can:
Ø Divide the binary number into right justified nibbles
Ø Convert each nibble into its corresponding hexadecimal digit.

Notice the mapping between 4

binary bits and one hex digit.

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 Hexadecimal to Binary Conversion
§ Convert from hexadecimal to binary we can:
Ø Convert each hexadecimal digit into its corresponding 4-bit binary nibble
Ø Combine the nibbles into a single binary number.

Notice that each hex digit maps

into 4 binary bits.

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 Signed vs. Unsigned Numbers
§ Precision and Bytes
Ø Precision is the number of distinct or different values.
Ø Alternatives are defined as the total number of possibilities.
• For example, an 8-bit number format can represent 256 different numbers.
Ø A byte contains 8 bits. We specify b7 as the most significant bit or MSB, and
b0 as the least significant bit or LSB.

§ Observation:
Ø If the least significant binary bit is zero, then the number is even.
Ø Consider an 8-bit unsigned number system.
• If bit 7 is low, then the number is between 0 and 127, and if bit 7 is high then the
number is between 128 and 255.

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 2's Complement
§ Most common approach used to define signed numbers.
Ø Negate a number (we complement each bit (like one’s complement), then add
1)
Ø For example, if 25 equals 000110012 in binary, then –25 is 111001112
Ø The basis elements of an 8-bit signed number are {-128, 64, 32, 16, 8, 4, 2, 1}.
Ø The most significant bit in a two’s complement signed number will specify the
sign.
Ø Example : signed 1000 1101 to dec?

§ A word on the ARM Cortex M will have 32 bits. Consider an unsigned

number with 32 bits, where each bit b31,...,b0 is binary and has the value
1 or 0.
Ø In C :
• Define a 32-bit variable as signed using the long data type.
• Define a 32-bit variable as unsigned using the unsigned long data type.

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 Binary, Hexadecimal, and Decimal formats
§ Example : 8-bit number (Cortex M, 32-bit numbers)
Ø 0x20 in hexadecimal is 00100000 in binary
• In other words 0x20 has only bit 5 set, and the other bits are 0.
Ø 0xDF in hexadecimal is 11011111 in binary.
• In other words 0xDF has only bit 5 clear, and the other bits are 1.
Cortex M4 Systick
System Bus Interface NVIC

GPIO Port A GPIO Port B

PA7 PB7
PA6 Four PB6
PA5/SSI0Tx Eight PB5
PA4/SSI0Rx UARTs I2Cs PB4
PA3/SSI0Fss PB3/I2C0SDA
PA2/SSI0Clk Four PB2/I2C0SCL
PA1/U0Tx CAN 2.0 PB1
SSIs
PA0/U0Rx PB0

PC7 GPIO Port C GPIO Port D PD7

PC6 PD6
PC5 USB 2.0 Twelve PD5
PC4 Timers PD4
PC3/TDO/SWO PD3
PC2/TDI JTAG Six PD2
PC1/TMS/SWDIO 64-bit wide PD1
PC0/TCK/SWCLK PD0

GPIO Port E GPIO Port F

PE5
PE4 ADC Two Analog PF4
PE3 2 channels Comparators PF3
PE2 12 inputs PF2
PE1 12 bits Two PWM PF1
PE0 Modules PF0

Advanced High Performance Bus Advanced Peripheral Bus

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 Contents
§ Embedded System Development Platform
§ Processor and Memory
§ Microcontroller / Architecture
§ Four Types of Memories
§ Programming Embedded Systems
§ I/O Ports
§ Number representation
§ IDE Keil and Launchpad

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 Integrated Development Environment - Keil

Editor KeilTM uVision®

Simulated Processor
Source code Start Microcontroller
Start
; direction register Debug
LDR R1,=GPIO_PORTD_DIR_R Session Memory
LDR R0,[R1]
ORR R0,R0,#0x0F
; make PD3-0 output I/O
STR R0, [R1]

Build Target (F7)

Object code Real Processor

Microcontroller
0x00000142
0x00000144
4912
6808
Download
0x00000146 F040000F Memory
0x0000014A 6008 Start
Debug
Session I/O
Address Data

Assembly language or C development process.

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 Integrated Development Environment - Keil

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 Integrated Development Environment - Keil
§ IDE includes an editor, assembler, compiler, and simulator. Furthermore,
it can be used to download and debug software on a real microcontroller.
Ø 1. We first use an editor to create our source code. Source code contains specific
set of sequential commands in human-readable-form.
Ø 2. We use an assembler or compiler to translate our source code into object
code.
• On ARM Keil™ uVision® we compile/assemble by executing the command Project-
>Build Target (short cut F7). Object code or machine instructions contains these same
commands in machine-readable-form.
• The assembler/compiler may also produce a listing file, which is a human-readable
output showing the addresses and object code that correspond to each line of the source
program.

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 Integrated Development Environment - Keil
Ø 3. The target specifies the platform on which we will be running the object
code.
• When testing software with the simulator, we choose the Simulator as the target.
When simulating, there is no need to download, we simply launch the simulator by
executing the Debug->Start Debug Session command.
• In a real system, we choose the real microcontroller via its JTAG debugger as the
target. In this way the object code is downloaded into the EEPROM of the
microcontroller. The JTAG is both a loader and a debugger. We program the
EEPROM by executing the Flash->Download command. After downloading we
can start the system by hitting the reset button on the board or we can debug it by
executing Debug->Start Debug Session command in the uVision® IDE.

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 Functional Debugging
§ Functional debugging involves the verification of input/output
parameters.
Ø Static process where inputs are supplied, the system is run, and the outputs are
compared against the expected results.
§ Many debuggers allow you to set the program counter to a specific
address then execute one instruction at a time.
Ø The debugger provides three stepping commands Step, StepOver and StepOut.
Ø Step is the usual execute one assembly instruction. However, when debugging
C we can also execute one line of C.
Ø StepOver will execute one assembly instruction, unless that instruction is a
subroutine call, in which case the debugger will execute the entire subroutine
and stop at the instruction following the subroutine call.
Ø StepOut assumes the execution has already entered a subroutine, and will
finish execution of the subroutine and stop at the instruction following the
subroutine call.

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 Breakpoint
§ A breakpoint is a mechanism to tag places in our software, which
when executed will cause the software to stop.
§ The use of print statements is a popular and effective means for
functional debugging.
Ø One difficulty with print statements in embedded systems is that a standard
“printer” may not be available.
Ø Another problem with printing is that most embedded systems involve time-
dependent interactions with its external environment.

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 Debug Menu and Commands

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 Tiva LaunchPad
§ LaunchPad evaluation board is a low-cost development board available as
part number EK-LM4F120XL and EK-TM4C123GXL

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