Layout and LVS
Open-Source Analog Design Flow
Specifications
Design Flow
Schematic Design
& Simulation
for Analog
Integrated
Layout Generation
Circuits
DRC & LVS
Parasitic Extraction
& Simulation
GDS
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Fabrication and PDK
Process Design Kit:
Set of specifications of the fabrication process,
defined by the foundry. It includes:
● Available layers
● Physical and electrical properties
● Device primitives
● Simulation models
+ Set of rules that ensure manufacturability
of the design (Design Rule Check o DRC)
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Layout
Since the vertical order of
the layers is known, it is
sufficient to represent the
design seen from above,
like a blueprint.
The shape of the polygons
drawn in the different layers
provide information of the
physical geometry and
distribution of the designed
devices.
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Layout
Before layout
During schematic design, once
the simulations show the desired
behaviour, the (preliminary) size
of the devices are chosen.
In the following example, we consider the layout of a
CMOS inverter, with lengths L = 0.3 um and widths
Wn = 1.5 um and Wp = 4.5 um.
In the example we use Magic and work with the
iic-osic-tools Docker from JKU.
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www.opencircuitdesign.com/magic/
Magic: GUI
Grid options DRC check Information:
technology, layer
Selection Box
Layers: left click to make
layer visible, wheel to paint
the box and right click to
Console
make layer invisible
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Magic: commands left click lower left corner of the box
right click upper right corner of the box
‘a’ select everything in the box
Comandos: ‘b’ box information
‘c’ copy
box <x1> <y1> <x2> <y2> Choose box coordinates ‘d’ delete
paint <layer_name> Paint box ‘s’ select polygon
getcell <cell_name> Instantiate .mag file ‘m’ move
sideways Mirror horizontally ‘u’ undo
upsidedown Mirror vertically shift + ‘u’ redo
rotate [degrees] Rotate (90º by default) ‘z’ zoom in
label <name> <dir> <layer> Put label box shift + ‘z’ zoom out
source <file_name> Run .tcl script
extract Extract devices
ext2spice Convert extraction into .spice Note: all the actions in the GUI can be
save <cell_name> Save .mag file executed with commands, and written in
load <cell_name> Load .mag file .tcl scripts
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1.0x1.5 ndiffusion 0.3x1.8 polysilicon
¿Which type is
the substrate? [ NMOS Layout
0.05
Execute magic and check technology in
the upper right corner.
¿Where are
Draw the NMOS from the image, size
the transistor W=150nm and L=30nm
terminals?
Rule Value
difftap.1 diffusion min width 0.15um
difftap.3 diff. to diff. min spacing 0.27um
poly.1a polysilicon min width 0.15um
poly.2 poly to poly min spacing 0.21um
poly.7 ndiffusion overhang of nFET 0.25um
[
0.1 difftap.2 Transistor min width 0.42um
poly.8 min poly overhang of FET 0.13um
0.2x1.2 ndcontact
0.3x1.4 locali
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1. 2.
On the window menu, select a
0.5um grid and enable snap to grid.
Paint a 1.0um*1.5um rectangle
width ndiffusion layer.
Change the grid size to 0.05 and
paint a 0.3um*1.8um rectangle with
polysilicon.
This will generate a 0.3um*1.5um
ntransistor.
3. 4.
Paint a 0.2um*1.2um rectangle with
ndcontact on each side.
Paint a 0.3um*1.4um rectangle with
locali on each side.
Check DRC
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PMOS Layout Scripting
A PMOS transistor has a similar construction Remembering that all actions can be
to the NMOS, except is is inside an nwell done by commands, .tcl scripts can be
and diffusions are p+ type. The required used to do layout that is easily
layers are: reproduced and changed.
nwell
pdiffusion
polysilicon
pdcontact
locali
For the example inverter we need a PMOS
with W=4.5um y L=0.3um. What about
aspect ratio?
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Device Generator
It is not necessary to do layout manually for
each device.
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Layout v/s Schematic
Layout v/s Schematic (LVS)
In Xschem:
- Generate .spice by pressing ‘Netlist’
- Open netlist with ‘Simulation>Edit Netlist’
- Save .spice in work directory
In Magic:
- Extract with: extract
- Configure with: ext2spice lvs
- Configure with: ext2spice subcircuit top off
- Get .spice: ext2spice
Once both netlists are in the same directory, execute netgen
netgen -batch lvs net1.spice net2.spice $PDK_PATH/libs.tech/netgen/sky130A_setup.tcl lvs.log
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LVS log http://opencircuitdesign.com/netgen/tutorial/tutorial.html#Results
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Post-Layout Simulation
Parasitic Netlist for LVS
extraction
extract
ext2spice cthresh 0
ext2spice rthresh 0 Netlist with parasitics
ext2spice
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