7} -, Y5 IIT ROORKEE Indian Institute of Technology Roorkee B.Tech IV Year Project: EEN 400 A Report On Analysis and Design of Current Source Gate Driver for Silicon Carbide(SiC)MOSFETs Author: Satyam Suman (21115129) Author: Tanish Pathak (21115147) Author: Utkarsh Patel (21115152) Author: Yash Pandey (21115160) Supervisor: Professor Satish Belkhodeprotection are ci Abstract This report provides a detalled comparison of two voltage source gate driver (VSD) configurations—VSD | and VSD II—focusing on their design, working principles, and performance. VSD | employs the TLP250 gate driver and the QA02 DC-DC converter to deliver dual outputs of +15V and -8.7V for efficient MOSFET switching. This configuration offers galvanic isolation, protecting the control circuit from high-voltage transients while enhancing switching efficiency and reducing electromagnetic interference (EMI). VSD Il, on the other hand, utilizes a more advanced optocoupler-based gate driver, incorporating components such as the AFBR-2624Z optical receiver, SN74LVC1G27DBVRE4 complementary pulse generator, and delay circuits to ensure faster switching speeds and improved noise immunity. This design is specifically optimized for high-performance SiC MOSFETs, making it ideal for applications requiring high-speed, accurate switching, such as motor drives, inverters, and DC-DC converters. To assess the performance of these configurations, the Dual Pulse Test (DPT) is utilized. This method provides a precise evaluation of switching losses, turn-on and turn-off characteristics, and thermal behavior under real operating conditions. The DPT is crucial for understanding the dynamic behavior of gate drivers and opt efficiency. This report analyzes the strengths and weaknesses of VSD | and VSD Il, respective suitability for applications where accuracy, speed, and I.Contents Section Title Page No Section 1 Literature Review 4 Section 2 Model and Concept 4 © Voltage Source Gate Driver I Voltage Source Gate Driver IT Section 3 Dual Pulse Test Signal 8 Section 4 Difference between VSD I and VSD Il 9 Section 5 Project Progress Table and Concluding Remarks 10 List of Figures Totem Pole Configuration Totem Pole Simulation Result CSD circuit diagram 6 Current Source Circuit Diagram 6 CSD Gate Voltage Waveform 7 CSD Gate Voltage and Gate Current during switching | 7 VSD Schematic Diagram 9Section 1- Literature Review Gate drivers are essential in controlling power semiconductor devices like MOSFETs and IGBTs by providing the required voltage and current to switch these devices efficiently. Farly gate driver designs focused on simple voltage regulation and basic switching functions. However, modem applications demand advanced features like isolation, high-speed switching, and thermal management to ensure improved performance and protection VSD I utilizes the TLP2S0 gate driver paired with the QA02 DC-DC converter, which provides galvanic isolation and dual-voltage outputs (+15V and -8.7V) for efficient MOSFET operation. This configuration is widely used in applications like motor drives and inverters due to its reliability and ability to protect the control circuit from high-voltage spikes. VSD I is an advanced configuration incorporating optocoupler-based components such as the AFBR-2624Z, optical receiver and SN74LVC1G27DBVRE4 complementary pulse generator. This design offers faster switching speeds, better noise immunity, and enhanced protection, making it ideal for controlling SiC MOSFETs in high-frequency applications. Section 2 Model and Concept 2.41. Voltage Source Gate Driver I The TLP250 gate driver is a widely used optically isolated gate driver designed for switching power MOSFETs and IGBTS. Its primary function is to provide electrical isolation between the low-voltage control circuit and the high-voltage power circuit, ensuring protection against voltage spikes and noise. In this configuration, the Momnsun QA02 DC-DC converter is employed to supply the necessary +15V and -8.7V isolated power to the gate driver, ensuring optimal performance and reliable operation of the MOSFET. The TLP250 is crucial in high-speed switching applications where the control circuit must be protected from the high-voltage section. The use of the QA02 DC-DC converter ensures that the gate driver has an independent and stable power supply, enhancing gate drive efficiency and reducing switching losses. 2.1.1. Overview of the Gate Driver Circuit The gate driver circuit involves several critical components working together to achieve efficient MOSFET switching. The key clements in this configuration include: 1, TLP250 Gate Driver: Provides optical isolation and translates low-voltage PWM signals into high-voltage gate drive pulses. 2, QA02 DC-DC Converter: Delivers isolated +15V and -8.7V power to the TLP250 for reliable gate drive.3, TALVC2G125 Buffer IC: Buffers and strengthens the PWM signal from the controller, ensuring clean and fast signal transitions. 4, Voltage Regulator (MC7805): Converts a 12V input to a stable SV to power the buffer and control circuitry. 2 ion of the QA02 DC-DC Converter The QA02 DC-DC converter is a specialized module designed to provide dual outputs (+15V and -8.7V) from a 12V DC input. This dual output is essential for the TLP250 gate driver to perform both turn-on and turn-off functions efficiently. Key Specifications of QA02 DC-DC Converter: Parameter ‘Value Input Voltage 12V DC ‘Output Voltage HSV /-8.7V ‘Output Current +80mA 1 -40mA, Isolation Voltage 3000V AC Efficienc, 80% Why Dual Outputs? ‘© +15V Output: Provides the necessary gate drive voltage to fully tum ON the MOSFET. * -8.7V Output: Provides a negative bias to quickly discharge the MOSFET gate capacitance, ensuring fast turn-off and reducing power losses. The high 3000V AC isolation protects the control side from transients or voltage spikes originating from the power side. 2.1.3. Working Principle of the Gate Driver Circuit The operation of the gate driver circuit can be broken down into the following stages: A. PWM Signal Input and Conditioning 1. A PWM signal is generated by a microcontroller or another control system. 2, This signal is fed into the 74LVC2GI25 buffer IC, which strengthens and conditions the PWM. pulse to ensure clean and sharp edges. B. Optical Isolation and Signal Transfer 1. The conditioned PWM signal drives the LED inside the TLP250 gate driver. 2. When the PWM signal is HIGH, the LED emits light, which is detected by a photodetector on the output side, This optical coupling ensures galvanic isolation between the low-voltage and high-voltage sections, . Powering the Gate Driver 1, The QA02 DC-DC converter provides isolated +15V and -8,7V to the Vee and GND pins of the TLP2S0. 2. This dual-voltage setup allows the gate driver to output both positive and negative gate drive signals. D. Driving the MOSFE1 1, When PWM is HIGH: The TLP250 outputs +15V to the gate of the MOSFET, turing it ON. 2, When PWM is LOW: The TLP250 outputs -8.7V, rapidly pulling the gate down and turning the MOSFET OFF,‘This rapid switching ensures minimal power loss and improves the efficiency of the circuit. 2.1.4, Advantages of Using QA02 DC-DC Converter ‘The use of the QA02 DC-DC converter in this gate driver configuration offers several significant advantages: 1. Galvanic Isolation: The QA02 provides 3000V AC isolation, protecting the low-voltage control side from high-voltage transients. 2. Dual Output Voltage: ‘The +15V ensures complete MOSFET enhancement, while -8.7V allows rapid gate discharge, reducing switching times. 3. Improved Switching Performance: Faster turn-on and turn-off reduces switching losses, which enhances overall circuit efficiency. 4. Compact and Efficient Design: With an efficiency of approximately 80%, the QA02 minimizes power loss and heat generation. 5. Versatile Input Range: The 12V input is compatible with most industrial and automotive applications. T T Z 7 BamE re } ; | ds de P — B ! B} ‘TLP250 GATE DRIVER, | Dc-De CONVERTER = ve i voc Ic : ' 2 Pon ner PL | if a ' 7 1317 ay your fo hedfela | = 3 a | 7 be ' ao b a ce Sheet: 1 | 1 x I 3 4 Fig 2.1.2 Schematic Diagram for VSD 12.2. Voltage Source Gate Driver II The Optocoupler-based Gate designed for driving high-power MOSFETs or IGBTs, specifically SiC MOSFETs, It ensures efficient switching, isolation, and protection in high-voltage applications like DC-DC converters, inverters, and motor drives. It Prevents high-voltage transients from damaging control circuits and Ensures safety by electrically isolation low power and high-power Sections. SiC MOSFETs require fast gate drive signals to reduce losses and improve efficiency. 2.2.1. Overview of the Gate Driver Circuit The gate driver circuit involves several critical components working together to achieve efficient MOSFET switching. The key elements in this configuration include: 1) Optical Receiver AFBR-2624Z: Optical receiver converts an incoming optical signal into an electrical PWM signal. This is useful for providing galvanic isolation between the control unit, The optical receiver module detects an incoming optical signal and converts it into a digital PWM electrical signal. 2) 12V to SV Generation SSW-102: It steps down the 12V input to SV using a switching regulator ora linear voltage regulator. The input 12V is fed into the voltage regulation circuit. The voltage regulator ensures that a stable SV output is generated. This SV powers the logic circuits, ensuring compatibility with microcontrollers and other digital components. 3) Complimentary Pulse Generation SN74LVC1G27DBVREA: It generates complementary PWM signals, which means it produces two signals that are opposite in phase. Why is this needed? In half-bridge and full-bridge circuits, MOSFETs are operated in complementary fashion. Ifone MOSFET is ON, the other should be OFF. It ensures that one pulse is the inverse of the other. Working Principle The input PWM signal is fed into SN74LVC1G27DBVRE&, which processes the signal. Resistances help define the pulse shape. The output consists of PWM_H (high-side gate drive signal) and PWM_L. (low-side gate drive signal). 4) Delay Generation SN74HCSO9DR: It ensures that there is a dead time (small delay) between turning off one MOSFET and turing on the other. Why is this needed? If both MOSFETs in a half-bridge or full-bridge tur on simultaneously, it causes shoot-through current, damaging the circuit. A delay prevents this by ensuring that before one switch tums ON, the other has completely tuned OFF, Working Principle: input PWM signals go through a timing circuit (resistors and capacitors). SN74HCSO9DR processes these signals and adds a small delay before switching the next MOSFET. The delayed PWM signals are then sent to the gate driver circuit. 5) Gate Driver Optocoupler-based: ‘These circuits take the delayed complementary PWM signals and provide the required gate drive voltage to the power MOSFETs Why optocoupler: Isolation: Protects low-voltage control circuits from high-power switching noise. Fast switching: Optocoupler-based gate drivers like HCPL-3120 and ACPL-W346 can switch MOSFETs at high speeds. Working PrincipleThe complementary and delayed PWM signals enter U1 to U4 (optocouplers). The optocouplers isolate and amplify the signals to provide the required gate drive voltage (often 15V or higher for SiC MOSFETs). Zener diodes (ZD8A, ZD8B) protect the MOSFET gates from voltage spikes. The final processed signals ate then applied to the MOSFET gate terminals. 6) Power Stage (MOSFET Gate Driving): It processed signals from the gate drivers are applied to MOSFET gates for switching, Gate resistors (RGA, RGB) help control the switching speed and reduce ringing, Zener diodes (ZD7, ZD8) help in clamping the voltage and protecting the MOSFET gate from excessive voltage. Working Principle: The final PWM signals drive the MOSFET gates via G1 and G2. When the gate voltage is HIGH, the MOSFET turns ON and allows current to flow. When the gate voltage is LOW, the MOSFET turns OFF, stopping the current. The switching process allows the circuit to control power conversion efficiently. Advantages of Isolated Gate Driver Circuits: Galvanic Isolation for Safety © The circuit uses optocouplers (ACPL-W346) to isolate low-voltage control signals from high-voltage power circuits © Prevents ground loops and protects microcontrollers or control units from high voltage transients. 2.2.2. High-Speed and Efficient Switching © SiC MOSFETs require fast switching, and this circuit ensures low propagation delay and high-frequency operation © The use of complementary pulse generation and delay circuits optimizes switching transitions. «Reduces switching losses, improving overall system efficiency. 3. Reduced Power Losses and EMI (Electromagnetic Interference) © The dead-time generation block prevents both MOSFETs from conducting simultancously, reducing shoot-through current losse: © The circuit design ensures clean PWM signals, minimizing EMI and noise in high-frequency applications. © Zener diodes (ZD) and capacitors provide voltage clamping and filtering, improving signal integrity. 4, Compatibility with Different Power Levels © The NMG1224SC DC-DC converter allows operation at different voltage levels (e.g, 12V to 24V). © The 12V to SV conversion stage ensures compatibility with logic-level control systems. © Supports a wide range of MOSFETs and IGBTs, making it adaptable for DC-DC converters, inverters, and motor drives. 5, Fault Detection and Protection * The delay generation block also helps in fault detection (c.g, preventing short circuits due to fast switching transitions). © The isolation and controlled pulse generation help protect the MOSFETs from overvoltage and. overcurrent conditions. The separate high-side (11S) and low-side (LS) PWM signals ensure safe and controlled operation. 6. Modular and Scalable Design© The circuit is modular, allowing easy modification for different switching frequencies, voltage levels, and load conditions. © Can be integrated with microcontrollers (MCUs), DSPs, or FPGA-based controllers for advanced control strategies ov AFBR “ a Snsit Sms s Fig 2.1.2 Block Diagram for VSD Il 2.3. DPT The Dual Pulse Test (DPT) is a method used to evaluate the switching characteristics of power semiconductors like MOSFETs and IGBTs. It involves generating two pulses—a longer first pulse and a shorter second pulse separated by a defined gap. This test allows for precise measurement of switching losses, turn-on and turn-off times, and thermal behavior under controlled conditions. The DPT is essential for analyzing the efficiency and robustness of the gate driver circuit, ensuring that it can handle the required voltage, current, and switching speeds without malfunction. This helps optimize gate drive parameters, minimize energy losses, and improve the overall performance of the power switching system, 2.3.1. Difference Between Single Pulse and Dual Pulse Test The Single Pulse Test evaluates basic switching characteristics with one continuous pulse. It is mainly ‘used to measure turn-on and turn-off times, threshold voltage, and on-state resistance (Rds(on)). This method is useful for initial gate driver testing and quick verification but does not capture the dynamic behavior or thermal effects during continuous switching.In contrast, the Dual Pulse Test provides a more detailed analysis by generating two pulses with a controlled gap. It measures both turn-on and tum-off losses, reverse recovery, gate charge, and dv/at (rate of voltage change). This test is better suited for advanced applications requiring high-speed switching and provides deeper insights into the thermal behavior and long-term reliability of the gate driver under repetitive switching conditions. 2.3.2. Use of Single Pulse and Dual Pulse Test The Single Pulse Test is used for basic assessments such as verifying gate driver output, measuring simple switching characteristics, and performing initial testing. It is easy to implement but is limited in analyzing complex switching behaviors and energy losses. The Dual Pulse Test is used for advanced evaluations, including measuring switching losses, analyzing dynamic response, and assessing the thermal effects during continuous switching cycles. It is crucial for optimizing gate drive circuits, ensuring precise control, and improving efficiency in applications like motor drivers, inverters, and switch-mode power supplies. The Dual Pulse Test is more comprehensive than the Single Pulse Test, making it essential for advanced power semiconductor testing and gate driver optimization. Fig 2.1.2 DPT Signal Oscilloscope Output 10include “F2ex project. 4° fieFine SASCUC FREQUENCY 200000000 efine EP FaEQ Se00000 Uineas Yong pulse us = 205, tines gap Eine bintas stort polee bintas total perled ws seid sniteromceio() c pioctrnegs.GORURL.Dit.c109 = 15 picctrinoge. coor. bit. cree ~ > ‘oid setupenwn_oer(uintas long pulse, Ulntas gap-tine, Uintis short pulse, vintas total period) c (S¥Scux_FREQUENEY / (PR.CLK DIV * EDALEREQ)) * total perkad / 25, Lines CAPA VALLE = (SYSCLKFREQLERCY /(PACLK DIV * EMAL FREQ)) * long pilse / 25 ints cHBRLSTART = (SYECLE_FREQUERCY / (AMPLCLKBIV * ERBLFREQ)) * (Longepulse + gap time) / 25 Uineie cRBBLEND = (SYSCLK FREQUENCY /|(HMLCLK DIV * EMLFREQ)) * (Long pulse + gap-tive + short pulse) / 25 ‘ntegs OCTL.O$¢.CTREDE ~ T8_COUNT-UPSEH, ‘hamaRegs.THETL OGL CLADIV mtReysTHCTL bit ASPCLADIV ‘mtRegsEPRD ~ TEPRO VALUE: ‘atRegs.cFPA- hal CAPA = CAPA VALLES hamtRegs AGETLALBEC-2R0 = 8Q-SET3 Regs AgcTLAbSt. CA = AQ-CLEAR, PemRegs CAPS hal CAPS ~ CAPE STARTS ntRegs AQCTLA-bEt-CBU = AQ SET; hamtRogs AGETLA.BS®. CBD = AQ-CLEARS ) ‘id main(void) € nitsysctr1005 Initehampio()3 mnitpiectrl()s ‘SHtupeP_Dev (long pulse_ss, exp-tine-us, short pulse_us, total_period.us)s spite(ay Fig 2.1.2 DPT Signal Generation Code for TMS320F28379D TI Board Section 3- Difference between VSD I and VSD II? Gate Driver Type: VSD I: Uses the TLP250 optocoupler gate driver. It works by converting the PWM signal from the controller into an isolated output that drives the MOSFET gate. This driver requires +15V for the output stage and -8.7V for fast gate discharge, both supplied by the QA02 DC-DC converter. "1SD II: Uses a complementary optocoupler-based gate driver with additional circuits like the AFBR-2624Z, optical receiver. This design provides more precise gate control by generating complementary pulses (both positive and negative) through pulse-shaping circuits. This improves the speed and efficiency of switching. Power Supply Configuration: VSD I: Requires an external DC-DC converter (like QA02) to supply +15V and -8.7V for gate drive. This configuration provides isolation between the control side and the power side. VSD Ii: Uses a more integrated power design, where advanced circuits regulate gate voltages internally. It directly handles high-speed transitions without requiring an external DC-DC converter for separate voltages. Switching Control: VSD I: Controls the MOSFET gate using a single-ended signal. The output from TLP250 turns the MOSFET ON with +15V and OFF by pulling the gate to -8.7V. This method is slower due to the optocoupler's longer propagation delay. VSD Il: Uses complementary signals for faster gate transitions. It generates two outputs—one to turn the MOSFET ON and another to turn it OFF. This reduces switching delay, allowing faster transitions and better performance in high-speed applications. Noise Handling: VSD I: Relies on the basic galvanic isolation from the TLP2S0 to prevent noise from affecting the control side. However, it lacks advanced noise filtering, making it vulnerable in noisy environments. 12VSD II: Incorporates complementary pulse shaping and active noise rejection circuits. These provide better noise immunity and prevent signal interference, making it more suitable for high-speed, high-frequency environments. Circuit Complexity: VSD I: Is simpler because it consists of the TLP2S0 gate driver, QA02 DC-DC converter, and basic MOSFET switching circuitry. This makes it easier to implement and maintain. VSD Ii: Is more complex due to additional circuits like the AFBR-2624Z optical receiver and pulse-shaping circuits. This complexity improves performance but increases design effort and cost. Gate Drive Capability: VSD I: Suitable for standard MOSFETs with moderate gate charge requirements. It is slower due to longer optocoupler propagation delay. VSD Ii: Designed for SiC MOSFETs and other high-speed devices. Its complementary drive allows for faster gate charge/discharge cycles, improving switching speed and efficiency. Which is Better? VSD Lis better for basic applications where simplicity, lower cost, and moderate switching speeds are sufficient. It is ideal for general motor drives and inverters. VSD Il is better for advanced applications requiring faster switching, better noise handling, and higher precision, especially for SiC MOSFETs in high-frequency environments. 134.2. Concluding Remarks We have studied the advantage of the current source gate driver circuit over traditionally used voltage source gate drivers. Implemented voltage source gate driver (Totem Pole) also studied the switching behavior like power loss of DUT (Device under test) Mosfet using Dual Pulse Test setup. We have done Simulation of Current Source Gate Driver, Now, We are designing Voltage Source Gate Driver using Kicad software and fabricating it on PCB board. Our next step is designing of circuit parameter for CSD and fabricate them on PCB board. After that we will try to find the experimental results along with its comparison for different gate driver circuits for a SiC MOSF! Reference [1] Shahane, Rajat, Satish Belkhode, and Anshuman Shukla. "Current Source Gate Drivers: Topolagies, Applications, and Recent Trends." IEEE Transactions on Power Electronics (2024). [2] Eberle, Wilson, et al. “A current source gate driver achieving switching loss savings and gate energy recovery at 1-MHz." IEEE Transactions on Power Electronics 23.2 (2008): 678-691. [3] Shahane, Rajat, Satish Belkhode, and Anshuman Shukla. "Current Source Gate Drivers: Topologies, Applications, and Future Research Needs.” IEEE Transactions on Power Electronics 39.9 (2024): 10731-10753, [4] Ludecke, Christoph, et al. "Experimental comparison of voltage and current source gate drivers for IGBTS." 2017 IEEE 12th International Conference on Power Electronics and Drive Systems (PEDS). IEEE, 2017, [5] Nel, B. J., & Perinpanayagam, S. (2017). A brief overview of SIC MOSFET failure modes and design reliability, Procedia CIRP, 59, 280-285. 14Satyam Suman BtpMidTermReport II.docx B stuere naan Document Details sipmtremepr ison FDturritin rc Flturitin mess yon ii cele 9% Overall Similarity ‘match Groups Top Sources @ vse 6 @ tmamasores16