BEC601

Model Question Paper-1 with effect from 2022(CBCS Scheme)

USN

6th Semester B.E. Degree Examination

Subject Title – Embedded Systems Design
TIME: 03 Hours Max. Marks: 100

Note: Answer any FIVE full questions, choosing at least ONE question from each MODULE.

*Bloom’s COs
Module -1 Taxonomy Marks
Level
Q.01 a Define Embedded System. Classify an embedded system based on L1 CO1 10
(i) generation (ii) Complexity (iii) Triggering
b Explain the following: L2 CO1 10
(i) Optocoupler (ii) Zig-Bee (iii) Wi-Fi (iv)SPI bus (v) USB
OR
Q.02 a List the features of the following : (i)I2C Bus (ii)IrDA (iii)1-wire
L1 CO1 10
Interface (iv)keyboard (v)UART
b Illustrate the architectural block diagram of embedded system and
L2 CO1 10
mention the components used.
Module-2
Q. 03 a Discuss the Operational and Non-Operational Quality Attributes L2 CO2 10
of an Embedded System.
b Compare (i) DFG and CDFG models with an example. L2 CO2 10
(ii) C v/s Embedded C (iii) Compiler v/s Cross-Compiler
OR
Q.04 a Explain the assembly language based embedded firmware
development with a diagram and mention its advantages and L2 CO2 10
disadvantages.
b Demonstrate coin operated telephone system with a FSM , CO2
L2 10
function of states and state transition diagram.
Module-3
Q. 05 a Explain monolithic and micro kernels with suitable example for L2 CO3 06
each.
b Discuss the terms tasks, process and threads. L2 CO3 08
c Three processes with process IDs P1, P2 and P3 with estimated L3 CO3 06
completion time 10,5,7 ms respectively enter the ready queue
together in order P1, P2 , P3. Calculate waiting time and turn
around time for each process and average waiting time and
TAT.(Assume there is no I/O waiting for the processes.
OR
Q. 06 a Write a note on IAP [In Application Programming] and In System L2 CO3 04
Programming.
b Demonstrate a block schematic of IDE environment for embedded CO3
L2 08
system design and explain their functions in brief. - 08
c Illustrate the concept of ‘deadlock’ with a neat diagram. Mention L3 CO3 08
the different conditions which favors a deadlock situation.
Module-4
 Q. 07 a List the different registers of ARM CORTEX – M3 and mention CO4
L1,L2 08
their use. Explain the use of R13, R14 and R15 registers.

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BEC601
b Summarize the CPSR configuration. Illustrate how to access L2 CO4 06
different subdivisions of PSR.
c Explain exceptions and interrupts of ARM CORTEX – M3. L2 CO4 06
OR
Q. 08 a Describe with a block schematic, explain the function of various CO4
L1,L2 10
units in ARM Cortex M3 processor architecture in brief.
b Discuss any 5 applications of ARM cortex M3 based on its
L2 CO4
05
features.
c Explain all the processor modes of ARM Cortex M3 along with a CO4
L2 05
diagram.
Module-5
Q. 09 a Explain the following 32 bit instructions with an example for each L2 CO5 08
: ADC, BIC, LSL and PUSH.
b Describe CMSIS with diagram and its functions, organization and L2 CO5 07
scope.
c Write an ALP to add the first 10 integer numbers using Cortex M3 CO5
L3 05
processor.
OR
Q. 10 a Explain the operation of following instruction with syntax and an CO5
example for each : (i)ADD.W (ii)LDMIA (iii)BEQ (iv) LSR L2 10
(v)IF-THEN
b Explain different rotate and reverse instructions of Cortex M3 with L3 CO5 10
example for each.
*Bloom’s Taxonomy Level: Indicate as L1, L2, L3, L4, etc. It is also desirable to indicate the COs and POs to be
attained by every bit of questions.
 Page 02 of 02
Answers
1]a)Ans- An embedded system is a combination of 3 types of components: a. Hardware b.
Software c. Mechanical Components and it is supposed to do one specific task only.
Based on generation
First Generation:
➢ The early embedded systems built around 8bit microprocessors like 8085 and Z80 and 4bit
microcontrollers.
➢ Examples: Digital telephone keypads.

Second Generation:
➢ Embedded Systems built around 16 bit microprocessors and 8 or 16bit microcontrollers,
following the first generation embedded systems.
➢ Examples: SCADA systems

Third Generation:
➢ Embedded Systems built around high performance 16/32 bit Microprocessors/controllers.
➢ Application Specific Instruction set processors like Digital Signal Processors (DSPs), and
Application Specific Integrated Circuits (ASICs).
➢ Examples: Robotics, Media, etc.

Fourth Generation:
➢ Embedded Systems built around System on Chips (SoCs), Re configurable processors and
multicore processors.
➢ Highly complex & very powerful.
➢ Examples: Smart Phones.
Based on Complexity & performance requirements
Small-scale:
➢ Simple in application need
➢ Performance not time-critical.
➢ Built around low performance& low cost 8 or 16 bit μp/μc. Example: an electronic toy

Medium-scale:
➢ Slightly complex in hardware & firmware requirement.
➢ Built around medium performance & low cost 16 or 32 bit μp/μc.
➢ Usually contain operating system.
➢ Examples: Industrial machines.

Large-scale:
➢ Highly complex hardware & firmware.
➢ Built around 32 or 64 bit RISC μp/μc or PLDs or Multicore-Processors.
➢ Response is time-critical
➢ Examples: Mission critical applications.

Based on triggering
Embedded systems which are “Reactive” in nature can be classify based on triggering.
Reactive systems can be:
➢ Event triggered
➢ Time triggered

1]b)An-a)Optocoupler
➢ Optocoupler is a solid state device to isolate two parts of a circuit.
➢ Optocoupler combines an LED and a photo-transistor in a single housing (package)
➢ In electronic circuits, optocoupler is used for suppressing interference in data
communication, circuit isolation, High voltage separation, simultaneous separation and
intensification signal etc.

b)ZigBee
➢ ZigBee is targeted for low power, low cost, low data rate and secure applications for
Wireless Personal Area Networking (WPAN)
➢ The ZigBee specifications support a robust mesh network containing multiple nodes. This
networking strategy makes the network reliable by permitting messages to travel through a
number of different paths to get from one node to another.
➢ ZigBee operates worldwide at the unlicensed bands of Radio spectrum, mainly at 2.400 to
2.484 GHz, 902 to 928 MHz and 868.0 to 868.6 MHz
➢ ZigBee Supports an operating distance of up to 100 meters and a data rate of 20 to
250Kbps
➢ ZigBee is primarily targeting application areas like Home & Industrial Automation, Energy
Management, Home control/security, Medical/Patient tracking, Logistics & Asset tracking and
sensor networks & active RFID
➢ In the ZigBee terminology, each ZigBee device falls under any one of the following ZigBee
device category:
➢ ZigBee Coordinator (ZC)/Network Coordinator. The ZigBee coordinator acts as the root of
the ZigBee network. The ZC is responsible for initiating the ZigBee network and it has the
capability to store information about the network.
➢ ZigBee Router (ZR)/Full function Device (FFD) Responsible for passing information from
device to another device or to another ZR.
➢ ZigBee End Device (ZED)/Reduced Function Device (RFD): End device containing ZigBee
functionality for data communication. It can talk only with a ZR or ZC and doesn't have the
capability to act as a mediator for transferring data from one device to another

c)Wi-Fi
➢ Wi-Fi or Wireless Fidelity is the popular wireless communication technique for networked
communication of devices.
➢ Wi-Fi follows the IEEE 802.11 standard.
➢ Wi-Fi is intended for network communication and it supports Internet Protocol (IP) based
communication.
➢ It is essential to have device identities in a multipoint communication to address specific
devices for data communication.
➢ In an IP based communication each device is identified by an IP address, which is unique
to each device on the network.
➢ Wi-Fi based communications require an intermediate agent called Wi-Fi router/Wireless
Access point to manage the communications.
➢ The Wi-Fi router is responsible for restricting the access to a network, assigning IP address
to devices on the network, routing data packets to the intended devices on the network.
➢ Wi-Fi enabled devices contain a wireless adaptor for transmitting and receiving data in the
form of radio signals through an antenna.
➢ The hardware part of it is known as Wi-Fi Radio.
➢ Wi-Fi operates at 2.4 GHz or 5 GHz of radio spectrum and they co-exist with other ISM
band devices like Bluetooth.
➢ Figure illustrates the typical interfacing of devices in a Wi-Fi network
d)Serial Peripheral Interface (SPI) Bus:
➢ The Serial Peripheral Interface Bus (SPI) is a synchronous bi-directional full duplex four
wire serial interface bus.
➢ The concept of SPI is introduced by Motorola.
➢ SPI is a single master multi-slave system. It is possible to have a system where more than
one SPI device can be master, provided the condition only one master device is active at any
given point of time, is satisfied.
➢ SPI requires four signal lines for communication. ▪ Master Out Slave In (MOSI): Signal line
carrying the data from master to slave device. It is also known as Slave Input/Slave Data In
(SI/SDI)
▪ Master In Slave Out (MISO): Signal line carrying the data from slave to master device. It is
also known as Slave Output (SO/SDO)
▪ Serial Clock (SCLK) : Signal line carrying the clock signals
▪ Slave Select (SS/) : Signal line for slave device select. It is an active low signal

➢ The bus interface diagram shown in the figure illustrates the connection of master and
slave devices on the SPI bus.
➢ The master device is responsible for generating the clock signal.
➢ Master device selects the required slave device by asserting the corresponding slave
device’s slave select signal ‘LOW’. The data out line (MISO) of all the slave devices when not
selected floats at high impedance state
➢ The serial data transmission through SPI Bus is fully configurable.
➢ The Serial Peripheral Control Register holds the various configuration parameters like
master/slave selection for the device, baudrate selection for communication, clock signal
control etc. The status register holds the status of various conditions for transmission and
reception.
➢ SPI works on the principle of ‘Shift Register’. The master and slave devices contain a
special shift register for the data to transmit or receive. The size of the shift register is device
dependent. Normally it is a multiple of 8.
➢ During transmission from the master to slave, the data in the master’s shift register is
shifted out to the MOSI pin and it enters the shift register of the slave device through the
MOSI pin of the slave device. At the same time the shifted out data bit from the slave
device’s shift register enters the shift register of the master device through MISO pin
f)Universal Serial Bus (USB)
Universal Serial Bus (USB) is a wired high speed serial bus for data communication. The first
version of USB (USB 1.0) was released in 1995.
The USB communication system follows a star topology with a USB host at the centre and
one or more USB peripheral devices/USB hosts connected to it.
A USB host can support connections up to 127, including slave peripheral devices and other
USB hosts.
Figure illustrates the star topology for USB device connection.
➢ USB transmits data in packet format. Each data packet has a standard format. The USB
communication is a host initiated one.
➢ The USB host contains a host controller which is responsible for controlling the data
communication, including establishing connectivity with USB slave devices, packetizing and
formatting the data.
➢ There are different standards for implementing the USB Host Control interface:
• Open Host Control Interface (OHCI)
• Universal Host Control Interface (UHCI)
➢ The physical connection between a USB peripheral device and master device is
established with a USB cable.
➢ The USB cable supports communication distance of up to 5 metres.
➢ The USB standard uses two different types of connector at the ends of the USB cable for
connecting the USB peripheral device and host device.
➢ 'Type A' connector is used for upstream connection (connection with host) and Type B
connector is used for downstream connection (connection with slave device).
➢ The USB connector present in desktop PCs or laptops are examples for 'Type A' USB
connector.
➢ Both Type A and Type B connectors contain 4 pins for communication
➢ Each USB device contains a Product ID (PID) and a Vendor ID (VID).
• Embedded into the USB chip by the USB device manufacturer.
• The VID for a device is supplied by the USB standards forum.
• PID and VID are essential for loading the drivers corresponding to a USB device for
communication.
➢ USB supports four different types of data transfers:
➢ Control transfer : Used by USB system software to query, configure and issue commands
to the USB device.
➢ Bulk transfer : Used for sending a block of data to a device.
• Supports error checking and correction.
• Transferring data to a printer is an example for bulk transfer.
➢ Isochronous data transfer : Used for real-time data communication.
• Data is transmitted as streams in real-time.
• Doesn't support error checking and re-transmission of data in case of any transmission loss.
• All streaming devices like audio devices and medical equipment for data collection make
use of the isochronous transfer.
➢ Interrupt transfer : Used for transferring small amount of data.
• Interrupt transfer mechanism makes use of polling technique to see whether the USB
device has any data to send.
• The frequency of polling is determined by the USB device and it varies from 1 to 255
milliseconds.
• Devices like Mouse and Keyboard, which transmits fewer amounts of data, uses Interrupt
transfer.

2]a)Ans- I2C (Inter Integrated Circuit) Bus:

➢ The Inter Integrated Circuit Bus (I2C or I 2 C Pronounced 'I square C') is a synchronous bi-
directional half duplex two wire serial interface bus.

➢ The concept of I2C bus was developed by Philips Semiconductors in the early 1980s.
➢ The original intention of I2C was to provide an easy way of connection between a
microprocessor/microcontroller system and the peripheral chips in television sets.
➢ The I2C bus comprise of two bus lines:
• (Half duplex - one-directional communication at a given point of time)
▪ Serial Clock (SCL line) – responsible for generating synchronisation clock pulses
▪ Serial Data (SDA line) – responsible for transmitting the serial data across devices
➢ I2C bus is a shared bus system to which many number of I2C devices can be connected.
Devices connected to the I2C bus can act as either ‘Master’ device or ‘Slave’ device
➢ The ‘Master’ device is responsible for controlling the communication by
initiating/terminating data transfer, sending data and generating necessary synchronization
clock pulses
➢ ‘Slave’ devices wait for the commands from the master and respond upon receiving the
commands
➢ ‘Master’ and ‘Slave’ devices can act as either transmitter or receiver
➢ Regardless whether a master is acting as transmitter or receiver, the synchronization clock
signal is generated by the ‘Master’ device only
➢ I2C supports multi masters on the same bus

The following bus interface diagram illustrates the connection of master and slave devices on
the I2C bus

➢ The I2C bus interface is built around an input buffer and an open drain or collector
transistor.
➢ When the bus is in the idle state, the open drain/collector transistor will be in the floating
state and the output lines (SDA and SCL) switch to the 'High Impedance' state.
➢ For proper operation of the bus, both the bus lines should be pulled to the supply voltage
(+5 V for TTL family and +3.3V for CMOS family devices) using pull-up resistors.
➢ With pull-up resistors, the output lines of the bus in the idle state will be 'HIGH'➢ The
address of a I2C device is assigned by hardwiring the address lines of the device to the
desired logic level. Done at the time of designing the embedded hardware.
➢ The sequence of operations for communicating with an I2C slave device is listed below: 1.
The master device pulls the clock line (SCL) of the bus to 'HIGH'
2. The master device pulls the data line (SDA) 'LOW', when the SCL line is at logic 'HIGH' (This
is the 'Start' condition for data transfer)
3. The master device sends the address (7 bit or 10 bit wide) of the 'slave' device to which it
wants to communicate, over the SDA line. ▪ Clock pulses are generated at the SCL line for
synchronizing the bit reception by the slave device.
▪ The MSB of the data is always transmitted first.
▪ The data in the bus is valid during the 'HIGH' period of the clock signal
4. The master device sends the Read or Write bit (Bit value = 1 Read operation; Bit value = 0
Write operation) according to the requirement
5. The master device waits for the acknowledgement bit from the slave device whose
address is sent on the bus along with the Read/ Write operation command.
Slave devices connected to the bus compares the address received with the address assigned
to them
6. The slave device with the address requested by the master device responds by sending an
acknowledge bit (Bit value 1) over the SDA line
7. Upon receiving the acknowledge bit, the Master device sends the 8 bit data to the slave
device over SDA line, if the requested operation is 'Write to device’.
If the requested operation is 'Read from device', the slave device sends data to the master
over the SDA line
8. The master device waits for the acknowledgement bit from the device upon byte transfer
complete for a write operation and sends an acknowledge bit to the Slave device for a read
operation
9. The master device terminates the transfer by pulling the SDA line 'HIGH' when the clock
line SCL is at logic 'HIGH' (Indicating the 'STOP' condition
Infrared (IrDA)
➢ Infrared (IrDA) is a serial, half duplex, line of sight based wireless technology for data
communication between devices.
➢ It is in use from the olden days of communication and you may be very familiar with it.
E.g.: The remote control of TV, VCD player, etc. works on Infrared.
➢ Infrared communication technique uses infrared waves of the electromagnetic spectrum
for transmitting the data.
➢ It supports point-point and point-to-multipoint communication, provided all devices
involved in the communication are within the line of sight.
➢ The typical communication range for IrDA lies in the range 10 cm to 1 m. The range can be
increased by increasing the transmitting power of the IR device.
➢ IR supports data rates ranging from 9600bits/second to 16Mbps.
➢ Depending on the speed of data transmission IR is classified into:
• Serial IR (SIR) – supports data rates ranging from 9600bps to 115.2kbps.
• Medium IR (MIR) – supports data rates of 0.576Mbps and 1.152Mbps.
• Fast IR (FIR) – supports data rates up to 4Mbps.
• Very Fast IR (VFIR) – supports high data rates up to 16Mbps.
• Ultra Fast IR (UFIR) – targeted to support a data rate up to 100Mbps.
➢ IrDA communication involves a transmitter unit for transmitting the data over IR and a
receiver for receiving the data.
➢ Infrared Light Emitting Diode (LED) is the IR source for transmitter and at the receiving end
a photodiode acts as the receiver.
➢ Both transmitter and receiver unit will be present in each device supporting IrDA
communication for bidirectional data transfer. Such IR units are known as 'Transceiver’.
➢ Certain devices like a TV remote control always require unidirectional communication and
so they contain either the transmitter or receiver unit. The remote control unit contains the
transmitter unit and TV contains the receiver unit.
➢ Infrared Data Association (IrDA) is the regulatory body responsible for defining and
licensing the specifications for IR data communication.
➢ IR communication has two essential parts: a physical link part and a protocol part.
➢ The physical link is responsible for the physical transmission of data between devices
supporting IR communication. Protocol part is responsible for defining the rules of
communication.
➢ The physical link works on the wireless principle making use of Infrared for
communication.
➢ IrDA is a popular interface for file exchange and data transfer in low cost devices.
➢ IrDA was the prominent communication channel in mobile phones before Bluetooth's
existence.
1-Wire Interface
➢ 1-wire interface is an asynchronous half-duplex communication protocol developed by
Maxim Dallas Semiconductor.
➢ It is also known as Dallas 1-Wire protocol.
➢ It makes use of only a single signal line (wire) called DQ for communication and follows
the master-slave communication model.
➢ One of the key feature of 1-wire bus is that it allows power to be sent along the signal wire
as well.
➢ The slave devices incorporate internal capacitor (typically of the order of 800 pF) to power
the device from the signal line.
➢ The 1-wire interface supports a single master and one or more slave devices on the bus.
➢ The bus interface diagram shown in the figure illustrates the connection of master and
slave devices on the 1-wire bus.
➢ Every 1-wire device contains a globally unique 64bit identification number stored within it.
➢ This unique identification number can be used for addressing individual devices present
on the bus in case there are multiple slave devices connected to the 1-wire bus.
➢ The identifier has three parts: an 8-bit family code, a 48-bit serial number and an 8-bit
CRC computed from the first 56 bits.
➢ The sequence of operation for communicating with a 1-wire slave device is listed below:
1. The master device sends a 'Reset' pulse on the 1-wire bus.
2. The slave device(s) present on the bus respond with a 'Presence' pulse.
3. The master device sends a ROM command (Net Address Command followed by the 64 bit
address of the device). This addresses the slave device(s) to which it wants to initiate a
communication.
4. The master device sends a read/write function command to read/write the internal
memory or register of the slave device.
5. The master initiates a Read data/Write data from the device or to the device.
➢ All communication over the 1 -wire bus is master initiated.
➢ The communication over the 1-wire bus is divided into timeslots of 60 microseconds.
➢ The 'Reset' pulse occupies 8 time slots. For starting a communication, the master asserts
the reset pulse by pulling the 1-wire bus 'LOW' for at least 8 time slots (480 μs).
➢ If a 'slave' device is present on the bus and is ready for communication it should respond
to the master with a 'Presence' pulse, within 60 μs of the release of the 'Reset' pulse by the
master.
➢ The slave device(s) responds with a 'Presence' pulse by pulling the 1-wire bus 'LOW' for a
minimum of 1 time slot (60 μs).
➢ For writing a bit value of 1 on the 1-wire bus, the bus master pulls the bus for 1 to 15 μs
and then releases the bus for the rest of the time slot.
➢ A bit value of ‘0' is written on the bus by master pulling the bus for a minimum of 1 time
slot (60 μs) and a maximum of 2 time slots (120 μs).
➢ To Read a bit from the slave device, the master pulls the bus 'LOW' for 1 to 15 μs.
➢ If the slave wants to send a bit value ‘1' in response to the read request from the master, it
simply releases the bus for the rest of the time slot.
➢ If the slave wants to send a bit value '0', it pulls the bus 'LOW' for the rest of the time slot.

c)write general knowledge on keyboard.

Universal Asynchronous Receiver Transmitter (UART)
➢ Universal Asynchronous Receiver Transmitter (UART) based data transmission is an
asynchronous form of serial data transmission.
➢ It doesn't require a clock signal to synchronise the transmitting end and receiving end for
transmission.
➢ Instead it relies upon the pre-defined agreement between the transmitting device and
receiving device.
➢ The serial communication settings (Baudrate, number of bits per byte, parity, number of
start bits and stop bit and flow control) for both transmitter and receiver should be set as
identical
➢ The start and stop of communication are indicated through inserting special bits in the
data stream.
➢ While sending a byte of data, a start bit is added first and a stop bit is added at the end of
the bit stream. The least significant bit of the data byte follows the 'start' bit.
➢ The 'start' bit informs the receiver that a data byte is about to arrive. The receiver device
starts polling its 'receive line' as per the baud rate settings.
➢ The receiver unit polls the receiver line at exactly half of the time slot available for the bit.
➢ If parity is enabled for communication, the UART of the transmitting device adds a parity
bit (bit value is 1 for odd number of 1s in the transmitted bit stream and 0 for even number
of 1s).
➢ The UART of the receiving device calculates the parity of the bits received and compares it
with the received parity bit for error checking.
➢ The UART of the receiving device discards the 'Start', 'Stop' and 'Parity’ bit from the
received bit stream and converts the received serial bit data to a word
➢ In the case of 8 bits/byte, the byte is formed with the received 8 bits with the first
received bit as the LSB and last received data bit as MSB.
➢ For proper communication, the 'Transmit line' of the sending device should be connected
to the 'Receive line' of the receiving device.
➢ In addition to the serial data transmission function, UART provides hardware handshaking
signal support for controlling the serial data flow.

3]a)Ans-Quality Attributes of Embedded Systems

➢ Quality attributes are the non-functional requirements that need to be documented
properly in any system design.
➢ If the quality attributes are more concrete and measurable it will give a positive impact on
the system development process and the end product.
➢ The quality attributes in any embedded system development are broadly classified into
two:
• Operational Quality Attributes
• Non-Operational Quality Attributes
Operational Quality Attributes
 ➢ The operational quality attributes represent the relevant quality attributes related to the
embedded system when it is in the operational mode or 'online' mode.
➢ The important operational quality attributes are:
1. Response
2. Throughput
3. Reliability
4. Maintainability
5. Security
6. Safety
Response
➢ Response is a measure of quickness of the system.
➢ It gives you an idea about how fast the system is tracking the changes in input variables.
➢ Most of the embedded systems demand fast response which should be almost Real Time.
➢ For example, an embedded system deployed in flight control application should respond
in a Real Time manner. Any response delay in the system will create potential damages to the
safety of the flight as well as the passengers.
➢ It is not necessary that all embedded systems should be Real Time in response. For
example, the response time requirement for an electronic toy is not at all time-critical. There
is no specific deadline that this system should respond within this particular timeline.
THROUGHPUT
➢ Throughput deals with the efficiency of a system.
➢ Throughput can be defined as the rate of production or operation of a defined process
over a stated period of time.
➢ The rates can be expressed in terms of units of products, batches produced, or any other
meaningful measurements. In the case of a Card Reader, throughput means how many
transactions the Reader can perform in a minute or in an hour or in a day.
➢ Throughput is generally measured in terms of 'Benchmark’. A 'Benchmark' is a reference
point by which something can be measured. Benchmark can be a set of performance criteria
that a product is expected to meet or a standard product that can be used for comparing
other products of the same product line.
RELIABILITY
➢ Reliability is a measure of how much percentage you can rely upon the proper functioning
of the system or what is the percentage susceptibility of the system to failures.
➢ System reliability is defined using two terms:
➢ Mean Time Between Failures (MTBF): Gives the frequency of failures in
hours/weeks/months.
➢ Mean Time To Repair (MTTR): Specifies how long the system is allowed to be out of order
following a failure. For an embedded system with critical application need, it should be of the
order of minutes.
MAINTAINABILITY
➢ Maintainability deals with support and maintenance to the end user or client in case of
technical issues and product failures or on the basis of a routine system check-up.
➢ Reliability and maintainability are considered as two complementary disciplines.
➢ A more reliable system means a system with less corrective maintainability requirements
and vice versa.
➢ Maintainability can be broadly classified into two categories:
• Scheduled or Periodic Maintenance (preventive maintenance): For example,
replacing the cartridge of a printer after each 'n' number of printouts to get quality
prints.
• Maintenance to unexpected failures (corrective maintenance): For example,
repairing the printer if the paper feeding part fails.
➢ Maintainability is also an indication of the availability of the product for use.
➢ In any embedded system design, the ideal value for availability is expressed

Security
➢ Confidentiality, Integrity, and Availability are the three major measures of information
security.
➢ Confidentiality deals with the protection of data and application from unauthorised
disclosure.
➢ Integrity deals with the protection of data and application from unauthorised
modification.
➢ Availability deals with protection of data and application from unauthorized users.
➢ A very good example of the 'Security' aspect in an embedded product is a Personal Digital
Assistant (PDA). The PDA can be either a shared resource (e.g. PDAs used in LAB setups) or an
individual one.
➢ If it is a shared one there should be some mechanism in the form of a user name and
password to access into a particular person's profile—This is an example of 'Availability’.
➢ Also, all data and applications present in the PDA need not be accessible to all users.
➢ Some of them are specifically accessible to administrators only.
➢ For achieving this, Administrator and user levels of security should be implemented —An
example of Confidentiality.
➢ Some data present in the PDA may be visible to all users but there may not be necessary
permissions to alter the data by the users.
➢ That is Read Only access is allocated to all users—An example of Integrity.
Safety
➢ Safety deals with the possible damages that can happen to the operators, public and the
environment due to the breakdown of an embedded system or due to the emission of
radioactive or hazardous materials from the embedded products.
➢ The breakdown of an embedded system may occur due to a hardware failure or a
firmware failure.
 ➢ Safety analysis is a must in product engineering to evaluate the anticipated damages and
determine the best course of action to bring down the consequences of the damages to an
acceptable level.
➢ Some of the safety threats are sudden (like product breakdown) and some of them are
gradual (like hazardous emissions from the product)
Non-Operational Quality Attributes
➢ The quality attributes that needs to be addressed for the product 'not’ on the basis of
operational aspects are grouped under this category.
➢ The important non-operational quality attributes are:
1. Testability & Debug-ability
2. Evolvability
3. Portability
4. Time-to-prototype and market
5. Per unit and total cost
Testability & Debug-ability
➢ Testability deals with how easily one can test his/her design, application and by which
means he/she can test it.
➢ For an embedded product, testability is applicable to both the embedded hardware and
firmware.
➢ Embedded hardware testing ensures that the peripherals and the total hardware
functions in the desired manner, whereas firmware testing ensures that the firmware is
functioning in the expected way.
➢ Debug-ability is a means of debugging the product as such for figuring out the probable
sources that create unexpected behaviour in the total system.
➢ Debug-ability has two aspects in the embedded system development context, namely,
hardware level debugging and firmware level debugging.
➢ Hardware debugging is used for figuring out the issues created by hardware problems
whereas firmware debugging is employed to figure out the probable errors that appear as a
result of flaws in the firmware.
Evolvability
➢ For an embedded system, the quality attribute 'Evolvability’ refers to the ease with which
the embedded product (including firmware and hardware) can be modified to take
advantage of new firmware or hardware technologies.
Portability
➢ Portability is a measure of 'system independence’.
➢ An embedded product is said to be portable if the product is capable of functioning 'as
such' in various environments, target processors/controllers and embedded operating
systems.
➢ A standard embedded product should always be flexible and portable.
➢ In embedded products, the term 'porting' represents the migration of the embedded
firmware written for one target processor (e.g. Intel x86) to a different target processor (say
Hitachi SH3 processor).
 ➢ If the firmware is written in a high level language like ‘C’, it is very easy to port the
firmware
➢ If the firmware is written in Assembly Language for a particular family of processor (say
x86 family), the portability is poor.
Time-to-Prototype and Market
➢ Time-to-market is the time elapsed between the conceptualisation of a product and the
time at which the product is ready for selling (for commercial product) or use (for non
commercial products).
➢ The commercial embedded product market is highly competitive and time-to-market the
product is a critical factor in the success of a commercial embedded product.
• Competitor might release their product before you do.
• The technology used might have superseded with a new technology.
➢ Product prototyping helps a lot in reducing time-to-market.
➢ Prototyping is an informal kind of rapid product development in which the important
features of the product under consideration are developed.
➢ The time-to-prototype is also another critical factor.
• If the prototype is developed faster, the actual estimated development time can be
brought down significantly.
• In order to shorten the time to prototype, make use of all possible options like the use of
off-the-shelf components, re-usable assets, etc.
Per Unit Cost and Revenue
➢ Cost is a factor which is closely monitored by both end user and product manufacturer.
➢ Cost is a highly sensitive factor for commercial products.
➢ Any failure to position the cost of a commercial product at a nominal rate, may lead to the
failure of the product in the market.
➢ Proper market study and cost benefit analysis should be carried out before taking a
decision on the per-unit cost of the embedded product.
➢ The budget and total system cost should be properly balanced to provide a marginal
profit.
➢ The product life cycle of every embedded product has different phases: Design and
Development Phase:
➢ The product idea generation, prototyping, Roadmap definition, actual product design and
development are the activities carried out during this phase. There is only investment and no
returns.
Product Introduction Phase:
➢ Once the product is ready to sell, it is introduced to the market. During the initial period
the sales and revenue will be low. There won't be much competition and the product sales
and revenue increases with time. Growth Phase
➢ The product grabs high market share.

Maturity Phase:
➢ The growth and sales will be steady and the revenue reaches at its peak. Product
Retirement/Decline Phase:
➢ Drop in sales volume, market share and revenue.
➢ The decline happens due to various reasons like competition from similar product with
enhanced features or technology changes, etc.
➢ At some point of the decline stage, the manufacturer announces discontinuing of the
product.
➢ The different stages of the embedded products life cycle—revenue, unit cost and profit in
each stage are represented in the following Product Life-cycle graph

➢ From the graph, it is clear that the total revenue increases from the product introduction
stage to the product maturity stage.
➢ The revenue peaks at the maturity stage and starts falling in the decline/retirement Stage.
➢ The unit cost is very high during the introductory stage. A typical example is cell phone; if
you buy a new model of cell phone during its launch time, the price will be high and you will
get the same model with a very reduced price after three or four months of its launching).
➢ The profit increases with increase in sales and attains a steady value and then falls with a
dip in sales.
➢ You can see a negative value for profit during the initial period.
➢ It is because during the product development phase there is only investment and no
returns.

3]b)Ans-dfg and cdfg-

Feature DFG (Data Flow Graph) CDFG (Control and Data Flow Graph)
A representation of data A combination of control flow and data
Definition
dependencies in a computation. flow in a program or system.
Focuses only on the flow of data Represents both control flow
Focus
between operations. (conditions, branches) and data flow.
Control No control flow information is Includes control flow elements like if-
Information present. else, loops, etc.
Used in compiler design, behavioral
Used in high-level synthesis and
Usage synthesis, and control-intensive
signal processing applications.
designs.
Feature DFG (Data Flow Graph) CDFG (Control and Data Flow Graph)
Nodes: operations or
Contains multiple DFGs connected by
Representation computations; Edges: data
control edges.
dependencies.
A conditional structure that includes
Addition, multiplication, etc.,
Example multiple DFGs under different control
linked by data values.
paths.
Best for purely data-driven Suitable for applications with both
Suitability
applications. control and data aspects.

‘C’ vs. ‘Embedded C’

Feature C Embedded C
General-purpose programming Extension of C used for
Definition
language for software development. programming embedded systems.
Desktop applications, OS Microcontrollers, real-time systems,
Usage Area
development, etc. IoT devices, etc.
High-level systems with OS (e.g., Low-level hardware with limited
Target Platform
Windows, Linux). resources (no OS or RTOS).
Hardware Direct hardware access (e.g., using
Limited – usually through OS APIs.
Interaction registers, I/O ports).
Uses standard libraries (stdio.h, Uses hardware-specific libraries
Libraries
stdlib.h). (e.g., avr/io.h, pic18.h).
Memory More dynamic memory usage is Limited memory usage; often no
Management allowed. dynamic allocation.
Less portable – code is often
Portability Highly portable across systems.
specific to the hardware.
Standard C compilers (GCC, Turbo Specialized compilers (Keil, MPLAB,
Compiler
C). IAR).
Controlling LEDs, reading sensors,
Examples File handling, graphics, networking.
interfacing with peripherals.

Compiler and cross compiler

Feature Compiler Cross Compiler
A compiler that converts source code A compiler that generates machine
Definition into machine code for the same code for a different target system than
system where it runs. the one it runs on.
Execution
Host and target systems are the same. Host and target systems are different.
Platform
Developing on a PC but compiling code
Example Developing and compiling a program
for an embedded device like a
Use Case on a PC for that same PC.
microcontroller.
Feature Compiler Cross Compiler
Output
Binary executable for the host system. Binary executable for the target system.
Format
GCC used on Windows to compile ARM GCC used on Windows to compile
Examples
Windows apps. for ARM-based boards.
Used in general software Used in embedded systems, IoT
Purpose
development. devices, mobile development, etc.

4]a)Ans-Embedded Firmware Development Languages

➢ For embedded firmware development, we can use either
• a target processor/controller specific language (Generally known as Assembly language or
low level language) or
• a target processor/controller independent language (Like C, C++, JAVA, etc. commonly
known as High Level Language) or
• a combination of Assembly and High level Language.
Assembly Language Based Development
➢ Assembly language is the human readable notation of 'machine language’
• ‘Machine Ianguage' is a processor understandable language.
➢ Machine language is a binary representation and it consists of 1s and 0s.
➢ Machine language is made readable by using specific symbols called 'mnemonics’.
➢ Hence machine language can be considered as an interface between processor and
programmer.
➢ Assembly language and machine languages are processor/controller dependent and an
assembly program written for one processor/controller family will not work with others.
➢ Assembly language programming is the task of writing processor specific machine code in
mnemonic form, converting the mnemonics into actual processor instructions (machine
language) and associated data using an assembler.
➢ Assembly Language program was the most common type of programming adopted in the
beginning of software revolution.
➢ Even today also almost all low level, system related, programming is carried out using
assembly language.
➢ In particular, assembly language is often used in writing the low level interaction between
the operating system and the hardware, for instance in device drivers.
➢ The general format of an assembly language instruction is an Opcode followed by
Operands.
➢ The Opcode tells the processor/controller what to do and the Operands provide the data
and information required to perform the action specified by the opcode.
• For example: MOV A, #30
• Here MOV is the Opcode and A, #30 is the operands
➢ The Assembly language program written in assembly code is saved as .asm (Assembly file)
file or an .src (source) file (also. s file).
➢ Any text editor like ‘Notepad' or 'WordPad' from Microsoft or the text editor provided by
an Integrated Development (IDE) tool can be used for writing the assembly instructions.
➢ Similar to 'C' and other high level language programming, we can have multiple source
files called modules in assembly language programming.
• Each module is represented by an '.asm' or '.src' file.
• This approach is known as 'Modular Programming’.
➢ Modular programming is employed when the program is too complex or too big.
• In 'Modular Programming', the entire code is divided into submodules and each module is
made re-usable.
• Modular Programs are usually easy to code, debug and alter.
Advantages of Assembly Language Base Development
➢ Efficient Code Memory and Data Memory Usage (Memory Optimisation)
• Since the developer is well versed with the target processor architecture and memory
organisation, optimised code can be written for performing operations.
• This leads to less utilisation of code memory and efficient utilisation of data memory.
➢ High Performance
• Optimised code not only improves the code memory usage but also improves the total
system performance
• Through effective assembly coding, optimum performance can be achieved for a target
application.
➢ Low Level Hardware Access
• Most of the code for low level programming like accessing external device specific registers
from the operating system kernel, device drivers, and low level interrupt routines, etc. are
making use of direct assembly coding since low level device specific operation support is not
commonly available with most of the high-level language cross compilers.
➢ Code Reverse Engineering
• Reverse engineering is the process of understanding the technology behind a product by
extracting the information from a finished product.
• Reverse engineering is performed by 'hawkers' to reveal the technology behind
'Proprietary Products’.
• Though most of the products employ code memory protection, if it may be possible to
break the memory protection and read the code memory, it can easily be converted into
assembly code using a dis-assembler program for the target machine.
Drawbacks of Assembly Language Based Development
➢ High Development Time
• Assembly language is much harder to program than high level languages.
• The developer must pay attention to more details and must have thorough knowledge of
the architecture, memory organisation and register details of the target processor in use.
• Learning the inner details of the processor and its assembly instructions is highly time
consuming and it creates a delay impact in product development.
4]b)Ans-➢ Design a coin operated public telephone unit based on FSM model for the
following requirements.
• The calling process is initiated by lifting the receiver (off-hook) of the telephone unit.
• After lifting the phone the user needs to insert a 1 rupee coin to make the call.
• If the line is busy, the coin is returned on placing the receiver back on the hook (on-hook).
• If the line is through, the user is allowed to talk till 60 seconds and at the end of 45th
second, prompt for inserting another 1 rupee coin for continuing the call is initiated.
• If the user doesn't insert another 1 rupee coin, the call is terminated on completing the 60
seconds time slot.
• The system is ready to accept new call request when the receiver is placed back on the
hook (on-hook).
• The system goes to the 'Out of Order' state when there is a line fault.

5]a)Ans-
Monolithic Kernel
All kernel services run in the kernel space
All kernel modules run with in the same memory space under a single kernel thread
 The tight internal integration of kernel modules in monolithic kernel architecture allows the
effective utilization of the low-level features of the underlying system
The major drawback of monolithic kernel is that any error or failure in anyone of the kernel
modules leads to the crashing of the entire kernel application
LINUX,SOLARIS,MS-DOS kernels are examples of monolithic kernel

Microkernel
The micro kernel design in corporates only the essential set of Operating System services
into the kernel
Rest of the Operating System services are implemented in programs known as ‘Servers’
which runs in user space
The kernel design is highly modular provides OS-neutral abstraction
Memory management, process management, timer systems and interrupt handlers are
examples of essential services, which forms the part of the microkernel
QNX ,Minix 3 kernels are examples for microkernel

5]b)Ans-
Tasks, Processes &Threads
In the Operating System context, a task is defined as the program in execution and the
related information maintained by the Operating system for the program
Task is also known as ‘Job ’in the operating system context
A program or part of it in execution is also called a ‘Process’
The terms ‘Task’, ‘job’ and ‘Process’ refer to the same entity in the Operating System context
and most often they are used inter changeably
 A process requires various system resources like CPU for executing the process, memory for
storing the code corresponding to the process and associated variables, I/O devices for
information exchange etc.

The structure of a Processes

The concept of ‘Process’ leads to concurrent execution (pseudo parallelism) of tasks and
there by the efficient utilization of the CPU and other system resources
Concurrent execution is achieved through the sharing of CPU among the processes
A process mimics a processor in properties and holds a set of registers, process status, a
Program Counter(PC) to point to the next executable instruction of the process, a stack for
holding the local variables associated with the process and the code corresponding to the
process
A process, which inherits all the properties of the CPU, can be considered as a virtual
processor, awaiting its turn to have its properties switched in to the physical processor
When the process gets its turn, its registers and Program counter register becomes mapped
to the physical registers of the CPU

Threads
A thread is the primitive that can execute code
A thread is a single sequential flow of control with in a process
‘Thread’ is also known as light weight process
A process can have many threads of execution
Different threads, which are part of a process, share the same address space; meaning they
share the data memory, code memory and heap memory area
Threads maintain their own thread status (CPU register values), Program Counter (PC) and
stack
5]c)Ans-Given:
Process Burst Time (ms)
P1 10
P2 5
P3 7
Arrival order: P1, P2, P3
All arrive at the same time (t = 0).
SJF is non-pre emptive, so the process with the shortest burst time goes first.
Step 1: Order of Execution (based on burst time)
P2 (5ms) → P3 (7ms) → P1 (10ms)
Step 2: Calculate Waiting Time (WT)
Process Start Time Finish Time Waiting Time = Start Time - Arrival Time
P2 0 5 0
P3 5 12 5
P1 12 22 12
Step 3: Calculate Turnaround Time (TAT)
Turnaround Time = Completion Time - Arrival Time (0 for all)
So, TAT = Completion Time
Process Completion Time Turnaround Time
P2 5 5
P3 12 12
P1 22 22

FINAL TABLE
Process Burst Time Waiting Time Turnaround Time
P2 5 0 5
P3 7 5 12
P1 10 12 22
Averages:
• Average Waiting Time (AWT) = (0 + 5 + 12) / 3 = 5.67 ms
• Average Turnaround Time (ATAT) = (5 + 12 + 22) / 3 = 13.0 ms

6]a)Ans-In Application Programming

In Application Programming (IAP) is a technique used by the firmware running on the target
device for modifying a selected portion of the code memory. It is not a technique for first
time embedding of user written firmware. It modifies the program code memory under the
control of the embedded application. Updating calibration data, look-up tables, etc., which
are stored in code memory, are typical examples of IAP.
• The Boot ROM resident API instructions which perform various functions such as
programming, erasing, and reading the Flash memory during ISP- mode, are made available
to the end-user written firmware for IAP.
• Thus, it is possible for an end-user application to perform operations on the Flash memory.
• A common entry point to these API routines is provided for interfacing them to the end-
user's application.
• Functions are performed by setting up specific registers as required by a specific operation
and performing a call to the common entry point.
• Like any other subroutine call, after completion of the function, control will return to the
end-user's code.
• The Boot ROM is shadowed with the user code memory in its address range. This
shadowing is controlled by a status bit.
• When this status bit is set, accesses to the internal code memory in this address range will
be from the Boot ROM.
• When cleared, accesses will be from the user's code memory. Hence the user should set
the status bit prior to calling the common entry point for IAP operations.
In System Programming (ISP)
• Here, the programming is done 'within the system', meaning the firmware is embedded
into the target device without removing it from the target board.
• It is the most flexible and easy way of firmware embedding.
• The only pre-requisite is that the target device must have an ISP support.
• Apart from the target board, PC, ISP cable and ISP utility, no other additional hardware is
required for ISP.
• The target board can be interfaced to the utility program running on PC through Serial
Port/Parallel Port/USB.
• The communication between the target device and ISP utility will be in a serial format.
• The serial protocols used for ISP may be 'Joint Test Action Group (JTAG)' or 'Serial Peripheral
Interface (SPI)' or any other proprietary protocol.
In order to perform ISP operations, the target device should be powered up in a special ‘ISP
mode’. ISP mode allows the device to communicate with an external host, such as a PC or
terminal, through a serial interface. The device receives commands and data from the host,
erases and reprograms code memory according to the received command. Once the ISP
operations are completed, the device is re-configured so that it will operate normally by
applying a reset or a re-power up.
Devices with SPI - In System Programming support contains a built- in SPI interface (Serial
Peripheral Interface) and the on-chip EEPROM or FLASH memory is programmed through
this interface.
• The primary I/O lines involved in SPI - In System Programming are:
• MOSI - Master Out Slave In
• MISO - Master In Slave Out
• SCK - System Clock
• RST - Reset of Target Device
• GND - Ground of Target Device
PC acts as the master and target device acts as the slave in ISP. The program data is sent to
the MOSI pin of target device and the device acknowledgement is originated from the MISO
pin of the device.
• SCK pin acts as the clock for data transfer.
• Since the target device works under a supply voltage less than 5V (TTL/CMOS), it is better
to connect these lines of the target device with the parallel port of the PC. Since parallel port
operations are also at 5V logic, no need for any other intermediate hardware for signal
conversion. Standard SPI-ISP utilities are feely available on the internet and there is no need
for going for writing own program.
6]b)Ans-Embedded System Development Environment
The embedded system development environment consists of:
A Development Computer (PC) or Host, which acts as the heart of the development
environment,
Integrated Development Environment (IDE) Tool for embedded firmware development and
debugging,
Electronic Design Automation (EDA) Tool for Embedded Hardware design,
An emulator hardware for debugging the target board,
Signal sources (like Function generator) for simulating the inputs to the target board,
Target hardware debugging tools (Digital CRO, Multimeter, Logic Analyser, etc.) and
The target hardware.

The Integrated Development Environment (IDE) and Electronic Design Automation (EDA)
tools are selected based on the target hardware development requirement and they are
supplied as Installable files in CDs by vendors. These tools need to be installed on the host PC
used for development activities. These tools can be either freeware or licensed copy or
evaluation versions
6]c)Ans-DEADLOCK
7]a)Ans-A programmer can think of an ARM core as functional units connected by data
buses, as shown in the following Figure.
Data enters the processor core through the Data bus. The data may be an instruction to
execute or a data item.
o Figure shows a Von Neumann implementation of the ARM—data items and instructions
share the same bus. (In contrast, Harvard implementations of the ARM use two different
buses).
The instruction decoder translates instructions before they are executed. Each instruction
executed belongs to a particular instruction set.

The ARM processor, like all RISC processors, uses load-store architecture—means it has two
instruction types for transferring data in and out of the processor:
The arrows represent the flow of data, the lines represent the buses, and the boxes
represent either an operation unit or a storage area.
* load instructions copy data from memory to registers in the core
* store instructions copy data from registers to memory
There are no data processing instructions that directly manipulate data in memory. Thus,
data processing is carried out in registers.
Data items are placed in the register file—a storage bank made up of 32-bit registers.
* Since the ARM core is a 32-bit processor, most instructions treat the registers as holding
signed or unsigned 32-bit values. The sign extend hardware converts signed 8-bit and 16-bit
numbers to 32-bit values as they are read from memory and placed in a register.
ARM instructions typically have two source registers, Rn and Rm, and a single result or
destination register, Rd. Source operands are read from the register file using the internal
buses A and B, respectively.
The ALU (arithmetic logic unit) or MAC (multiply-accumulate unit) takes the register values
Rn and Rm from the A and B buses and computes a result. Data processing instructions write
the result in Rd directly to the register file.
Load and store instructions use the ALU to generate an address to be held in the address
register and broadcast on the Address bus.
* One important feature of the ARM is that register Rm alternatively can be preprocessed in
the barrel shifter before it enters the ALU. Together the barrel shifter and ALU can calculate a
wide range of expressions and addresses.
After passing through the functional units, the result in Rd is written back to the register
file using the Result bus.
For load and store instructions the Incrementer updates the address register before the
core reads or writes the next register value from or to the next sequential memory location.
The processor continues executing instructions until an exception or interrupt changes the
normal execution flow.
The ARM processor has three registers assigned to a particular task or special function: r13,
r14,and r15. They are given with different labels to differentiate them from the other
registers.
o Register r13 is traditionally used as the stack pointer (sp) and stores the head of the stack
in the current processor mode.
o Register r14 is called the link register (lr) and is where the core puts the return address
whenever it calls a subroutine.
o Register r15 is the program counter (pc) and contains the address of the next instruction to
be fetched by the processor.

7]b)Ans-CURRENT PROGRAM STATUS REGISTER:

The ARM core uses the cpsr to monitor and control internal operations. The cpsr is a
dedicated 32-bit register and resides in the register file. The following Figure shows the basic
layout of a generic program status register. Note that the shaded parts are reserved for
future expansion.
 Figure: A Generic Program Status Register (psr)

The cpsr is divided into four fields, each 8 bits wide: flags, status, extension, and control. In
current designs the extension and status fields are reserved for future use.
The control field contains the processor mode, state, and interrupt mask bits.
The flags field contains the condition flags.
Some ARM processor cores have extra bits allocated. For example, the J bit, which can be
found in the flags field, is only available on Jazelle-enabled processors, which execute 8-bit
instructions.
It is highly probable that future designs will assign extra bits for the monitoring and control of
new features.

7]c)Ans-
When an exception or interrupt occurs, the processor sets the pc to a specific memory
address. The address is within a special address range called the vector table.
*The entries in the vector table are instructions that branch to specific routines designed to
handle a particular exception or interrupt.
* The memory map address 0x00000000 (or in some processors starting at the offset
0xffff0000) is reserved for the vector table, a set of 32-bit words.
When an exception or interrupt occurs, the processor suspends normal execution and
starts loading instructions from the exception vector table (see the following Table).
 Each vector table entry contains a form of branch instruction pointing to the start of a
specific routine:
*Reset vector is the location of the first instruction executed by the processor when power is
applied. This instruction branches to the initialization code.
* Undefined instruction vector is used when the processor cannot decode an instruction.
* Software interrupt vector is called when you execute a SWI instruction. The SWI instruction
is frequently used as the mechanism to invoke an operating system routine.
* Prefetch abort vector occurs when the processor attempts to fetch an instruction from an
address without the correct access permissions. The actual abort occurs in the decode stage.
* Data abort vector is similar to a prefetch abort, but is raised when an instruction attempts
to access data memory without the correct access permissions.
* Interrupt request vector is used by external hardware to interrupt the normal execution
flow of the processor. It can only be raised if IRQs are not masked in the cpsr.
* Fast interrupt request vector is similar to the interrupt request, but is reserved for
hardware requiring faster response times. It can only be raised if FIQs are not masked in the
cpsr.

8]a)Ans- 7a same answer

8]b)Ans-
Application Area Key Cortex-M3 Features Utilized
Automotive Systems Real-time performance, low power, reliability
Industrial Automation Fast interrupts, peripheral integration, scalability
Medical Devices Power efficiency, security, compact design
Consumer Electronics Cost-effective, multifunctional, efficient processing
IoT/Wireless Sensor Nodes Low power modes, real-time responsiveness, connectivity

8]c)Ans-Processor Modes:
The processor mode determines which registers are active and the access rights to the cpsr
register itself. Each processor mode is either privileged or non-privileged:
* A privileged mode allows full read-write access to the cpsr.
* A non-privileged mode only allows read access to the control field in the cpsr, but still
allows read-write access to the condition flags.
There are seven processor modes in total:
* six privileged modes (abort, fast interrupt request, interrupt request, supervisor, system,
and undefined)
The processor enters abort mode when there is a failed attempt to access memory.
Fast interrupt request and interrupt request modes correspond to the two interrupt levels
available on the ARM processor.
Supervisor mode is the mode that the processor is in after reset and is generally the mode
that an operating system kernel operates in.
System mode is a special version of user mode that allows full read-write
Access to the cpsr.
 Undefined mode is used when the processor encounters an instruction that is undefined or
not supported by the implementation.
* one non-privileged mode (user).
User mode is used for programs and applications

9]a)Ans-1. ADC (Add with Carry)

➤ Description:
• Adds two operands and the carry flag (C).
• Used in multi-word arithmetic (e.g., 64-bit addition on a 32-bit processor).

➤ Syntax:
assembly
ADC Rd, Rn, Rm
 • Rd = destination register
• Rn = first operand
• Rm = second operand
• Adds: Rd = Rn + Rm + Carry
Example
; Assume R1 = 0xFFFFFFFF, R2 = 0x00000001, carry flag = 1
ADC R0, R1, R2
; R0 = 0xFFFFFFFF + 0x00000001 + 1 = 0x00000001 (with overflow)
2. BIC (Bit Clear)
➤ Description:
• Performs a bitwise AND of a register with the complement of another.
• Equivalent to: Rd = Rn AND (NOT Rm)

➤ Syntax:
assembly
BIC Rd, Rn, Rm
example
; Assume R1 = 0xFFFF00FF, R2 = 0x0000FF00
BIC R0, R1, R2
; R0 = R1 & ~(R2) = 0xFFFF00FF & 0xFFFF00FF = 0xFFFF00FF
3. LSL (Logical Shift Left)
➤ Description:
• Shifts bits left by a specified number.
• Fills with zeroes from the right.
• Often used for multiplication by powers of 2.

➤ Syntax (immediate):
assembly
LSL Rd, Rm, #n
*Rd = Rm << n (shift left by n bits)
Example:
assembly
; Assume R1 = 0x00000002
LSL R0, R1, #2
; R0 = 0x00000002 << 2 = 0x00000008
4. PUSH (Push Register to Stack)
➤ Description:
• Stores register(s) on the stack, decrementing the Stack Pointer (SP).
• Used to save context before function calls or interrupts.

➤ Syntax:
assembly
PUSH {Rn, Rm, ...}
Example:
assembly
PUSH {R4, R5}
; SP = SP - 8 (on 32-bit stack), stores R4 and R5 values at SP

9]b)Ans-CMSIS (Cortex Microcontroller Software Interface Standard)

CMSIS is a vendor-independent hardware abstraction layer for ARM Cortex-M processors,
developed by ARM. It standardizes the software interface for Cortex-M devices, enabling
code portability, easy software development, and toolchain support.
Main Functions of CMSIS
1. Hardware Abstraction
o Provides common interfaces to access core peripherals, NVIC, SysTick, and
registers.
2. Code Portability
o Allows software to be reused across different Cortex-M devices and vendors.
3. Toolchain Integration
o Enables consistent debugging, trace, and performance analysis.
4. DSP and Math Libraries
o Optimized Digital Signal Processing (DSP) functions for high-performance embedded
applications.
5. RTOS Interface
o Defines a standard API for RTOS kernels (CMSIS-RTOS) to improve interoperability.

CMSIS Organization (Architecture Diagram)

+----------------------------------------------------+

| Application Code (User) |

+------------------------+---------------------------+

| CMSIS-RTOS | CMSIS-DSP |

| (RTOS API abstraction)| (Optimized math functions)|

+------------------------+---------------------------+

| CMSIS-Core (Core Peripheral Access) |

| - NVIC, SysTick, SCB |

| - Register & Bit definitions |

+----------------------------------------------------+

| Device Peripheral Access Layer (Vendor-specific)|

| - Startup code, vector table |

| - Peripheral definitions |

+----------------------------------------------------+

| ARM Cortex-M Processor Core |

+----------------------------------------------------+
CMSIS Components Explained

Component Description
CMSIS-Core Access to core registers (e.g., NVIC, SCB, SysTick)
CMSIS-DSP DSP library for Cortex-M (e.g., FFT, FIR filters)
CMSIS-RTOS Standard API for real-time operating systems
CMSIS-SVD System View Description files for peripherals (used by debuggers/tools)
CMSIS-Pack Software pack management (drivers, libraries, and examples)
CMSIS-NN Neural network kernels optimized for Cortex-M

Scope of CMSIS

• Cortex-M0/M0+/M3/M4/M7/M23/M33 support
• Used in:
o IoT devices
o Wearables
o Industrial control
o Medical electronics
o Automotive microcontrollers

9]c)Ans-Assembly Program (ALP):

AREA ADD_NUMBERS, CODE, READONLY

ENTRY

MOV R0, #0 ; R0 will store the sum (initialize to 0)

MOV R1, #1 ; R1 is the counter (start from 1)

MOV R2, #10 ; R2 is the limit (up to 10)

LOOP

ADD R0, R0, R1 ; Add R1 to R0

ADD R1, R1, #1 ; Increment counter

CMP R1, R2 ; Compare counter with 10

BLE LOOP ; If R1 <= 10, repeat loop

B STOP ; Infinite loop to end program

STOP B STOP ; Stay here forever

END

Results:

After execution,
R0 = 1 + 2 + 3 + ... + 10 = 55
10]a)Ans-(i) ADD.W — Add (Wide)

➤ Syntax:
assembly
ADD.W Rd, Rn, Rm
➤ Operation:
• Performs a 32-bit addition:
Rd = Rn + Rm
• The .W ensures the instruction is encoded as a 32-bit instruction, allowing access to
high registers (R8–R15) or specific operand formats.
➤ Example:
assembly
ADD.W R8, R1, R2
; R8 = R1 + R2 (32-bit addition)
(ii) LDMIA — Load Multiple Increment After
➤ Syntax:
assembly
LDMIA Rn!, {Rlist}
➤ Operation:
• Loads multiple registers from memory starting at address in Rn, then increments Rn
after each load.
• ! means write-back: the updated Rn is written back.
➤ Example:
assembly
LDMIA R0!, {R1, R2}
; Loads value at [R0] into R1
; Loads value at [R0+4] into R2
; R0 = R0 + 8 (write-back)
(iii) BEQ — Branch if Equal
➤ Syntax:
assembly
BEQ label
➤ Operation:
• Branches to label if Zero flag (Z) is set (i.e., last comparison was equal).
➤ Example:
assembly
CMP R1, R2
BEQ Equal_ Label
; Branches to Equal_ Label if R1 == R2
(iv) LSR — Logical Shift Right
➤ Syntax:
assembly
LSR Rd, Rm, #n
➤ Operation:
• Shifts Rm right by n bits, filling zeroes from the left:
Rd = Rm >> n
➤ Example:
assembly
; R1 = 0x10 (00010000)
LSR R0, R1, #2
; R0 = 0x04 (00000100)
(v) IF-THEN (IT) — Conditional Execution Block
➤ Syntax:
assembly
IT <condition>
<conditional instruction>
➤ Operation:
• Enables conditional execution of 1–4 instructions based on a flag (e.g., EQ, NE).
➤ Example:
assembly
CMP R1, #0
IT EQ
MOVEQ R0, #1
; If R1 == 0, R0 is set to 1

10]b)Ans-Rotate Instructions (Cortex-M3)

In ARM Cortex-M3, rotation is used for operations like encryption, bit-level data manipulation, etc.
1. ROR (Rotate Right)
• Syntax: ROR Rd, Rm, #imm
• Function: Rotates the contents of register Rm to the right by #imm bits and stores result in Rd.
• Used In: Cryptographic operations, data encoding, circular buffers.
Example:
asm
MOV R0, #0x80000001 ; Load R0 with 1000...0001 binary
ROR R1, R0, #1 ; Rotate right by 1 → R1 = 0xC0000000
Explanation: Bit shifted from LSB rotates to MSB position.

Reverse Instructions (Cortex-M3)

Reverse instructions are often used in byte-order conversions, especially important in network
communication (endianness conversion).
1. REV (Reverse Byte Order)
• Syntax: REV Rd, Rm
• Function: Reverses the byte order of a 32-bit word.
• Use Case: Endianness conversion between little-endian and big-endian.
Example:
asm
MOV R0, #0x12345678 ; R0 = 0x12345678
REV R1, R0 ; R1 = 0x78563412
Explanation: Useful when reading data from devices with different byte ordering.

2. REV16 (Reverse Halfword Byte Order)

• Syntax: REV16 Rd, Rm
• Function: Reverses the byte order in each 16-bit halfword independently.
Example:
asm
MOV R0, #0x12345678 ; R0 = 0x12345678
REV16 R1, R0 ; R1 = 0x34127856
Explanation: Used when working with 16-bit data (like audio samples or sensor data).

3. REVSH (Reverse and Sign Extend Halfword)

• Syntax: REVSH Rd, Rm
• Function: Reverses the byte order of the lower 16 bits, and sign-extends it to 32 bits.
• Use Case: When reading signed 16-bit data from peripherals.
 Example:
asm
MOV R0, #0x0000FF80 ; R0 = 0x0000FF80 (lower 16 bits = 0xFF80 = -128)
REVSH R1, R0 ; R1 = 0xFFFFFF80 (signed 32-bit -128)
Explanation: Converts signed 16-bit little-endian sensor data to 32-bit.

2]b)Ans-Architectural Block Diagram of Embedded System

+---------------------------+
| Embedded System |
+---------------------------+
|
+-----------+-----------+------------+------------+-----------+
| | | | |
v v v v v
+--------+ +----------+ +------------+ +-------+ +---------+
| Sensor | | ADC/DAC | | Processor | | Memory| | Actuator|
+--------+ +----------+ +------------+ +-------+ +---------+
| | | | |
| | v | |
| +------------------> +--------+ | |
| | Timer | | |
| +--------+ | |
| | | |
| +-------+ | |
+-------------------------------> | I/O | <------+ |
| Ports | |
+-------+ |
| |
+-------------------+ |
| Communication | <---------+
| Interfaces (I2C, |
| UART, SPI, CAN) |

Component Description
Senses physical data (temperature, light,
1. Sensor
pressure) and sends it as electrical signals.
2. ADC (Analog to Digital Converts analog signals from sensors to
Converter) digital form for processing.
3. DAC (Digital to Analog Converts digital signals to analog form (if
Converter) required by actuators).
4. Processor The brain of the system. Processes input data
(Microcontroller/Microprocessor) and controls other parts.
Stores data, programs, and results temporarily
5. Memory (RAM/ROM/Flash)
or permanently.
Used for scheduling, delays, or counting
6. Timer/Counters
events. Crucial for real-time systems.
Interface between processor and external
7. I/O Ports
world (switches, LEDs, etc.).
Performs physical action based on output
8. Actuator
(e.g., motor, relay, display).
9. Communication Interfaces Allow data exchange between processor and
(I2C, SPI, UART, CAN) other components or devices.
Example Applications:
• Home Automation System → Sensors (motion), MCU, relay (actuator)
• Medical Device → Heart rate sensor, display, memory
• Automotive System → Speed sensor, brake actuator, CAN bus interface