Average Current Mode Control

of Switch-Mode Power Supplies

A Leading Provider of Smart, Connected and Secure Embedded Control Solutions

Digital Control of Switch-Mode Power Supplies

Presented by Andreas Reiter
March 15th 2023
12th OMICRON Lab Power Analysis & Design Symposium 2023
Agenda
Power Supply Control Modes

Average Current Mode Control Implementation

Enforced Phase-Locking Method

Summary

12th OMICRON Lab Power Analysis & Design Symposium 2023

Agenda
Power Supply Control Modes

Average Current Mode Control Implementation

Enforced Phase-Locking Method

Summary

12th OMICRON Lab Power Analysis & Design Symposium 2023

 Switch-Mode Power Supply Control Modes
Comparison of typical, analog feedback loop implementations
Voltage Mode Control Peak Current Mode Control Adaptive Constant On Time
VIN VOUT VIN VOUT VIN VOUT
Power Converter Plant Power Converter Plant Power Converter Plant
GP(s) GP(s) GP(s)
IL IL
Voltage Feedback Loop Peak Current ACOT Block

H(z)
Trigger Voltage Voltage
Q R
S Ref Loop Q R
S
ZCD
Loop
HV(z) tON
HV(z)
Clock Clock

• Indirect Control Method Hysteretic Mode Control

• Universal, Topology-Agnostic* VIN VOUT
• Single (uncritical) Feedback Signal Power Converter Plant
• Applicable for GP(s)
• Fixed Frequency IL
• Variable Frequency PK
VRP Voltage
• Phase Shift Q R
• Limitations S Loop
ZCD VRV HV(z)
• Limited System Linearization
• Varying Impedance Hysteric Block
• No Over Current Protection
6 12th OMICRON Lab Power Analysis & Design Symposium 2023
 Digital Control Scheme
Voltage Mode Plant GP(s)
60 180
40 120

Magnitude [dB]
Single Voltage Mode Control Loop 20 60

Phase [°]
0 0
-20 -60
Anti- -40 -120

Windup -60 -180

error Compensator output Plant VOUT 10 100 1000 10000 100000

VREF +- PWM GP(s)

Frequency [Hz]
HC(s)
Type III Feedback Loop HC(s)
Voltage 60 180

Voltage Loop Divider 40 120

Magnitude [dB]
20 60

Phase [°]
input 0 0
ADC -20 -60
-40 -120
-60 -180
10 100 1000 10000 100000
Frequency [Hz]

Open Loop Transfer Function GOL(s)

60 180
40 120

Magnitude [dB]
20 60

Phase [°]
0 0
-20 -60
-40 -120
-60 -180
10 100 1000 10000 100000
Frequency [Hz]

7 12th OMICRON Lab Power Analysis & Design Symposium 2023

 Switch-Mode Power Supply Control Modes
Comparison of typical, analog feedback implementations
Voltage Mode Control Peak Current Mode Control Adaptive Constant On Time
VIN VOUT VIN VOUT VIN VOUT
Power Converter Plant Power Converter Plant Power Converter Plant
GP(s) GP(s) GP(s)
IL IL
Voltage Feedback Loop Peak Current ACOT Block

H(z)
Trigger Voltage Voltage
Q R
S Ref Loop Q R
S
ZCD
Loop
HV(z) tON
HV(z)
Clock Clock

• Indirect Control Method • Direct Control Method Hysteretic Mode Control

• Universal, Topology-Agnostic* • Modified Switch-Node Commutation VIN VOUT
• Single (uncritical) Feedback Signal • Inductor Current Control is Part of Switch Power Converter Plant
• Applicable for Node (not the feedback loop) GP(s)
• Fixed Frequency • Applicable for IL
• Variable Frequency • Fixed Frequency PK
VRP Voltage
• Phase Shift • Variable Frequency Q R
• Limitations S Loop
• Phase Shift ZCD VRV HV(z)
• Limited System Linearization • COT and Hysteretic Control Applicable
• Varying Impedance for Variable Frequency Only Hysteric Block
• No Over Current Protection
8 12th OMICRON Lab Power Analysis & Design Symposium 2023
 Switch-Mode Power Supply Control Modes
Comparison of typical, analog feedback implementations
Voltage Mode Control Peak Current Mode Control Adaptive Constant On Time
VIN VOUT VIN VOUT VIN VOUT
Power Converter Plant Power Converter Plant Power Converter Plant
GP(s) GP(s) GP(s)
IL IL
Voltage Feedback Loop Peak Current ACOT Block

H(z)
Trigger Voltage Voltage
Q R
S Ref Loop Q R
S
ZCD
Loop
HV(z) tON
HV(z)
Clock Clock

• Indirect Control Method • Direct Control Method Hysteretic Mode Control

• Universal, Topology-Agnostic* • Modified Switch-Node Commutation VIN VOUT
• Single (uncritical) Feedback Signal • Inductor Current Control is Part of Switch Power Converter Plant
• Applicable for Node (not the feedback loop) GP(s)
• Fixed Frequency • Applicable for IL
• Variable Frequency • Fixed Frequency PK
VRP Voltage
• Phase Shift • Variable Frequency Q R
• Limitations S Loop
• Phase Shift ZCD VRV HV(z)
• Limited System Linearization • COT and Hysteretic Control Applicable
• Varying Impedance for Variable Frequency Only Hysteric Block
• No Over Current Protection
9 12th OMICRON Lab Power Analysis & Design Symposium 2023
 Digital Control Scheme PCMC
Current Mode Plant GP(s)
60 180
40 120

Magnitude [dB]
Peak Current Switch-Node Commutation 20 60

Phase [°]
0 0
-20 -60
Anti- -40 -120
error Windup output
IREF -60 -180

Compensator Plant VOUT 10 100 1000 10000 100000

VREF +- HC(s)
R Q PWM GP(s)
Frequency [Hz]
S
Type II Feedback Loop HC(s)
Clock IL 60 180
Voltage Loop Current
40 120

Magnitude [dB]
20 60

Phase [°]
Sense
0 0
-20 -60
-40 -120
Voltage
-60 -180
Divider 10 100 1000 10000 100000

input Frequency [Hz]

ADC Open Loop Transfer Function GOL(s)

60 180
40 120
• Unfiltered “Open Loop” Adjustment of the Inductor Current

Magnitude [dB]
20 60

Phase [°]
• Injects Noise with every change in reference and load 0 0
• Unfiltered PWM Signal Jitter -20 -60

• Indeterministic Current Limiting -40 -120

• Requires Synchronous Real Time Current Feedback -60

10 100 1000 10000 100000
-180

Frequency [Hz]

10 12th OMICRON Lab Power Analysis & Design Symposium 2023

 Peak Current Modulation
Fixed Frequency Continuous Conduction Operation at DC < 50%

IL TSW TSW

TON TOFF

Ipk*
VL Ipk
-m2
Iavg
m1
IDC
DIDC1 DIDC2
t
DIDC2 < DIDC1

11 12th OMICRON Lab Power Analysis & Design Symposium 2023

 Peak Current Modulation
Fixed Frequency Continuous Conduction Operation at DC > 50%

IL TSW TSW

TON TOFF

Ipk*
Ipk
-m2
Iavg
m1 IDC
DIDC1
DIDC2
t
DIDC2 > DIDC1

12 12th OMICRON Lab Power Analysis & Design Symposium 2023

 PCMC Current Modulation
Fixed Frequency Continuous Conduction Operation at DC < 50%
3.5
3.0

Inductor Current [A]

2.5
DC = 30%
2.0
IPK = 3A
1.5
IDC = 1A
DI0 1.0 DIREF = 50mA
0.5 n=4
0.0
0.0
15.0 2 10.0
3 4
15.0 20.0 25.0 30.0 35.0 40.0 45.0 50.0
Time [usec]

IL IL* IL_REF IL_AVG IL*_AVG

3.5
3.0
Inductor Current [A]

DC = 40%
2.5
2.0
IPK = 3A
IDC = 1A
DI0 1.0
1.5
DIREF = 50mA
0.5 n=9
0.0
0.0
15.0 2 10.0
3 4
15.0
5
20.0
625.0 7 30.0
8 9
35.0 40.0 45.0 50.0
Time [usec]

IL IL* IL_REF IL_AVG IL*_AVG

13 12th OMICRON Lab Power Analysis & Design Symposium 2023

 PCMC Current Modulation
Fixed Frequency Continuous Conduction Operation at DC < 50%
3.5
3.0
DC = 50%

Inductor Current [A]

2.5
IPK = 3A
2.0
IDC = 1A
1.5
DI0 1.0 DIREF = 300mA
0.5 n= 
0.0
0.0 5.0 Static
10.0 Oscillation
15.0 at20.0
exactly 25.0
50% Duty
30.0Cycle 35.0 40.0 45.0 50.0
Time [usec]

IL IL* IL_REF IL_AVG IL*_AVG

4.0

3.0
DC = 58%
Inductor Current [A]

2.0 IPK = 3A
DI0 1.0 IDC = 1A
0.0
DIREF = 300mA
0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 n 50.0
=9
-1.0

-2.0 1 2 3 4 5 6 7 8 9
Time [usec]

IL IL* IL_REF IL_AVG IL*_AVG

14 12th OMICRON Lab Power Analysis & Design Symposium 2023

 PCMC Current Modulation
Slope Compensation Implentation

DCCLAMP Period DCCLAMP Period

Type II Peak Current Mode Control Compensator /w Desired on-time
internal Slope Compensation

PWM
Uncompensated on-time
Slope Compensation
C3
Output Ramp
Voltage C2 Generator PWM Clock
R2
Ra Slope Variations causing
on-time variations
Feedback –
IREF

Switch Current
EA – –
+ CMP Output
Rb + Compensation ramp
REF
(A) (B) Uncompensated
Peak Current waveform
Feedback Input
IDC
DC-offset DC-offset

Desired waveform

Response of voltage loop is slowed down with increasing duty cycle.

Side effects: Gain variations and Voltage Droop

15 12th OMICRON Lab Power Analysis & Design Symposium 2023

Agenda
Power Supply Control Modes

Average Current Mode Control Implementation

Enforced Phase-Locking Method

Summary

12th OMICRON Lab Power Analysis & Design Symposium 2023

 Digital Control Scheme PCMC
Current Mode Plant GP(s)
60 180
40 120

Magnitude [dB]
Peak Current Switch-Node Commutation 20 60

Phase [°]
0 0
-20 -60
Anti-
SolutionWindup -40 -120
error output •Direct Control Method
IREF -60 -180

𝐻𝐶 𝑧 Average Current Mode Plant • VOUT Topology-Agnostic*

Universal,
10 100 1000 10000 100000

VREF +- R Q Control
PWM Frequency [Hz]
(Compensator) S GP(s) •Constant Impedance
VIN VOUT •Over Current Protection
Type II Feedback Loop HC(s)
Power Converter Plant Clock IL 60 180
•Constant Current40Limit
Voltage Loop GP(s)
Current•
120
Applicable for 20

Magnitude [dB]
IL 60

Phase [°]
Sense • Fixed Frequency
Average Voltage 0 0

Current Loop • Variable Frequency

-20 -60

Loop Ref • Phase Shift -40

Voltage
-120
-60 -180
HI(z) HV(z) Divider 10 100 1000 10000 100000

input • Challenges Frequency [Hz]

ADC • Complex Feedback Circuit

Open Loop Transfer Function GOL(s)
60 180
40 120
• Unfiltered “Open Loop” Adjustment of the Inductor Current

Magnitude [dB]
20 60

Phase [°]
• Injects Noise with every change in reference and load 0 0
• Unfiltered PWM Signal Jitter -20 -60

• Indeterministic Current Limiting -40 -120

• Requires Synchronous Real Time Current Feedback -60

10 100 1000 10000 100000
-180

Frequency [Hz]

17 12th OMICRON Lab Power Analysis & Design Symposium 2023

 Digital Control Scheme ACMC
Cascaded Average Current Mode Control Loop(s)
Anti- Anti- VOUT
Windup Windup
error Compensator output error Compensator output Plant
VREF + + PWM
- HCV(s) IREF - HCI(s) GP(s)
IL
Voltage Loop Current Loop
input Current
ADC Sense

input Voltage
ADC Divider

The average current feedback loop is established by cascading a dedicated voltage and current loop compensator, each tied to
its respective feedback signal. Just like in peak current mode control, the outer voltage loop compensator output provides the
reference for the inner current loop, where a second compensation filter adjusts the average inductor current by adjusting the
modulated switch node control signal.

18 12th OMICRON Lab Power Analysis & Design Symposium 2023

 Digital Control Scheme ACMC
Current Mode Plant GP(s)
60 180
40 120

Magnitude [dB]
Step 1: Single Current Loop Controller 20 60

Phase [°]
0 0
-20 -60
Anti- VOUT -40 -120

Windup -60 -180

error Compensator output Plant Current

10 100 1000 10000 100000

IREF +- PWM Frequency [Hz]

HC(s) GP(s) Sense
Type II Feedback Loop HC(s)
IL
60 180

Const. Current Loop 40 120

Magnitude [dB]
20 60

Phase [°]
input 0 0
ADC -20 -60
-40 -120
-60 -180
10 100 1000 10000 100000

Transient Injection Frequency [Hz]

Open Loop Transfer Function GOL(s)

60 180
When we measure the inner current loop, we find the current mode plant transfer function 40 120

Magnitude [dB]
being almost identical to its peak current mode counter part, mainly shaped by one dominant 20 60

Phase [°]
plant pole. 0 0
-20 -60
-40 -120
-60 -180
10 100 1000 10000 100000
Frequency [Hz]

19 12th OMICRON Lab Power Analysis & Design Symposium 2023

 Digital Control Scheme ACMC
Step #2: Closing the Voltage Loop

Anti- Anti- VOUT

Windup Windup
error Compensator output error Compensator output Plant
VREF + + PWM
- HCV(s) IREF - HCI(s) GP(s)
IL
Voltage Loop Current Loop
input Current
ADC Sense

input Voltage
ADC Divider

20 12th OMICRON Lab Power Analysis & Design Symposium 2023

 Average Current Mode Step Response
Control Loop Response vs. Output Voltage

3.32 0.025
3.30
3.28 0.020

Controller Input (Error) [U]

3.26

Output Voltage [V]

3.24 0.015
3.22
3.20 0.010
3.18
3.16 0.005
3.14
3.12 0.000
0 5 10 15 20 25 30
Sample Point n

Vout Error

21 12th OMICRON Lab Power Analysis & Design Symposium 2023

 Average Current Mode Step Response
Control Loop Current Response

IL

22 12th OMICRON Lab Power Analysis & Design Symposium 2023

 Digital Control Scheme ACMC
Step #2: Closing the Voltage Loop
Transient Injection Transient Response

Anti- Anti- VOUT

Windup Windup
error Compensator output error Compensator output Plant
VREF + + PWM
- HCV(s) IREF - HCI(s) GP(s)
IL
Voltage Loop Current Loop
input Current
ADC Sense

Transient Response
input Voltage
ADC Divider

Inductor current responds within one switching cycle while the voltage across the filter
capacitor responds slower, depending on its size and impedance. Hence, the current loop is
stimulated by two transients simultaneously with different frequency and phase angle. Transient Injection

23 12th OMICRON Lab Power Analysis & Design Symposium 2023

 Current Loop Transient Profile
Transient signal waveform when stimulated on Reference and Feedback
Transient Frequency seen by Current Loop
2.5

1.5

0.5
Magnitude

0
0 20 40 60 80 100 120 140 160 180 200

-0.5

-1

-1.5

-2

-2.5
Time

24 12th OMICRON Lab Power Analysis & Design Symposium 2023

 Voltage-to-Current Loop Synchronization
Approach #1: Sample Frequency Decoupling
Transient Injection Transient Response

Anti- Anti- VOUT

Windup Windup
error Compensator output error Compensator output Plant
VREF + + PWM
- HCV(s) IREF - HCI(s) GP(s)
Transient IL
Voltage Loop Current Loop
input Current
ADC Sense

input Voltage
ADC Divider
Transient Representation Transient Reception
𝑓𝑆𝐼
𝑓𝑆𝑉 =
10

Transient Injection
Control Frequency Sampling Frequency
25 12th OMICRON Lab Power Analysis & Design Symposium 2023
 Voltage-to-Current Loop Synchronization
Approach #1: Sample Frequency Decoupling
Transient Injection Transient Response

Transient
Anti- Representation Transient
Anti- Reception
V OUT
Windup Windup
error Compensator output error Compensator output Plant
VREF + + PWM
- HCV(s) IREF - HCI(s) GP(s)
IL
Voltage Loop Current Loop
input Current
ADC Sense

Control Frequency Sampling Frequency

input Voltage
ADC Divider
Transient Response
Transient Representation Transient Reception
𝑓𝑆𝐼
𝑓𝑆𝑉 =
10

Transient Injection
Control Frequency Sampling Frequency
26 12th OMICRON Lab Power Analysis & Design Symposium 2023
 Discrete Time Domain Data Acquisition

DTADC
VREF

DTSAM

Feedback
• The acquired signal is represented in “instantaneous” steps
• Signal sampling and conversion invokes phase shift
Vout[n/V]

• The last sample is valid until it is updated by the next sample

Input
Sample

Time / n →

27 12th OMICRON Lab Power Analysis & Design Symposium 2023

 Alias Frequencies
Sufficient Oversampling Ratio (Alias-free Result)
Waveform sampled at 18x fIN
1.5

0.5

0
0 45 90 135 180 225 270 315 360

-0.5

-1

-1.5

Feedback Sampled Input

28 12th OMICRON Lab Power Analysis & Design Symposium 2023

 Alias Frequencies
First Visible Sub-Frequency Component @ fIN  1/8th of fSAMPLE
Waveform sampled at 8x fIN
1.5

Artificial Frequency Component

1

0.5

0
0 45 90 135 180 225 270 315 360

-0.5

-1

-1.5

Feedback Sampled Input

29 12th OMICRON Lab Power Analysis & Design Symposium 2023

 Aliasing
Highly distorted Result @ fIN = fNYQUIST = ½ of fSAMPLE
Waveform sampled at 2x fIN
1.5

Artificial Frequency Component

1

0.5

0
0 45 90 135 180 225 270 315 360

-0.5

-1

-1.5

Feedback Sampled Input

30 12th OMICRON Lab Power Analysis & Design Symposium 2023

 Aliasing Example
• Once injected, alias frequencies cannot be distinguished from real
frequencies!

510 𝑘𝐻𝑧
160 𝑘𝐻𝑧
70 𝑘𝐻𝑧
𝑓𝑆𝐴𝑀
2 𝑓𝑆𝐴𝑀
25 𝑘𝐻𝑧
30 𝑘𝐻𝑧
40 𝑘𝐻𝑧
10 𝑘𝐻𝑧
Magnitude

Input Frequency

Input Frequency

Input Frequency
50k 100k Frequency
31 12th OMICRON Lab Power Analysis & Design Symposium 2023
 Voltage-to-Current Loop Synchronization
Approach #1: Sample Frequency Decoupling
Transient Injection Transient Response

Anti- Anti- VOUT

Windup Windup
error Compensator output error Compensator output Plant
VREF + + PWM
- HCV(s) IREF - HCI(s) GP(s)

Transient Injection IL
Voltage Loop Current Loop
input Current
ADC Sense

input Voltage
ADC Divider
AVG
Transient Representation Transient Reception

Heavy Input Filtering Required

• Analog Anti-Alias Filter
• Digital Moving Average Filter Transient Injection
Control Frequency Sampling Frequency
32 12th OMICRON Lab Power Analysis & Design Symposium 2023
Voltage-to-Current Loop Synchronization
Approach #1: Sample Frequency Decoupling
• Challenges
• Fast current response injects noise into voltage feedback
• High frequency noise must be filtered preventing alias frequencies from affecting the
voltage loop, making the voltage loop even slower
• Slow voltage loop response injects step artefacts into output voltage
• Low bandwidth response

• Applicable
• Driving large capacitive loads (e.g. battery chargers)
• Power Factor Correction

12th OMICRON Lab Power Analysis & Design Symposium 2023

 Voltage-to-Current Loop Synchronization
Approach #2: Low Gain Voltage Loop
Transient Response
Transient Response

fX = 1.2 kHz Anti- Anti-

fX = 10 kHz VOUT
Windup Windup
error Compensator output error Compensator output Plant
VREF + + PWM
- HCV(s) IREF - HCI(s) GP(s)
Transient IL
Voltage Loop Current Loop
input Current
ADC Sense

input Voltage
ADC Divider

𝑓𝑆𝑉 = 𝑓𝑆𝐼
Transient Reception Transient Injection

34 12th OMICRON Lab Power Analysis & Design Symposium 2023

 Voltage-to-Current Loop Synchronization
Fast Inner Current Loop Open Loop Transfer Function (fX = 10 kHz) EPC9151
300 W 16th Brick
Interleaved Buck Converter

 = 63°

m = -20 dB/dec

GM = -11 dB

EPC9151, 300 W 16th Brick Power Module

2-Phase Interleaved Buck Converter
fSW = 250 kHz

35 12th OMICRON Lab Power Analysis & Design Symposium 2023

 Voltage-to-Current Loop Synchronization
Slow Outer Voltage Loop Open Loop Transfer Function (fX = 1.2 kHz) EPC9151
300 W 16th Brick
Interleaved Buck Converter

 = 58°

m = -26 dB/dec

GM = -28 dB
EPC9151, 300 W 16th Brick Power Module
2-Phase Interleaved Buck Converter
fSW = 250 kHz

36 12th OMICRON Lab Power Analysis & Design Symposium 2023

Voltage-to-Current Loop Synchronization
Approach #2: Low Gain Voltage Loop
• Results
• Very good high frequency noise rejection without additional filtering
• Minimum perturbation of current reference
• Low bandwidth response

• Applicable
• Battery chargers
• LED Drivers
• Low-Performance DC/DC Converters
• Power Factor Correction

12th OMICRON Lab Power Analysis & Design Symposium 2023

Agenda
Power Supply Control Modes

Average Current Mode Control Implementation

Enforced Phase-Locking Method

Summary

12th OMICRON Lab Power Analysis & Design Symposium 2023

 Kuramoto Synchronization *
Approach #3: Enforced Phase-Locking Method
• *This is not a Kuramoto model implementation but warm
Thank You to Yoshiki Kuramoto for pointing us into the right
direction
• And to OMCRON Lab giving us the tool we needed to work out
how to implement it ☺

• The Kuramoto model in Mechanics describes the

synchronization of a large set of coupled oscillators.
• Famous example: self-synchronization of metronomes
swinging at different frequencies being forced into
synchronization by being coupled through a moving base.

39 12th OMICRON Lab Power Analysis & Design Symposium 2023

 “Kuramoto” Synchronization*
Approach #3: Enforced, Full Phase-Locking
*Screenshot of animation on Wikipedia
• *This is not a full Kuramoto model implementation but warm
Thank You to Yoshiki Kuramoto for pointing us into the right
direction
• And to OMCRON Lab giving us the tool to work out how to
implement it ☺

• The Kuramoto model in Mechanics describes the

synchronization of a large set of coupled oscillators.
Nil, partial and full phase-locking in an all-to-all network of Kuramoto oscillators. Phase-
• Famous example: self-synchronization of metronomes
locking is governed by the coupling strength K and the distribution of intrinsic frequencies
swinging at different
. Here,frequencies being forced
the intrinsic frequencies into from a normal distribution (M=0.5Hz,
were drawn
synchronization by being coupled
SD=0.5Hz). The yellow through
disk marksathemoving base.Its radius is a measure of
phase centroid.
coherence.

40 12th OMICRON Lab Power Analysis & Design Symposium 2023

 “Kuramoto” Synchronization*
Approach #3: Enforced, Full Phase-Locking
*Screenshot of animation on Wikipedia
• *This is not a full Kuramoto model implementation but warm
Thank You to Yoshiki Kuramoto for pointing us into the right
direction
• And to OMCRON Lab giving us the tool to work out how to
implement it ☺

• The Kuramoto model in Mechanics describes the

synchronization of a large set of coupled oscillators.
Nil, partial and full phase-locking in an all-to-all network of Kuramoto oscillators. Phase-
• Famous example: self-synchronization
locking is governed Doesby not
the apply
coupling
of metronomes
for strength
power supplies as the
K and the plant is not
distribution a
of intrinsic frequencies
swinging at different
. Here,frequencies being forced
strong
the intrinsic frequencies intomedium.
coupling
were drawn from a normal distribution (M=0.5Hz,
synchronization by beingBut
SD=0.5Hz). coupledthere through
Theisyellow another
disk marks athemoving
way tophase
enforcebase.
full phase-locking?
centroid. Its radius is a measure of
coherence.

41 12th OMICRON Lab Power Analysis & Design Symposium 2023

 Enforced Phase-Locking Method
Inner Current Loop Tuning
Voltage Mode Plant GP(s) Current Mode Type II/2P2Z Feedback Loop HC(s)
60 180 60 180

40 90° 120 40
70° 120

Magnitude [dB]
Magnitude [dB]

20 60 20 60

Phase [°]
Phase [°]
0 0 0 0

-20 -60 -20

Zero-Location -60

-40 -120 -40 -120

-60 -180 -60 -180

10 100 1000 10000 100000 10 100 1000 10000 100000
Frequency [Hz] Frequency [Hz]

Current Mode Plant GP(s) Open Loop Transfer Function GOL(s)

60 180 60 180

40 120 40 90° 120

Magnitude [dB]
Magnitude [dB]

20
90° 60 20 60

Phase [°]

Phase [°]
0 0 0 0

-20 -60 -20 -60

-40 -120 -40 -120

-60 -180 -60 -180

10 100 1000 10000 100000 10 100 1000 10000 100000
Frequency [Hz] Frequency [Hz]

4.7 kHz 4.7 kHz

42 12th OMICRON Lab Power Analysis & Design Symposium 2023
 Alternate Current Plant Measurement
Current Plant seen from Voltage Loop
Plant
L
A VOUT
VFB
COUT

IFB Unity Gain Loop makes voltage loop

“transparent” but injects transients in
current reference B
Rinj
PWM Logic Current Loop Controller Voltage Loop Controller
A
ADC
PER -
PWM Current + Voltage
Unity Gain - Ra
PDC S REF S ADC
Compensator Compensator
Loop +
PWM Clock
Anti- Anti- Rb
Windup REF
Windup

43 12th OMICRON Lab Power Analysis & Design Symposium 2023

 Enforced Phase-Locking Method
Results: Voltage Response of Current Loop Plant
1
When current loop gain is too high,
loop generates sub-harmonics
slightly above
90° fSAMP/[Length of Error History]

2
• Phase angle = 90° @ fR LC
• One pole at fR LC

Voltage Loop Compensation

• Type II (2P2Z) Compensator
• Zero Location < 4.7kHz (Compensating Pole)
• Pole Location < 60 kHz (Suppressing High Frequency Oscillations)

4.7 kHz 85 kHz

44 12th OMICRON Lab Power Analysis & Design Symposium 2023
 Alternate Current Plant Measurement
Current Plant seen from Voltage Loop
Plant
L
A VOUT
VFB
COUT

IFB Unity Gain Loop makes voltage loop

“transparent” but injects transients in
current reference B
Rinj
PWM Logic Current Loop Controller Voltage Loop Controller
A
ADC
PER -
PWM Current + Voltage
Unity Gain - Ra
PDC S REF S ADC
Compensator Compensator
Loop +
PWM Clock
Anti- Anti- Rb
Windup REF
Windup

45 12th OMICRON Lab Power Analysis & Design Symposium 2023

 Enforced Phase-Locking Method
Average Current Mode Control Open Loop Transfer Function Results

75°

53°

-8dB
-11dB

8 kHz
46 12th OMICRON Lab Power Analysis & Design Symposium 2023
Enforced Phase-Locking Method
Wrap-Up
• Most Recent Results
• Enforced Phase-Locking of Voltage and Current loop result in a stable and reliable system
• As a result, Current Loop is slower than the Voltage Loop
• Until today, results only verified on forward-type converters with fast current sense circuits

• Future Work
• Evaluation of application in other topology types
• Evaluation of impact of current feedback bandwidth/phase shift limitations

12th OMICRON Lab Power Analysis & Design Symposium 2023

Agenda
Power Supply Control Modes

Average Current Mode Control Implementation

Enforced Phase-Locking Method

Summary

12th OMICRON Lab Power Analysis & Design Symposium 2023

Summary
• Average Current Mode Control is a universal control mode applicable in
• Constant Current and Constant Voltage Sources
• PFC and DC/DC Converters
• Battery Chargers & LED Drivers
• Allows current-oriented control algorithms (e.g. MPPT, Bidirectional Control)
• Sustained Current Limit capability
• Less restrictive on current feedback quality
(simplifies current sense circuits)

• Higher CPU load in digital control loop implementations

• Classic configurations have limited bandwidth
• Promising: Phase-Locking may be key to mitigate bandwidth limitations
12th OMICRON Lab Power Analysis & Design Symposium 2023
 Q&A

12th OMICRON Lab Power Analysis & Design Symposium 2023

 Thank You!
May the power be with you!

12th OMICRON Lab Power Analysis & Design Symposium 2023