Mid 2 ADE bit bank
Unit-3
1.How many combination are there for four input gates
a) 2 b) 4 c)1 6 d) 8
2. The don’t care condition could be used in order to simplify the Boolean expressions in
the ___________.
a) Latches b) K-maps c) Terms d) Registers
3. Simplify the expression: FT’ + F’ + T’F’.
a) F’ + T b) FT’ c) (FT)’ d) T’ + F
4.If all the inputs are HIGH then the output is HIGH
a) AND b) NAND c) OR d) NOR
5. The output of SUM is equal to output of
a) OR gate b) AND gate c) X-OR gate d) X-Nor gate
UNIT-IV
6.A combinational circuit which is used to change a BCD number into an equivalent decimal number is
(a) Decoder b) Encoder c) Multiplexer d) Demultiplexer
7. How many data select lines are required for selecting eight inputs?
a) 1 b) 2 c) 3 d) 4
8.The binary subtraction 0 – 0 =
a) difference = 0, borrow = 0 c) difference = 1, borrow =1
b) difference = 1, borrow = 0 d) difference = 0, borrow = 1
9. 3 bits full adder contains ________
a) 3 combinational inputs b) 4 combinational inputs
c) 6 combinational inputs d) 8 combinational inputs
10. In a combinational circuit, the output at any time depends only on the _______ at that
time.
a) Voltage b) Intermediate values c) Input values d) Clock pulses
11. Decimal digit in BCD can be represented by ____________
a) 1 input line b) 2 input lines c) 3 input lines d) 4 input lines
UNIT-V
12. Which of the following is correct for a gated D flip-flop?
a) The output toggles if one of the inputs is held HIGH.
b) Only one of the inputs can be HIGH at a time.
c) The output complement follows the input when enabled.
d) Q output follows the input D when the enable is HIGH.
13. What is the hold condition of a flip-flop?
a) both S and R inputs activated b) no active S or R input c) only S is active d) only R is active
14. What is a shift register that will accept a parallel input, or a bidirectional serial load and internal shift
features, called?
a) tristate b) end around c) universal d) conversion
15. In what type of shift register do we have access to only the leftmost and rightmost flipflops?
a) Serial-in serial-out shift register b) Serial-in parallel-out shift register c) Parallel-in serial-out shift
register d) Parallel-in Parallel-out shift register
16. Whose operations are more faster among the following?
a) Combinational circuits b) Sequential circuits c) Latches d) Flip-flops
17. For realization of JK flip-flop from SR flip-flop, the input J and K will be given as
___________
a) External inputs to S and R b) Internal inputs to S and R
c) External inputs to combinational circuit d) Internal inputs to combinational circuit
18. The toggle mode of J-K flipflop is
a) J=0,K=0 b) J=0, K=1 c)J=1,K=0 d)J=1,K=1
19. The minimum number of flip flops required for a mod-12 ripple counter is
a)3 b)4 c) 6 d) 12
20. An Asynchronous sequential circuit
a) does not use clock pulses b)only one inpu can change at a time
c)consists of combinational circuit and latches d) meets all above condions
FILL IN THE BLANKS
UNIT III:
21. The Boolean expression C + CD is equal to _____,_C_____.
22. The equality (A ∙ B ∙ C)’ = A’ + B’ + C’ is better known as ___De Morgan's Law._____________ Law.
23. A+AB+ABC+ABCD+ABCDE+….=_____A_________.
24. The logic expression F= AB+B´C+AC is in ___Sum of Products_SOP________ form.
25. The number of cells in 6- variable K-Map is____2^6=64_________ .
UNIT IV:
26. BCD stands for ___Binary-Coded Decimal_____________.
27. Multiplexers, demultiplexers, decoders, encoders are _____Combinational________ logic circuits.
28. In a 1-to-16 demultiplexer, the number of control input will be __2^4 = 16)____.
29. If there are n selection lines, then the number of maximum possible input lines is _2^n___.
30. A logic expression form most suitable for realization using only NOR gates is _____Product of Sums
(POS)_____.
31. _____n (or)___ Select__ inputs are used to control the operation of decoder.
32. A parallel adder in which carry out of each full adder is the carry in to the nest most significant adder
is called __Ripple Carry Adder___________.
33.A decimal to BCD encoder ia a ______10__ line to _____4____ line encoder
34.In BCD addition , 0110 is added to the sum for getting correct result, if ___the sum exceeds
9_________.
35. A multiplexer with four select lines is __16:1 multiplexer (since 24=162^4 = 16)___________
multiplexer.
UNIT-V:
36. On a J-K flip-flop, when is the flip-flop in a hold condition J = ___0__ , K = __0____.
37. In synchronous systems, the exact times at which any output can change state are determined by a
signal commonly called the __Clock______.
38. The advantage of a J-K flip-flop over an S-R FF is that _It eliminates the invalid state issue where
both S and R are 1 simultaneously._______.
39. A type of shift register that requires access to the Q outputs of all stages is __Universal shift
register______.
40.The Characteristic equation of T flipflop is ______Qn+1=T⊕Qn__________________.
41. A circuit used to count the number of pulses is called a _Counter__________.
42. A _Flip-flop__________ is called a single bit register.
43. Asynchronous counters are also called as ___Ripple___________ counters.
44. Data is said to be in parallel form if the bits are available
___Simultaneously___________________.
45. ___T flip-flop ___________ flipflop is preferred for counting and __D flip-
flop________ is preferred for data transfer.
46. Combinational circuits are __Level _______ triggered and sequential circuits are
_Edge_________ triggered.
47. To design a counter with 4bits , the number of flipflops used are __4_________.
48. The maximum modulus of a counter with seven flipflops is
_____27=128_____________.
49. The number of flipflops required in a counter to count 68 pulses is
__⌈log2(68)⌉=7__________.
50. The flipflop has two outputs which are __Q and Q' (complement of
Q)_________________.
51.When an inverter is placed between the inputs of SR flipflop , the resulting flipflop is __
D flip-flop___________.
