MID-TERM EVALUATION NO.

2 OF 3 2024/2025 Date: 20 January 2025

Student’s Name: Duration: 2 Hours

Subject: COMPUTER SCIENCE Student’s Number :

Class: LOWER SIXTH SCIENCE Number Sat :

COMPETENCE TO BE ATTAINED

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APPRECIATION OF COMPETENCE (KINDLY TICK)

NOT ATTAINED STILL TO BE ATTAINED ATTAINED

EVALUATION MARK

Section A: ….............. Section C: …......... Total Marks: ……………

Section B: ….............. Section D: …........

PARENT’S OR GUARDIAN’S VISA

Name and
surname: …………………………………………………………………………....................
Date: ….................................................... Tel: …................................................................

Parent’s
remarks ………………………………………………………………………………………
………………………………………………………………………………………………
Parent’s Signature: …............................................................................................................
SECTION A: ANSWER ALL QUESTION. COPY THE CORRECT ANSWER INTO
THE TABLE BELOW
1. Two registers involved in the fetch- C. Require different amount of time
execute cycle are: difference between any two being same.
A. The program counter and the stack D. Require different amount with time
pointer difference between any two tasks being
B. B The Accumulator and the program different.
C. The accumulator and the current 7. Which of the following is NOT an
instruction register. advantage of Dynamic RAMs?
D. The memory address register and the A. High density
memory data register B. Low Cost
2. The ROM containing the BIOS can be C. High Speed
considered as D. No need of memory refreshed
A. A secondary storage unit. 8. In the memory hierarchy the fastest
B. A peripheral unit memory is
C. Part of the memory unit
A. RAM
D. A processing unit
B. Cache
3. The address bus of a certain computer
C. CPU Registers
has 8 lines. What is the maximum
D. Virtual Memory
number of addressable memory cells?
9. The virtual Memory of a computer
A. 265
system may be
B. 256
A. Of unlimited size
C. 252
B. As big as the maximum capability of the
D. 255
computer system
4. A CPU has a l6-bit program counter.
C. Of size equivalent to the total capacity
This means that the CPU can address:
of secondary storage plus that of RAM
A. 16K memory locations.
D. None of the above
B. 32K memory locations.
10. A multi-programming computer is one
C. 64K memory locations.
which:
D. 256K memory locations.
A. Has several processors working in
5. Program pre-emption is
parallel.
A. Forced withdrawal of CPU from a
program which is executing. B. Having multiple users working at the
B. Release of CPU from by a program after same time
completing its task. C. Is capable of running two or more
C. Forceful allotment of CPU by a program program apparently simultaneously
to itself. D. Multiple programs are made to run at
D. Program termination due to detection of the same time
an error.
6. The concept of pipelining is most 11. One job of the scheduler is to
effective in improving performance if A. Ensure hardware resources are kept free
the tasks being performed in different from where they are needed
stages: B. Provide acceptable response time to the
A. Require different amounts of time. users
B. Require about the same amount of
C. Ensure that one process does not D. 64 x 264
accidentally access another’s memory 16. Convert (77.34)8 to decimal:
location a) 63.5
D. Select a scheduling algorithm to achieve b) 63.45
maximum throughput c) 63.85
12. A process may be at any time running, d) 63.75
ready or suspended, which of the 17. The interrupt that comes from
following statement is true input/output devices are___________.
A. A process will join the queue of A. internal interrupts.
suspended jobs if, while it is running the B. external interrupts.
time slice expires C. software interrupts.
B. A process is ready if it is waiting for an D. hardware interrupts.
I/O device to become free 18. _________is a processor architecture
C. A process is running if it is in memory, that utilizes a small, simple, highly
waiting for the process to become free. optimized set of instructions.
D. A process is suspended if it is waiting A. RISC
for an I/O device to become free. B. CISC
13. On receiving an interrupt, the CPU: C. SIMD
A. Finishes executing the current D. MISD
instruction and moves to the interrupt 19. With the round robin CPU scheduling in
service routine a time-shared system ________.
B. Immediately moves to the interrupt A. Using very large time slice degenerates
service routine without completing in to first come first served algorithm
current instruction. B. Using extremely small time slices
C. Releases the control on I/O lines and improve performance
memory lines. C. Using extremely small time slices
D. Makes any peripheral device that degenerate in to last in first out
requested the interrupt to wait for a algorithm
fixed interval of time. D. Using medium sized time slices leads to
14. Which of the following source of shortest remaining time next algorithm
interrupt has the highest priority 20. Memory management is necessary
A. Division by zero because
B. Real-time clock A. The memory is finite.
C. Memory parity error B. Many programs have to run
D. Keyboard key pressed simultaneously
C. We operate in a multitask environment
15. A microprocessor has a data bus with 64
D. All of the above
lines and an address bus with 32 lines.
The maximum number of bits that can
be stored in memory is
A. 32 x 232
B. 32 x 264
C. 64 x 232
 ANSWER GRID
1 6 11 16
2 7 12 17
3 8 13 18
4 9 14 19
5 10 15 20

SECTION B
Answer any two questions: All questions carry equal marks

1. i) a) Describe the Von Neumann model and the stored program concept. (4marks)
b) How has the stored program concept helped to modernize computing as we find nowadays?
(3marks)
ii) a) Briefly describe the processes of polling and interrupts in hardware
communication. (4marks)
b) In a hospital setting, where surgical operations are done by a robot which is controlled by a
program installed in a general-purpose computer, when the operation process is started, which of
polling or interrupts should be used in managing hardware communication? Justify your choice
(4marks)
iii) Access to the cache memory is faster than accessing the RAM. Define CACHE
MEMORY. Why should the cache not be made large enough so as to replace the RAM?(5
marks)

2. (i) (a) What is an operating system? (2 marks)

(b) why is process management necessary in modern operating systems (4marks)
(ii) The processes p1 to p4 have burst times as shown in the table below
Process ID Burst
(PID) time (in ms)
P1 10
P2 6
P3 7
P4 15
Draw Gantt charts to show how the four processes obtain and use the processor from start to
termination following Round Robin and Shortest Remaining Time Next scheduling algorithms.
The time slice is 5ms. (assume the processes are in the same order in the ready queue)
(4 marks)
Calculate the average turnaround time (Att) for each of the algorithms (2 marks)
Which of the algorithms would be preferable to implement for these processes? (2 marks)

R1
P1 P2 R+

P3 R2 P4 R3 P5

P6 R4 R5

R6 P7

(iii) The following is a resource allocation graph for resources R1-R6 and the processes P1 –P7,
From this graph, is there a possibility of deadlock? If yes give the deadlock cycle (3 marks)
If R+ were an instance of R3 is the possibility of deadlock completely eliminated? Explain! (3
marks)

3. i) a) Describe how swapping is used in solving the problem of inability of memory to host
all executing programs (3marks)
b) What technique is used to execute a program whose size is bigger than the Ram size?
(1mark)
c) Briefly describe the technique of paging in virtual memory. (3marks)
ii) a) Why do we have to manage memory? (3marks)
b) Differentiate between logical and physical addresses.
(2marks)
Using an 8-bits 2’s complement notation, perform the following computations:

a) - 35 + (- 11) and 19 – (- 4) (2 marks)

b) Add (93)16 and (DE)16 (2 marks)
c) -25 – (- 38) (2 marks)

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4. a) Give the syntax and flowchart representation of:

i. Selection control structure (IF statement) (2 marks)
ii. Iteration while (2 marks)
iii. Looping repeat until (1 marks)
iv. Nested IFs (2 marks)
b)Differentiate between stacks and queues data structures. (2 marks)

c) Differentiate between IF statement and the CASE statement and give the syntax of each. (2 marks)

d) Algorithm whatamidoing
2.var f,n,i:integer
3.START
4. Display (” enter a positive integer”)
5. read(n)
6. i=1
7 .f=1
8. WHILE(i<=n)
9. f=f*i
10. i=i+1
11. endwhile
12. Display (the value of f is:”f)
13.stop
Given the algorithm above

1. What is the name given to the segment from :

i. Line 8 to line 11.
ii. Line 4 to line 7. (2 marks)
2.write the output of the algorithm when n takes the following values. (3 marks)
i. N=4.
ii. N=5
iii. N=6
3.bearing in mind your output in question 2, state in one sentence what this algorithm does? (1 marks)
4. write a flowchart of the above algorithm. (3 marks)