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Virtuoso Power Manager Guide: Product Version IC23.1 August 2024

The Virtuoso Power Manager Guide provides comprehensive instructions for using the Virtuoso Power Manager software, including licensing requirements and toolbar functionalities. It details the power management flow, setup for automatic extraction of power intent, and the import and export processes for power intent in designs. The guide also covers in-design checks, design verification, and various modeling techniques essential for effective power management in electronic design automation.

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Virtuoso Power Manager Guide: Product Version IC23.1 August 2024

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Virtuoso Power Manager Guide

Product Version IC23.1

August 2024
© 2025 Cadence Design Systems, Inc.

Printed in the United States of America.

Cadence Design Systems, Inc. (Cadence), 2655 Seely Ave., San Jose, CA 95134, USA.
Open SystemC, Open SystemC Initiative, OSCI, SystemC, and SystemC Initiative are trademarks or
registered trademarks of Open SystemC Initiative, Inc. in the United States and other countries and are
used with permission.
Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. contained in this document
are attributed to Cadence with the appropriate symbol. For queries regarding Cadence’s trademarks,
contact the corporate legal department at the address shown above or call 800.862.4522. All other
trademarks are the property of their respective holders.
Restricted Permission: This publication is protected by copyright law and international treaties and
contains trade secrets and proprietary information owned by Cadence. Unauthorized reproduction or
distribution of this publication, or any portion of it, may result in civil and criminal penalties. Except as
specified in this permission statement, this publication may not be copied, reproduced, modified, published,
uploaded, posted, transmitted, or distributed in any way, without prior written permission from Cadence.
Unless otherwise agreed to by Cadence in writing, this statement grants Cadence customers permission to
print one (1) hard copy of this publication subject to the following conditions:
1. The publication may be used only in accordance with a written agreement between Cadence and its
customer.
2. The publication may not be modified in any way.
3. Any authorized copy of the publication or portion thereof must include all original copyright,
trademark, and other proprietary notices and this permission statement.
4. The information contained in this document cannot be used in the development of like products or
software, whether for internal or external use, and shall not be used for the benefit of any other party,
whether or not for consideration.
Disclaimer: Information in this publication is subject to change without notice and does not represent a
commitment on the part of Cadence. Except as may be explicitly set forth in such agreement, Cadence does
not make, and expressly disclaims, any representations or warranties as to the completeness, accuracy or
usefulness of the information contained in this document. Cadence does not warrant that use of such
information will not infringe any third party rights, nor does Cadence assume any liability for damages or
costs of any kind that may result from use of such information.
Cadence is committed to using respectful language in our code and communications. We are also active in
the removal and replacement of inappropriate language from existing content. This product documentation
may however contain material that is no longer considered appropriate but still reflects long-standing
industry terminology. Such content will be addressed at a time when the related software can be updated
without end-user impact.
Restricted Rights: Use, duplication, or disclosure by the Government is subject to restrictions as set forth
in FAR52.227-14 and DFAR252.227-7013 et seq. or its successor
Virtuoso Power Manager User Guide

Contents
1
Virtuoso Power Manager ......................................... 9
Licensing Requirements of Virtuoso Power Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power Manager Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2
Virtuoso Power Manager Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Basic Flow in Power Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Recommended Use Model for Power Intent Creation and Verification . . . . . . . . . . . . . . 17
Power Intent of Large Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3
Setup for Automatic Extraction of Power Intent . . . . . . . . . . . . . . . 21
Registering Name-Based Supply Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Registering Regular Expressions-Based Supply Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Supply NetSet Properties Prefix Registration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Excluding Power and Ground Nets from Name-Based Registration . . . . . . . . . . . . . . . . 30
Registering Monitor Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
User-Defined Macros Registration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Registering Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Special Cell and Standard Cell Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Design Sub-Block Modeling During Top-Level 1801 Design Model Extraction . . . . . . . . 38
Reference Libraries or Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
MLDB Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Registering Device and Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Passive Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Resistors as Short Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Backtrace Enable Signals of Special Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Single Rail Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

August 2024 3 Product Version IC23.1

Stack Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Terminal Name Registration for Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Performing In-Design Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Voltage Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Setting Supply States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Registering Supply Set and Power Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Registering Port Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Miscellaneous Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Setup File Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Loading Power Intent Extraction Options from a File . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Saving Power Intent Extraction Options to a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

4
Power Intent Import. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Import Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Importing Power Intent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Redirected netSet Property Creation and Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Tie Connection Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Handling of Low Power Special Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Support of Hierarchical 1801 for Import Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Honoring Command Sequence and Precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Removing Imported Power Intent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

5
Running In-Design Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Defining the Severity of Design Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Level Shifter Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Isolation Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Bulk Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Checking a Design in Foreground Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Checking a Design in Background Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Loading the Violations Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Filtering Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Generating Signal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

August 2024 4 Product Version IC23.1

6
Exporting Power Intent of a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Export Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Extracting the Power Intent from a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Identification of Design Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Design Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Creation of Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Default Power Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Power View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Exporting 1801 Design Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Exporting 1801 Power Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Exporting Liberty Power Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Special Isolation Cells in Liberty Power Model Export . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Export of Switch Function and Isolation Enable Condition Expressions . . . . . . . . . . . . 174

7
Verifying Power Intent of a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Preparing and Running CLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Checking Design Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Power Intent Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Power Intent Verification Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

A
Virtuoso Power Manager Environment Variables . . . . . . . . . . . 185
addNotInGndPgFunction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
allowConstantExpressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
allowDomainWithoutElements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
allowEmptyDomains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
allowInoutLDOPins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
allowInoutMonitorPins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
allowInOutPortAsRegulated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
allowIsUnconnectedAsAttrInLiberty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
autoCorrectNativePSWOptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
considerShortThreshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

August 2024 5 Product Version IC23.1

createExtractionLogFile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
createPinsOnImport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
delimiterForInternalPower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
enableCDMAttr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
enableGlobalBTCaching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
exportSwitchFunctionDerivationForAllUsedVirtualSupplies . . . . . . . . . . . . . . . . . . . 206
exportIsoEnableConditionDerivationForAllTopIsolatedPorts . . . . . . . . . . . . . . . . . . 207
extractionLogPath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
extractParasiticDiode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
lpDBGlobalSearchLibs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
lpDBGlobalSearchViews . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
lpDBPurgeOnDesignPurge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
lsSingleRailInputPrefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
maxConsecutiveTxChannelCrossingsForABT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
maxConsecutiveTxGateCrossingsForABT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
maxInputPinsForAlgoStdCellABT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
maxOutputPinsForAlgoStdCellABT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
minTimeElapseForProgressInfo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
overrideSigTypeFromSetup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
powerDownFunctionForIOPorts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
printAliveAndPermitAttributesinDotlib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
printBusBitDirectionInLiberty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
printCoupledSupplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
printModelInSDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
printProgressInfo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
printSupplyNetInfo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
reduceBoolExpressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
removeHierADSupForPorts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
removeHierSupForInPorts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
removeHierSupForOutPorts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
removeInternalNetFromPgFn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
removePST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
runIDCInBackground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
separatorForBit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
signalPortsForIsoEnableConditionDerivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
singleRailAttrPropagation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

August 2024 6 Product Version IC23.1

specialCellInfoFile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
stopViewList . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
switchPinForNoPortAtSwitchablePower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
switchViewList . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
updateRelatedSuppliesForNorNandIsoPorts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
updateShortAttribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
updateUnconnPortsforAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
useANDForMultipleSupplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
useNandNorBaseIsolationTypes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
vbHierScopeLevel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
vbMaxHierDepth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
virtualSuppliesForSwitchFunctionDerivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
writeMixedFormatPST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

B
Virtuoso Power Manager SKILL Functions . . . . . . . . . . . . . . . . . . . 257
vpmDefinePowerSwitchInstance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
vpmExportDotLib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
vpmExportPowerIntent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
vpmExportPowerModel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
vpmExportPowerIntentSetup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
vpmExtractPowerIntent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
vpmGenerateSigInfo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
vpmImportPowerIntent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
vpmImportPowerIntentSetup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
vpmLoadInDesignViolations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
vpmRemoveImportedPowerIntent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
vpmRemovePowerSwitchInstance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
vpmRunInDesignChecks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
vpmSetViolationBrowserOptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

C
1801 Support in Power Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
General 1801 Command Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
1801 Special Cell Definition Command Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

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Customized Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

Liberty Attributes Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

D
Virtuoso Power Manager Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Add 1801 File Binding Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Add Device Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Add Port Attributes Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Add Power Domain Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Add Supply Nets Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Add Supply Sets Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Add Supply State Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Export Liberty Model Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Export Power Intent Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Generate Signal Information Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Import Power Intent Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Load Violations Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Power Manager Setup Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Supply Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
In-Design Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Export . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Prepare CLP Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Run CLP Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Run In-Design Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Run In-Design Checks (Non-Blocking) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

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1
Virtuoso Power Manager

Virtuoso Power Manager provides an interface to specify, import, and export low power
intent for designs. It provides the capability to perform static low power verification on
designs by using Conformal Low Power (CLP) integration with Virtuoso and supports
analog, digital, and mixed-signal implementations.
Power Manager, by using the import flow, can annotate and stitch the top-down power
connectivity for a hierarchical design by using the connectivity model for inherited
connections. Using the export flow, you can extract the power intent of a fully connected
design schematic. You can also generate a Liberty-based macro cell for custom blocks using
Power Manager for full-chip power intent verification.
When using special power-saving techniques for efficient power consumption, you often
implement stringent power schemes throughout the design that add to the overall complexity
while verifying the design. In addition, there are design scenarios that should be verified for
the correct functioning of a circuit, for example, the correct biasing of MOS devices. To
reduce the complexity, you should be able to perform a few basic-to advanced-level circuit
design checks on schematic designs. The In-Design Checks feature in Power Manager
provides such static checks that do not require circuit simulation.

An important consideration in IC design is to conserve power. Designers use special power

saving techniques to achieve this objective. Some examples of these techniques include:
■ Supplying different voltages for different groups of cells, therefore, creating multiple
power domains.
■ Using low power special cells to switch between the power-supply levels or to shut off
groups of cells during specific periods of circuit activity, in turn, creating different power
modes.

The definitions of the power domains, power modes, and low power special cells specify the
power intent for a design. When you create a design that has some low power design
techniques applied, you should be able to:
■ Package and export the power intent along with the design by extracting the same from
a hierarchical schematic.

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■ Verify the power intent of the design along with the functionality before it is further
instantiated in other designs.
■ Import an existing power intent and annotate it on the hierarchical schematic in terms of
a completely resolved top-down power connectivity.

Power Manager addresses the need for the creation and verification of power-aware designs,
including validating power intent changes during IP authoring. It provides the capability to
annotate the design's power intent-related issues on the schematic. Therefore, it helps in the
timely correction of power-related violations in the design.

Use Power Manager to specify, import, extract, and export the low power intent for designs.
You can capture the power intent for the design (including its submodules) and map the power
domains of an IP block with the domains of the designs. This helps in integrating an IP in the
design.

Power intent definition at the design level is needed to connect IP blocks, which could be
empty, partially complete, or non-structural, to top-level power ground (PG) pins. This
definition, along with incremental change in power intent resulting from design edits, can be
exported.

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Low power verification is required to ensure structural and electrical accuracy for mixed-
signal designs. Native low power checks within the Virtuoso Power Manager environment
help in detecting low power violations during the IP authoring stage. The early feedback saves
iterations later in the cycle. In-design checks work at the device level and enable the structural
verification of custom AMS blocks. These are static circuit checks, which can be performed
to fix design issues before proceeding to the dynamic verification (simulation) stage. The
checks are performed after voltage propagation is done on the topology of a circuit. The
voltage propagation does not require a transient simulation; therefore, a static check is faster
than a dynamic check.
In-design checks are targeted to provide hints to designers about various low power and
structural discrepancies in the design and help in improving the efficiency of the design
development cycle by reporting design issues that can be fixed while the schematic design
is still under development.

Verification can happen early in the design cycle and natively within the Virtuoso environment
without invoking other tools; therefore, no data sharing or data translation occurs between
tools. All formats are supported for checks, such as 1801, Liberty, or dotlib. Inherited and
global power supply connections are also supported. In-Design Checks are applicable to
discrete devices. The checks also work on hierarchical and read-only designs.

You can start Virtuoso Power Manager by clicking Power Manager from the Launch menu.

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The Power Manager workspace window is opened.

Related Topics

Licensing Requirements of Virtuoso Power Manager

Power Manager Toolbar

Licensing Requirements of Virtuoso Power Manager

You need the following licenses to use Power Manager.

Base Product Name License Feature Name License Type

Virtuoso Schematic Editor XL Virtuoso_Schematic_Editor_XL UHD
(95115)
Virtuoso Power Manager VIRTUOSO_POWER_MANAGER J
(95127)

The VIRTUOSO_POWER_MANAGER license is used until the last Power Manager

schematic window along with the Power Manager Setup form is closed.

Related Topic

Virtuoso Power Manager

Power Manager Toolbar

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Power Manager Toolbar

In the Power Manager workspace, the following commands are available on the Power
Manager toolbar in the workspace.

The toolbar lets you access the various commands and related forms supported by Power
Manager. It is dockable and can be placed at the desired location within the window.

Refer to the following table for more information about the options on the toolbar.

Icon Command Use to... Form

Setup Specify the setup Setup for Automatic
information for running In- Extraction of Power
Design checks, importing, Intent
exporting, extracting, or
removing power intent.
Import Power Import the power intent for Power Intent Import
Intent the given cellview.

Remove Power Remove all the power intent Removing Imported

Intent information from the current Power Intent
cellview.
Extract Power Extract the power intent of Extracting the Power
Intent the given cellview. Intent from a Design

Export Power Export the power intent of Exporting 1801 Power

Intent the current cellview by using Model
a .upf file.
Export Liberty Export the Liberty model of Exporting Liberty Power
Model the current cellview by using Model
a .lib file.
Prepare CLP Generate the input files at a Preparing and Running
user-specified location and CLP
therefore, provide an
opportunity to view, inspect,
and edit the files.

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Icon Command Use to... Form

Run CLP Start CLP and use the files Preparing and Running
created during CLP CLP
preparation, for power
verification
Run In-Design Perform static checks on the Running In-Design
Checks given design. Checks

Load Violations Load the file containing Loading the Violations

violations after the design Database
check.
Generate Signal Generate an output file that Generating Signal
Info contains the net voltages for Information
supply and signal nets,
which are computed based
on supply net and
technology information
provided in the Power
Manager setup.

Alongside, these options are also available from the Power Manager pull-down menu in the
workspace.

Related Topic

Virtuoso Power Manager

Licensing Requirements of Virtuoso Power Manager

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2
Virtuoso Power Manager Flow

The flows in Virtuoso Power Manager offer an automated solution for capturing the power
intent of a design. Usually for small designs, it is convenient to write the power intent
manually. As the design complexity increases, it becomes mandatory to have an automated
solution. The complexity in designs can be about multiple power domains, different voltage
levels, switchable power domains, or the functionality implemented using low power design
techniques by the use of low power special cells, such as level shifters, isolation cells, and
power switches.
You can seamlessly capture the power intent of digital, analog, and mixed-signal designs
and verify that the power intent has been implemented correctly. In addition, you can also
track power intent changes during IP authoring. You can export the power intent of the IP
design in the standard IEEE 1801 format, which can be further utilized by the SOC
verification team for full-chip low power verification.

Related Topics

Basic Flow in Power Manager

Recommended Use Model for Power Intent Creation and Verification

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Basic Flow in Power Manager

The basic Power Manager flow is illustrated below.

The Power Manager flow includes the following main tasks:

1. Prepare setup for capturing power intent.
2. Import existing 1801 power intent on a hierarchical schematic.
3. Update design.
4. Run In-Design Checks.
5. Extract relevant power intent information from design.
6. Export the extracted design information in the IEEE 1801format.
7. Verify the exported power intent of the design.

Related Topics

Virtuoso Power Manager Flow

August 2024 16 Product Version IC23.1

Recommended Use Model for Power Intent Creation and Verification

Recommended Use Model for Power Intent Creation and

Verification
Follow the use model described by the steps given below to get an accurate power intent for
your design:
1. Prepare a setup file for importing power intent on a design, running In-Design Checks,
or extracting power intent from a design. This requires registration of the components
that describe power intent. For example, you can register power nets, ground nets, and
special low power cells.
See Setup for Automatic Extraction of Power Intent.
2. Register special low power cells or custom standard cells by using the Liberty definitions
or a 1801 special cell definition file.
See Registration of Low Power Special Cells and Standard Cells.
3. If there is an incomplete hierarchical design that already has the power intent available,
for example, a digital block, use the import 1801 flow to complete the power connectivity
of that hierarchical design. Perform the schematic hierarchy check while importing an
existing 1801 power specification on a hierarchical schematic.
See Power Intent Import.
4. Open the design in Power Manager and check for an existence of primitive cell instances
or single supply cells, such as transistors or resistors at the top level of designs. If these
cells exist at the top level, create one or more new blocks and move these cells to the
new blocks.
This is required because the primitive instances do not have a power pin or ground pin
and therefore, are not assigned to any power domain or domain mapping. In such a case,
the design netlist generated for the verification includes these primitive cell instances, but
the exported 1801 file does not include these instances. As a result, during power intent
verification, when CLP does not find the power intent for these instances in the1801 file,
it reports errors or warnings. These can be avoided during netlisting by using the
appropriate flags to customize the netlist so that it does not extract primitives.
See Verifying Power Intent of a Design.
5. Load the setup file, including the customizations required for running the In-Design
checks. Check the analog or mixed signal custom blocks using static, pre-configured in-
design checks, and verify the low power design implementation.

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See Running In-Design Checks.

Once the results obtained are satisfactory, extract the power intent details of the top
design. Power Manager extracts the power intent of hierarchical design, which can be
exported to a 1801 file. A separate OA view called the power view is also generated at
the time of extraction that captures all the setup information, internal data structure, and
the power intent details. This view can be reused in the same Virtuoso session.
See Exporting Power Intent of a Design.
6. The standard and special cells in the design should have their associated schematic or
Verilog Symbol views with the PG pin information. This is a requirement for the tool to
generate a Verilog netlist with the PG information, before verifying the power intent.

Tip
CLP is a digital verification tool. It supports the inherited connections and global nets
with explicit p/g connections to the standard cells because it needs maximum low
power check coverage. CLP performs physical low power verification by tracing the
explicit p/g nets and deriving power domain information accordingly. This is the most
comprehensive design structural check.
7. Verify the power intent of your design.
See Verifying Power Intent of a Design.

Related Topics

Virtuoso Power Manager Flow

Basic Flow in Power Manager

Power Intent of Large Designs

If the top design is large, the power intent extraction step might lead to memory-related
issues. In such cases, follow the bottom-up approach, where you first extract the power intent
of sub-blocks separately in 1801 files and then, associate the 1801 files with their respective
instances in the top design. Consequently, when you extract power intent for the top design,
the tool consumes less memory. Also, you can apply the bottom-up approach when extraction
options cannot be shared between the top design and the sub-blocks. For example, when the
power / ground nets definitions, power / ground net voltage definitions, or power net–ground
net voltage pair definitions in the top design are different from the sub-block definitions, use
the bottom-up approach.

August 2024 18 Product Version IC23.1

Related Topics

Virtuoso Power Manager Flow

Basic Flow in Power Manager

Recommended Use Model for Power Intent Creation and Verification

August 2024 19 Product Version IC23.1

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3
Setup for Automatic Extraction of Power
Intent

To run in-design checks or to extract the power intent from a design, you need to provide
inputs that are required by the tool for correct identification of design topology and define key
set of rules. For example, you can define a setup that identifies all the power nets in your
design, creates power domains, creates supply states, or redefines the severity of certain
checks.

The Power Manager setup can be classified as:

■ Common setup: This type of setup information is common to a set of designs. It includes
technology, environment, data integrity checks, and so on. This setup information is
stored in a CSF-searchable location and is applied when no design-specific information
is found.
■ Project-specific setup: This information consists of the project-specific setup and design-
specific details. It includes all types of settings and it is automatically applied if available
for a design. You can register and specify values in the Power Manager Setup form and
save them in the setup file for a project to ensure that each command is implemented
according to the project setup.

A setup file can be placed at one of the following three locations:

■ Device-level information inside PDK Library in lpLibSetup.il
■ Project-level common settings at the CAD level inside .cadence/dfII/vpm or some
other CSF-compatible path in lpSetup.il
■ User-defined settings that are defined in Power Manager Setup form through registration
and saved in a setup template file

There are two options in the setup template to control the enabling of the project-level (CAD)
settings in the final merged setup loaded for Power Manager.
■ loadEnvironmentOptions:

August 2024 21 Product Version IC23.1

Controls whether the.cadence/dfII/vpm/lpSetup.il file is loaded automatically

as a part of the final merged setup.
❑ If set to true, the project-level settings are considered as a part of the final setup.
❑ If set to nil, the project level settings are ignored for the final setup.
❑ If this option is not specified in the Power Manager setup template, it is assumed to
be true and is considered for the final setup.
■ pushUnmodifiedEnvOptions:
Controls the reading of the project-level (CAD) settings, at a later stage. For example, if
there is any update in the project-level settings and the changes need to be applied in
the final merged setup for the Power Manager.
❑ If set to true, any changes done in the project-level settings are read and updated.
❑ If set to nil, any changes done in the project-level settings are ignored in the final
setup.

You can define these options in the setup if you want to read the project-level setup initially or
always want to ensure that the user-defined setup is synchronized with the project-level
(CAD) setup.

The final setup is the result of merging all the three setups, which can be verified by exporting
in the file:
vpmExportPowerIntentSetup("random_computation_flat" "random_computation_top"
"schematic" "lpSetup_export.il" ?filter "allSetupOptions" ?overwriteExisting t)

Currently, if there are common settings in the setup file, for example, supply nets are specified
in CAD and user-defined setup, the user-defined setup has a higher precedence.

Caution
The Power Manager Setup form gives you the flexibility to dynamically
switch and update more than one design for power information. However,
it is recommended to update one design at a time, close the form, and
reopen it for updating the power intent information for a different design.
This ensures that the setup information is not inadvertently lost when
switching from the setup for one design to the other.

Related Topics

Registering Name-Based Supply Nets

August 2024 22 Product Version IC23.1

Registering Regular Expressions-Based Supply Nets

Registering Libraries

Registering Device and Cell

Performing In-Design Checks

Registering Supply Set and Power Domain

Miscellaneous Settings

Setup File Template

Loading Power Intent Extraction Options from a File

Saving Power Intent Extraction Options to a File

Registering Name-Based Supply Nets

You can set a rule to register certain names as names of power nets or ground nets. If a net
in your design has one of the registered names, the net is identified accordingly. It is
recommended to follow a similar naming convention for supply net naming across the design
hierarchy. Here are the steps to register the supply nets.
1. Double-click the fields in the Registered Supply Nets table to edit.
2. To add the supply nets, click .
It opens the Add Supply Nets form.
3. Specify the values in the form for registering supply nets.
4. Click to remove added supply nets.

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5. Press Shift + Ctrl to select nets and register them as power or ground. Simultaneous
registration of existing and user-defined nets as power/ground is possible.

Important
The existing nets shown in the Add Supply Nets form are the nets corresponding to
the top-level ports of the design in consideration.

You need to specify the voltage values of the net for the top-level supply nets. You also need
to register internal nets, such as low drop out (LDO) nets or output of a voltage divider, and
provide the voltage values for such internal nets. For a hierarchical design, the voltage values
specified from the top-level nets are propagated to the levels below in the following ways:

August 2024 24 Product Version IC23.1

■ If the cells used in the design do not have their associated Liberty file, the voltage
propagation for them happens hierarchically as per the top-level voltage values.
■ If the cells used in the design have their associated Liberty/1801 cell bindings, the
voltage map (from Liberty) or power states (from 1801) are expected to match the
voltage levels specified for top level supplies.

You can also define multiple voltages for a top-level net. If you define multiple voltages for both
power nets and ground nets, Power Manager considers all possible supply states based on
all the supply net voltages provided in the setup. In-Design Checks consider all possible
supply states based on all the supply net voltages provided in the setup information. The
supply states are created depending upon the unique voltage values for a power net–ground
net pair.

Consider a voltage specification with supplies VDD, VSS, and VDD1V2 where VDD is 0.8V and
1.0V, VSS = 0.0V and 0.4V, and VDD1V2=1.2v.
netVoltages (("VDD" (0.8 1.0))
("VDD1V2" (1.2))
("VSS" (0.0 0.4)))

The following power modes are created:

Supplies VDD VDD1V2 VSS

State OFF OFF OFF
ON(0.8V) ON(1.2V) ON(0V)
ON(0.8V) ON(1.2V) ON(0.4V)
ON(1.0V) ON(1.2V) ON(0V)
ON(1.0V) ON(1.2V) ON(0.4V)

You must provide the supply net voltage values for creating the power states based on the
switching behavior of the corresponding supply nets.

Specifying net voltages in the setup is not mandatory if the import flow is used.

Related Topics

Registering Libraries

Registering Device and Cell

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Performing In-Design Checks

Registering Supply Set and Power Domain

Miscellaneous Settings

Setup File Template

Loading Power Intent Extraction Options from a File

Saving Power Intent Extraction Options to a File

Registering Regular Expressions-Based Supply Nets

If you do not know the names of the nets that exist down the hierarchy, there are some naming
conventions followed. Here are the steps to register the regular expressions-based supply
nets.
1. Specify regular expressions for nets in the Power Nets or Ground Nets fields on the
Supply Nets tab of the Power Manager Setup form.
For example, if you add vdd as a regular expression, such as iovdd, avddd1, or any
net name that contains this is considered as power net. Similarly, if GND is specified as a
regular expression, names such as GNDA, GNDD, and so on, are considered as ground
nets. Also, if [v][V], [d][D], and [d][D] are defined as regular expressions, all
combinations are considered, such as vdd, VdD, VDD, Vdd, and so on.
2. Specify the registration information in the Pwell, Nwell, Deep Pwell, or Deep Nwell
fields on the Supply Nets tab of the Power Manager Setup form.

August 2024 26 Product Version IC23.1

3. Click OK.

Power Manager checks for the presence of the registered nets and identifies them as power
or ground nets. These registered nets are used to create power domains.
Note: You must register the top-level supply nets for cells that do not have an associated
Liberty model.

Related Topics

Registering Name-Based Supply Nets

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Registering Libraries

Registering Device and Cell

Performing In-Design Checks

Registering Supply Set and Power Domain

Miscellaneous Settings

Setup File Template

Loading Power Intent Extraction Options from a File

Saving Power Intent Extraction Options to a File

Supply NetSet Properties Prefix Registration

Registration of supply net properties includes identifying and registering of supply nets by
using the property name prefix for inherited connections that have been specified in the

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Supply NetSet Properties Prefix section on the Supply Nets tab of the Power Manager
Setup form.

For non-Liberty cells, the supply name can also be derived from the prefix of the property
name used in the net expression for supply net connectivity. Power Manager creates property
names for net expressions with a specific prefix as specified in the setup. Prefix matching
helps to identify the power/ground type for lower level cells when the tool creates redirected
netSets for resolving supply net connectivity to the top level supplies.

For power/ground type, precedence is given to supply net names that are already registered
in the setup. Else, the property prefix name is used. The prefix name is registered in the setup
for different supply types such as follows:

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powerNetPropPrefix - vdd

groundNetPropPrefix - vss

pwellNetPropPrefix - hSup_sub

nwellNetPropPrefix - lSup_sub

deeppwellNetPropPrefix - hSup_sub2

deepnwellNetPropPrefix - lSup_sub2

Related Topics

Redirected netSet Property Creation and Optimization

Registering Name-Based Supply Nets

Registering Regular Expressions-Based Supply Nets

Registering Libraries

Registering Device and Cell

Performing In-Design Checks

Registering Supply Set and Power Domain

Miscellaneous Settings

Excluding Power and Ground Nets from Name-Based

Registration
Net names with a certain pattern can be detected as a regular expression during the supply
nets name-based registration. It can lead to an incorrect registration for the net as a power or
ground net, for example, the Monitor and Sense pins used in the design to sense and test the
supply signal level during functioning of the design.

To exclude power and ground nets from name-based registration:

1. Use the Names field in the Excluded Nets section on the Supply Nets tab of the Power
Manager Setup form to exclude a subset of specific net names. These names are

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defined in the Regular Expression Based Registration section or defined using the
signal type.
2. Use the Regular Expressions field in the Excluded Nets section to specify one or
more power or ground regular expressions that have been registered using the Regular
Expression Based Registration section or defined using the signal type.
For example, if the regular expression of power net is VDD, the nets such as VDD, VDDD,
AVDD VDD_SUB, VDD_PH, VDD_PHY, VDD_PH1, and so on, are specified as power nets.
However, if you want to exclude all nets containing OUTVDDE from being power nets, you
can specify OUTVDD to be excluded as a regular expression.
3. Click OK.

In a setup file, the excluded nets are represented as follows:

;;; Exclude Nets
excludePG (nil
names ("VDD_PROBE" "VSS_PROBE")
regExprs( "vdd.*en vdd.*fb vss.*en vss.*fb" )
)

Related Topics

Registering Name-Based Supply Nets

Registering Regular Expressions-Based Supply Nets

Registering Libraries

Registering Device and Cell

Performing In-Design Checks

Registering Supply Set and Power Domain

Miscellaneous Settings

Setup File Template

August 2024 31 Product Version IC23.1

Loading Power Intent Extraction Options from a File

Saving Power Intent Extraction Options to a File

Registering Monitor Nets

Use the Monitor Nets section on the Supply Nets tab of the Power Manager Setup form to:
1. Register a net as Monitor/Sense, to designate it as a net or port for probing or testing.
2. Specify the regular expression for probing or testing.

Specify values in the Names field to register a subset of specific net names that have been
registered in the Regular Expression Based Registration section or defined using the
signal type as Monitor Nets.

Similarly, specify values in the Regular Expressions field to register a subset of power or
ground regular expressions that have been registered in the Regular Expression Based
Registration section or defined using the signal type as Monitor Nets.

In a setup file, the monitor nets are represented as shown below:

monitor (nil
names ("VDD_PROBE" "VSS_PROBE")
regExprs( "vdd.*sense vss.*sense" )
)
)

Related Topics

User-Defined Macros Registration

Resistors as Short Devices

Connectors

August 2024 32 Product Version IC23.1

Single Rail Cells

Stack Transistors

User-Defined Macros Registration

Any hierarchical blocks in design can be registered as macro. This helps in improving the
extraction speed. These blocks can be iterative instances with hierarchical content, sub-
blocks with iterations, iterative ports connected to instances, or deep hierarchical blocks with
multiple instantiations.

In a setup file, you can specify user-defined macro cells in following manner:
userMacroCells ( ("hierCell2" "pwr_test" "hierCell2" "schematic")
("hierCell" "pwr_test" "hierCell" "schematic"))

userMacroCells ("hierCell" "hierCell2")

Related Topics

Excluding Power and Ground Nets from Name-Based Registration

Registering Name-Based Supply Nets

Registering Regular Expressions-Based Supply Nets

Registering Libraries

Registering Device and Cell

Performing In-Design Checks

Registering Supply Set and Power Domain

Miscellaneous Settings

Setup File Template

Loading Power Intent Extraction Options from a File

Saving Power Intent Extraction Options to a File

August 2024 33 Product Version IC23.1

Registering Libraries
Use the registration options on the Libraries tab to register the libraries-related information.
This information is used by Power Manager to read the standard and special cells modeling
information. It is required to extract the power-related attributes of standard and special cells
and avoids the need to access these cells for tracing the related supplies corresponding to
the boundary ports.

Use the Liberty/Tech Files and 1801 File binding sections to specify the Liberty models
or 1801 special cell definition files as follows:
1. Click to add and to remove the Liberty/Tech Files.
Optionally, you can register a cell and bind it to its existing 1801 power intent file. The
power-related information is read from the existing 1801 bound to the cell.

August 2024 34 Product Version IC23.1

2. Click to add, to modify, and to remove the binding information. It opens

the Add 1801 File Binding form.
3. Specify the values in the Cell and 1801 File fields. Click OK.
Note: This option is commonly used for black-boxing contents of a digital sub-block that has
power intent.

Related Topics

Registering Libraries

Special Cell and Standard Cell Modeling

Design Sub-Block Modeling During Top-Level 1801 Design Model Extraction

Special Cell and Standard Cell Modeling

The IEEE 1801 standard is a must for the design and verification of low power integrated
circuits, the correct identification and mapping of all power attributes, topology-related
attributes, and the functions of low power special cells or standard cells. This is achieved by
the proper registration of the special cells and the standard cell models. If cells are registered,
they are identified in the schematic view accordingly.

Low power special cells and standard cells include:

■ Isolation cell
■ Level shifter cell
■ Power switch cell
■ Always on cell
■ State retention cell
■ Combinational/Sequential elements

Power Manager extracts level shifter strategy, isolation strategy, and power switch strategy in
the power intent based on the definition provided in a 1801 special cell definition file or Liberty
models. The in-design checking uses the same information to verify the power domain
crossings with or without these special cell instances.

You can register these cells in any of the following two ways:

August 2024 35 Product Version IC23.1

■ By using the Liberty models of the cells

Special cells and standard cells, which have their Liberty model available, are recognized
for their topology and various supply-related attributes by including the corresponding
Liberty files. The Liberty files enable the following:
❑ The pg_pin attributes specified in the Liberty files help in identifying the nets used
inside the cells as power or ground.
pg_pin(VDD) {
voltage_name : VDD;
pg_type : primary_power;
direction : inout;
}

❑ The voltage map specified in the Liberty files is used to extract the voltage levels of
the corresponding supply and ground nets used.
voltage_map( VDD , 1.100000);

❑ The cell type specified in the Liberty files is used to identify the type of low power
special cell or the standard cell, and extract it accordingly during 1801 power intent
extraction or running In-Design Checks.
cell(Isolation_Cell) {
is_isolation_cell : true;

❑ The function attributes specified in the Liberty files are used as follows:
❍ The switch/enable function of the low power special cells is used for finding the
switch functions, enable conditions, and for backtracing the control/enable
signals of the special cells, such as power switch cell, isolation cell, and enable
level shifter cells, for any of the boundary ports.
pg_pin(VDDSW){
switch_function : "psw_en";

pin(out_iso) {
isolation_enable_condition : "en_iso";

❍ The output function of the standard cells is used during backtracing of the
control/enable signals of the low power special cells that are generated by some
combinational logic, for example, output of a NAND gate. Here for a NAND gate
Liberty function attribute of its output can be used.
pin (Y) {
direction : "output";
function : "(!((!AN) B))";

■ By using the 1801 special cell definition file

August 2024 36 Product Version IC23.1

When you provide a special cell definition file at the location specified in the setup file,
before extracting the power intent, Power Manager reads the given file and recognizes
the cells specified in that file as special cells. The 1801 special cell definition file aids in
modeling of these cells by specifying the related attributes in their definition.
❑ Cell type
❑ Supply ports/Switchable supply ports
❑ Data ports
❑ Enable/control ports
❑ Voltage range
❑ Cell-specific attributes
Example:
define_isolation_cell -cells ISOHLDX1_OFF -power ExtVDD -ground VSS -
clamp_cell low -enable !ISO
define_level_shifter_cell -cells LSLHX1_TO -direction both -input_power_pin
ExtVDD -output_power_pin VDD -ground VSS -input_voltage_range {{0.8 1.4}} -
output_voltage_range {{0.8 1.4}}
define_power_switch_cell -cells HSWX1 -type header -power ExtVDD -
power_switchable VDD -ground VSS -stage_1_enable PSO -stage_1_output PSO_out -
exclude { HeadSwitch_WrapperA HeadSwitch_WrapperB }

Note: Use this method to register special cells for the standard and verified standard cell
libraries, which do not have the Liberty models available. This method can also be used
to register custom standard cells.
Setup registration for Liberty models and the special cell definition file is as follows:

libFiles (
"libs/fast_vdd1v0_basicCells.lib"
"libs/fast_vdd1v2_extvdd1v0.lib"
"libs/macro_lib.lib"
"libs/Headswitch.upf"
)

Note: Power Manager also allows you to define specific level-shifter, isolation, and
power switch instances. For more information, contact Cadence customer Support

Related Topics

Registering Libraries

August 2024 37 Product Version IC23.1

Design Sub-Block Modeling During Top-Level 1801 Design Model Extraction

Reference Libraries or Cells

MLDB Libraries

Design Sub-Block Modeling During Top-Level 1801

Design Model Extraction
The modeling information of hierarchical design blocks can be provided to digital verification
tools, such as Conformal Low Power (CLP) as follows:
■ Liberty macro models: The contents of analog sub-blocks need to be modeled in terms
of Liberty power model export to be provided to CLP. CLP identifies the modeling
information and reads the power-related attributes of the boundary ports of the block for
crossing analysis.
The Macro Liberty power model for a sub-block can be specified as a Liberty file on the
Library tab of the Power Manager Setup form and therefore, binding it to that block.
■ 1801 file binding: If the power intent of a hierarchical sub-block is already available as a
1801 design model, the same can be bound to that block in the 1801 File binding
section on the Library tab of the Power Manager Setup form. These blocks are locked
for extraction of 1801 power intent by Power Manager. The tool does not traverse down
the hierarchy but just one level inside its schematic to make the interface connectivity to
the top-level 1801 file. A 1801 file used for importing the power intent on a digital sub-
block can also be used for cell binding of that block.
During the top-level 1801 design model extraction, Macro Liberty Power Model, the
special cell definition file and the available power intent of the sub-blocks are consumed
together. The top-level design model can further be verified using CLP.
Cell bindings can be registered in the setup as:
cell1801Bindings (
("data_LevelShifter" "./data_LevelShifter.upf")
)

Note: If the top design is large, the power intent extraction step might lead to memory-
related issues. Therefore, for large designs, follow the bottom-up approach. In this
approach, you can first extract the power intent of sub blocks separately in 1801 files and
then associate the 1801 files with their respective instances in the top design. After this,
when you extract power intent for the top design, the tool consumes less memory. Also,
you can apply the bottom-up approach when extraction options cannot be shared
between the top design and the sub blocks. For example, when the power / ground nets

August 2024 38 Product Version IC23.1

definitions, power / ground net voltage definitions, or power net-ground net voltage pairs
definitions in the top design are different from the sub block definitions.

Related Topics

Exporting Power Intent of a Design

Registering Libraries

Special Cell and Standard Cell Modeling

Reference Libraries or Cells

MLDB Libraries

Reference Libraries or Cells

If the design contains instances of any library or a particular cell, apart from the Liberty cell,
it can be read-only, black box, or a reusable block. You can register those as reference
libraries. The cells in reference libraries are not edited during the 1801 import flow. If the input
1801 file has a connect supply net command for a instance inside the blackbox cell, the cell
is not edited to create the netSet or any supply ports. During import, the hierarchy is traversed
to map all the supply nets to the supply set at the instance boundary. You can specify library
and cells in the Add Reference Cells form on the Libraries tab of the Power Manager Setup
form.

Reference library registration in the setup is as follows:

refLibCells(
("analogLib" "*buf*"))

Related Topics

Registering Libraries

Special Cell and Standard Cell Modeling

Design Sub-Block Modeling During Top-Level 1801 Design Model Extraction

MLDB Libraries

August 2024 39 Product Version IC23.1

MLDB Libraries
Power Manager processes the Liberty files to read the standard cell, special cell, and macro
cell model definitions and stores them in an OpenAccess-based proprietary database. This
avoids the need to reprocess the Liberty files every time a command is executed. Such a
database is called Model Library database (MLDB). MLDB reads and stores the PG pins,
pins, and the non-characterized attributes for the various cell models provided through Liberty
files. These attributes are saved in a different library than the design or PDK library, which can
be utilized in various projects to extract details instead of parsing the Liberty files every time.
This can save a lot of run time that is required to parse large Liberty files if it has to be done
repeatedly for extracting power-related attributes. If no user-specified library is provided, the
database is in-memory and can be used only for a particular Virtuoso session.

MLDB creation requires a new library to be created. The library includes a tech.db file,
which contains all the power-related attribute information that is extracted by a single traversal
from the registered Liberty files. The setup registration for MLDB is:
projectMldbLibName "MLDB_TESTCELL"

A new .lib file is added to MLDB only in one of the following conditions:
■ You have re-imported a modified setup specifying additional .lib files and removed
.lib files that are not required anymore.
■ You have run a VPM command, such as extract power intent or import power intent.

The modified MLDB is saved when closing all the files or exiting Virtuoso.

Related Topics

Registering Libraries

Special Cell and Standard Cell Modeling

Design Sub-Block Modeling During Top-Level 1801 Design Model Extraction

Reference Libraries or Cells

Registering Device and Cell

Register the device and terminal related information on the Devices tab of the Power
Manager Setup form. This information is used by Power Manager to read the device type and
its topology in the design. For devices with more than two terminals, you can associate
terminals to have specific mapping. Correct recognition and identification of device type is

August 2024 40 Product Version IC23.1

important for the supply traversal to find the related supplies of the boundary ports associated
with the design logic.

To register cells as devices:

1. Use Filter in the Cells group box to search for a cell. The Filter option gives the flexibility
to easily filter and sort the desired choice of devices to be registered.
2. Select a cell or a set of cells to register in the Cells group box.
3. Select the device type for assigning the devices in the Device Type group box.
4. Use to perform the assignment.

August 2024 41 Product Version IC23.1

To register devices by using a wildcard-character-based registration:

1. Click to open the Add Device form.
2. Specify a library and cell name based on a wild character notation and register the device
in the corresponding Device Type.
For example, specifying gpdk* and nmos* registers all the devices with a name
matching the pattern nmos* in all the libraries with the name matching the pattern
gpdk* to the device type nfet.
3. Click to remove the assignment.
4. Specify conditions/criteria with the assigned device by clicking .
5. Click OK.

If the Library Name or a cell name field is left blank, all available libraries (for a particular cell
name pattern) or all available cells (for a particular library name pattern) will be accounted for
and register based on the wild character specification.

Devices used in the design, such as MOS devices, resistors, capacitors, and diodes, need to
be registered in the setup under the following categories.
■ Transistors (nfet, pfet, npn, pnp)
■ Short devices (including devices with n terminals)
■ Pad cells
■ Cells to be ignored

In a setup file, the device registration is represented as shown below:

;;; Devices
devices (nil
pfet (
(nil "pmos*" nil)
("analogLib" "pmos*" nil)
("gpdk*" "pmos*" nil)
)
nfet (
(nil "nmos*" nil)
("analogLib" "nmos*" nil)
("gpdk*" "nmos*" nil)
)
pnp (

August 2024 42 Product Version IC23.1

(nil "pnp" nil)

("analogLib" "pnp*" nil)
("gpdk*" "pnp*" nil)
)
npn (
(nil "npn" nil)
("analogLib" "npn*" nil)
("gpdk*" "npn*" nil)
)

Related Topics

Registering Name-Based Supply Nets

Registering Libraries

Registering Device and Cell

Performing In-Design Checks

Miscellaneous Settings

Passive Devices
Passive devices, such as resistors, capacitors, short, and diodes are considered as special
cells and registered in the setup depending upon how they are placed in the design.

Resistors as Short Devices

Resistors are registered in setup as short devices. You can short the terminals of devices that
have more than two terminals.

In a setup file, the short device registration is represented as shown below:

short (
("analogLib" "res" nil)
("myLib" "wireshortcell" nil (nil shortedTerminalMap (("t1" "t2")("t3" "t4" "t5")
)))
)

August 2024 43 Product Version IC23.1

Ensure that you register passive devices associated to a condition as mentioned in the setup
file. For example, certain configurations in designs might require the resistors not to be
registered as short devices.

The multi-term shorting of devices under the Short category is considered only during macro
model extraction. However, it is not considered while netlisting, which is a part of CLP
integration. Therefore, it leads to an error during CLP verification.

Connectors
You can register cells under the connectors in the following scenarios:
■ While relating power nets with ground nets for establishing power ground net pairing.
When the extractor traces the power to the ground paths in order to pair power and
ground nets, if there is a connector instance in the path, the related terminals of the
registered connector instance (a multi-terminal cell) help to continue tracing from one
end to the other end.
■ While backtracing the data path from the control pins of the special cells to the macro or
design ports to generate the enable or shutoff condition for low power rules or power
domains.

In a setup file, the connector registration is represented as shown below:

connector (
(nil "stdBuf*" nil)
("ALIB" "PMU" nil (nil shortedTerminalMap (("p" "q") ("o" "y"))))
)

Capacitors used in the data path mostly for the purpose of AC coupling are treated as
connectors. The capacitors that are directly connected to power or ground for the purpose of
blocking DC signal are treated as ignored or open. These are blocked for supply/ground
tracing. The multi-terminal capacitors are also registered as devices.

In a setup file, the capacitor registration is represented as shown below:

cap (
(nil "cap" nil)
(nil "mimcap" nil
(nil
shortedTerminalMap (("PLUS" "MINUS"))
)
)

August 2024 44 Product Version IC23.1

Note: You can also use the wildcard character in the Ignore, Short, Buffer, and Inverter
registration.

Diodes can be used in the design for the different purpose like in an antenna or ESD clamp
structures. Their registration in a setup is specific to the polarity configuration in which they
are connected.

In a setup file, the diode registration is represented as shown below:

diode (
("analogLib" "diode" nil (nil pTerm "PLUS" nTerm "MINUS"))
)

A diode is referred to as an antenna diode if the nTerm of diode is connected to power and
pTerm of diode is connected to a pin. Or, pTerm of diode is connected to ground and nTerm
of diode is connected to a pin.

Antenna diode-specific attributes are printed for input & inout terms connected to the antenna
diode.

Power Type:
pin (MyInput) {
antenna_diode_related_power_pins : "VDD";
...
}

Ground Type:
pin (MyInput) {
antenna_diode_related_ground_pins : "VSS";
...
}

Power and Ground:

pin (MyInput) {
antenna_diode_related_power_pins : "VDD";
antenna_diode_related_ground_pins : "VSS";
...
}

August 2024 45 Product Version IC23.1

A parasitic diode is formed between the source or drain terminal of a MOS device and the
bulk terminal. Here is an example of a PMOS device and a parasitic diode.

For a PMOS device, a diode that has the anode connected to the signal net and the cathode
connected to the power supply is extracted. In this case, it is a power type diode.

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antenna_diode_related_power_pins : "VDD";

For an NMOS device, a diode that has the cathode connected to signal net and the anode
connected to ground supply is extracted. In this case, it is a ground type diode.
antenna_diode_related_power_pins : "VSS";

Related Topics

Passive Devices

Backtrace Enable Signals of Special Cells

Connectors

Single Rail Cells

Stack Transistors

Terminal Name Registration for Devices

August 2024 47 Product Version IC23.1

Backtrace Enable Signals of Special Cells

This involves backtracing of the internal net to map the enable or control signals of special
cells to the boundary ports. Backtracing is required to get the appropriate functional attribute
related to the enable or control signals in the Liberty macro model after detecting the
corresponding function of the logic generating the signals.

Liberty registration for standard and special cells in the setup is a mandatory requirement to
extract a correct function for the enable or control signals of low power special cells as per the
design implementation

The backtracing is supported for following registered configurations:

■ For buffers, shorts, and inverters, the two-terminal devices with single input and output,
such as inverters and buffers, can be backtraced. The polarity of the signal does not
change while backtracing through instances, unless the instances are inverter cells. You
can register these cells as Inverter. If an instance with more than two terminals is present
in the path, backtracing stops and an error message is displayed. Inverter and buffer
registration is done as shown below.
inverter (
(nil "stdInv*" nil)
("gpdk*" "inv*" nil)
)

buffer (
(nil "stdBuf*" nil)
("gpdk*" "buf*" nil (nil shortedTerminalMap (("p" "q") ("o" "y"))))
)

Note: The terminal map is a mandatory requirement for backtracing when a cell contains
multiple input and output and is registered as an inverter or a buffer.
■ For standard isolation or level-shifter instances, signals are backtraced from output pin
to input pins. For power switch instances, the signals are backtraced from the
acknowledge pin (buffered enable) to enable the pin of the instance. This lets the
backtracing to be performed for the control signals of all the power switch cells to the
same macro port resulting in the correct enable and shutoff conditions.
■ For simple logic gate, the backtracing is done through the special cell enable pin to the
output pin of the logic gate that has multiple input pins is supported. All input pins of a
logic gate can be backtraced separately to the maximum extent possible.
However, a cell can be registered as LogicGate (simple logic gate) only if it matches any
of the following criteria:

August 2024 48 Product Version IC23.1

❑ There are no multiple output pins in the cell.

❑ The boolean function is present in the setup file.
❑ Only AND, NAND, OR, NOR, and XOR Boolean functions are considered.
The cells are registered as LogicGate devices along with Boolean functions of the cells.
logicGate (
("sample" "or*" nil (nil booleanFunction "OR"))
("sample" "xor*" nil (nil booleanFunction "XOR"))
("sample" "and*" nil (nil booleanFunction "AND"))
("sample" "nand*" nil (nil booleanFunction "NAND"))
("sample" "inv" nil (nil booleanFunction "NOR"))
)

■ A custom logic can also be registered with the desired terminal mapping between its
output and input ports to be suitably backtraced if it lies in between the enable/control
signal and the boundary port generating it. For any block net, all the modules from parent
of leaf cell to parent of block net are checked if one or more of these are custom devices.
In case, more than one modules are found as custom devices, the top most module is
given the priority.
customLogic (
("ALIB" "WiFi" nil (nil relatedTerminalMap
"y1=x1&x2,y2=x3|x4,y3=x5^x6"))
)
)

■ Algorithm Standard Cell

The function of output pins is extracted in terms of input pins by backtracing through
transistors or other primitive elements, such as resistors and capacitors. You can use the
maxInputPinsForAlgoStdCellABT and maxOutputPinsForAlgoStdCellABT flags while
doing logic extraction for any unregistered cells.
■ Cells registered as transistors
While back tracing through transistors back tracing would stop if the successive channel
or gate crossings before continuing back tracing reaches a predefined limit. The
maxConsecutiveTxGateCrossingsForABT and
maxConsecutiveTxChannelCrossingsForABT flags are utilized while back tracing
through transistor logic, either seen in its flat form or seen inside algorithm standard cell.
Which back-tracing through the transistors, the back tracing would stop if the successive
channel or gate crossings before continuing back tracing reaches a predefined limit.

August 2024 49 Product Version IC23.1

■ The user-defined macros and switch functions in internal and regulated nets can be
backtraced.
■ You can print the derivations of switch_function and isolation_enable_condition
expressions.
■ Power Manager also extracts the following user defined attributes:
❑ switch_function_off:
❍ String type user-defined simple attribute for pg_pin group
❍ Printed along with a switch_function
❍ A boolean expression of macro cell input pins that evaluates to 1 only when
output supply is fully OFF.
❑ isolation_enable_condition_off
❍ String type user-defined simple attribute for pin group
❍ Printed along with the isolation_enable_condition
❍ A boolean expression of macro cell input pins that evaluates to 1 only when the
isolation function of a level shifter or isolation cell is fully disabled.
■ The reporting of automatically identified transfer functions of cells/pins in the backtracing
path is also supported.

Related Topics

Passive Devices

Connectors

Single Rail Cells

Stack Transistors

Terminal Name Registration for Devices

Single Rail Cells

Single rail cells are custom cells. These can be custom standard cells, an unimplemented
sub-block, or a complex hierarchical custom logic having a single primary power and ground
supplies. Usually, a Liberty model does not exist for such cells. Consequently, the single rail

August 2024 50 Product Version IC23.1

cell registration enables blackboxing of any hierarchical sub-block so that the extractor
recognizes it as a leaf cell. All ports connected to a single rail cell (directly or through some
elements) are mapped according to the port definitions as defined in standard cell
registration.

Single rail devices commonly used have the following features:

■ Single rail device registration can be done with global attributes set at the cell level for
multiple cells. In addition, the registration can also be done explicitly for a single cell.
■ Defining the global supply values is optional.
■ By default, all non-supply and non-bias pins are considered to be data pins. These data
pins are related to the supply pins (RPP/RPG) and the bias pins (RBP).
■ Single rail cells are also supported for bias supplies, which might be different from
primary supplies.

On the Device tab in the Power Manager Setup form, when you click after selecting the
singleRailCell device type, the singleRailCell Attributes form opens. Additionally, you
can view the form by selecting any cell registered as a single rail cell device.

In a setup file, the singleRailCell registration is represented as shown below:

singleRailCell ( nil
cells (
("myLib" "aBuf*" nil)
( nil "bBuf*" nil)
("myLib" "cBuf*" nil
(nil
power "VDD"

August 2024 51 Product Version IC23.1

ground "VSS"
pwell "VPP"
nwell "VNN"
deeppwell "VPPP"
deepnwell "VNNN"
)
)
)
power "VDD"
ground "VSS"
pwell "VPP"
nwell "VNN"
deeppwell "VPPP"
deepnwell "VNNN"
)

Related Topics

Passive Devices

Backtrace Enable Signals of Special Cells

Connectors

Stack Transistors

Terminal Name Registration for Devices

Stack Transistors
Stack Transistor devices are used in the advanced node designs for reduced power
consumption at lower gate lengths. Stack Transistor devices commonly used have the
following features:
■ The same master is used for creating different device variants, such as PMOS or NMOS.
■ The Stack Transistor device has a series of cascaded PMOS or NMOS devices inside.

August 2024 52 Product Version IC23.1

■ A parameter on the device Pcell master defines the device type used inside for stacking.

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On the Device tab in the Power Manager Setup form, when you click after selecting the
stackTransistor device type, the Device Parameter Names form opens.

When you click the stackMosfet device type, the Device Parameter Names form opens.

It is used to specify the device parameter names for the stack MOS device to define the device
as PMOS or NMOS. You can specify more than one parameter names.
Note: If the device terminal have names different from the conventional naming, you need to
provide a terminal mapping for the same during device registration.

In a setup file, the stack MOS device registration is represented as shown below:
stackTransistor (

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(nil “STACKMOS*" nil)

("analogLib" “STACKMOS*" nil)
("gpdk*" “STACKMOS*" nil)
)
stackTransistorDeviceParamNames "SourceCell"

Related Topics

Passive Devices

Backtrace Enable Signals of Special Cells

Connectors

Single Rail Cells

Terminal Name Registration for Devices

While traversing through the connections of transistor instances, the Power Manager needs
to identify the gate, source, and drain terminals of the registered transistor devices. Therefore,
in addition to registering the devices, you need to register the names of the device terminals
of these devices. You can register terminal names with an appropriate terminal type in the
Power Manager Setup form and subsequently, in the setup file as shown below:
txTermTypeNames (nil
source "s S source SOURCE Source"
drain "d D drain DRAIN Drain"
gate "g G gate GATE Gate"
bulk "b B BULK well SUB"
collector "c C collector"
emitter "e E emitter"
base "b B base BASE Base"
substrate "S BULK well SUB"

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Caution
If you are using a PDK that is not provided by Cadence, it is essential to
register the transistors and terminal names to ensure correct extraction
of boundary ports and automatic pairing of power nets and ground nets.

Related Topics

Passive Devices

Backtrace Enable Signals of Special Cells

Connectors

Single Rail Cells

Stack Transistors

Performing In-Design Checks

Power Manager supports running a set of predefined and configurable circuit checks for
mixed-signal designs that include devices and standard cells. You can define the severity of
reporting of these checks on the In-Design Checks tab.

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To perform in-design checks:

1. Specify the severity level of the results reported for the Level Shifter, Isolation, and
Bulk checks in the Checks Categories section.

Note: For reporting violations generated from a specific check, the error severity for that
check must be set to Error or Warning. If set to Ignore, the reporting of violations for
the corresponding check is disabled.

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2. Add filter patterns in the Filters field to filter some of the error and warning messages.

These errors are reported and exist in the design, but these are not a problem for the
design in the given scenario.

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Voltage Tolerance
The Tolerance section provides the flexibility to add tolerance for power and ground rail
supply net voltage values for level shifter checks. All data path crossings within the tolerance
limits are not flagged as violations. All the upper bound tolerances are positive numbers or
zero and the lower bound tolerances are negative numbers or zero. The missing level shifters
are reported for the signal crossings operating at different voltages when at least one of the
following conditions, indicated by the GUI options, is true:
■ Input Voltage Upper Bound: The driver power voltage is more than the receiver power
voltage by the upper bound input voltage tolerance. This value should be >=0.
■ Input Voltage Lower Bound: The driver power voltage is less than the receiver power
voltage by the lower bound input voltage tolerance. This value should be <=0.
■ Input Ground Voltage Upper Bound: The driver ground voltage is more than the
receiver ground voltage by the upper bound ground input voltage tolerance. This value
should be >=0.
The following table shows an example of scenario's which would reflect a level shifter
error and the ones which would not reflect the error.

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■ Input Ground Voltage Lower Bound: The driver ground voltage is less than the
receiver ground voltage by the lower bound ground input voltage tolerance. This value
should be <=0.

Related Topics

Registering Name-Based Supply Nets

Registering Libraries

Registering Device and Cell

Miscellaneous Settings

August 2024 60 Product Version IC23.1

Setting Supply States

When a design uses multiple voltages for efficient power management, they can be switched
on and off or scaled up or down to different voltage values as per design requirements. These
are power states. A power state can be defined as a set of power and ground nets with their
respective voltage values. IC designers choose the states as per the performance need of a
design. Some common schemes that use the power states are dynamic voltage, frequency
scaling, and run and standby performance modes.

As the number of power and ground supplies increases, their combination increases multiple
folds. To perform checks, it is critical to define the valid power states. Check the specified
supply states in a design. A voltage net can be ON at different supply voltages and off at a
particular voltage value.

For a power net, OFF is considered as 0 and ON can be 1.0V, 1.1V, 0.8V, and so on.

For a ground net, OFF is considered as the signal that is not available.

To populate the supply states:

1. Click to add the supply states in a design. It opens the Add Supply State form.
2. Click the Get Default Supply State button to remove all the existing voltages/values
pairs from the Add Supply State form if already existing.You have an option to apply this
default state directly or after adding/deleting/modifying some supplies and their values.
The default supply states have a unique non existent name.

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3. Optionally, click to modify, and to remove the supply states.

4. Additionally, use to copy existing supply states from the table. The Copy Supply
State form shows all the supplies with their respective voltage values of the currently
selected Supply State in the table. By default, the name of the copied state is shown as

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"State Name + _copy". You can add, delete, or edit voltages and their values. You can
also modify the name of the state.

The Registered Supply Nets table in the Supply Nets tab is always in synchronized
with the Supply States. If the supply nets are already available and registered in the
Registered Supply Nets table, the same nets are available for selection in the Add
Supply State form along with different voltage values in the lists. Conversely, while filling

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the Add Supply State form, if you introduce a new supply net with a set of voltage values,
the values are automatically updated in the Register Supply Nets table.

Note: The supply information registered in the Supply States table is read by the Power
Manager when the Use Supply States option is selected. If it is not selected, the supply
information is read from the Registered Supply Nets table in the Supply Nets section
of the Power Manager Setup form.
5. Select the check boxes in the Report Options section based on your preferences.

August 2024 64 Product Version IC23.1

Related Topics

Registering Port Attributes

Performing In-Design Checks

Registering Supply Set and Power Domain

A power domain is a part of the design that operates at a specific voltage. While capturing the
power intent, you need to specify the power domains for the top level of the design. There can
be a single or multiple power domains associated with the different sections of the design
addressed by a specific supply set.

During automatic extraction, Power Manager identifies a power net and a ground net from the
pair defined explicitly in the setup as a supply set in the Export tab of the Power Manager
Setup form. It associates the supply set with the power domain as specified in the setup.

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You can specify a supply set as a primary supply set for the power domains mentioned in the
setup. In addition, you can also define the supply set for the power and ground that cannot be
paired by traversing the design hierarchy or parsing the Liberty file.

To register supply set and power domain:

1. Click to add, to modify, and to remove the supply set and power domain
information.
It opens the Add Supply Set and Add Power Domain forms, respectively.
2. Click OK.

The Supply Set field is automatically populated if the field is found blank or the user-defined
names are in the SS<delimiter>XYZ<delimiter>ABC format. The automatically
generated supply set names follow the
<SS><delimiter><powerSupply><delimiter><groundSupply> format.

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The Power Domain field is automatically populated if the field is found blank or the user-
defined names are in the PD<delimiter>XYZ format. The automatically generated power
domain name follows the <domainPrefix><delimiter><supplySetName> format.

In the following example, the power net VDD and VSS are registered as a supply set, also a
top-level power domain is registered as PD_TOP, which is associated with this supply set
having power nets and ground nets as VDD and VSS, respectively.
;;; Supply Sets
supplySets (
(nil
supplySetName "SS_VDD_VSS"
power "VDD"
ground "VSS"
)
(nil
supplySetName "SS_VDDA_VSSA"
power "VDDA"
ground "VSS"
)
)

;;; Power Domains

powerDomains (
( nil
domainName "PD_TOP"
elements "."
primarySupplySet "SS_VDD_VSS"
includeScope t
)
( nil
domainName "PD_LS"
elements "I0"
primarySupplySet "SS_VDDA_VSS"
)
)

Note: Specifying supply sets and power domains in the setup is not mandatory if the 1801
import flow is used.

If you do not register power net and ground net pairs, the ground net associated with a power
net is automatically traced, consequently, creates a supply set and an associated power
domain. Consequently, all the other supply sets are created. This is possible only when there

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exists a path from a power net to a ground net through a network of transistors and/or two
terminal devices. In other cases, you need to register the supply set.

Related Topics

Add Supply Set

Add Power Domain

Registering Supply Set and Power Domain

Performing In-Design Checks

Registering Port Attributes

There are specific design configurations where a boundary port is connected to different
blocks that have different supply sets. This leads to ambiguities during the 1801 power intent
extraction or the In-Design checks to associate the boundary ports to a power domain.

To register port attributes:

1. Add ports by using the Add Port Attributes form in the Port Attributes section on the
Export tab of the Power Manager Setup form to resolve such an ambiguity. For analog
macros, Power Manager offers a mechanism of hierarchical supply traversal till device
level to extract power attributes for the boundary ports.
2. Specify the port names or regular expression in the Ports field.
3. Define the direction attribute by using Applies To.
4. Define the ports for exclusion in the Exclude Ports field.
5. Select the driver and receiver supply set.

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6. Specify if it is the an Analog, Unconnected, and Feedthrough port and click OK.

Alternatively, you can use portAttributes in the setup template as shown:

portAttributes(
(nil
ports "enable_pin"
driverSupplySet"SS_VDD_GND"
receiverSupplySet"SS_VDD_GND"
isAnalog<t/nil>
isUnconnected<t/nil>))

You can specify the following for a particular list of ports defined using
portAttributes:
Driver and receiver supply set associated with the digital ports.
Analog and unconnected ports, where you can add a separate set of ports that do not
have the driverSupplySet or receiverSupplySet.
The port attributes specified using portAttributes should take the highest
precedence and override other definitions. The 1801 power intent extraction or the in-
design checks consider the attributes specified for ports by using portAttributes, if
registered in the setup template. If you specify both the driver and the receiver supply set
for a port, they are used during extraction. If you specify only a driver supply set for input

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port, the 1801 power intent extraction or the In-Design Checks use it and trace only the
receiver supply set and conversely.

7. Select the following options in the Export Options section to control the extractor
behavior for the specific design scenarios:
❑ Consider inputOutput terms for internal power criterion: For details, see
allowInoutLDOPins.
❑ Consider inputOutput terms for monitor power criterion: For details, see
allowInoutMonitorPins.
❑ Consider symmetrical source and drain for supply tracing: Defines a port with
a predefined supply set or power domain that can be checked for the correct or
compatible connection at the receiver side. By default, this option is deselected.
Supply tracing is done by Power Manager for MOS terminals (Source and Drain) by
considering them asymmetric in nature. When this option is selected, Power
Manager traces through all devices irrespective of the way they are connected in the
design.
❑ Use anonymous supply for top level ports: Enables the use of an anonymous
supply for the top-level ports instead of the default supply set.

Related Topics

Add Port Attributes Form

Registering Supply Set and Power Domain

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Performing In-Design Checks

Miscellaneous Settings
Specify the generic settings on the Miscellaneous tab.

■ Delimiter
Used for specific notations, for example, redirect netSets created during the 1801 import
flow, automatically generated supply set and power domain names, and so on.
■ Switch View List to schematic symbol: It controls the order of the traversal of the
design hierarchy during power intent extraction.
■ Stop View List to symbol: It defines the stop point where the design traversal must be
stopped by the extractor during power intent extraction.
switchViewList and stopViewList can be specified in the Power Manager setup
template or defined using the switchViewList and stopViewList environment variables.
■ Use Signal Type (considerSignalType) to ignore or consider the sigType attribute
of nets for detecting the supply nets during power intent extraction. By default, this option
is set to nil and the attribute is not considered during name-based registration for
detecting supply nets. However, if set to t and there is a conflict between the sigType
attribute and name-based registration, name-based registration takes precedence.
❑ Setting the signal type to identify the power nets and ground nets
Each net has a Signal Type attribute that when set to power or ground can be
used to identify the net as a power net or a ground net, respectively. The default
signal type of a net is signal. During the automatic extraction, Power Manager

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looks for the considerSignalType attribute. When set to true, it creates power
domains considering all the nets that have the signal type defined as power or
ground.
Note: If there is a conflict between the sigType attribute and name-based
registration, name-based registration takes precedence.
You can set the signal type for pins or nets in your design in one of the following
ways:
❍ Select a pin or net on the schematic and in the Property Editor assistant, update
the Signal Type property.

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❍ Right-click a net and choose Properties to open the Edit Object Properties
form. Update the Signal Type property in this form.

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❍ Specify the appropriate signal type while creating a new pin by using the
Create Pin form. The Signal Type field, which is by default set as signal,
specifies the pin type.

For the power pins, you can set the value in this field as power.
If you use a specific set of names, such as, vdd, vdd!, or VDD, for the power pins in
your designs and vss, vss!, or VSS, for the ground pins, it is recommended that
you register those names by using the ciRegisterNet API in .cdsinit file. If you
use a registered name for a pin on the Create Pin form and the signal type is set
as signal, the default value, the tool automatically sets the signal type of that pin
as power or ground respectively. In that case, you need not specify the signal type
explicitly for each new pin or net created in the design. Later, if you do not need to
use the registered names, you can set the registration as nil.
The name-based registration in the setup file template for the Power Manager is as
follows:
;;; Supply Nets
supplyNets (nil
power (nil
names ("vdd" "avdd" "dvdd" "VDD" "AVDD" "DVDD")
regExprs ("[vV][dD][dD]" "[vV][cC][cC]")

August 2024 74 Product Version IC23.1

)
ground (nil
names ("vss" "avss" "dvss" "VSS" "AVSS" "DVSS")
regExprs ("[vV][sS][sS]" "[gG][nN][dD]" "gnd*")

❑ Select Load Setup From Environment and Use Setup Changes From
Environment to load setup or change the environment setup.

Related Topics

Registering Name-Based Supply Nets

Registering Libraries

Registering Device and Cell

Performing In-Design Checks

Setup File Template

lpSetupOptions = '(nil

;;; Supply Nets

supplyNets (nil
monitor (nil
names ("VDD_PROBE" "VSS_PROBE")
regExprs ("VDD_PROBE*" "VSS_PROBE*")
)
excludePG (nil
names ("OUTVDD")
regExprs ("OUTVDD*")
)
ground (nil
names ("Vss" "Vssa" "Vss_Int")
regExprs ("[vV][sS][sS]")
)
power (nil
names ("Vdd_1v8" "Vdd_3v3" "Vdd_Int")
regExprs ("[vV][dD][dD]" "[vV][cC][cC]")
)
)

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;;; Supply Net Voltages

netVoltages (
("Vss_Int" (0.0))
("Vdd_1v8" (1.8 1.0))
("Vssa" (0.0))
("Vdd_3v3" (3.3))
("Vss" (0.0))
("Vdd_Int" (3.3 1.0))
)

;;; External Switchable Nets

externalSwitchableNets nil

;;; Devices
devices (nil
cap (
("analogLib" "cap" nil)
)
pfet (
(nil "pmos*" nil)
("analogLib" "pmos*" nil)
("gpdk*" "pmos*" nil)
)
nfet (
(nil "nmos*" nil)
("analogLib" "nmos*" nil)
("gpdk*" "nmos*" nil)
)
short (
("analogLib" "res" nil)
("analogLib" "rcwireload" nil
(nil
shortedTerminalMap (("t1" "t2") ("t3" "t4" "t5"))
)
)
)
diode (
("analogLib" "diode" nil
(nil
pTerm "PLUS"
nTerm "MINUS"

August 2024 76 Product Version IC23.1

)
)
)
)

;;; Transistor Terminal Names

txTermTypeNames (nil
substrate "S BULK well SUB"
bulk "B BULK well SUB"
emitter "e E emitter"
collector "c C collector"
source "s S source SOURCE Source"
drain "d D drain DRAIN Drain"
gate "g G gate GATE Gate"
base "b B base BASE Base"
)

;;; Library Files

libFiles (
"./DESIGN1/LIBRTY/fast_vdd1v0_basicCells.lib"
"./DESIGN1/LIBRTY/macro.lib"
"./DESIGN1/TECHUPF/diode.upf"
"./DESIGN1/TECHUPF/lshifter.upf"
"./DESIGN1/TECHUPF/isolation.upf"
"./DESIGN1/TECHUPF/pswitch.upf"
"./DESIGN1/LIBRTY/macro.lib"
"./DESIGN1/LIBRTY/VPMWS_ANA_OpAmp.lib"
)

;;; Text Files Specifying Library Files

libInputFiles nil

;;; Cell 1801 File Bindings

cell1801Bindings nil

;;; User Macro Cells

userMacroCells nil

;;; Reference Library-Cells

refLibCells nil

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;;; Supply Sets

supplySets (
(nil
supplySetName "SS_vdd3v3_vss"
power "Vdd_3v3"
ground "Vss"
)
(nil
supplySetName "SS_vdd1v8_vss"
power "Vdd_1v8"
ground "Vss"
)
(nil
supplySetName "SS_vddsw_vss"
power "Vdd_Int"
ground "Vss_Int"
)
)

;;; Power Domains

powerDomains (
(nil
domainName "PD_vddsw_vss"
elements "I4"
primarySupplySet "SS_vddsw_vss"
)
(nil
domainName "PD_vdd3v3_vss"
elements "."
primarySupplySet "SS_vdd3v3_vss"
includeScope t
)
(nil
domainName "PD_vdd1v8_vss"
elements "I0 I2"
primarySupplySet "SS_vdd1v8_vss"
)
)

;;; Port Attributes

portAttributes nil

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;;; Maximum number of similar violations to be reported

maxSimilarViolations1

;;; Use supplyStates

useSupplyStatest

;;; Supply States

supplyStates (
("SS1" ("Vss 0.000000" "Vdd_Int 3.300000" "Vdd_3v3 3.300000" "Vssa
0.000000" "Vdd_1v8 1.800000" "Vss_Int 0.000000"))
("SS2" ("Vss 0.000000" "Vdd_Int 3.300000" "Vdd_3v3 OFF" "Vssa 0.000000"
"Vdd_1v8 1.800000" "Vss_Int 0.000000"))
)

;;; Input Voltage Tolerance Lower-Bound

inputVoltageToleranceLowerBound-0.100000

;;; Input Voltage Tolerance Upper-Bound

inputVoltageToleranceUpperBound0.100000

;;; Input Ground Voltage Tolerance Lower-Bound

inputGroundVoltageToleranceLowerBound-0.100000

;;; Input Ground Voltage Tolerance Upper-Bound

inputGroundVoltageToleranceUpperBound0.100000

;;; In-Design Checks Filter Patterns

lprcFilters nil

;;; Missing Level-Shifter Check Severity

missingLSCheckSeverity"error"

;;; Incompatible Level-Shifter Check Severity

incompatibleLSCheckSeverity"error"

;;; Redundant Level-Shifter Check Severity

redundantLSCheckSeverity"warning"

;;; Protected Level-Shifter Check Severity

protectedLSCheckSeverity"info"

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;;; Unprotected Level-Shifter Check Severity

unprotectedLSCheckSeverity"error"

;;; Unreliable Level-Shifter Check Severity

unreliableLSCheckSeverity"ignore"

;;; Floating Level-Shifter Check Severity

floatingLSCheckSeverity"error"

;;; Always Enabled Level-Shifter Check Severity

alwaysEnabledLSCheckSeverity"error"

;;; Unused Enable Level-Shifter Check Severity

unusedEnableLSCheckSeverity"error"

;;; Missing Isolation Check Severity

missingISOCheckSeverity"warning"

;;; Incompatible Isolation Check Severity

incompatibleISOCheckSeverity"warning"

;;; Redundant Isolation Check Severity

redundantISOCheckSeverity"warning"

;;; Incompatible Bulk Check Severity

incompatibleBulkCheckSeverity"error"

;;; Report isolation violations for always-on-switched domain crossings

reportOnOffISOViolationsnil

;;; Check ports without any portAttributes definition in setup

checkPortsWithoutAttributesnil

;;; Report violations for all net voltages

reportLPRCViolationsForAllNetVoltagesnil

;;; Prefixes for Supply Net netSet Props

powerNetPropPrefix "vdd"
groundNetPropPrefix "vss"
pwellNetPropPrefix "vdd_sub"

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nwellNetPropPrefix "vss_sub"
deeppwellNetPropPrefix"vdd_sub2"
deepnwellNetPropPrefix"vss_sub2"

;;; Project MLDB Library Name

projectMldbLibName""

;;; Reference MLDB Library Names

referenceMldbLibNames nil

;;; replaceExistingLibs
replaceExistingLibst

;;; Replicates missing driver_supply_set or receiver_supply_set for input,

output ports respectively.
replicateMissingDriverReceiverSupplySetnil

;;; Power Domain Name Prefix

powerDomainNamePrefix"PD"

;;; Enable Automatic Creation of Power Domains

autoCreatePowerDomainsnil

;;; Consider signal type for detecting PG nets

considerSignalTypenil

;;; Set the mode (design/auto) for extraction

extractionMode"design"

;;; Set how the PST/Power State are Created

powerStateCriteria"Conservative"

;;; Set if All Off PST/Power Stated are Created

includeAllOffStatesnil

;;; Control printing of nets identified as supply nets

printSupplyNetInfonil

;;; Set if inout pins are allowed as LDO pins

allowInoutLDOPinsnil

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;;; Set if inout pins are allowed as monitor pins

allowInoutMonitorPinsnil

;;; Delimiter for use in power intent objects like Supply Set Names
delimiter"__"

;;; View Name list for hierarchy elaboration

switchViewList"schematic symbol"

;;; Stack transistor device param names

stackTransistorDeviceParamNames""

;;; View Name list for pruning the hierarchy elaboration

stopViewList"symbol"

;;; Set if the environment options are to be loaded

loadEnvironmentOptionsnil

;;; Set if the options not overridden by the user are to be updated
pushUnmodifiedEnvOptionst

;;; Use anonymous supply set for non-annotated top level ports
topPortsHaveAnonSupplyt
)

Related Topics

Registering Name-Based Supply Nets

Registering Libraries

Registering Device and Cell

Performing In-Design Checks

Loading Power Intent Extraction Options from a File

If you have the power intent extraction setup options in a template file, you can load them and
reuse them for the same or a different design.

To load the extraction options,

August 2024 82 Product Version IC23.1

1. In the Power Manager toolbar, click Power Manager Setup.

2. In the Power Manager Setup form, click Load to select the template file.
3. Browse the file. The tool reads all the extraction options and loads the settings.
Note: The format of the loaded setup file should match the format of a standard setup
file.
4. To apply the changes, click OK.

Important
The Load option adds setup information from the file to the setup form. To put on the
changes, click Apply.

The setup can also be imported by using the vpmImportPowerIntentSetup SKILL function.
This can be used for batch mode processing. The common settings can also be saved in
.cadence/dfII/vpm/lpSetup.il without the need to reload the setup. These settings
can be referenced in any cellview.

Related Topics

Saving Power Intent Extraction Options to a File

Setup File Template

Saving Power Intent Extraction Options to a File

You can save the power intent extraction setup options in the setup form to a template file and
reuse them for the same or a different design.

To save the extraction options,

1. In the Power Manager toolbar, click Power Manager Setup.
2. In the Power Manager Setup form, click Save.

3. Browse the file. The tool saves all the extraction options and settings to the file.
4. To apply the changes, click OK.

August 2024 83 Product Version IC23.1

Important
A confirmation dialog is displayed when you click the Cancel button of the Setup
form. It ensures that the unsaved data can be saved in time.

Related Topics

Loading Power Intent Extraction Options from a File

Setup File Template

August 2024 84 Product Version IC23.1

4
Power Intent Import

If the power intent for a design is available in the required (1801) formats, you can import it to
update the design with the specified power intent. For this, it is required that the cellview is
editable. You can import the power intent to specify it for a cell being instantiated in the design.
If you create instances of an IP block in the design for which power intent is available in a 1801
or Liberty file, you can import the file and update the design as per the power intent in the file.
This helps in correctly connecting the power domains of the IP to the power domains of the
top-level design. In addition, you can register special low power cells that are imported from
the library.

Related Topics

Import Flow

Redirected netSet Property Creation and Optimization

Tie Connection Resolution

Handling of Low Power Special Cells

Support of Hierarchical 1801 for Import Flow

Removing Imported Power Intent

Import Flow
You can import the power intent and utilize it in the following scenarios:
■ Use the power intent specified for a design in the top-down power propagation scheme.
If you have a hierarchical schematic design for which the power intent is available in a
1801 file, you can import the 1801 file and update the power connectivity of each
hierarchical block used in the design as per the power intent. This enables in correctly
connecting the power domains of the IP to the power domains of the top design (SOC or
a chip).

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■ If you have a digital block with a Verilog netlist available from a digital place and route
tool, supply connectivity can be built for this block by using the Cadence Verilog Import
flow along with the initial imported power intent available for SOC where the digital block
is integrated. This defines the power requirements across digital and analog boundaries.
■ Register special low power cells that are imported from a 1801 special cell definition file.
The registered details are consumed by all the designs that use this file for creating the
power connectivity of the cells as per their power domains. The special cell definition file
is registered to be included as per the setup. For details, refer to Registering Supply Set
and Power Domain.

The illustration below gives an overview of the import flow.

Here are the key stages of the import flow.

■ Traversal of design hierarchy to find supply net expressions and explicit terminals.
Elaboration and traversal of the complete design hierarchy is done to identify the
standard and special cells that have an associated Liberty model or a special cell
definition file. This is done for the supply and topology recognition. These cells are
considered as stop cells and the tool does not traverse through these cells for power/
ground nets. Only the top level is read to collect the supply information (inherited nets or
explicit terminals), which is further mapped to the power/ground information specified in
the Liberty model or the special cell definition file.
■ Standard and special cells identification using Liberty models or the 1801 special cell
definition file.

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The special cell rules are read as specified in the input 1801 file to create the
corresponding supply connections and resolve them for the top supplies. In a hierarchical
design for cells that do not have an associated Liberty or a special cell definition, supply
nets information is gathered from the different levels of hierarchy. Power Manager
traverses down the hierarchy to the level where it finds supply nets of inherited nets (Net
Expressions) or explicit supply terminals.
■ Reading the input 1801 power specification.
The power intent is read from the 1801 file and is updated in the design with all the 1801
commands supported by Power Manager. All unsupported commands or unsupported
arguments of the supported commands are flagged in the log.
■ Creation and optimization of the redirected netSets.
netSet properties are created in the design hierarchy, wherever required. This enables
the top-level block to be instantiated in another top-level SoC schematic. The inherited
pins are created in the block schematic. The inherited terminals have the same name as
the supply nets in the 1801 file. The tie connections are resolved in the design hierarchy.
■ Creation of the top-level supply ports and supply nets.
Supply pins are created corresponding to the power domain nets and global nets during
1801 import by reading the create_supply_port and create_supply_net
commands for a successful LVS check.
Refer to the following scenarios that are considered while creating the pins.
❑ If a pin already exists and it belongs to the same net as mentioned in the 1801 file,
it is used.
❑ To create an inherited pin, a pin that exists in the same net as mentioned in the 1801
file is used. However, the pin net should be global and should match the power
domain net for which the pin needs to be created. The pin is converted into an
inherited pin by associating a terminal net-expression with the existing pin. If the
existing pin is already an inherited pin but with the different net-expression, the net-
expression is replaced.
❑ All pins created during the 1801 import are removed when you click Remove Power
Intent. If any pin existed prior to import and was converted to an inherited pin or the
net-expression was changed, it is converted back to a normal pin or the original net-
expression is restored, respectively.
❑ For the 1801 import flow, pins are not created in the design schematic for the supply
nets that do not have a corresponding create_supply_port command in the
input 1801 file. These supply nets are internally generated supply nets that have a
corresponding create_supply_net command in the input 1801 file.

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The direction of the pins created aligns with the direction specified in the
create_supply_port command in the input 1801 file.

Tip
It is recommended that after importing a 1801 file, you run Check – Hierarchy or
the File – Check and Save. These commands create nets corresponding to the
netSet properties and set the signal type of power nets and ground nets according
to the power intent.

Related Topics

Importing Power Intent

Redirected netSet Property Creation and Optimization

Tie Connection Resolution

Handling of Low Power Special Cells

Support of Hierarchical 1801 for Import Flow

Removing Imported Power Intent

Importing Power Intent

To import the power intent for the currently open cellview:

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1. Click Power Manager – Import Power Intent. It opens the Import Power Intent form.
The currently opened cellview details are specified in the form automatically.

2. Specify the switch view list sequence as mentioned in the setup.

3. Specify the name of the 1801 file in the 1801 File field. Alternatively, browse to select
the 1801 file to import the power intent for the design.
4. Select the Resolve Top netSets check box to control the creation of the global net
along with the port creation.
5. Click OK.

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The following illustration shows the output for the supply port VDDA import when
createPinsOnImport has been set and Resolve Top netSets is deselected.

Important
Alternatively, the vpmImportPowerIntent SKILL function has been provided to
import the power intent information for a cellview.

Related Topics

vpmImportPowerIntent

Import Power Intent Form

Miscellaneous Settings

Redirected netSet Property Creation and Optimization

Tie Connection Resolution

Handling of Low Power Special Cells

Support of Hierarchical 1801 for Import Flow

Removing Imported Power Intent

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Redirected netSet Property Creation and Optimization

While creating the supply connectivity across the design hierarchy, there could be conflicts
where the same net expression property gets resolved to different supply nets at the top. For
correct supply connectivity resolution in such scenarios, a redirecting netSet property is
created and an optimization algorithm is executed to ensure that the redirection of netSet
property happens across the design hierarchy only where required. Redirection is done
where having a pure global net expression can cause issues in the supply connectivity across
the design hierarchy. This ensures minimum number of netSet properties at the top instance.

Wherever the property name is created, the prefix is added as mentioned in the setup to
identify various pg_type. Redirected property name is realized as

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[@Prefix_cellname_count:%:topsuplyname!]. The illustration below represents the

creation of redirected netSet property in the design.

In a design if there is a hierarchy and no Liberty stop cell, Power Manager traverses to the
level where net expressions exist. Or, if the net expressions are already redirected to have
different property names, it is the reference for the tool to make the connectivity.

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Related Topics

Importing Power Intent

Redirected netSet Property Creation and Optimization

Tie Connection Resolution

Handling of Low Power Special Cells

Support of Hierarchical 1801 for Import Flow

Removing Imported Power Intent

Tie Connection Resolution

In a Verilog netlist if an input pin of a standard cell instance or a special low power cell, such
as level shifter or isolation cell instance, is connected to a numerical constant 1'b1 or 1'b0,
the input pin gets connected to a global supply net in the schematic created after Verilog
import using Verilog In. The name of the global supply net is specified at the time of Verilog
import. After Verilog import, all such input pins connect through a common wire creating tie
connections. The label of the common wire matches the global supply net name.

To avoid shorting of nets after importing the 1801 file, it is important that all such pins are
connected to wire stubs with a label. However, the wire stubs are not physically connected to
each other. To achieve this, use the two connect by name options, Connect Power Net By
Name and Connect Ground Net By Name, during Verilog import. This connects each tied-
off input pin with the wire stub that has a label. It enables you to modify the tied-off input pin

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connections without creating incorrect connectivity in the design through shorting of the nets
during the 1801 import. Use create Net Expression as per the design requirement.

To resolve the tie connections of various instances, all the labels that require an update are
identified during import. The labels on the wire stubs that are attached to the tied-off input
pins are updated. These labels present at the top level or in the lower level block are identified
for updates based on the following conditions:
■ The label is attached to a wire, which has one end point floating (not connected to
anything) and the other end point connected to an instance.
■ The wire net name is registered as a power or ground in a setup.
■ Wire nets must have a netType property associated. The power nets must have the
netType property as supply1. The ground nets must have the netType property as
supply0.

Wire net having the netType property is one of the conditions because it ensures that the label
and wire have been added using Verilog In.

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It avoids modification of labels in standard cells, for example, an inverter schematic can have
terminal MOS devices with bulk/source/drain terminals connected to wire stubs that have a
label, and the wire nets are registered as power or ground in the setup.

Once the target wire label is identified, the 1801 import flow processes these nets to create
unique inherited tie nets for each occurrence of such nets in the entire design hierarchy, for
example, tie0! or tie1!. This prevents shorting of nets during the import flow. The tie net
expression is further resolved based on whether it is a top-level net or a sub-block net.

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■ For tie net at the top level, the instance pin to which it is connected is identified along with
the related power and ground net of the connected instance pin. The wire labels are
updated according to the 1801 file definition.

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■ For a tie net in a sub-block, the instance pin to which it is connected is identified along
with the related power and ground net of the connected instance pin. The tie net
expression is resolved to its final power or ground value based on a netSet property.

The final resolution of the tie connections in schematic designs to the appropriate power and
ground nets mentioned in the 1801 file is aligned to the following rules:
■ For standard cell instances, the tie connection at the input pin is resolved with the power/
ground net of the power domain of the instance.
■ For isolation instances, the data pin with tie connection is resolved with the power/ground
net of the power domain in which the isolation cell is located.
■ For isolation instances, the enable pin with tie connection at the input pin is resolved with
the power or ground net of the always-on power domain of an isolation instance. This
depends on the –isolation_supply_set or default_isolation arguments
according to location or domain.

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■ For level shifter instances, the data pin with tie connection is resolved with the power/
ground net of the input_supply_set argument.
■ For enabled level shifter instances, the enable pin with tie connection is resolved with the
power or ground net of the output power domain of the enabled level-shifter instance. If
the output_supply_set argument is not available, the supply set of the receiving logic
is considered.
■ For isolation and level shifter combo cell instances, the enable pin with tie connection is
resolved with the power/ground net of the input power domain of the enabled level shifter
instance.

Related Topics

Importing Power Intent

Redirected netSet Property Creation and Optimization

Handling of Low Power Special Cells

Support of Hierarchical 1801 for Import Flow

Removing Imported Power Intent

Handling of Low Power Special Cells

The 1801 import flow supports the following low power special cells:
■ Level Shifter
Import 1801 flow supports different level shifter configurations, such as single rail, dual
rail and enabled single /dual rail (combo cell). For each level shifter instance, the load
and drivers along with their power domains are determined and the netSet properties are
created based on the criteria mentioned below.
❑ If a level shifter cell is connected to a standard cell or port at both ends, the load and
driver domains are used to resolve PG connections.
❑ If a level shifter instance is a multi-rail cell, the driver domain resolves the input
supply connections and the load domain resolves the output supply connections.
Level shifter rule specified in the input 1801 file enables in determining the load and
the driver domains. The rule is considered to find the supply set based on
input_supply_set and output_supply_set argument. Level shifter rules are
specified in input 1801 as:

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set_level_shifter ls_rule -domain pd_ls -applies_to inputs -rule

low_to_high -location self -input_supply_set SS_VDD_VSS -output_supply_set
SS_VDDA_VSS

If not specified, Power Manager finds the driver and load supply set for the level
shifter by traversing the design path and resolving the connectivity accordingly.
❑ If a level shifter instance is a single-rail cell, the load domain resolves the output PG
connections. input_signal_level is required in the Liberty model of the level
shifter to identify the cell type as single rail level shifter.
❑ If a level shifter instance is connected to an isolation cell at one end, the load or
driver domain on the other end is determined. If the driver domain is known, it
resolves the input supply connections. If the load domain is known, it resolves the
output supply connections.
Note: A single-rail level shifter cell has only output supply.
❑ If a level shifter instance is connected to an isolation cell at one end, the power
domain for the end connected to the isolation instance is determined from the
isolation instance. Therefore, the power domain at the isolation cell intersection is
the same as the power domain of the isolation cell itself.
■ Isolation Cell
Initially, the load and driver of the isolation cell are traced and then, the netSet properties
are created based on the criteria mentioned below.
❑ If an isolation cell is connected to a standard cell or a port on both the ends, the
power domains of the load as well as the driver are used to resolve the PG
connections and create netSet properties.
❑ If an isolation cell instance is a multi-rail cell and has a switchable power or ground
pin, then the switchable domain is used to resolve the switchable PG connections.
The non-switchable domain resolves the non-switchable PG connections.
❑ If an isolation cell instance is a single-rail isolation cell, only one of the load or driver
domain that is non-switchable is used to resolve the PG connections. The isolation
rule specified in input 1801 file assists in determining the load and the driver
domains. The rule will be considered to find a supply set based on
isolation_supply_set defined in the isolation rule. Isolation rules are specified in
input 1801 file as:
set_isolation ISO -domain PD_VDD_VSS -location self -elements {I1/In} -
isolation_supply_set SS_VDD_VSS -isolation_signal I0/en -isolation_sense
high -location self

Note: isolation_supply_set is required if default_isolation is not

mentioned in the power domain stated in the input 1801 file.

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Note: You can provide an expression containing multiple pins for enable in the
tech.upf file for isolation cells and level shifter cells. For example,
define_isolation_cell -cells ISOHX1_OFF -enable
"EN1&EN2&!EN3" -power VDD -ground VSS.
■ Power Switch
For power switch, the load and drivers supply along with the control net are determined
and the netSet properties are created accordingly. The power switch rule specified in
input 1801 file enables in determining the load and the driver domains. The rule is
considered to find a supply set based on input_supply_port,
output_supply_port and control_port.
Power switch rules are specified in the input 1801 file as:
create_power_switch I3_I0 -output_supply_port { VDD VDDSW } -input_supply_port
{ ExtVDD VDD } -control_port { PSO psw_en } -on_state { on ExtVDD {!PSO} }
-off_state { off PSO } -domain PD_TOP

If the create_power_switch has a -instance option, the name of the switch

instance(s) are provided that are covered by the power switch rule. If the
create_power_switch has a -domain option, the power switch rule targets all power
switches that are inserted within the domain boundary.

Related Topics

Importing Power Intent

Redirected netSet Property Creation and Optimization

Tie Connection Resolution

Support of Hierarchical 1801 for Import Flow

Removing Imported Power Intent

Support of Hierarchical 1801 for Import Flow

The import 1801 flow in Power Manager also supports a hierarchical 1801 input file. A
hierarchical 1801 has the load_upf and set_scope commands which set the scope to
each of the specified list of instances and executes the set of 1801 commands in the child
1801 file, specified as the argument of the load_upf command. Upon return, the current
scope is restored to what it was prior to invocation. Supply nets and ports will be created for
load_upf/set_scope block, based on the create_supply_net and

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create_supply_port commands mentioned in the parent 1801 file, along with that, it will
also obey the settings for createExtractionLogFile and ResolveTopNets.

For all the instances in the design, domain assignment is based on create_power_domain
and if no element has the power domain specified, it will belong to default power domain. In
case there is no default power domain in the scope, then its upper scope default power
domain will be looked at to assign the power domain.

Honoring Command Sequence and Precedence

The traversal of the input 1801 file in the import flow follows a set of the below-mentioned
rules related to the command sequence and their precedence.
■ Any explicit assignment of the elements (instances) in the create_power_domain
command takes precedence over the extent that includes elements (instances) as a part
of that power domain.
If there is an existing explicit domain assignment with create_power_domain in the
elements section, irrespective of the ordering of create_power_domain, set_scope,
or load_upf commands, the precedence of scope is defined by the nearest ancestor
that has an explicit domain assignment using create_power_domain.
This can be shown in the following case considering the sequence of commands in the
input 1801file:
set_scope "/"
create_power_domain PD2 -elements {I0/I2} ….
create_power_domain PD1 -element { . } ....
set_scope "I0"
create_power_domain PD3 -elements {.} ….

Result: I0/I2 gets assigned to the power domain PD2 and not PD3
■ Explicit assignment of multiple domains to the same instance is an error and 1801 stops
the import process. This can be shown in the following case:
set_scope "/"
create_power_domain PD1 -elements {I0} ….
set_scope "I0"
create_power_domain PD2 -element { . } ….

Result: Error case

■ connect_supply_net always takes precedence over create_power_domain. If
there are more than one connect_supply_net commands for the same supply net,
the last command in the order is honored. In case of multiple connect_supply_net
commands, the last command is applicable.

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set_scope "/"
create_power_domain PD1 -elements {I0} ….
set_scope "I0"
create_power_domain PD2 -element { . }….

Result: I0/vdd is connected to VDD2

Related Topics

Importing Power Intent

Redirected netSet Property Creation and Optimization

Tie Connection Resolution

Handling of Low Power Special Cells

Removing Imported Power Intent

To remove the updates done in the design using Import 1801 flow, which include newly
created pins, nets, net expressions, and netSet properties on the blocks, you can use the
Remove Power Intent option. This removes these objects and restores the previous state of
the design before the importing the power intent. This can be accessed from the Power
Manager menu and the Power Manager toolbar.

To remove the power intent information from a design:

1. Click Launch – Power Manager – Remove Power Intent.
2. Click Yes.

Alternatively, use the vpmRemoveImportedPowerIntent SKILL function for removing the

power intent.

Related Topics

Importing Power Intent

Redirected netSet Property Creation and Optimization

Tie Connection Resolution

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Handling of Low Power Special Cells

Support of Hierarchical 1801 for Import Flow

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5
Running In-Design Checks

The in-design checks aim to provide hints to designers for multiple design guidelines or
checks and helps in improving the efficiency of the design development cycle. Such checks
help checking complex mixed-signal designs that have multiple voltage islands, an increased
fusion of analog and digital blocks, more interfaces to check within analog blocks, an
increased use of complex power distribution, different modes for achieving power savings,
and the use of third-party IPs in various forms. You can also generate signal information for
the design, which can be used as a good debugging aid to analyze different power domain
crossings in a design.

In-design checks can be run on any physical design schematic having complete power
connectivity. Designs that have the power connectivity introduced post the 1801 Import flow
are also suitable candidates for running in-design checks.

The In-Design Checks functionality includes the following structural checks:

■ Low power checks
❑ Level Shifter Checks
❑ Isolation Checks
■ Bulk Checks

Related Topics

Level Shifter Checks

Isolation Checks

Bulk Checks

Checking a Design in Foreground Mode

Checking a Design in Background Mode

Loading the Violations Database

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Filtering Violations

Generating Signal Information

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Defining the Severity of Design Checks

Power Manager through its in-design checking functionality performs various static low power
structural checks for level shifters and isolation cells. It also aids in checking for invalid
connectivity of bulk node for transistors used in the design by performing the bulk checks.

To define the severity for the checks:

1. On the In-Design Checks tab of the Power Manager Setup form, select the Level Shifter
or Isolation tab.
2. Specify the severity level for various low power checks in the Severity section.

Related Topics

Level Shifter Checks

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Isolation Checks

Bulk Checks

Checking a Design in Foreground Mode

Checking a Design in Background Mode

Loading the Violations Database

Filtering Violations

Generating Signal Information

Level Shifter Checks

The following checks are performed for various types of level shifters in a design.
■ Missing Level Shifter check
Checks all the data connections for voltage compatibility. If the voltage values for driver
and receiver are not compatible, an error is generated. In this check, the type of missing
level shifter (high-to-low or low-to-high) is reported. The driver supplies might be MOS
drain terminals, standard cell output, or output macro domain ports. Loads can be MOS
gate terminals, standard cell input, or macro domain ports. In addition, domain crossings
operating at different voltages without level shifters are reported in one of the following
scenarios:
❑ The driver power voltage is less than the receiver power voltage by the lower bound
input voltage tolerance.
❑ The driver power voltage is more than the receiver power voltage by the upper
bound input voltage tolerance.
❑ The driver ground voltage is less than the receiver ground voltage by the lower
bound ground input voltage tolerance.

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❑ The driver ground voltage is more than the receiver ground voltage by the upper
bound ground input voltage tolerance.

❑ The driver voltage value is less than the maximum device voltage.

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❍ The driver voltage is less than the receiver voltage

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❍ No maximum device voltage found.

❍ The device-specific maximum device voltage value has been defined. The
violations are reported at:
❍ Pass-tx gate (exceeds maximum device voltage)

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❍ M9 and M10 gates (exceeds maximum device voltage)

❍ The device-specific tolerance value has been defined. The violations are
reported at
❍ Pass-tx gate (missing level shifter)
❍ M9 and M10 gates (exceeds maximum device volatge)

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❍ No violations reported at pass-tx source/drain

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❍ Negative voltage with common ground supply. The violations are reported for
PM1, NM1 (exceeds maximum device voltage)

❑ Tolerance Settings

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You can define the lower and upper tolerance values for input and input ground voltages
in the Tolerance section.

The default value of the lower limit of the input power and input ground voltage is -0.10.
It should be less than or equal to 0.
The default value of the upper limit of the input power voltage and input ground voltage
is 0.10. It should be greater than or equal to 0.

The missing level shifter check also supports the following:

■ User-defined Registering Port Attributes for checking the boundary ports.
■ Supply States for explicit voltage values.
Note: Power states that are OFF are not considered for reporting missing level shifter
errors.

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■ Incompatible Level Shifter check

In this check, all domain crossings at different operating voltages are checked for the
level shifters voltage ranges. An error is reported if operating voltages are found
incompatible, for example, high level shifters in a low-to-high crossing or conversely.
Incompatibility in operating voltages can arise due to the following:
❑ Voltage levels of signals
This checks for incompatible driver or receiver for a data pin with respect to input or
output supply voltage range for a level shifter.
❑ Voltage levels of supply
This checks for incompatibility of level shifter supplies with respect to the input or
output voltage range supported by the level shifter.

■ Redundant Level Shifter check

All domain crossings with level shifters at the same operating voltages are reported. In
addition, the domain crossings at the macro boundary with a redundant level shifter are
reported.
Note: A valid level shifter in one supply state is not considered redundant in any other

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power state.

■ Protected Level Shifter check

The data is protected by using an enable signal. The protected level shifters in design
along with their enable condition are highlighted.

■ Unprotected Level Shifter check

An unprotected dual rail level shifter is reported when all the following conditions are true:
❑ Level shifter instance has no enable pin.
❑ One domain of the level shifter instance is in the OFF state.

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❑ The second domain of level shifter instance is in ON state.

■ Floating Level Shifter check

The floating level shifters have their enable signal evaluated as floating. During the
check, the level shifter is reported if its enable input can be traced to a floating value.
While performing the in-design checks, the tool should ignore all supply states where all
supplies are in OFF state. The tool also ignores all supply states in which no power
supply or no ground supply is in the ON state. An information message is issued to
indicate that the supply states are ignored.

■ Potentially Floating Level Shifter check

This check identifies if a level shifter is driven by logic elements, such as an inverter or
buffer, which have their input tied to a power net and the supply is in the OFF state. Such
a level shifter cannot be considered as floating because the supply net could have carried

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some charge while in the ON state and could be slowly discharging towards 0V. This
discharge might enable PMOS gates and clamp the level shifter. Consequently, such
level shifter instances are categorized as potentially floating level shifters.

■ Always Enabled Level Shifter check

This check highlights the level shifters that have the enable pin tied to a fixed supply
voltage and therefore, the state of the level shifter never changes. It keeps the data
output always clamped. While trying to determine the enable expressions for enabled
level shifters, the sense value for a signal (an occurrence net) is used if the
corresponding module net and the module have a signal-sense registered using the
define_signal_attribute.

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and the occurrence net (top level net) for at least, one of the off_supplies mentioned in
the definition, is in off state. If there are conflicting definitions across the span of the net,
a warning message is issued.

■ Unused Enable Level Shifter check

This check highlights a level shifter that has the enable pin tied to a fixed supply voltage
of opposite polarity. In this case, the enable pin is not used effectively.The unused enable
level shifters have an enable signal tied to a fixed voltage and data output is never
clamped.

Related Topics

Defining the Severity of Design Checks

Isolation Checks

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Bulk Checks

Checking a Design in Foreground Mode

Checking a Design in Background Mode

Loading the Violations Database

Filtering Violations

Generating Signal Information

Isolation Checks
The following checks are performed for various types of isolation or level shifters in a design.
■ Missing isolation check
Reports all domain crossing involving at least one switchable domain and another
switchable or always on domain without isolation. The driver supply could be MOS drain
terminals, standard cell output, or output macro domain ports. Similarly, load could be
MOS gate terminals, standard cell input, or macro domain ports.

In addition, reports violations for the following scenarios when a receiver supply can be
floating if the driving isolation or level shifter cell supply is off.

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❑ A level shifter output is considered floating if the level shifter output supply is off.
❑ A non-enabled isolation cell output is considered floating when the isolation supply
is off.
❑ A NAND isolation output can be considered valid if ground supply is off and enable
driver supply is on and the output pin is not specified as non-floating.
❑ A NOR isolation output can be considered valid if power is off and enable driver
supply is on and the output pin is not specified as non-floating.
❑ Any other enabled isolation cell output is always considered floating when the
isolation supply is off.
The check reports violations for the following scenarios where level shifter and isolation
cell data pins can be floating if the driver output supply is floating.
❑ A non-enabled level shifter input data pin that cannot accept a floating input.
❑ An enabled level shifter data pin that can receive a floating input if the supply for the
enable driver is on and the level shifter data pin is not specified as non-floating. A
non-enabled isolation cell data pin that cannot accept a floating input if the cell is
single rail.
❑ A non-enabled isolation cell data pin that receives a floating input if the cell is dual
rail and if the backup supply is on and the isolation cell data pin is not specified as
non-floating.
❑ An enabled isolation cell data pin that can receive a floating input if the supply for
the enable driver is on and the isolation cell data pin is not specified as non-floating.
■ Incompatible isolation check
Reports violation for an enabled isolation or level shifter cell if the related supply for cell's
enable pin is on but the supply for the enable pin's driver if off.
■ Redundant isolation check

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Reports an error if the driver and receiver of an isolation cell are switched on and off
simultaneously or they are never turned off. This helps in optimizing the design area and
power by indicating the redundant circuit elements.

Related Topics

Defining the Severity of Design Checks

Level Shifter Checks

Bulk Checks

Checking a Design in Foreground Mode

Checking a Design in Background Mode

Loading the Violations Database

Filtering Violations

Generating Signal Information

Bulk Checks
The incompatible bulk check flags transistors, which have the bulk terminal-related supply
incompatible with the related supply of its source or drain terminal.
■ For a P-type transistor, a violation is reported in the following scenarios:
❑ The voltage for the related bulk supply net is less than the voltage for the related
source or drain supply net.

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❑ The bulk node is OFF compared to either the source or drain terminal that are fully
ON in a particular supply state.
■ For an N-type transistor, a violation is reported in the following scenarios:
❑ The voltage for the related bulk supply net is more than the voltage for the related
source or drain supply net.
❑ The bulk node is fully ON compared to the source or drain terminal that are OFF in
a particular supply state.

Related Topics

Defining the Severity of Design Checks

Level Shifter Checks

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Isolation Checks

Checking a Design in Foreground Mode

Checking a Design in Background Mode

Loading the Violations Database

Filtering Violations

Generating Signal Information

Checking a Design in Foreground Mode

To run the In-Design Checks in foreground mode, perform the following steps:
1. Load the setup in the Power Manager Setup form.
2. Choose Power Manager – Run In-Design Checks. The Run In-Design Checks form
is opened.

3. Select the appropriate value for the Scope field. The Library, Cell, View, and Instance
Path are read-only fields.
You should choose the Current Cellview option in the following scenarios:
❑ You have a Power Manager setup for the specific design. The setup includes specific
information for the design, such as supply states, supply nets, net voltage, and so
on.

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❑ You want to validate the complete design.

If you are making changes to a part of an existing design and you want to know how the
changes in the hierarchy affect the accuracy of the design within that sub-hierarchy, you
can validate a portion of the design by choosing the Hierarchical Instance option in the
following scenarios:
❑ You have a Power Manager setup for the top-level design, which includes all relevant
information about supply states, supply nets, net voltage, and so on.
❑ You want to descend to the lower-level cell and want the scope of the design checks
limited to the hierarchy of the lower cell and its interface connections.
4. Click OK. An inDesign.log file, such as the one shown here, appears.

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Related Topics

Defining the Severity of Design Checks

Level Shifter Checks

Isolation Checks

Bulk Checks

Checking a Design in Background Mode

Loading the Violations Database

Filtering Violations

Generating Signal Information

Checking a Design in Background Mode

While checking a design, you can enable background mode to perform other processes in the
same Virtuoso session while the in-design checks are run in the background. To run the In-
Design Checks in background mode, perform the following steps:
1. Set the runIDCInBackground environment variable to t.
2. Load the setup in the Power Manager Setup form.

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3. Choose Power Manager – Run In-Design Checks. The Run In-Design Checks (Non-
Blocking) form is opened.

4. Select the appropriate value for the Scope field. The Library, Cell, View, and Instance
Path are read-only fields.
5. Specify the run directory.
6. Select Overwrite Existing Directory (directory will be removed) to replace any
existing run directory with the same name.
7. Click Start to initiate the In-Design Checks run in the background. Only the on-disk copy
of design is used for running the checks.

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The View Run Log button is enabled to view the replay log for the background process.

8. [Optional] View the Run Status field and the graphic on the form being updated as the
run progresses.
9. Click the View Audit Log button when the background process has completed
successfully to view the audit log for the In-Design Checks run. Similarly, click the Load

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Violations button when the background process has completed to view the
backannotated violations on the design.

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10. [Optional] Click Stop to halt the active in-design checks run in the background if an
incorrect version of design is used or some updates need to be done in the design. The
run is stopped after you confirm.

11. [Optional] Click Close to halt the active in-design checks run in the background and
close the form. The run is stopped and the form is closed after you confirm.
Note: If you specify the run directory of a specific Virtuoso session in some other Virtuoso
session, the last saved status of the run is loaded. Subsequently, you can view the last results,
related setup file, and violations. You can complete the run if it was not completed earlier.

Related Topics

Defining the Severity of Design Checks

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Level Shifter Checks

Isolation Checks

Bulk Checks

Checking a Design in Foreground Mode

Loading the Violations Database

Filtering Violations

Generating Signal Information

Loading the Violations Database

The errors generated are cross-probed to the accurate schematic location to enable the
editing and correction. While analyzing violations using the Annotation Browser, the mode in
which a marker cellview is opened depends upon the Annotation Browser options. This
means that it is possible that the marker cellview is opened in edit mode even if the top
cellview or current design is opened in read-only mode. If a marker cellview is opened in edit
mode and you perform any action that attempts to close the marker cellview, you are
prompted to save or discard the changes.

To load the violations database, perform the following steps:

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1. Choose Power Manager – Load Violations.

2. Select the appropriate value for the Scope field. The Library, Cell, View, and Instance
Path are read-only fields.

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3. Specify the file name and click OK. The Annotation Browser displays the violations in the
design.

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4. Specify the scope of the violations, which is based on the cellview hierarchy, to be
displayed in the Annotation Browser.

Annotation Browser provides easy and in-context error browsing mechanism through
context menu for the violation nodes.
Here is the list of the levels until which you can probe for various nodes:
❑ Right-click the Always Enabled Level Shifter node. Then, click Probe –
Inst/Driver/ Receiver.
❑ Right-click the Incompatible Level Shifter Signal node. Then, click Probe
– Net/Inst/Driver/ Receiver.

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❑ Right-click the Incompatible Level Shifter Supply node. Then, click Probe
– Inst.

❑ Right-click the Missing Level Shifter node. Then, click Probe – Net/Driver/
Receiver.

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❑ Right-click the Protected Level Shifter node. Then, click Probe – Inst/
Driver/ Receiver.

❑ Right-click the Redundant Level Shifter node. Then, click Probe – Inst.
❑ Right-click the Unused Enabled Level Shifter node. Then, click Probe –
Inst/Driver/ Receiver.
❑ Right-click the Bulk Error node. Then, click Probe – Inst.
❑ Right-click the Missing Isolation node. Then, click Probe – Net/Driver/
Receiver.
❑ Right-click the Incompatible Isolation signal node. Then, click Probe –
Driver/ Receiver.
❑ Right-click the Redundant Isolation signal node. Then, click Probe – Inst.

Related Topics

Defining the Severity of Design Checks

Level Shifter Checks

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Isolation Checks

Bulk Checks

Checking a Design in Foreground Mode

Checking a Design in Background Mode

Filtering Violations

Generating Signal Information

Filtering Violations
You can add the filter patterns to waive off violations in the Filters field on the Runs In-Design
Checks tab of the Power Manager Setup form. These indicate the permissive deviations in
the design. The tool filters the errors messages or violations matching the pattern specified
in the Filters field. The Annotation Browser does not display the filtered violations. All
matching violations are reported as the filtered messages in the In-Design Checks Report.
See Performing In-Design Checks.

Related Topics

Defining the Severity of Design Checks

Level Shifter Checks

Isolation Checks

Bulk Checks

Checking a Design in Foreground Mode

Checking a Design in Background Mode

Loading the Violations Database

Generating Signal Information

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Generating Signal Information

You can assign the voltage information to each design net based on the possible voltage
values defined in the Signal Information Report that the net can have under multiple design
conditions.

To generate the signal information report:

1. Load the setup file. The setup file is needed for identifying the design elements and
registering voltage values for different nets.
2. Choose Power Manager – Generate Signal Info. Alternatively, use
vpmGenerateSigInfo. The Signal Information Report is created.

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Related Topics

Defining the Severity of Design Checks

Level Shifter Checks

Isolation Checks

Bulk Checks

Checking a Design in Foreground Mode

Checking a Design in Background Mode

Loading the Violations Database

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6
Exporting Power Intent of a Design

The power intent of the design specified in the 1801 file acts as a design source along with
the logical intent (synthesized Verilog netlist). This collection of source input files is utilized by
different tools, including the formal verification tools. The 1801 information is expected to
successively refine at various design stages, one of which is the case where the design
information changes (ECO). Here, a 1801 file incorporating all the design changes is required
to be regenerated to have a logical equivalence with the updated design schematic.

The export flow enables you to extract the design connectivity from the schematic and export
the low power design intent to a 1801 file. This helps in adding the updated content in
incremental stages of IP authoring, which can finally be verified for correctness using CLP
along with a VerilogPG netlist.

Related Topics

Export Flow

Extracting the Power Intent from a Design

Exporting 1801 Design Model

Exporting 1801 Power Model

Exporting Liberty Power Model

Special Isolation Cells in Liberty Power Model Export

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Export Flow
The illustration below gives an overview of the export flow.

Here are the key stages of the export flow.

■ Extraction of design
❑ Partitioning of the design
❑ Identification of PG net types, standard, special and other cell types
❑ Propagation of power information to sub blocks down the hierarchy
❑ Creation of power domains and power modes
■ Creation and export of Design Model of the design
■ Creation and export of Power Model of the design
■ Creation and export of Liberty Macro Model of the design

Related Topics

Identification of Design Objects

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Design Partitioning

Exporting 1801 Design Model

Exporting 1801 Power Model

Exporting Liberty Power Model

Special Isolation Cells in Liberty Power Model Export

Extracting the Power Intent from a Design

If your design includes objects that describe the power intent for the design, you can extract
the power intent, which can further be exported to a 1801 file, to be used further in design
flow.

To extract power intent from a design:

1. Open the design in Power Manager.
2. Prepare the setup for automatic extraction. Load the setup from Power Manager toolbar
or menu.
3. On the Power Manager toolbar or menu, click Extract from Design.
The Extract Power Intent form appears.

The library, cell, and view name list of the currently open cellview are shown in the form. The
fields specify the information of the cellview, which is non-editable, being extracted.

For a pure schematic-based design, Power Manager always extracts a flat (design model,
power model, or macro model) 1801. If there are hierarchical blocks in the design that have
their own associated 1801 file, the tool does not extract details of that block and generates a
hierarchical 1801, instead by integrating the 1801 file of the lower-level blocks. During the

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extraction of design schematic the identification of design objects and partitioning is

performed.

Related Topics

Setup for Automatic Extraction of Power Intent

Export Flow

Identification of Design Objects

Design Partitioning

Exporting 1801 Design Model

Exporting 1801 Power Model

Exporting Liberty Power Model

Special Isolation Cells in Liberty Power Model Export

Identification of Design Objects

The design extraction involves the identification of the essential design objects, which are
required for building a correct power intent. These include:
■ Identification of power and ground nets associated with each cell in the design hierarchy
by using the name-based registration in the setup file.
■ Identification of the standard and special cells that have associated Liberty models or a
1801 special cell definition file at the path specified in the setup. When found, the tool
identifies the cells defined in the 1801 file as standard or special cells.

Related Topics

Design Partitioning

Setup for Automatic Extraction of Power Intent

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Design Partitioning
A design can contain different types of cells. For example, the following example design
contains various types of blocks.

During extraction, the extractor handles each type of cell differently. For example, if a cell is
already bound with a 1801 file that was previously imported in the schematic of the cell, the
extractor refers to the1801file instead of re-extracting the power information of the cellview.

Similarly, for all multi-supply cells that contain primitive cell instances that were identified
during the partitioning stage, the extractor extracts the cellview-level power domain
information and stitches it to the top-level domains. Instances of single supply cells are
considered as standard cells and their power attributes are derived from their corresponding
Liberty model and stitched to the top-level power domains. Therefore, before extracting power
intent, the tool needs to identify different types of cells and blocks in the design.

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During partitioning, the Schematic Editor traverses through the design and identifies the
following types of cells:

Cell Type Description

Primitive cells A cell that meets the following criteria:
■ Does not contain any instances
■ Does not have any power pin or
ground pin
Examples: PMOS, NMOS, RES
Passive cells A cell that meets the following criteria:
■ Contains only primitive instances
■ Does not have any power pin or
ground pin
Examples: resistor bank or capacitor
bank
Low power special cells A cell that is registered as a special low
power cell.
Examples: isolation cell, level shifter,
power switch
Single supply voltage cells A cell that meets the following criteria:
■ Contains zero or more primitive cell
or passive cell instances
■ Has one power pin and one ground
pin
Example: single-rail cell
Multiple supply voltage A cell that meets the following criteria:
cells
■ Contains zero or more primitive cell
or passive cell instances
■ Has more than one power pin and
one or more ground pins
Example: multi-rail cell

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Cell Type Description

1801 cells A cell that contains the existing 1801
model. The power intent that has been
imported by using the File – Import
Power Intent command is being applied
to this cell.
Macro cells A cell that meets any one of the following
criteria:
■ Contains one or more instances of
primitive cell or passive cell and one
or more instances of single supply
cell, multiple supply voltage cell, or
1801 cell
■ Contains one or more instances of
primitive cell or passive cell and has
more than one power pin and one or
more ground pin
■ Has more than one power pin and
one or more ground pin, but does not
contain any cell, that is, an empty cell
with multiple supply voltages
Hierarchy cells A cell that meets the following criteria:
■ Contains instances of single supply
cell, multiple supply voltage cell,
macro cell, or 1801 cell
■ Does not contain any primitive cell or
passive cell

After the design partitioning, the next step is the design elaboration. The design elaboration
involves the creation of an Embedded Module Hierarchy (EMH), which is a model for storing
the hierarchical design data supported at the open access database level. For Power
Manager, this open access cellview is called the power view. The extractor traverses the
entire schematic hierarchy to achieve the following:
■ Builds a data structure that contains the OA equivalent objects from the database objects
encountered. The structure includes a top-level design, instances, nets, terms, instTerms
and net connectivity.

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■ Utilizes all the instances of the cells that have Liberty models, associated power views,
and associated 1801 model.
■ Extracts power intent by tracing the connectivity. The connectivity tracing is done
considering the block domain of open access cellview, that is, the flat representation of
the entire schematic hierarchy in EMH.
■ Identifies power nets and ground nets and their equivalent power or ground nets by the
sigType in the schematic or the name-based registration in the setup.
■ Identifies switchable or non-switchable power nets or ground nets. This is the output from
switch supply pin of switch cell instances (Power Switch).
■ Pairs the power nets and ground nets. PG net pairing is done by looking at the related
PG pins of standard cell instances, special cell instances, macro cell instances. In
addition, pairing is also done by tracing a path between the top-block power and ground
nets through the source-drain terminals of transistors, shorts, and connector devices in
the top block.
■ Models various states where every single supply each state is assigned a specific
voltage or the state of supply sets, that is, collection of supplies instead of individual
supplies by using PST for exporting design and power models.
■ Assigns instances to the power domains.
■ Creates power states and the power modes. Also, assigns power domains to these
power modes.
■ Identifies boundary ports and assigns these ports to the power domains. This
identification is done based on tracing the connectivity through transistors and two
terminal devices. Related power and ground nets of ports are derived by analyzing the
related supplies of the driver or receiver instTerms in the top block. While identifying ports
for creating power domains, it is checked whether the port could be related to more than
one power domain by virtue of its connections to one or more instances that may belong
to multiple power domains. In such a situation, the port is not associated with any power
domain and the warning messages are issued depending on the situation. There are
three scenarios where the ports are not related to any of the power domains due to
ambiguity in deciding the power domain:
Case 1: In this scenario, port C can be related to either of the two supply sets
(SS__VDD__VSS and SS__VDDext__VSS) due to its connectivity to M2, which falls in

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the path of VDD, VSS as well as ExtVDD, VSS. Therefore, port C is not related to any
supply set because there is ambiguity related to its power domain.

Case 2: In this scenario, the port IN1 is driving two inverter instances that belong to
different supply sets and so it can be assigned either to SS__VDD__VSS or

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SS__vdd__vss. Therefore, port IN1 is not related to any supply set because there is
ambiguity related to its power domain.

Case 3: In this scenario, the port TOP_IN drives two pins, IN1 and IN2, of a hierarchical
instance. Inside the instances (not shown in the image), IN1 and IN2 are separately
driving two inverters, which are in two separate supply sets SS__VDD1__VSS and
SS__VDD2__VSS, respectively. The port TOP_IN can be assigned either

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SSVDD1VSS or SSVDD2VSS, therefore, it is not related to any supply set due

to ambiguity in its power domain.

In such scenarios, you can provide the information of data ports to explicitly specify their
supply set, forcing the tool to associate the data ports to the desired power domain.

While extracting power intent, Power Manager gives precedence to the explicit registration of
the port attributes and traces connectivity through transistors and the two-terminal devices.
Each data terminal that can be traced to a power terminal is created as a boundary port for
the corresponding power domain. If a data terminal is connected to more than one power
terminal, it is attached to the power domain as specified in the port attribute registered in the
setup for that data terminal. If the port attribute is not registered in the setup, the tool would
associate the data terminal to all possible power domains found by connectivity tracing.
Note: While extracting power intent, the tool checks each macro cell and the top cell to find
ports that are not related to any supply terminal. The tool does not assign such ports to any
power domain and displays a warning message for each cell to report such ports in that cell,
as shown below:

\w WARNING (LP-3034): Could not determine driver/receiver supplies

for logic port 'enps_3v3_i, dll_amux_ao, dll_ibias_10u_ai' in the

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Liberty or setup files. Ensure that the required supplies are defined
in the files.
■ Derives domain shutoff conditions by backtracing the enable pins of switch cell instances
in the top block to the top block ports and combining those ports in suitable expression
as per the design.
■ Integrates sub blocks that have their own 1801files.
❑ If the 1801 block has a power intent specified as a Liberty macro model, it identifies
the top-level domain that maps to the macro-level domain and creates a domain
mapping. PG net voltages in macro cells are assigned from the top net voltages.
This might lead to a conflict if the net voltage specified in the macro model are of
different voltage levels as compared to the voltage levels of the top net voltage. This
conflict can be noted at the verification stage of the power intent.
❑ If the 1801 block has power intent of the design model type, Power Manager collates
all the power domains in the 1801 block hierarchy and integrates the 1801 cell in the
same way as for a block with the macro model type.
■ Identifies low power special cells and creates power switch rules, isolation rules, and
level shifter rules, as required. Enable conditions are derived by backtracing the enable
pins of special cells.
Note: If a level shifter cell contains an enable pin, it is identified as both an isolation cell and
as a level shifter cell. Such cells are also referred as combo cells. In this case, while extracting
power intent, the tool defines it as a level shifter cell as well as an isolation cell. In addition,
corresponding level shifter and isolation rules are defined.

Related Topics

Identification of Design Objects

Power Intent Import

Power View

Registering Supply Set and Power Domain

Power Intent Import

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Creation of Power Domains

While extracting power intent, Power Manager automatically identifies the power nets and
ground nets in the design as described below. Further, for each power net, it finds the ground
net associated with it and for each unique pair of power net and ground net, creates a power
domain.

Identifying Switchable and Non-Switchable Power Nets and Ground Nets

■ A net is identified as a non-switchable power net if either of the following conditions are
met:
❑ The sigType property of the net is power
❑ The net name is registered as a power net
❑ The net is not an output of a switch cell and cannot be hierarchically traced to an
output of a switch cell.
■ A net is identified as a switchable power net if either of the following conditions are met:
❑ The net is an output of a head-switch cell
❑ The net can be hierarchically traced to an output of a head-switch cell
■ A net is identified as a non-switchable ground net if:
❑ The sigType of the net is ground.
❑ The net name is registered as a ground net.
❑ The net is not an output of a switch cell and cannot be hierarchically traced to an
output of a switch cell.
■ A net is identified as a switchable ground net if either of the following conditions are met:
❑ The net is an output of a foot-switch cell
❑ The net can be hierarchically traced to an output of a foot-switch cell
Note: If you have not registered any names for power nets and none of the nets in the design
have their signal type set to power, then Power Manager does not extract any power domains.

After identifying the power nets and ground nets, the unique power net/ground net pairs
(Supply sets) are identified. For this, the tool traces the paths from a power net to a ground
net. The tool also considers the power net/ground net pairs registered in the setup.

Supply sets can be defined in the setup for the following scenarios.

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■ The primary supply set for the power domains mentioned in the setup.
■ The power and ground nets that cannot be paired by traversing the design hierarchy or
parsing the Liberty in case of a Liberty cell.

Supply set identification can be done explicitly in a setup template or by automatic

identification.

If you want to partition the design for assigning a particular instance to some power domain,
provide the list of domain, instances, and primary supply set.

If power domains and supply set information is provided in the setup, the following is the
sequence of tasks being done:
■ create_power_domain commands are created in the exported 1801 file based on the
number of power domains.
■ Primary supply set are referred from the setup.
■ Extra supplies that need not to be a part of setup are identified by the tool.
■ connect_supply_net command is generated for supply nets that are a part of extra
supplies.
■ For any other instance that is not a part of any power domain remains in the default
domain.
■ If there is no power domain assignment, a single power domain is created and all the
instances are connected by using connect_supply_net.

The following examples show how power domains are created:

Example 1:

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Consider the following design that does not have the user-defined supply sets and power
domains specified in the setup:

In this case, the tool traverses though the design and creates the following power domains:
■ SS__VDD1__GND1
■ SS__VDD2__GND2
■ SS__VDD3__GND3

Example 2:

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Now, consider the following design that contains a head-switch.

In this case, the tool creates one default power domain and two supply sets:
■ pd__VDD__VSS
■ SS_VDD_VSS
■ SS_NET1_VSS

Example 3:

If a primitive instance has one netSet property each for a power and ground supply, it is added
to the power domain created for that power and ground supply pair even if the instance does
not have any power/ground pins in the symbol/schematic view. If a power domain does not
exist for that power and ground supply pair, a new power domain is created and the primitive
instance is added to it. However, if the primitive instance has more than one netSet property
for power or ground, it does not contribute towards the creation of a power domain and a
warning message is displayed in the power intent extraction log.

Default Power Domain

If the create_power_domain command has the -include_scope or -elements {.}
switch, it is considered as the default domain. When no such default domain is found, any
create_power_domain command that does not have the -elements switch is considered
as the default domain. However, multiple create_power_domain commands cause the
1801 import to fail with an appropriate error message.

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Related Topics

Export Flow

Exporting 1801 Design Model

Exporting 1801 Power Model

Exporting Liberty Power Model

Special Isolation Cells in Liberty Power Model Export

Registering Supply Set and Power Domain

Power View
Power view is an OpenAccess view generated corresponding to each cell that is being
extracted to export the power intent. The power view stores the following information:
■ Set up information of the cellview prior to extraction
■ Extracted and/or imported power intent information
■ The design information derived from the schematic design (EMH and native OA objects)
■ Internal data structures

The power view is co-managed with the schematic view of the design. The view is
automatically updated upon extraction when the setup or design changes. There is no need
to explicitly load the setup for each successive extraction run until the power view exists for a
cell and there is no change in the setup information of the design. The power view by default
gets created in the design library within the design cell, adjacent to the design view/
schematic. If the parent library is non-editable, lpDBGlobalSearchLibs and
lpDBGlobalSearchViews can be used to save the power view in an editable user-defined
library. The power view is also automatically purged when the associated schematic cellview
is purged for reasons, such as on closing the schematic or calling the dbPurge/dbClose
SKILL function.

Related Topics

lpDBGlobalSearchLibs

lpDBGlobalSearchViews

Export Flow

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Extracting the Power Intent from a Design

Creation of Power Domains

Exporting 1801 Design Model

Exporting 1801 Power Model

Exporting Liberty Power Model

Special Isolation Cells in Liberty Power Model Export

Exporting 1801 Design Model

You can export the power intent specified for your design to a 1801 design model file. To
export power intent from a design:
1. Open the design in Power Manager.
2. Prepare the setup for automatic extraction. For more details about how to prepare the
setup, refer to Setup Preparation for Automatic Extraction of Power Intent. Load the setup
from Power Manager toolbar/menu.
3. Click Power Manager – Extract from Design.
4. Click Power Manager – Export from Design.
The Export Power Intent form appears. The library, cell, and view names of the cell that
is currently open are displayed by default in the form.

5. In the 1801 File field, specify the path and the name of file for exporting the power intent.

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6. Select the Overwrite Existing File check box to overwrite the file.
7. Click OK.

The vpmExportPowerIntent SKILL function has been provided to export the 1801 Design
Model information for a cellview.

In 1801 design model, the power intent of the sub-blocks is exported along with power intent
of the top design. For a pure schematic-based design, the Power Manager always extracts a
flat 1801.

An example of an exported 1801 design model file is shown below:

set_design_attributes -attribute top_ports_have_anon_supply 0
##### Supply Ports (Section 1)###################################################
create_supply_port VDD -direction inout
create_supply_port VDDA -direction inout
create_supply_port VDDSW -direction inout
create_supply_port VSS -direction inout

##### Supply Nets (Section 2)####################################################

create_supply_net VDD -resolve parallel
create_supply_net VDDA -resolve parallel
create_supply_net VDDSW -resolve parallel
create_supply_net VSS -resolve parallel

##### Supply Net Connections (Section 3)##########################################

connect_supply_net VDD -ports { VDD }
connect_supply_net VDDA -ports { VDDA }
connect_supply_net VDDSW -ports { I3/I0/VDD }
connect_supply_net VSS -ports { VSS }

##### Supply Sets (Section 4)####################################################

create_supply_set SS_VDDA_VSS -function { power VDDA } -function { ground VSS }
create_supply_set SS_VDDSW_VSS -function { power VDDSW } -function { ground VSS }
create_supply_set SS_VDD_VSS -function { power VDD } -function { ground VSS }

##### Power Domains (Section 5)##################################################

create_power_domain PD_TOP -include_scope -supply { primary SS_VDD_VSS } \
-supply { extra_supplies_1 SS_VDDSW_VSS }
create_power_domain PD_LS -elements { I0 } -supply { primary SS_VDDA_VSS } \
-supply { extra_supplies_1 SS_VDD_VSS }

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###### Standard Cells (Section 6)#############################################

connect_supply_net VDD -ports { I0/I20/I0/VDD }
connect_supply_net VDDSW -ports { I3/I1/VDD }
###### Special Cells ###################################
connect_supply_net VDD -ports { I0/I22/ExtVDD }
connect_supply_net VDDSW -ports { I3/I0/VDD }
###### Macro Cells ####################################
connect_supply_net VDD -ports { I2/VDD_ext }
connect_supply_net VSS -ports { I2/VSS_ext }

##### Port Attributes (Section 7)############################################

set_port_attributes -port en_iso -receiver_supply SS_VDD_VSS
set_port_attributes -port in1 -receiver_supply SS_VDD_VSS
######### Isolation Rules #####################################
set_isolation PD_TOP_ISO_0 -domain PD_TOP -elements { out_iso } -
isolation_supply_set SS_VDD_VSS -isolation_signal en_iso -isolation_sense high -
location self -clamp_value 0

######### Level Shifter Rules (Section 8)############

set_level_shifter PD_LS_ls_0 -domain PD_LS -elements {I0/out_ls } -
input_supply_set SS_VDDA_VSS \ -output_supply_set SS_VDD_VSS -location self -rule
both
##### Switch Rules ##################
create_power_switch I3_I0 -output_supply_port { VDD VDDSW } -input_supply_port {
ExtVDD VDD } \
-control_port { PSO psw_en } -on_state { on ExtVDD {!PSO} } -off_state { off PSO }
-domain PD_TOP

##### Supply Port States (Section 9) ###########################################

add_port_state I3/I0/VDD -state { V110 1.1 } -state { OFF off }
add_port_state VDD -state { V110 1.1 } -state { OFF off }
add_port_state VDDA -state { V130 1.3 } -state { OFF off }
add_port_state VSS -state { OFF 0 }

##### Power State Table (Section 10) ###########################################

create_pst top_pst -supplies [list I3/I0/VDD VDD VDDA VSS ]
add_pst_state State_1 -pst top_pst -state { V110 V110 V130 OFF }
add_pst_state State_2 -pst top_pst -state { OFF V110 V130 OFF }
add_pst_state State_3 -pst top_pst -state { OFF OFF OFF OFF }

The following points explain the different sections of the exported 1801 design model:
■ Section1: The create_supply_port command defines a supply port in the scope of
the power domain. These are created for all the top-level supply ports identified.

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■ Section2: The create_supply_net command creates a supply net in the scope of

the power domain. These are created for all the top-level supply nets identified.
■ Section3: The connect_supply_net command connects a supply net to the
specified ports. These commands are for handling the interface connectivity. The
commands are for both the top level as well as for hierarchical interface connectivity. This
resolves the connectivity of PG nets from down the hierarchy to the top level PG nets for
different blocks. Section6 also performs the same task.
■ Section4: The create_supply_set command creates the supply set name within the
current scope. This defines the primary and extra supply sets or available supplies
associated with the different power domains.
■ Section5: The create_power_domain command defines a power domain and the set
of instances that are in the extent of the power domain. It may also specify whether the
power domain can be partitioned further by the subsequent commands.
■ Section6: The connect_supply_net command defines the standard, special, and
macro cells.
■ Section7: The set_port_attributes command specifies the information
associated with data ports of instances. The attributes of this command identify a port's
related supplies (driver or receiver) and the boundary of a power domain.
■ Section8: These commands define the low power strategy (Level Shifters, Isolation, and
Power Switch) adopted for the ports on the interface of a power domain. This is required
to correct for voltage differences between the driving and receiving supplies of a port or
to ensure correct electrical and logical functionality when domains are in different power
states.
The correct strategy adopted is also based on the cell type identified while reading the
schematic based on their Liberty model or special cell definition file registered in the
setup.
■ Section9: The add_port_state command adds the state information to a supply port.
If the voltage values are specified, the supply net state is FULL_ON and the voltage value
is the single nominal value or within the range of min to max. If the supply net state is off,
the voltage value is OFF.
■ Section10: The add_pst_state command defines the name for a specific state of the
supply nets defined for the power state table (PST). This command defines system
power states of the IP.

The output supply port that is the output of a power switch, output of a LDO, or voltage
regulator can be identified by explicit user registration in the setup. In addition, the output
supply port can be identified from the Liberty model or the 1801 file, if available for the block.

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The commands associated with the output port would appear in Section1, Section2,
Section9, and Section10.

A hierarchical internal net is not generated for commands related to Section1, Section2,
Section3, and Section6. Any block with internal net (not available at the top) should be
extracted and 1801 generated. Then, use the 1801 binding for the top block.

For more information on the 1801 commands, refer to IEEE Standard for Design and
Verification of Low-Power Integrated Circuits.

Related Topics

vpmExportPowerIntent

Registering Supply Set and Power Domain

Registering Device and Cell

Extracting the Power Intent from a Design

Creation of Power Domains

Exporting 1801 Power Model

Exporting Liberty Power Model

Special Isolation Cells in Liberty Power Model Export

Exporting 1801 Power Model

You can export the power intent specified for the design to a 1801 power model file. To export
power intent from a design,
1. Open the cellview in Power Manager.
2. Prepare the setup for automatic extraction.
3. Load the setup from the Power Manager toolbar/menu.
4. On the Power Manager toolbar/menu, click Extract from Design.
5. Use vpmExportPowerModel to export the 1801 Power Model information for a
cellview.

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In the 1801 power model, the power intent of the top design is only exported as the power
intent information, with no sub-block power intent details. A power model is used to define the
power intent of a hard IP cell. The command pair begin_power_model and
end_power_model create a definitive boundary for the power intent for the hard IP cell. A
model name is created, and it is targeted for a specific macro cell.

The interfaces of the hard IP power model include the top-level power domain for this IP cell
and all the supplies of IP. This power domain is also used to specify the system power states
at the hard IP level.

An example of an exported 1801 power model file is shown below:

upf_version 2.1
##### Power Model Initialization (Section 1)##################################
begin_power_model top_model -for top
##### Supply Ports (Section 2)###################################################
create_supply_port VDD! -direction inout
create_supply_port VDDA! -direction inout
create_supply_port VSS! -direction inout
##### Supply Nets (Section 3)####################################################
create_supply_net VDD -resolve parallel
create_supply_net VDD1 -resolve parallel
create_supply_net VDDA -resolve parallel
create_supply_net VDDSW -resolve parallel
create_supply_net VSS -resolve parallel
create_supply_net VSS1 -resolve parallel
connect_supply_net VDD -ports { VDD }
connect_supply_net VDDA -ports { VDDA }
connect_supply_net VDDSW -ports { I3/I0/VDD }
connect_supply_net VSS -ports { VSS }
##### Supply Sets (Section 4)####################################################
create_supply_set SS_VDDA_VSS -function { power VDDA } -function { ground VSS }
create_supply_set SS_VDDSW_VSS -function { power VDDSW } -function { ground VSS
}
create_supply_set SS_VDD_VSS -function { power VDD } -function { ground VSS }
##### Power Domains (Section 5)#################################################
create_power_domain PD_MACRO -elements {.} \
-supply { primary SS_VDD_VSS } \
-supply { extra_supplies_0 SS_VDD+VDDSW_VSS } \
-supply { extra_supplies_1 SS_VDDA_VSS } \
-supply { extra_supplies_2 SS_VDDSW_VSS }
##### Port Attributes (Section 6)############################################
set_port_attributes -port en_iso -receiver_supply SS_VDD_VSS

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set_port_attributes -port in1 -receiver_supply SS_VDD_VSS

set_port_attributes -port in2 -receiver_supply SS_VDD_VSS
set_port_attributes -port in3 -receiver_supply SS_VDD_VSS
set_port_attributes -port in4 -receiver_supply SS_VDD+VDDSW_VSS
set_port_attributes -port out1 -driver_supply SS_VDD_VSS
set_port_attributes -port out2 -driver_supply SS_VDD_VSS
set_port_attributes -port out3 -driver_supply SS_VDD_VSS
set_port_attributes -port out_iso -driver_supply SS_VDD_VSS
set_port_attributes -port out_psw -driver_supply SS_VDD_VSS
set_port_attributes -port outvdd -driver_supply SS_VDD_VSS
set_port_attributes -port psw_en -receiver_supply SS_VDD_VSS

##### Power States (Section 7)###########################################

add_power_state SS_VDDA_VSS -supply \
-state { ON -simstate NORMAL \
-supply_expr { power == { FULL_ON 1.300000 } &&
ground == { FULL_ON 0.000000 } }} \
-state { OFF -simstate CORRUPT \
-supply_expr { power == OFF && ground == OFF }}

add_power_state SS_VDDSW_VSS -supply \

-state { ON -simstate NORMAL \
-supply_expr { power == { FULL_ON 1.100000 } &&
ground == { FULL_ON 0.000000 } }} \
-state { OFF -simstate CORRUPT \
-supply_expr { power == OFF && ground == OFF }}

add_power_state SS_VDD_VSS -supply \

-state { ON -simstate NORMAL \
-supply_expr { power == { FULL_ON 1.100000 } &&
ground == { FULL_ON 0.000000 } }} \
-state { OFF -simstate CORRUPT \
-supply_expr { power == OFF && ground == OFF }}

add_power_state PD_MACRO -domain \

-state { S0 -logic_expr { SS_VDD_VSS == ON && SS_VDDSW_VSS
== ON && SS_VDDA_VSS == ON }} \
-state { S1 -logic_expr { SS_VDD_VSS == ON && SS_VDDSW_VSS
== ON && SS_VDDA_VSS == OFF }} \
-state { S2 -logic_expr { SS_VDD_VSS == ON && SS_VDDSW_VSS
== OFF && SS_VDDA_VSS == ON }} \
-state { S3 -logic_expr { SS_VDD_VSS == ON && SS_VDDSW_VSS
== OFF && SS_VDDA_VSS == OFF }}

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##### Power Model End (Section 8)######################################

end_power_model

The following points explain the different sections of the exported 1801 power model:
■ Section1: The begin_power_model command defines the boundary condition for the
power model. This marks the beginning of the power model.
■ Section2: The create_supply_port command defines a supply port in the scope of
the power domain. These are created for all the top-level supply ports identified.
■ Section3: The create_supply_net command creates a supply net in the scope of
the power domain. These are created for all the top-level supply nets identified.
■ Section4: The create_supply_set command creates the supply set name within the
current scope. This section associates the interface supplies to the boundary supply
ports or internally generated supplies.
■ Section5: The create_power_domain command defines a power domain and the set
of instances that are in the extent of the power domain. It may also specify whether the
power domain can be partitioned further by subsequent commands.
■ Section6: The set_port_attributes command specifies the information
associated with data ports of instances. The attributes of this command identify a port’s
related supplies (driver or receiver) and define the boundary of a power domain.
■ Section7: The add_power_state command adds the state information to a supply
port. If the voltage values are specified, the supply net state is FULL_ON and the voltage
value is the single nominal value or within the range of min to max. If the supply net state
is off, the voltage value is OFF.
■ Section8: The end_power_model command defines the boundary condition for the
power model. The power model ends here.

Related Topics

Setup for Automatic Extraction of Power Intent

vpmExportPowerModel

Registering Name-Based Supply Nets

Extracting the Power Intent from a Design

Creation of Power Domains

Exporting 1801 Design Model

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Exporting Liberty Power Model

Special Isolation Cells in Liberty Power Model Export

Exporting Liberty Power Model

You can export the power intent specified for the design as a Liberty power model template
file with the non-characterized attributes for pg_pin and pin groups of a library or cell, such
as related_power_pin, related_ground_pin, pg_type, direction,
is_isolated, isolation_enable_condition, switch_pin, pg_function,
switch_function, and so on.

To export power intent from a design:

1. Open the cellview in the Power Manager.
2. Prepare the setup for automatic extraction. For more details about how to prepare the
setup, refer to Setup for Automatic Extraction of Power Intent.
3. Load the setup from the Power Manager toolbar/menu.
4. Click Power Manager – Extract from Design.
5. Click Power Manager – Export Liberty Model.
The Export Liberty Model Form form appears. The library, cell, and view names of the
cellview that is currently open are displayed by default in the form.

6. In the Liberty File field, specify the path and the name of the file for exporting the Liberty
power model.

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7. Select the Overwrite Existing File check box to overwrite the file.
8. Click OK.
Note: vpmExportDotLib has been provided to export the Liberty power model information
for a cellview.

Liberty power model is the power intent at the macro model level, for complex design blocks.
This can also be referred as a black box model of the power characteristics of a complex
design block or a hard IP. Power Manager helps in automatically extracting the power intent
from the design schematic and exporting the low power attributes to a Liberty Power Model
template. It can be further integrated while extracting the power intent of the top design. The
Exported Liberty Power Model, having the PG attributes can be stitched to the baseline
Liberty model from an IP characterization tool to generate a complete liberty file for schematic
IP ready for verification and implementation.

While creating the Liberty power model for a macro cell, the following tasks are performed:
■ Identifies power nets and ground nets and their equivalent power or ground nets.
■ Identifies switchable or non-switchable power nets or ground nets.
■ Identifies boundary ports for the macro.
■ Relates the boundary ports to the related power and ground supply pairs by tracing.
■ Identifies low power special cells and the boundary ports associated with boundary ports
to print the relevant attributes.
■ Backtraces the data path from the control pins of the low power special cells to the macro
or design ports for generating enable or shutoff conditions.
The Liberty power model also enables creation of analog ports. Analog ports are a list of
ports of a macro cell or a design that either drive the analog circuits or are driven by them. In
a Liberty power model, a port is considered an analog port in the following cases:
■ There is a user override, by defining portAttribute, in the setup that declares the pin
as analog.
■ The pin has a related power or a related ground found by tracing the power and ground
path.
■ The pin is not a driver or load of one or more instance pins that produce digital output,
such as (Liberty or user-defined) standard cell input/output pin, which has a related
power and a related ground attribute.
■ The pin is not feedthrough and unconnected.
Ports identified as analog ports have the is_analog attribute associated with them.

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An example of an exported Liberty Power Model file is shown below:

####################################################################
/*
Liberty Power Model Template (Section 1)
=============================
library : upf_export;
cell : top;
Program Version : sub-version IC6.1.8-64b.main.174 ;
*/
##################(Section 2)###################################################
library(upf_export) {

date : "Wed Mar 6 18:02:38 2019 ";

comment : "Generated by Virtuoso Power Manager";
voltage_unit : "1V";

voltage_map( VDD , 1.100000);

voltage_map( VDDA , 1.300000);
voltage_map( VDDSW , 1.100000);
voltage_map( VSS , 0.000000);
#####################(Section 3)################################################
cell(top) {
switch_cell_type : fine_grain;
is_macro_cell : true;
pg_pin(VDD) {
voltage_name : VDD;
pg_type : primary_power;
direction : inout;
}
pg_pin(VDDA) {
voltage_name : VDDA;
pg_type : primary_power;
direction : inout;
}
pg_pin(VSS) {
voltage_name : VSS;
pg_type : primary_ground;
direction : inout;
}
pg_pin(VDDSW) {

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switch_function : "psw_en";
voltage_name : VDDSW;
pg_function : VDD;
pg_type : internal_power;
direction : internal;
}
######################################################
pin(en_iso) {
related_ground_pin : VSS;
related_power_pin : VDD;
direction : input;
}
pin(in1) {
related_ground_pin : VSS;
related_power_pin : VDD;
direction : input;
}
pin(out1) {
power_down_function : "!VDD + VSS";
related_ground_pin : VSS;
related_power_pin : VDD;
direction : output;
}
pin(out_iso) {
is_isolated : true;
power_down_function : "!VDD + VSS";
related_ground_pin : VSS;
related_power_pin : VDD;
isolation_enable_condition : "en_iso";
direction : output;
}
pin(out_psw) {
power_down_function : "!VDD + VSS";
related_ground_pin : VSS;
related_power_pin : VDD;
direction : output;
}
pin(outvdd) {
power_down_function : "!VDD + VSS";
related_ground_pin : VSS;
related_power_pin : VDD;

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direction : output;
}
pin(psw_en) {
antenna_diode_related_ground_pins : "VSS";
switch_pin : true;
related_ground_pin : VSS;
related_power_pin : VDD;
direction : input;
}
} /* end of cell top */

} /* end of library upf_export */

The following points explain the different sections of the exported Liberty power model:
■ Section1: This section includes the basic design information in terms of the library and
cell names for which the Liberty power model has been extracted and the software
version used for the same.
■ Section2: This section represents the library description. These are library level
features and attributes.
The library level voltage_map attribute associates the voltage name with the relative
voltage values. These specified voltage names are referenced by the pg_pin groups
defined at the cellview level. The voltage map can be a combination of both the primary
power and ground supplies and bias power and ground supplies. Voltage values in the
Liberty power model should follow the voltage values of the top-level design power intent
where model is integrated unless a corresponding error is flagged at the power intent
verification stage by CLP.
■ Section3: This section represents the cell group information and the related attributes.
The cell group statement gives the name of the cell being described. It appears at the
library group level. The Liberty power model exports the power intent of the design,
therefore, the information in this group comprises of:
❑ is_macro_cell: The attribute identifies whether a cell is a macro cell.
❑ switch_cell_type: This attribute supports macro cells with internal switches
present to generate internal power. The valid values for this attribute are
coarse_grain and fine_grain.
❑ Pin level attributes: The different pin level attributes, such as pg_pin, pg_type,
power_down_function, related_power_pin, related_ground_pin,
input_signal_level and output_signal_level describe the specific
information extracted from the design schematic by Power Manager extractor for all

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the boundary ports (PG and data). The state of these attributes is dependent on the
setup registration for PG nets, connectivity, and design topology.
❑ Macro Cell Modeling: The attributes is_isolated,
isolation_enable_condition, switch_pin, switch_function,
pg_function, and pg_types are required for macro cell modeling. These are
required to model the cells, which use low power special cells, such as isolation cells
and power switch cells connected to boundary ports.

For more information on the 1801 commands, refer to Liberty User Guides and Reference
Manual Suite (Version 2017.06).

Related Topics

Setup for Automatic Extraction of Power Intent

vpmExportDotLib

Extracting the Power Intent from a Design

Creation of Power Domains

Exporting 1801 Design Model

Exporting 1801 Power Model

Special Isolation Cells in Liberty Power Model Export

Ports connected to NOR or NAND type isolations cells must be handled carefully in the Libert
power model export flow to ensure there are enough attributes to indicate related power or
ground for actual data receivers in a megacell or to indicate that enable pins cannot be off in
the partial power down state.

The following three scenarios are addressed in the tool while handling ports connected to
isolation cells:
■ Input ports connected to NOR/NAND isolation cell data pins
❑ No changes are made to the related_power_pin or related_ground_pin
attribute values.

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❑ The alive_during_power_up attribute is added if a NOR/NAND isolation cell

has inverted input. This ensures that the input cannot be floating when ports related
power and ground pins are on.
❑ The isolation_sink_power_pin and isolation_sink_ground_pin
attributes are added to indicate related power/ground pins for a data receiver inside
a megacell.
■ Input ports connected to NOR/NAND isolation cell enable pins
❑ When the value of updateRelatedSuppliesForNorNandIsoPorts = t.
❍ If the sink of the isolation cell is some logic visible inside a macro, the
related_power_pin or related_ground_pin values are updated based
on the supply powering the logic connected to the isolation output. The
alive_during_partial_power_down or permit_power_down attributes
are not added.
❍ If the immediate fanout of an isolation cell is a top-level port, there is no change
made to the related_power_pin / related_ground_pin attribute values.
The alive_during_partial_power_down attribute is added only if the
isolation cell output is not inverted to indicate that the enable driver supply must
be on when the cell is in the partial power down state.The
permit_power_down attribute is added only if the isolation cell output is not
inverted. This attribute is added on the power pin for a NOR isolation cell and
on the ground pin for a NAND isolation cell to indicate that the related supply
can be off while in isolation mode.
❑ When the value of updateRelatedSuppliesForNorNandIsoPorts = nil
(default).
❍ No changes are done in the related_power_pin or related_ground_pin
attribute values. The alive_during_partial_power_down attribute is
added only if the isolation cell output is not inverted to indicate that the enable
driver supply must be ON when the cell is in the partial power down state. The
permit_power_down attribute is added to the related power or ground
pg_pin only if the isolation cell output is not inverted.
■ Output ports connected to NOR/NAND isolation cell output pin
❑ When the value of updateRelatedSuppliesForNorNandIsoPorts = t.
❍ If the isolation enable immediate driver is not a macro input port, the related
power pin or related ground pin values are updated based on the supply of the
driver of the isolation cell enable pin.

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❍ The isolation_data_power_pin and isolation_data_ground_pin

attributes are added to indicate related power/ground for a data driver inside a
megacell.
❍ If the isolation enable immediate driver is a macro input port, no changes are
required in the related_power_pin or related_ground_pin attribute
values. The alive_during_partial_power_down attribute is added to the
output pin if the NOR/NAND isolation cell is without an inverted output. The
permit_power_down attribute is added on the power pg pin of a NOR
isolation cell or ground pg pin of a NAND isolation cell. The
isolation_data_power_pin and isolation_data_ground_pin
attributes are added to indicate the supply of the isolation cell data pin. A
warning message is issued that the isolation enable signal is not buffered and
is a direct connection to a macro port.
❑ When the value of updateRelatedSuppliesForNorNandIsoPorts = nil
(default).
❍ No changes are made to the related_power_pin or
related_ground_pin attribute values. The
alive_during_partial_power_down attribute is added only if the NOR/
NAND isolation cell is without an inverted output. The permit_power_down
attribute is added only if the isolation cell is without an inverted output. This
attribute is added on the power pg pin of a NOR isolation cell or ground pg pin
of a NAND isolation cell.
❍ The isolation_data_power_pin and isolation_data_ground_pin
attributes are added to indicate related power/ground for a data driver inside a
megacell.
❍ If the isolation enable immediate driver is not a macro input port, the
power_down_function attribute is updated to include clamp driver supplies
and the isolation_enable_condition attribute.
❍ If the isolation enable immediate driver is a macro input port, the
power_down_function attribute is updated to include a macro input port
connected enable pin. The alive_during_partial_power_down is set
true on the macro port connected to an enable pin. A warning message is
issued that the isolation enable signal is not buffered and is a direct connection
to a macro port.

Related Topics

printAliveAndPermitAttributesinDotlib

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updateRelatedSuppliesForNorNandIsoPorts

Extracting the Power Intent from a Design

Creation of Power Domains

Exporting 1801 Design Model

Exporting Liberty Power Model

Export of Switch Function and Isolation Enable Condition

Expressions
In a Liberty Power Model export, it is important to export the derivation or knowledge to
interpret switch_function and isolation_enable_condition expressions to ensure
that you are able to perform the following tasks:
■ Correlate the generated expressions with a schematic.
■ Establish the accuracy of the generated expressions and design intent.

You can register the names of virtual supply nets that need the switch_function
derivation by using the following option in a setup file.

virtualSuppliesForSwitchFunctionDerivation "VVDD VVDD_CPU VVDD_LDO"

You can register the names of the data port names that need the
isolation_enable_condition derivation by using the following option in a setup file.

signalPortsForIsoEnableConditionDerivation "OUT OUT2 IN1"

Regular expressions for virtual supply and port names is supported. The step-by-step
derivation of switch_functions for registered virtual supply nets and
isolation_enable_conditions for registered data ports appear in the CIW and in the
extractor log file. However, this information is shown only if the pg_pin or data pin is included
in a Liberty model.

Alternatively, you can use the environment variables to export the derivations.

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Related Topics

exportSwitchFunctionDerivationForAllUsedVirtualSupplies

exportIsoEnableConditionDerivationForAllTopIsolatedPorts

signalPortsForIsoEnableConditionDerivation

virtualSuppliesForSwitchFunctionDerivation

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7
Verifying Power Intent of a Design

After completing the power intent specification for your design, you need to verify the
correctness of the power intent as per the design. When you verify the design by using Power
Manager, the tool automatically runs Conformal Low Power (CLP) that reads the power intent
and generates a report with appropriate messages.

Related Topics

Preparing and Running CLP

Checking Design Hierarchy

Power Intent Verification Requirements

Preparing and Running CLP

Ensure that the following setup is done before you start verification using CLP:
■ You have set the license for the Mixed-signal Option to Conformal Low Power (95127).
■ You have set the path to the binary file of CLP, lec, in the UNIX path.
■ You have checked the design hierarchy and ensured that there are no errors in the
design.
■ You have checked the power intent of the design to ensure its completeness.
■ You have defined the reference Verilog and Liberty files by including read library
statements in the dofile (a file with set of commands required as inputs for power intent
verification). This ensures that Conformal Low Power does not report the missing
reference libraries. For more information on Conformal Low Power, refer to Conformal
Low Power User Guide.

To verify the power intent:

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1. Click Power Manager – Run CLP if you already have the required dofiles.

2. [Optional] Otherwise, before running the CLP, use the Prepare CLP form to generate the
1801 file, Verilog netlist, and CLP dofile at the specified path.

Note: The 1801 File and Liberty Files field do not require explicit user inputs, if a setup
template file already exists and is loaded for the cellview to extract and verify the power
intent.
The netlist generated by the Prepare CLP form is different from the general netlist
created by NC-Verilog. This netlist includes a list of Verilog stub views for the macro
models, single supply analog modules along with their power and ground pins, and the
blocks that are binded to the existing power intent (1801). This makes the netlist more
compatible with CLP. The log file generated, after the preparations for the CLP run are
over, displays the results along with the following details:
❑ Date and time

August 2024 178 Product Version IC23.1

❑ Design details
❑ Form field values
❑ Netlist/1801/dofile file paths
❑ Netlist error/warnings
❑ The ‘si.env’ file used for netlisting
❑ CLP log file path

August 2024 179 Product Version IC23.1

❑ The CLP Run command for command line

3. Click Run CLP to start CLP and use the files created during CLP preparation, for power
verification. The CLP run initiates when you click OK.

This two-step process, which includes preparing for CLP and running CLP, lets you check the
input files and resolve issues, if any, before proceeding for the CLP run. Subsequently, you
can run CLP from Power Manager by specifying a run directory and a CLP dofile.

August 2024 180 Product Version IC23.1

Alternatively, you can run CLP from the command line once the input files are generated
using Power Manager.

After the verification is complete, the generated report is displayed in a separate log window
as shown below.

Related Topics

Power Intent Check

Prepare CLP Form

Verifying Power Intent of a Design

August 2024 183 Product Version IC23.1

If you explicitly specify a netlist control file during preparation for running CLP, set the
following flags appropriately:
❑ To ensure that the power and ground information is correctly captured in the netlist.
This is required for correct power intent verification of the design.
❍ hnlInhConnUseDefSigName='t
❍ vlogifDeclareGlobalNetLocal='t
❍ hnlPrintInhConAtTop='t
❍ hnlHonorInhConnEscapeName='t
❍ hnlVerilogDeclareScalarSig='t
❍ simVerilogEnableEscapeNameMapping= 't
❍ hnlMapNetInName
❍ hnlMapTermInName
❑ To ensure that redundant information does not show at the module or instance level
in the netlist. For example, information of primitive devices (mos/resistor/capacitors
and diodes).
hnlUserIgnoreCVList
❑ For creating the stub view (no module definition) for macro Liberty blocks, just an
instance line with power/ground nets that is identified by traversing the schematic.
hnlUserStubCVList

Related Topics

Virtuoso NC Verilog Environment User Guide

Open Simulation System Reference

Verifying Power Intent of a Design

Checking Design Hierarchy

August 2024 184 Product Version IC23.1

A
Virtuoso Power Manager Environment
Variables

The topic provides information on the names, descriptions, and graphical user interface
equivalents for the Virtuoso Power Manager environment variables.

August 2024 185 Product Version IC23.1

addNotInGndPgFunction
lp addNotInGndPgFunction boolean { t | nil }

Description

Controls printing pg_function for ground switchable supplies. The pg_function value is
printed as VSS if the variable is set to nil. The default value is nil.

GUI Equivalent

None

Example
envGetVal("lp" "addNotInGndPgFunction")
envSetVal("lp" "addNotInGndPgFunction" 'boolean nil)

Related Topics

Handling of Low Power Special Cells

August 2024 186 Product Version IC23.1

allowConstantExpressions
lp allowConstantExpressions boolean { t | nil }

Description

Prints original expressions instead of constant-value expressions when set to nil. During
boolean optimization, if a function expression evaluates to true(1) or false(0), the
corresponding expression values printed by default in a dotlib or 1801 file are 1 or 0
respectively. However, if constant-value expressions are not required, you can print original
expressions.

GUI Equivalent

None

Example
envGetVal("lp" "allowConstantExpressions")
envSetVal( "lp" "allowConstantExpressions" 'boolean nil)

Related Topics

Exporting 1801 Design Model

Exporting 1801 Power Model

August 2024 187 Product Version IC23.1

allowDomainWithoutElements
lp allowDomainWithoutElements boolean { t | nil }

Description

Controls the creation of power domains exported in the 1801 file based on their constituent
elements.

When allowDomainWithoutElements is t, only power domains without elements are

exported in the 1801 file. If this variable is set to the default value nil, the power domains
that have instances/elements are exported in the 1801 file and the domains without any
elements are not exported in the 1801 file.

Default scenario
create_power_domain pd__vddB_init__vssB \
-elements { i_block } \
-supply { primary ss__vddB_init__vssB } \
-supply { extra_supplies "" }

create_power_domain pd__vddA__vssA \
-include_scope \
-supply { primary ss__vddA__vssA } \
-supply { extra_supplies "" }

Non Default scenario

create_power_domain pd__vddB_init__vssB \
-elements { i_block } \
-supply { primary ss__vddB_init__vssB } \
-supply { extra_supplies "" }

create_power_domain pd__vddB__vssB \
-supply { primary ss__vddB__vssB } \
-supply { extra_supplies "" }

create_power_domain pd__vddA__vssB \
-supply { primary ss__vddA__vssB } \
-supply { extra_supplies "" }

create_power_domain pd__vddA__vssA \
-elements {.} \

August 2024 188 Product Version IC23.1

-supply { primary ssvddAvssA } \

Description

Specifies whether to autocorrect the definition of the non-dedicated transistor switch

instance. The default value is t.

The valid values are t and nil.

■ t: Autocorrects the definition of the non-dedicated transistor switch instance as the
following:
❑ Power Manager autocorrects to gate terminal if the -stage_1_enable command
option is not a gate terminal.
❑ If the -power (Power) and -power_switchable (PSW) command options in
header switch are not source and drain terminals or drain and source terminals
or
❑ the -ground (Ground) and -ground_switchable (GSW) command options in
footer switch are not the source and drain terminals or drain and source terminals,
the Power Manager autocorrects as the following:

Power/Ground PSW/GSW Auto Correction By Power Manager

Source terminal of Drain No auto correction required
transistor terminal of
transistor
Drain terminal of Source No auto correction required
transistor terminal of
transistor
Source terminal of Source Changes the power_switchable argument in
transistor terminal of header transistor switch definition/
transistor ground_switchable argument in footer
transistor switch definition to drain terminal of
transistor and issue a warning message.
Drain terminal of Drain Changes power argument in header transistor
transistor terminal of switch definition/ground argument in footer
transistor transistor switch definition to source terminal of
transistor and issues a warning message.

August 2024 195 Product Version IC23.1

Source terminal of Gate Changes the power_switchable argument in

transistor terminal of header transistor switch definition/
transistor/ ground_switchable argument in footer
Bulk terminal transistor switch definition to drain terminal of
of transistor transistor and issues a warning message.
Drain terminal of Gate Changes the power_switchable argument in
transistor terminal of header transistor switch definition/
transistor/ ground_switchable argument in footer
Bulk terminal transistor switch definition to source terminal of
of transistor transistor and issues a warning message.
Gate terminal of Drain Changes power argument in header transistor
transistor/Bulk terminal of switch definition/ground argument in footer
terminal of transistor transistor switch definition to source terminal of
transistor transistor and issues a warning message.
Gate terminal of Source Changes power argument in header transistor
transistor/Bulk terminal of switch definition/ground argument in footer
terminal of transistor transistor switch definition to drain terminal of
transistor transistor and issues a warning message.

■ nil: Does not autocorrect the definition of the non-dedicated transistor switch instance
and displays an error message as the following:
❑ The tool reports an error if the -stage_1_enable command is not a gate terminal.
❑ The tool reports an error if the -power (Power) and power_switchable (PSW)
command options in header switch are not source and drain terminals or drain and
source terminals respectively;
or the ground (Ground) and ground_switchable (GSW) command options in
footer switch are not source and drain terminals or drain and source terminals
respectively as the following:

Power/Ground PSW/GSW Error

Source terminal of transistor Drain terminal of transistor No
Drain terminal of transistor Source terminal of transistor No
Source terminal of transistor Source terminal of transistor Yes
Drain terminal of transistor Drain terminal of transistor Yes
Source terminal of transistor Gate terminal of transistor/Bulk Yes
terminal of transistor

August 2024 196 Product Version IC23.1

Drain terminal of transistor Gate terminal of transistor/Bulk Yes

terminal of transistor
Gate terminal of transistor/Bulk Drain terminal of transistor Yes
terminal of transistor
Gate terminal of transistor/Bulk Source terminal of transistor Yes
terminal of transistor

GUI Equivalent

None

Example
envGetVal("lp" "autoCorrectNativePSWOptions")
envSetVal("lp" "autoCorrectNativePSWOptions" 'boolean nil)

Related Topics

Special Cell and Standard Cell Modeling

August 2024 197 Product Version IC23.1

considerShortThreshold
lp considerShortThreshold boolean { t | nil }

Description

Considers resistor elements as connectors or short devices based on the threshold value of
resistors specified in a setup file. The default value is t.

In a specific cellview, the parameter value of resistors is checked against the threshold value
and are considered as short devices if their parameter value is less than the threshold value.
If the parameter value is above the threshold value, the resistors are considered as connector
elements. When there is no threshold value defined, the default behavior is that resistors are
considered as short devices or connectors based on the category in which they are originally
registered.

For example, for CellA, parameter r is checked for its value. A value lower than 50 is
considered as a short. For CellB, parameter resVal is checked for its value. A value higher
than 10 is considered as connector.
connector (
("VPM_TEST_LIB2" "CellA" nil
(nil
ResthreshHold("r" 50)
)
)
("VPM_TEST_LIB1" "CellB" nil
(nil

ResthreshHold("resVal" 10)
)
)
("VPM_TEST_LIB2" "CellC" nil)
("VPM_TEST_LIB2" "CellD" nil)
)

GUI Equivalent

None

Example
envGetVal("lp" "considerShortThreshold")

August 2024 198 Product Version IC23.1

envSetVal("lp" "considerShortThreshold" 'boolean t)

Related Topics

Connectors

Resistors as Short Devices

August 2024 199 Product Version IC23.1

createExtractionLogFile
lp createExtractionLogFile boolean { t | nil }

Description

Prints extraction messages to a log file. The default value is nil.

GUI Equivalent

None

Example
envGetVal("lp" "createExtractionLogFile")
envSetVal("lp" "createExtractionLogFile" 'boolean nil)

Related Topics

Extracting the Power Intent from a Design

August 2024 200 Product Version IC23.1

createPinsOnImport
lp createPinsOnImport boolean { t | nil }

Description

Controls the creation of ports in the design while importing the 1801 file. This is based on the
create_supply_port command found in the input 1801 file.

The default value is t. When set to t, ports are created in the design. If set to nil, a supply
net with a global net expression or supply local net is created by using the
Create_supply_port and Create_supply_net commands in the input 1801 file based
on the resolveTopNets argument of vpmImportPowerIntent.

GUI Equivalent

None

Example
envGetVal("lp" "createPinsOnImport")
envSetVal("lp" "createPinsOnImport" 'boolean nil)

Related Topics

Extracting the Power Intent from a Design

vpmImportPowerIntent

August 2024 201 Product Version IC23.1

delimiterForInternalPower
lp delimiterForInternalPower string "__"

Description

Specifies a delimiter for internal supplies that are referenced by the Liberty file generated by
Power Manager. The default value is "__".
voltage_map( I0__gnd_int , 0.000000);
voltage_map( I0__vdd_int , 0.800000);

pg_pin(I0__vdd_int) {
witch_function : "!(Enable)";
voltage_name : I0__vdd_int;
pg_function : vdd;
pg_type : internal_power;
direction : internal;
}
pg_pin(I0__gnd_int) {
switch_function : "Sleep";
voltage_name : I0__gnd_int;
pg_function : gnd;
pg_type : internal_ground;
direction : internal;

pin(data) {
related_ground_pin : I0__gnd_int;
related_power_pin : I0__vdd_int;
direction : input;

GUI Equivalent

None

Examples
envGetVal("lp" "delimiterForInternalPower")
envSetVal("lp" "delimiterForInternalPower" 'string ",")

August 2024 202 Product Version IC23.1

Related Topics

Exporting Liberty Power Model

August 2024 203 Product Version IC23.1

enableCDMAttr
lp enableCDMAttr boolean { t | nil }

signalPortsForIsoEnableConditionDerivation

virtualSuppliesForSwitchFunctionDerivation

exportIsoEnableConditionDerivationForAllTopIsolatedPorts

August 2024 206 Product Version IC23.1

exportIsoEnableConditionDerivationForAllTopIsolatedPorts
lp exportIsoEnableConditionDerivationForAllTopIsolatedPorts boolean { t | nil }

Description

Provides isolation_enable_condition derivations for all isolated ports included in

dotlib, when set to t. The default value is nil, which means no derivation is printed in the
CIW.

GUI Equivalent

None

Examples
envGetVal("lp" "exportIsoEnableConditionDerivationForAllTopIsolatedPorts")
envSetVal("lp" "exportIsoEnableConditionDerivationForAllTopIsolatedPorts"
'boolean t)

Related Topics

Export of Switch Function and Isolation Enable Condition Expressions

signalPortsForIsoEnableConditionDerivation

exportSwitchFunctionDerivationForAllUsedVirtualSupplies

virtualSuppliesForSwitchFunctionDerivation

August 2024 207 Product Version IC23.1

extractionLogPath
lp extractionLogPath string "."

Description

Controls the printing of the extraction log file at the path provided. The default value is "."and
the extraction log is generated in the current working directory.

GUI Equivalent

None

Examples
envGetVal("lp" "extractionLogPath")
envSetVal("lp" "extractionLogPath" 'string ".abc/testlib/ext.log")

Related Topics

Extracting the Power Intent from a Design

August 2024 208 Product Version IC23.1

extractParasiticDiode
lp extractParasiticDiode boolean { t | nil }

Description

Controls the detection and printing of parasitic diode elements formed between the bulk
terminal and source terminal, bulk terminal and drain terminal, or between MOS devices.
When set to t, the parasitic diode information gets extracted in terms of the
antenna_diode_related_power_pins and
antenna_diode_related_ground_pins attributes corresponding to data pins at the
source or drain end of a MOS device. The default value is nil.

GUI Equivalent

None

Examples
envGetVal("lp" "extractParasiticDiode")

August 2024 209 Product Version IC23.1

With envSetVal("lp" "extractParasiticDiode" 'boolean t)

Related Topics

Connectors

August 2024 210 Product Version IC23.1

lpDBGlobalSearchLibs
lp lpDBGlobalSearchLibs string { "LibName" }

Description

Sets the library list look-up order for enabling the power view creation in a different library if
the parent library is not editable. This enables the power view creation and subsequent
access of the cellview.

By default, no library name is specified. The parent library is the location for power view
creation.

Else, the specified library name or a list of library names are considered as the location for
power view creation.

GUI Equivalent

None

Examples
envGetVal("lp" "lpDBGlobalSearchLibs")
envSetVal("lp" "lpDBGlobalSearchLibs" 'string "DESIGN_LIB_LDO DESIGN_NEW_LIB_LDO")

This would enable the creation and opening of the power view of the cell in the libraries
DESIGN_LIB_LDO or DESIGN_NEW_LIB_LDO. The order of look-up to create and access
the power view is from DESIGN_LIB_LDO until DESIGN_NEW_LIB_LDO. If the library
DESIGN_LIB_LDO is not editable, the power view is created and accessed from library
DESIGN_NEW_LIB_LDO.

Related Topics

Power View

August 2024 211 Product Version IC23.1

lpDBGlobalSearchViews
lp lpDBGlobalSearchViews string { "power" }

Description

Related Topics

Single Rail Cells

August 2024 215 Product Version IC23.1

maxConsecutiveTxChannelCrossingsForABT
lp maxConsecutiveTxChannelCrossingsForABT int channels

Description

Specifies the maximum number of channels for automatic backtracing of transistor logic seen
in its flat form or inside algorithm standard cell. The backtracing stops if the successive
channel crossings reach a predefined limit. The default value is 10 and it can be changed to
any integer less than or equal to 20.

GUI Equivalent

None

Examples
envGetVal("lp" "maxConsecutiveTxChannelCrossingsForABT")
envSetVal("lp" "maxConsecutiveTxChannelCrossingsForABT" 'int 15)

Related Topics

Backtrace Enable Signals of Special Cells

August 2024 216 Product Version IC23.1

maxConsecutiveTxGateCrossingsForABT
lp maxConsecutiveTxGateCrossingsForABT int gates

Description

Specifies the power_down_func attribute for inout ports in a Liberty file. The default value
is nil, in which case power_down_func is not printed for inout ports.

GUI Equivalent

None

Example
envSetVal("lp" "powerDownFunctionForIOPorts" 'boolean t)

August 2024 222 Product Version IC23.1

printAliveAndPermitAttributesinDotlib
lp printAliveAndPermitAttributesinDotlib boolean { t | nil }

Description

Prints the alive and permit attributes for ports connected to isolation cells. When set to
nil, the attributes are not printed.

GUI Equivalent

None

Example
envGetVal("lp" "printAliveAndPermitAttributesinDotlib")
envSetVal("lp" "printAliveAndPermitAttributesinDotlib" 'boolean t)

Related Topics

Special Isolation Cells in Liberty Power Model Export

August 2024 223 Product Version IC23.1

printBusBitDirectionInLiberty
lp printBusBitDirectionInLiberty boolean { t | nil }

Description

Controls the printing of the direction attribute for bus bits in the exported macro Liberty power
model. The default value is nil, in which case the direction attribute is printed at the bus
group level. When set to t, the direction attribute is printed for each individual bus bit.

GUI Equivalent

None

Examples
envGetVal("lp" "printBusBitDirectionInLiberty")

With the value of printBusBitDirectionInLiberty as nil ->

bus(OUT) {

bus_type : CDS_BUS_1_To_0;
related_power_pin : VDD;
related_ground_pin : VSS;
power_down_function : "!VDD + VSS";
}
pin(OUT[0]) {
related_power_pin : VDD;
related_ground_pin : VSS;
power_down_function : "!VDD + VSS";
}

With the value of printBusBitDirectionInLiberty as t ->

bus(OUT) {

bus_type : CDS_BUS_1_To_0;
pin(OUT[1]) {

August 2024 224 Product Version IC23.1

direction : output;
related_power_pin : VDD;
related_ground_pin : VSS;
power_down_function : "!VDD + VSS";
}
pin(OUT[0]) {
direction : output;
related_power_pin : VDD;
related_ground_pin : VSS;
power_down_function : "!VDD + VSS";
}

Related Topics

Exporting Liberty Power Model

August 2024 225 Product Version IC23.1

printCoupledSupplies
lp printCoupledSupplies boolean { t | nil }

Description

When two shorted supply ports are encountered in a design, prints the user-defined attribute
coupled_supplies in the exported macro Liberty power model and the corresponding
UPF_feedthrough attributes of the set_port_attributes statements in the 1801
power intent file. The default value is nil, which means that the coupled supply attributes are
not printed.

For example, the following user-defined attributes are printed for shorted supply ports VDD1
and VDD2 and shorted ground ports VSS1 and VSS2.

Liberty Power Model

library(DemoWebinar4) {
voltage_map( VDD1 , 1.000000);
voltage_map( VDD2 , 1.000000);
voltage_map( VSS1 , 0.000000);
voltage_map( VSS2 , 0.000000);
define (coupled_supplies, cell, string);
cell(TESTCELL_4) {
is_macro_cell : true;
short(VDD2,VDD1);
short(VSS2,VSS1);
coupled_supplies : "(VDD2 VDD1)(VSS2 VSS1)";
}

1801 Design Model

set_port_attributes -ports { VDD2 VDD1 } -attribute {UPF_feedthrough TRUE}
set_port_attributes -ports { VSS2 VSS1 } -attribute {UPF_feedthrough TRUE}

GUI Equivalent

None

Example
envGetVal("lp" "printCoupledSupplies")
envSetVal("lp" "printCoupledSupplies" 'boolean t)

August 2024 226 Product Version IC23.1

Related Topics

Exporting Liberty Power Model

Special Isolation Cells in Liberty Power Model Export

August 2024 227 Product Version IC23.1

printModelInSDA
lp printModelInSDA boolean { t | nil }

Description

Adds model names to the exported UPF file when set to t. The default value is nil. By
default, the command used is:
set_design_attributes -attribute top_ports_have_anon_supply 0

With value is set as t, the command used is:

set_design_attributes -models top -attribute top_ports_have_anon_supply 0

GUI Equivalent

None

Examples
envGetVal("lp" "printModelInSDA")
envSetVal("lp" "printModelInSDA" 'boolean nil)

Related Topics

Exporting 1801 Design Model

August 2024 228 Product Version IC23.1

printProgressInfo
lp printProgressInfo boolean { t | nil }

Description

August 2024 234 Product Version IC23.1

removeInternalNetFromPgFn
lp removeInternalNetFromPgFn boolean { t | nil }

Description

Checking a Design in Background Mode

August 2024 238 Product Version IC23.1

separatorForBit
lp separatorForBit string "<>"

Description

Specifies separators for pin names of the bus bits. The default value is "<>".
voltage_map( vdd_Int[0] , 0.800000);
voltage_map( vdd_Int[1] , 0.800000);
voltage_map( vdd_Int[2] , 0.800000);

pg_pin(vdd_Int[1]) {
voltage_name : "vdd_Int[1]";
pg_type : internal_power;
direction : "internal";
switch_function : "Enable[1]";
pg_function : "vdd";
}

pin(in1) {
direction : "inout";
related_power_pin : "vdd_Int[1]";
related_ground_pin : "I0[int]gnd_int[1]";
}

GUI Equivalent

None

Example
envGetVal("lp" "separatorForBit")
envSetVal("lp" "separatorForBit" 'string "[]")

Related Topics

Registering Name-Based Supply Nets

August 2024 239 Product Version IC23.1

signalPortsForIsoEnableConditionDerivation
lp signalPortsForIsoEnableConditionDerivation string "data_port_names"

Description

Registers the names of data ports in a setup file that need the
isolation_enable_condition derivation. The default value is "", which means no
derivation is printed in the CIW.

GUI Equivalent

None

Example
envGetVal("lp" "signalPortsForIsoEnableConditionDerivation")
envSetVal("lp" "signalPortsForIsoEnableConditionDerivation" 'string "OUT OUT2
IN1")

Related Topics

Export of Switch Function and Isolation Enable Condition Expressions

virtualSuppliesForSwitchFunctionDerivation

exportSwitchFunctionDerivationForAllUsedVirtualSupplies

exportIsoEnableConditionDerivationForAllTopIsolatedPorts

August 2024 240 Product Version IC23.1

singleRailAttrPropagation
lp singleRailAttrPropagation boolean { t | nil }

Description

Propagates attributes, such as input_signal_level and input_voltage_range, from

GUI Equivalent

None

Examples

If value is nil:
pin(Enable) {
direction : input;
related_power_pin : vdd;
related_ground_pin : I0__net7;
}

If value is t:
pin(Enable) {
direction : input;
switch_pin : true;
related_power_pin : vdd;
related_ground_pin : I0__net7;
}

Related Topics

Handling of Low Power Special Cells

August 2024 244 Product Version IC23.1

switchViewList
lp switchViewList string "viewnames"

Description

Specifies a space-separated list of cellview names that is used while reviewing the design
under test to control the order in which the design hierarchy is traversed. Power Manager
uses the switch view list for design traversal during the power intent extraction phase and also
to create the required design objects during the 1801 import flow.

The default value is "".

GUI Equivalent

None

Example
envGetVal("lp" "switchViewList")
envSetVal("lp" "switchViewList" 'string "cmos_sch cmos.sch schematic symbol")

Related Topics

Importing Power Intent

Related Topics

Checking a Design in Foreground Mode

Run In-Design Checks

August 2024 252 Product Version IC23.1

virtualSuppliesForSwitchFunctionDerivation
lp virtualSuppliesForSwitchFunctionDerivation string "virtual supply_net_names"

Description

Registers the names of virtual supply nets that need the switch_function derivation. The
default value is "", which means no derivation is printed in the CIW.

GUI Equivalent

None

Example
envGetVal("lp" "virtualSuppliesForSwitchFunctionDerivation")
envSetVal("lp" "virtualSuppliesForSwitchFunctionDerivation" 'string "VVDD VVDD_CPU
VVDD_LDO")

Related Topics

Export of Switch Function and Isolation Enable Condition Expressions

signalPortsForIsoEnableConditionDerivation

exportSwitchFunctionDerivationForAllUsedVirtualSupplies

exportIsoEnableConditionDerivationForAllTopIsolatedPorts

August 2024 253 Product Version IC23.1

writeMixedFormatPST
lp writeMixedFormatPST boolean { t | nil }

Description

Enables the use of syntax or semantics for writing mixed power states in the exported
1801power model file. This allows the printing of a mix of Unified Power Format 2.0 and
Unified Power Format 1.5 for specifying the power states in the extracted 1801 power model.
The default value is nil. If the environment variable is set to nil, the power states are written
using the add_power_state command only. The multiple supplies are printed as
ExtVDD+VDD. When set to t, power states are written by using the following commands:
■ add_power_state
■ create_pst
■ add_pst_state

When set to t
##### Power States ##################################################
add_power_state ss__vddA__vssA -supply -state { on_1p0 -supply_expr { (power == {
FULL_ON 1.000000 }) && (ground == { OFF }]}}
add_power_state ss__vddA__vssB -supply -state { on_1p0 -supply_expr { (power == {
FULL_ON 1.000000 }) && (ground == { OFF }]}}
add_power_state ss__vddB__vssB -supply -state { on_1p5 -supply_expr { (power == {
FULL_ON 1.500000 }) && (ground == { OFF }]}}
add_power_state ss__vddB_init__vssB -supply -state { on_1p5 -supply_expr { (power
== { FULL_ON 1.500000 }) && (ground == { OFF }]}} -state { off_0p0 \
-supply_expr { (power == { OFF }) && (ground == { OFF })}}
add_power_state pd__vddA__vssA -domain -state { mode0 -logic_expr {ss__vddB__vssB
== on_1p5 && ss__vddA__vssB == on_1p0 && ss__vddA__vssA == on_1p0 && \
ss__vddB_init__vssB == on_1p5 }} -state { mode1 -logic_expr { ss__vddB__vssB ==
on_1p5 && ss__vddA__vssB == on_1p0 && ss__vddA__vssA == on_1p0 && \
ss__vddB_init__vssB == off_0p0}}

When set to nil

##### Power States ##################################################
add_power_state ss__vddA__vssA -state { on_1p0 -supply_expr { power == { FULL_ON
1.000000 }}} -state { on_0p0 -supply_expr { ground == { FULL_ON 0.000000 }}}
add_power_state ss__vddA__vssB -state { on_1p0 -supply_expr { power == { FULL_ON
1.000000 }}} -state { on_0p0 -supply_expr { ground == { FULL_ON 0.000000 }}}
add_power_state ss__vddB__vssB -state { on_1p5 -supply_expr { power == { FULL_ON

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1.500000 }}} -state { on_0p0 -supply_expr { ground == { FULL_ON 0.000000 }}}

add_power_state ss__vddB_init__vssB -state { on_1p5 -supply_expr { power == {
FULL_ON 1.500000 }}} -state { on_0p0 -supply_expr { ground == { FULL_ON 0.000000
}}} \
-state { off_0p0 -supply_expr { power == { OFF }}}
##### PST ##################################################
create_pst cellA -supplies { ss__vddB__vssB.power ss__vddB__vssB.ground
ss__vddA__vssB.power ss__vddA__vssA.ground ss__vddB_init__vssB.power}
add_pst_state mode0 -pst cellA -state {on_1p5 on_0p0 on_1p0 on_0p0 on_1p5 }
add_pst_state mode1 -pst cellA -state {on_1p5 on_0p0 on_1p0 on_0p0 off_0p0 }

GUI Equivalent

None

Examples
envGetVal("lp" "writeMixedFormatPST")
envSetVal("lp" "writeMixedFormatPST" 'boolean t)

Related Topics

Exporting 1801 Power Model

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B
Virtuoso Power Manager SKILL
Functions

This topic describes the public SKILL functions in Power Manager.

■ vpmDefinePowerSwitchInstance
■ vpmExportDotLib
■ vpmExportPowerIntent
■ vpmExportPowerModel
■ vpmExportPowerIntentSetup
■ vpmExtractPowerIntent
■ vpmGenerateSigInfo
■ vpmImportPowerIntent
■ vpmImportPowerIntentSetup
■ vpmLoadInDesignViolations
■ vpmRemoveImportedPowerIntent
■ vpmRemovePowerSwitchInstance
■ vpmRunInDesignChecks
■ vpmSetViolationBrowserOptions

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vpmDefinePowerSwitchInstance
vpmDefinePowerSwitchInstance(
t_cellName
t_instName
g_type
g_stage1Enable
[ ?stage2Enable g_stage2Enable ]
[ ?stage1Output g_stage1Output ]
[ ?stage2Output g_stage2Output ]
[ ?power g_power ]
[ ?powerSwitchable g_powerSwitchable ]
[ ?ground g_ground ]
[ ?groundSwitchable g_groundSwitchable ]
)
=> t / nil

Description

Registers transistor instances as power or ground switches.

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Arguments

t_cellName The name of the parent cell name of power switch instance.
t_instName The name of the power switch instance.
g_type Specifies header for power switch or footer for ground
switch.
g_stage1Enable The stage 1 enable expression for power switch instance.
?stage2Enable g_stage2Enable
The stage 2 enable expression for power switch instance.
?stage1Output g_stage1Output
The stage 1 output expression for power switch instance.
?stage2Output g_stage2Output
The stage 2 output expression for power switch instance.
g_power The power pin of power switch instance.
?powerSwitchable g_powerSwitchable
The switchable pin of power switch instance.
g_ground The ground pin of ground switch instance.
?groundSwitchable g_groundSwitchable
The switchable pin of ground switch instance.

Value Returned

t The instances are registered successfully.

nil The instances could not be registered.

Example
vpmDefinePowerSwitchInstance("analog_blk" "M0" type "header" ?power "S"
?powerSwitchable "D" stage1Enable "!G")

■ M0 is power switch instance in the analog_blk cell.

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Related Topic

Handling of Low Power Special Cells

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vpmExportDotLib
vpmExportDotLib(
x_session_id
t_file_dot_lib
)
=> t / nil

Description

Exports the extracted power intent in the .lib file format.

Arguments

x_session_id The ID of the window for which you want to export the power
intent.
t_file_dot_lib The name of the file for exporting the power intent.

Value Returned

t The file is exported successfully.

nil The file could not be exported.

Example
vpmImportPowerIntentSetup( "test_pg" "pass_gate_SC" "schematic" "lpSetup.il")
session = (vpmExtractPowerIntent "test_pg" "pass_gate_SC" "schematic")
vpmExportDotLib (session "libModel.lib")

Exports the power intent as the Liberty Power Model libModel.lib file.

Related Topic

Exporting Liberty Power Model

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vpmExportPowerIntent
vpmExportPowerIntent(
x_session_id
t_file_1801
)
=> t / nil

Description

Exports the 1801 Design Model for a design. Ensure that the design has been extracted by
using vpmExtractPowerIntent or the GUI options in Virtuoso Schematic Editor. This function
requires a session ID, which is generated upon successful power intent extraction for the
design.

Arguments

x_session_id The ID of the window for which you want to export the power
intent.
t_file_1801 The name of the file for exporting the power intent.

Value Returned

t Returns t if the power intent is successfully exported.

nil Returns nil otherwise.

Example
vpmImportPowerIntentSetup( "test_pg" "pass_gate_SC" "schematic" "lpSetup.il")
session = (vpmExtractPowerIntent "test_pg" "pass_gate_SC" "schematic")
vpmExportPowerIntent (session "designmodel.upf")

Related Topic

Exporting 1801 Design Model

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vpmExportPowerModel
vpmExportPowerModel(
x_sessionID
t_output_file_name
)
=> t

Description

Exports the 1801 power model for a design. Ensure that the design has been extracted by
using vpmExtractPowerIntent, or using the GUI options in Virtuoso Schematic Editor.
This function requires a session ID, which is generated upon successful power intent
extraction for the design.

Arguments

x_sessionID The return value of vpmExtractPowerIntent.

t_output_file_name The name of the file for exporting the 1801 power model.

Value Returned

t Returns t if the 1801 power intent model is successfully

exported to the file.
Displays an error message.

Related Topic

Exporting 1801 Power Model

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vpmExportPowerIntentSetup
vpmExportPowerIntentSetup(
t_setup_file_name
[ ?overwriteExisting g_overwriteExisting ]
[ ?filter g_filter ]
[ ?lpDBLibName g_lpDBLibName ]
[ ?lpDBCellName g_lpDBCellName ]
[ ?lpDBViewName g_lpDBViewName ]
)
=> t / nil

Description

Exports the loaded setup to a specified file. This file can be verified for the setup options that
the Power Manager has used during import/export of power intent.

Arguments

t_setup_file_name Name of the file to which the loaded setup is exported.

?overwriteExisting g_overwriteExisting
Specifies if the exported file can overwrite an existing file with
the same name, if any.
?filter g_filter Specifies which setup options out of
environmentSetupOptions, userSetupOptions, or
allSetupOptions are to be exported to the filename
specified in t_output_file_name.
?lpDBLibName g_lpDBLibName
Name of the library in which the power view is generated.
?lpDBCellName g_lpDBCellName
Name of the cell in which the power view is generated.
?lpDBViewName g_lpDBViewName
Name of the power view generated.

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Value Returned

t Returns t if the loaded power intent setup is successfully

exported to the file specified.
nil Returns nil otherwise.

Example
vpmExportPowerIntentSetup( "test_pg" "pass_gate_SC" "schematic" "lpSetup.il"
?overwriteExisting t ?filter "allSetupOptions")

Related Topic

Setup for Automatic Extraction of Power Intent

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vpmExtractPowerIntent
vpmExtractPowerIntent(
t_lib
t_cellName
t_viewName
)
=> session_id / nil

Description

Extracts the power intent from the given design. It also identifies sub-hierarchical blocks in the
top-level design, which need macro model extraction or are associated with a 1801 file.

Argument

t_lib Name of the library of the cellview to be extracted.

t_cellName Name of the cell of the cellview to be extracted.
t_viewName View name from which power intent is to be extracted.

Value Returned

session_id Returns the session id if the power intent model is successfully

extracted.
nil Returns nil otherwise.

Example
vpmExtractPowerIntent ("test_pg" "pass_gate_SC" "schematic")

Related Topic

Extracting the Power Intent from a Design

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vpmGenerateSigInfo
vpmGenerateSigInfo(
t_libName
t_cellName
t_viewName
t_sigInfoFilePath
)
=> session_id / nil

Description

Adds the signal type and voltage values for all the canonical nets in the design. If a design
net spans across multiple levels in the hierarchy, the net at the highest level of the hierarchy
is considered as canonical.

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Argument

t_libName Name of the design cellview.

t_cellName
t_viewName
t_sigInfoFilePath Path of the text file that is created by the SKILL function that
contains the details of the canonical design nets. For each
canonical net listed in the file, its details include the signal type
and net voltages. If no file path is specified, the function
creates the file by the name of
t_libName_t_cellName.siginfo.txt in the current
working directory.

Value Returned

t Returns t if it is able to successfully generate the information

for canonical nets.
nil Returns nil in one of these situations:
■ The t_libName, t_cellName, t_viewName are not
strings or are empty strings.
■ The t_libName, t_cellName, t_viewName do not
point to a valid and readable Open Access cellview.
■ One of the t_libName, t_cellName, or t_viewName
argument is nil.
■ The t_sigInfoFilePath references to a directory
location that is not writable.
■ Appropriate licenses required by the function are not
available.
■ Power Manager Setup is not loaded for the specified
design.

Example

This example showcases how a signal information file is generated.

when(ret
;; If setup is loaded successfully, try to generate sigInfo

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ret = vpmGenerateSigInfo( "testlib" "adcTop" "schematic" )

when(ret
;; If the API run was successful it should have created a file by the name
of testlib_adcTop.siginfo.txt;
;; Open it in a view window to view the results
view( "./testlib_adcTop.siginfo.txt")
)
)

Related Topic

Generating Signal Information

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vpmImportPowerIntent
vpmImportPowerIntent(
t_libname
t_cellname
t_viewname
t_viewlist
t_file1801Path
[ ?resolveTopNets g_resolveTopNets ]
)
=> t / nil

Description

Imports the power intent for any cellview. It also creates the netSet properties and resolves
tie connections in the design hierarchy and creates supply pins corresponding to the power
domain nets and global nets.
Note: This function requires a Virtuoso Schematic Editor XL license, which is released when
the import is complete.

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Arguments

t_libname Name of the library of the cellview to be imported or exported

for power intent.
t_cellname Name of the cell to be imported or exported for power intent.
t_viewname Name of the view to be imported or exported for power intent.
t_viewlist Switch view list specifying the order of traversal of hierarchical
schematic to create the required OA objects.
t_file1801Path Name or path of the 1801 file to be imported.
?resolveTopNets g_resolveTopNets
Controls the generation of supply nets and supply ports in a
design.
When set to t,
■ Ports are created at the top level and their corresponding
nets are non-inherited.
■ Ports are created at the scope level and their
corresponding nets are inherited.
When set to nil (default),
■ Ports created at the top level and their corresponding nets
are inherited.
■ Ports created at the scope level and their corresponding
nets are inherited.
Local nets created using create_supply_net without ports
are non-inherited at both the scope level and top level.

Value Returned

t The power intent setup is successfully imported.

nil The power intent setup could not be imported.

Example
vpmImportPowerIntent( "test_pg" "pass_gate_SC" "schematic" "schematic symbol"
"import.upf" ?resolveTopNets t)

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vpmImportPowerIntentSetup
vpmImportPowerIntentSetup(
t_libname
t_cellname
t_viewname
t_setup_file_name
[ ?lpDBLibName g_lpDBLibName ]
[ ?lpDBCellName g_lpDBCellName ]
[ ?lpDBViewName g_lpDBViewName ]
)
=> t / nil

Description

Imports a SKILL file that contains the user-defined setup. This has the attributes required to
extract the desired information from the design cellview for importing or exporting the power
intent.

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Arguments

t_libname Name of the library of the cellview to be imported or exported

for power intent.
t_cellname Name of the cell to be imported or exported for power intent.
t_viewname Name of the view to be imported or exported for power intent.
t_setup_file_name Name of the user-defined setup file.
g_lpDBLibName Name of the library of the cellview in which the power view is
generated.
g_lpDBCellName Name of the cell in which the power view is generated.
g_lpDBViewName Name of the power view in the cellview.

Value Returned

t Returns t if the power intent setup is successfully imported or

loaded.
nil Returns nil otherwise.

Example
vpmImportPowerIntentSetup( "test_pg" "pass_gate_SC" "schematic" "lpSetup.il")

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vpmLoadInDesignViolations
vpmLoadInDesignViolations(
t_libname
t_cellname
t_viewname
t_vdbFilePath
)
=> t / nil

Description

Loads the specified violation database file that contains the violation details for a previous
check on a design. As the SKILL function processes each violation from the violations file, it
creates markers on relevant design objects.

Arguments

t_libname Name of the library of the cellview to be imported or exported

for power intent.
t_cellname Name of the cell to be imported or exported for power intent.
t_viewname Name of the view to be imported or exported for power intent.
t_vdbFilePath Name or path of the 1801 file to be imported.

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Value Returned

t Returns t if the violations are loaded successfully.

nil Returns nil in one of these situations:
■ t_libName, t_cellName, t_viewName are not strings,
or are empty strings.
■ t_libName, t_cellName, t_viewName do not point to a
valid and readable Open Access cellview.
■ One of the t_libName, t_cellName, t_viewName,
argument is nil, the user gets a SKILL error.
■ The t_libName, t_cellName, and t_viewName do not
match the library, cell, and view name of the design for
which the violation file was generated.
■ The t_vdbFilePath references are non-existent or non-
readable file.
■ Appropriate licenses required by the SKILL function are not
available.

Example
ret = vpmLoadInDesignViolations( "testlib" "adcTop" "schematic" "./
testlib.adcTop.vdb")

Related Topics
Loading the Violations Database

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vpmRemoveImportedPowerIntent
vpmRemoveImportedPowerIntent(
t_libName
t_cellName
t_viewName
)
=> t_viewlist/ nil

Description

Removes the entire power intent information that was imported for a cellview. This function
also removes the netSet properties, tie connections, supply pins, and so on.

This function is used only when the Schematic XL license is checked out. Therefore, it first
verifies whether the license is already checked out and if it is not, it tries to check out the
license. The function also releases the license before exiting.

The view list specified by t_viewlist is used for processing the removal of imported
objects for the view type instantiated in the top cellview.

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Argument

t_libname Name of the library of the cellview for which the power intent
will be removed
t_cellname Name of the cell of the cellview for which the power intent will
be removed
t_viewname Name of the view of the cellview for which the power intent will
be removed
t_viewlist List of the view names to be processed for removing the power
intent information.

Value Returned

t_viewlist Returns the list of the view names to be processed

for removing the power intent information.
nil Returns nil otherwise.

Examples
vpmRemoveImportedPowerIntent( "test_pg" "pass_gate_SC" "schematic" "schematic"
"symbol")

Related Topic

Removing Imported Power Intent

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vpmRemovePowerSwitchInstance
vpmRemovePowerSwitchInstance(
t_cellName
t_instName
)
=> t / nil

Description

Removes registered transistor instances as power or ground switches.

Arguments

t_cellName The name of the parent cell name of power switch instance.
t_instName The name of the power switch instance.

Value Returned

t The instances are removed successfully.

nil The instances could not be removed.

Example
vpmRemovePowerSwitchInstance("analog_blk" "M0" )

M0 is an instance in the analog_blk cell, which had been registered as a power switch using
SKIL API vpmDefinePowerSwitchInstance. This instance will not be treated as a power
switch any more.

Related Topic

Handling of Low Power Special Cells

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vpmRunInDesignChecks
vpmRunInDesignChecks(
t_libName
t_cellName
t_viewName
[ ?instPath t_instPath ]
[ ?logFilePath t_lprcFilePath ]
[ ?vdbFilePath t_vdbFilePath ]
)
=> t / nil

Description

Runs the In-Design Checks on a design specified by library, cell, and view.

Arguments

t_libname Name of the design cellview.

t_cellname
t_viewname
t_instPath Specifies the path of a hierarchical instance within the design
specified by t_libname, t_cellname, and t_viewname
on which the checks would be run. If it is not provided, the
checks are run on the complete design.
t_logFilePath Path of the In-Design Checks log file that reports the summary
and details of violations. If no value is specified, the function
creates the file by the name of
t_libName_t_cellName.inDesign.log in the current
working directory.
g_vdbFilePath Name of the violation database (.vdb). It contains the violation
details for the current run. If none is specified, the function
creates the file by the name of
t_libName_t_cellName.vdb in the current working
directory.

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Value Returned

t The Power Manager has been run successfully.

nil One or more of the following error conditions applies:
■ The t_libName, t_cellName and t_viewName are
not strings or are empty strings.
■ The t_libName, t_cellName, t_viewName do not
point to a valid and readable OpenAccess cellview.
■ One of the t_libName, t_cellName, or t_viewName
argument is nil.
■ If t_lprcFilePath references a directory location that
is not writable.
■ If t_vdbFilePath references to a directory location that
is not writable.
■ Appropriate licenses required by the function are not
available.
■ The setup information is not loaded for the specified
design.

Example

when(ret
ret = vpmRunInDesignChecks( "testlib" "adcTop" "schematic" )
when(ret
view( "./testlib_adcTop.inDesign.log")
)
)

Related Topic

Checking a Design in Foreground Mode

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vpmSetViolationBrowserOptions
vpmSetViolationBrowserOptions(
w_window
t_openMode
t_openLocation
x_hierarchyDepth
[ ?hierarchicalScope b_hierarchicalScope ]
=> t / nil

Description

Sets the Annotation Browser options for viewing the design violations.

Arguments

w_window A valid GE window where the Power Manager application is

running. When a valid window ID is a specified, the function
sets the specified options only for the specific Annotation
Browser assistant occurrence.
t_openMode The mode in which the marker cellview is opened when you
choose to navigate the marker using the Open option in the
Annotation Browser. The valid values are edit and read.
t_openLocation The location where the marker cellview is opened when
you choose to navigate the marker using the Open option
in the Annotation Browser. The valid values are current
tab, new tab, or new window.
x_hierarchyDepth The valid values can be an integer between 0 and 32.
b_hierarchicalScope The valid values are t and nil. It is an optional argument.
If set to t, it sets the Annotation Browser scope value to
Curren Cellview To Depth and the In-Design Checks
markers in the current cellview hierarchy are displayed.
When set to nil, then it sets the Annotation Browser scope
value to Current Cellview Only and only the In-
Design Checks markers in the current cellview are
displayed.

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Value Returned

t Returns t if the Annotation Browser options have been set

successfully.
nil Returns nil if the Annotation Browser options could not be set
successfully.

Example
when(window = hiGetCurrentWindow()
when(vpmSetViolationBrowserOptions(window ?hierarchicalScope t hierarchyDepth
32)
println("Successfully set browser options")
)
)

Related Topic

Loading the Violations Database

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C
1801 Support in Power Manager

This topic provides the list of commands supported in Virtuoso Power Manager.
■ General 1801 Command Support
■ 1801 Special Cell Definition Command Support
■ Liberty Attributes Support

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General 1801 Command Support

In the IC6.1.8 and ICADVM20.1 releases, Power Manager supports 1801 commands as
explained below:
■ All 1801 commands are imported from the given 1801 file. The schematic connectivity in
the 1801 Import flow happens according to the commands supported by the Power
Manager.
■ All supported commands and arguments are read from the tool and exported to a 1801
file.

The following table lists all the general 1801 commands and explains how they are supported
in the 1801 import and export processes of Power Manager. All supported commands are
indicated with an S and the unsupported commands with a U.

Support Support
Valid in IEEE
Command Options Comments for 1801 for 1801
1801 Version
Import Export
create_power_domain 2.0 2.1 S S
-elements 2.0 2.1 S S
-include_scope 2.0 2.1 Deprecated S S
in 2.1
-supply 2.0 2.1 S S
-scope 2.0 2.1 Deprecated S S
in 2.1
-update 2.0 2.1 S S
create_supply_port 2.0 2.1 S S
-direction 2.0 2.1 S S
create_supply_net 2.0 2.1 S S
-resolve 2.0 2.1 S S
connect_supply_net 2.0 2.1 S S
-ports 2.0 2.1 S S
create_supply_set 2.0 2.1 S S
-function 2.0 2.1 S S

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Support Support
Valid in IEEE
Command Options Comments for 1801 for 1801
1801 Version
Import Export
-update 2.0 2.1 S S
associate_supply_set 2.0 2.1 S S
-handle 2.0 2.1 S S
set_port_attributes 2.0 2.1 S S
-applies_to 2.0 2.1 S S
-ports 2.0 2.1 S S
-elements 2.0 2.1 S S
-attribute 2.0 2.1 S S
-driver_supply 2.0 2.1 S S
-receiver_supply 2.0 2.1 S S
-repeater_supply 2.0 2.1 Deprecated S S
in 2.1
add_port_state 2.0 2.1 U S
-state 2.0 2.1 Not needed U S
for 1801
Import
add_pst_state 2.0 2.1 U S
-pst 2.0 2.1 Not needed U S
for 1801
Import
-state 2.0 2.1 Not needed U S
for 1801
Import
create_pst 2.0 2.1 U S
-supplies 2.0 2.1 Not needed U S
for 1801
Import
create_power_switch 2.0 2.1 S S
-output_supply_port 2.0 2.1 S S

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Support Support
Valid in IEEE
Command Options Comments for 1801 for 1801
1801 Version
Import Export
-input_supply_port 2.0 2.1 S S
-domain 2.0 2.1 S S
-control_port 2.0 2.1 S S
-on_state 2.0 2.1 S S
-off_state 2.0 2.1 S S
-supply_set 2.0 2.1 S S
define_signal_attributes 2.0 2.1 S S
-model 2.0 2.1 S S
-signals 2.0 2.1 S S
-on_sense 2.0 2.1 S S
-off_sense 2.0 2.1 S S
-supplies 2.0 2.1 S S
set_level_shifter 2.0 2.1 S S
-domain 2.0 2.1 S S
-elements 2.0 2.1 S S
-source 2.0 2.1 S S
-sink 2.0 2.1 S S
-applies_to 2.0 2.1 S S
-no_shift 2.0 2.1 S S
-location 2.0 2.1 S S
-update 2.0 2.1 S S
-input_supply_set 2.0 2.1 S S
-output_supply_set 2.0 2.1 S S
-internal_supply_set 2.0 2.1 S S

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Support Support
Valid in IEEE
Command Options Comments for 1801 for 1801
1801 Version
Import Export
set_isolation 2.0 2.1 S S
-domain 2.0 2.1 S S
-elements 2.0 2.1 U S
-source 2.0 2.1 U S
-sink 2.0 2.1 U S
-diff_supply_only 2.0 2.1 S S
-isolation_supply_net 2.0 2.1 S S
-update 2.0 2.1 S S
-applies_to 2.0 2.1 S S
-clamp_value 2.0 2.1 S S
-no_isolation 2.0 2.1 S S
-isolation_signal 2.0 2.1 S S
-isolation_sense 2.0 2.1 S S
-location self 2.0 2.1 S S
-location parent 2.0 2.1 S S
load_upf 2.0 2.1 S S
-scope 2.0 2.1 S S
set_scope 2.0 2.1 S S
Instance 2.0 2.1 S S
begin_power_model 2.1 U S
power_model_name 2.1 U S
-for model_list 2.1 U S

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Support Support
Valid in IEEE
Command Options Comments for 1801 for 1801
1801 Version
Import Export
add_power_state 2.1 U S
-state 2.1 U S
-supply_expr 2.1 U S
-logic_expr 2.1 U S
-simstate 2.1 U S
end_power_model 2.1 U S

1801 Special Cell Definition Command Support

The following table lists all the 1801 special cell definition commands and explains how they
are supported in the 1801 import and export processes of Power Manager. All supported
commands are indicated with an S and the unsupported commands with a U.

Support Support
Valid in IEEE
Command Options Comments for 1801 for 1801
1801 Version
Import Export
define_isolation_cell 2.0 2.1 S S
-cells 2.0 2.1 S S
-power 2.0 2.1 S S
-ground 2.0 2.1 S S
-enable 2.0 2.1 S S
-power_switchable 2.0 2.1 S S
-ground_switchable 2.0 2.1 S S

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Support Support
Valid in IEEE
Command Options Comments for 1801 for 1801
1801 Version
Import Export
define_level_shifter_cell 2.0 2.1 S S
input_voltage_range 2.0 2.1 S S
-output_voltage_range 2.0 2.1 S S
-direction 2.0 2.1 S S
-input_power_pin 2.0 2.1 S S
-output_power_pin 2.0 2.1 S S
-input_ground_pin 2.0 2.1 S S
-output_ground_pin 2.0 2.1 S S
-ground 2.0 2.1 S S
-power 2.0 2.1 S S
-enable 2.0 2.1 S S
define_power_switch_cell 2.0 2.1 S S
-cells 2.0 2.1 S S
-type 2.0 2.1 S S
-stage_1_enable 2.0 2.1 S S
-stage_1_output 2.0 2.1 S S
-power_switchable 2.0 2.1 S S
-power 2.0 2.1 S S
-ground_switchable 2.0 2.1 S S
-ground 2.0 2.1 S S

August 2024 291 Product Version IC23.1

Customized Commands

define_power_switch_instance 2.0 2.1 S S

-instances 2.0 2.1 S S
-in_cell
-type 2.0 2.1 S S
-stage_1_enable 2.0 2.1 S S
-stage_2_enable 2.0 2.1 S S
-stage_1_output 2.0 2.1 S S
-power_switchable 2.0 2.1 S S
-power 2.0 2.1 S S
-ground_switchable 2.0 2.1 S S
-ground 2.0 2.1 S S
define_isolation_instance 2.0 2.1 S S
-instances 2.0 2.1 S S
-in_cell
-type 2.0 2.1 S S
-enable 2.0 2.1 S S
-clamp_cell 2.0 2.1 S S
-no_enable 2.0 2.1 S S
-valid_location 2.0 2.1 S S
-power_switchable 2.0 2.1 S S
-power 2.0 2.1 S S
-ground_switchable 2.0 2.1 S S
-ground 2.0 2.1 S S
define_level_shifter_instance 2.0 2.1 S S
-instances 2.0 2.1 S S
-in_cell

August 2024 292 Product Version IC23.1

-input_voltage_range 2.0 2.1 S S

-output_voltage_range 2.0 2.1 S S
-direction 2.0 2.1 S S
-input_power_pin 2.0 2.1 S S
-output_power_pin 2.0 2.1 S S
-input_ground_pin 2.0 2.1 S S
-output_ground_pin 2.0 2.1 S S
-ground 2.0 2.1 S S
-power 2.0 2.1 S S
-enable 2.0 2.1 S S
-clamp_cell 2.0 2.1 S S
- 2.0 2.1 S S
ground_input_voltage_
range
- 2.0 2.1 S S
ground_output_voltage
_range
-valid_location 2.0 2.1 S S

Liberty Attributes Support

The following table lists all the supported Liberty attributes and explains how they are
supported in the 1801 export processes of the Power Manager. All supported commands are
indicated with an S and the unsupported commands with a U.

Support
for Export
Comments
Attribute Valid in Liberty Versions Liberty
Power
Model
is_macro_cell 2014.09 2017.06 S
voltage_map 2014.09 2017.06 S

August 2024 293 Product Version IC23.1

Support
for Export
Comments
Attribute Valid in Liberty Versions Liberty
Power
Model
pg_pin 2014.09 2017.06 S
pg_type 2014.09 2017.06 S
direction 2014.09 2017.06 S
switch_function 2014.09 2017.06 S
related_power 2014.09 2017.06 S
is_isolated 2014.09 2017.06 S
isolation_enable_conditi 2014.09 2017.06 S
on
power_down_function 2014.09 2017.06 S
switch_pin 2014.09 2017.06 S
is_analog 2014.09 2017.06 S

August 2024 294 Product Version IC23.1

Related Topics

Importing Power Intent

createExtractionLogFile

August 2024 306 Product Version IC23.1

Load Violations Form

Lets you specify the cellview and review its design violations in the Annotation Browser.

Field Name Description

Scope Specifies whether to run the checks on the
complete design or the currently descended
hierarchical instance of the top cellview.
Library Specifies the library of the design that has
violations.
Cell Specifies the cell of the design that has violations.
View Specifies the view name of the design that has
violations.
Instance Path Specifies the path to the currently descended
hierarchical instance on which the checks are to
be run. This field appears only when the
Hierarchical Instance option is selected for the
Scope field.
Violations File Specifies the name of the file that will be uploaded
to view the design violations.

Related Topic

Performing In-Design Checks

Power Manager Setup Form

Use the Power Manager Setup form to specify inputs for user-defined settings though
registration. The form contains the following tabs.

Tab Description
Supply Nets Lets you register certain names or regular expressions as names of
power nets or ground nets.

August 2024 307 Product Version IC23.1

Tab Description
Libraries Lets you register the libraries-related information for reading the
standard and special cells modeling information.
Devices Lets you register the device and terminal related information for
reading the device type and its topology in the design.
In-Design Checks Lets you define the severity of reporting of a set of predefined and
configurable circuit checks and supply states to set multiple voltages
for efficient power management.
Export Lets you register a power net and a ground net from the pair defined
explicitly in the setup as a supply set and the associated power
domain and port attributes.
Miscellaneous Lets you specify some generic settings.

Supply Nets
The following table describes the fields available on the Supply Nets tab of the Power
Manager Setup form.

Section Description
Registered Supply Specifies names as names of power nets or ground nets.
Nets
Regular Expression Specifies regular expressions for nets in the Power Nets,
Based Registration Ground Nets, Pwell Nets, Nwell Nets, Deep Pwell Nets, and
Deep Nwell Nets fields.
Excluded Nets Specifies names or regular expressions for excluded nets in the
Names and Regular Expressions fields.
Monitor Nets Specifies names or regular expressions for monitor nets in the
Names and Regular Expressions fields.
Supply NetSet Specifies netSet properties prefix for nets in the Power Nets,
Properties Prefix Ground Nets, Pwell Nets, Nwell Nets, Deep Pwell Nets, and
Deep Nwell Nets fields.

August 2024 308 Product Version IC23.1

Libraries
The following table describes the fields available on the Libraries tab of the Power Manager
Setup form.

Section Description
Liberty/Tech Files Specifies a list of Liberty model library files.
1801 File Binding Specifies a list of 1801 special cell definition
library files.
Reference Library Cells Specifies the instances of any library or a
particular cell in a design, apart from the Liberty
cell, as reference libraries.
MLDB Libraries Specifies project library that can be stored in an
Model Library database (MLDB).

Devices
The following table describes the fields available on the Devices tab of the Power Manager
Setup form.

Field Description
Library Name Specifies the library to list the cells that will be
registered as various device types.
Category Specifies the types of cells in the specified library.
Cells Specifies the list of cells that are available to be
registered as various device types.
Device Type Specifies the types of devices that can be used for
registering the cells in a design.
Terminals Specifies the list of device terminals of the cell,
which has been already registered, for
registration.

August 2024 309 Product Version IC23.1

In-Design Checks
The following table describes the fields available on the In-Design Checks tab of the Power
Manager Setup form.

Field/Section Description
Checks Categories Specifies the severity level of the results reported
for the Level Shifter, Isolation, and Bulk checks
and provides the flexibility to add tolerance for
power and ground rail supply net voltage values
for level shifter checks.
Filters Specifies filter patterns to filter some of the error
and warning messages.
Supply States Specifies supply states in a design. Use the Add
Supply State form.
Use Supply States Provides a choice to use supply states in a
design.
Similar Violations Limit Defines the maximum number of violations that
are similar and should be reported. The default
value is 1. If the value is 0, all similar violations
are reported.
Violations for ports without Performs checks for the boundary ports that do
attributes not have any associated attributes, such as driver
or receiver supply sets. By default, in-design
checks do not report violations at the boundary
ports unless information about the related power
and ground nets of the boundary ports is
specified using the registration information.
Violations for all net voltages Reports violations for all net voltages specified in
various supply states or different voltage values
registered in the Registered Supply Nets table
provided in the setup.

Isolation violations for always-on to Reports violations for a missing isolation cell at
switched supply crossings: the always-on to switched supply crossings.

August 2024 310 Product Version IC23.1

Export
The following table describes the fields available on the Export tab of the Power Manager
Setup form.

Section/Field Description
Supply Sets Specifies a list of supply sets by making a power
net and a ground net from the pair defined
explicitly in the setup as a supply set.
Power Domains Specifies a list of power domains associated with
the different sections of the design addressed by
a specific supply set.
Domain Name Prefix Specifies the prefix of the names being assigned
to the power domains.
Port Attributes Specifies a list of ports to avoid ambiguities during
the 1801 power intent extraction or the In-Design
checks to associate the boundary ports to a
power domain.
Consider inputOutput terms for Identifies supply nets, meeting the LDO net
internal power criterion detection criteria, even when the nets are
connected to inout pin/term.
Consider inputOutput terms for Identifies supply nets, meeting the monitor net
monitor power criterion detection criteria, even when the nets are
connected to inout pin/term.
Consider symmetrical source and Defines a port with a predefined supply set or
drain for supply tracing power domain that can be checked for the correct
or compatible connection at the receiver side.
Use anonymous supply for top level Enables the use of an anonymous supply for the
ports top-level ports instead of the default supply set.

August 2024 311 Product Version IC23.1

Miscellaneous
The following table describes the fields available on the Miscellaneous tab of the Power
Manager form.

Field Description
Delimiter Specifies specific notations for redirect netSets
created during the 1801 import flow, automatically
generated supply set and power domain names,
and so on
Switch View List Controls the order of the traversal of a design
hierarchy during power intent extraction.

Stop View List Defines the stop point where the design traversal
must be stopped by the extractor during power
intent extraction
Use Signal Type Uses the sigType attribute of nets for detecting
the supply nets during power intent extraction.
Load Setup From Environment Loads the setup information from the
environment. The project-level settings are
considered as a part of the final setup.
Use Setup Changes From Uses setup changes from the environment setup.
Environment Any changes that are done to the project-level
settings are read and updated.

Related Topics

Registering Name-Based Supply Nets

Registering Regular Expressions-Based Supply Nets

Registering Libraries

Registering Device and Cell

Registering Supply Set and Power Domain

Checking a Design in Background Mode

August 2024 316 Product Version IC23.1

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