Introduction to op-amp

INTEGRATED CIRCUITS

An integrated circuit (IC) is a miniature ,low cost electronic

circuit consisting of active and passive components fabricated
together on a single crystal of silicon. The active components are
transistors and diodes and passive components are resistors and
capacitors.
Advantages of integrated circuits
1. Miniaturization and hence increased equipment density.
2. Cost reduction due to batch processing.
3. Increased system reliability due to the elimination of soldered
joints.
4. Improved functional performance.
5. Increased operating speeds.
6. Reduction in power consumption

2
 OPERATION AMPLIFIER

An operational amplifier is a direct coupled high gain

amplifier consisting of one or more differential amplifiers,
followed by a level translator and an output stage.
It is a versatile device that can be used to amplify ac as well
as dc input signals & designed for computing mathematical
functions such as addition, subtraction ,multiplication,
integration & differentiation
Symbol of op-amp

3
IC op-amp packages
1. Metal can package.

2. Dual-in-line package.

3. Ceramic flat package.

Pin Details:
Linear IC’s Manufacturers
1. Fairchild - µA, µAF
2. National Semiconductor - LM, LH, LF, TBA
3. Motorola - MC, MFC
4. RCA - CA, CD
5. Texas Instruments - SN
6. Signetics - N/S, NE/SE
7. Burr-Brown - BB
Different classes of IC 741
1. 741 - Military grade op-amp (-55° to 125°C)
2. 741C - Commercial grade op-amp ( 0 to 70°/75°C)
3. 741A - Improved version of 741
4. 741E - Improved version of 741C
5. 741S - Military grade op-amp with higher slew rate
Ideal op-amp Characteristics
open loop voltage gain AOL = ∞
Input Impedance Ri = ∞
Output Impedance Ro = 0
Band width BW= ∞

• An ideal op-amp draws no current at both input terminals.

Because of infinite input impedance , any signal source can drive
it and there is no loading on the preceding driver stage
• Since gain is ∞ the voltage between inverting and non-inverting
terminals is essentially zero for finite output voltage Vo
• The output voltage Vo is independent of the current drawn
from the output as Ro = 0. The output thus can drive an infinite
number of other devices
 Basic Block Diagram of Op-Amp
An Op-Amp can be conveniently divided in to four main
blocks
1. An Input Stage or Input Diff. Amp.
2. The Gain Stage
3. The Level Translator
4. An Out put Stage
Note: It can be used to perform various mathematical
operations such as Addition, Subtraction, Integration,
Differentiation, log etc.

V1 Level Out put

Input Stage Gain Stage (CE
I /P (Diff. Amp.) Amp.) Shifter Stage VO
V2 (Buffer)

Op-Amp IC
Equivalent circuit of op-amp

Open loop operation

AC CHARACTERISTICS of OP-AMP – Slew Rate

Slew rate decides the speed of operation of the op-amp

 DC characteristics
Input offset current
The difference between the bias currents at the input
terminals of the op- amp is called as input offset current.
The input terminals conduct a small value of dc current to
bias the input transistors. Since the input transistors cannot
be made identical, there exists a difference in bias currents

Input offset voltage

A small voltage applied to the input terminals to make
the output voltage as zero when the two input terminals
are grounded is called input offset voltage

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Input bias current
Input bias current IB as the average value of the
base currents entering into terminal of an op-amp
IB=IB+ + IB- /2

THERMAL DRIFT
Bias current, offset current and offset voltage change
with temperature. A circuit carefully nulled at 25oc may
not remain so when the temperature rises to 35oc. This is
called drift.
 CMRR-(Common mode rejection ratio)
• CMRR is expressed in dB
• Figure shows the signal operation of differential amplifier
• The ability of a differential amplifier to reject common mode
input signals is expressed in terms of common mode rejection
ratio (CMRR).
• The common mode rejection ratio of a differential amplifier is
mathematically given as the ratio of differential voltage gain of
the differential amplifier to its common mode gain.
• CMRR = | Ad / Ac|
• Ideally, the common mode voltage gain of a differential
amplifier is zero. Hence the CMRR is ideally infinite.
• AC value in hybrid modeling is given by
• RE value is inversely proportional to AC
• If RE is ∞ then AC = 0 so CMMR = ∞. RE cannot be made high
due to practical Limitations
• Hence, CMRR is improved by employing current mirror circuit
instead of RE in the differential amplifier
 Ideal vs Practical Op-Amp
Ideal Practical
Open Loop gain A ∝ 105
Bandwidth BW ∝ 10-100kHz
Input Impedance Zin ∝ >1MΩ
Output Impedance Zout 0Ω 10-100 Ω
Output Voltage Vout Depends only Depends slightly
on Vd = on average input
(V+−V−) Vc = (V++V−)/2
Differential Common-Mode
mode signal signal

CMRR ∝ 10-100dB
Closed Loop Operation - The Inverting Amplifier:
Configuration

• The positive input is grounded.

• A “feedback network” composed of resistors R1 and R2
is connected between the inverting input, signal source
and amplifier output node, respectively.
• To analyze an op-amp feedback circuit:
• Assume no current flows into either input terminal
• Virtual ground at input side - Constrain: V+ = V-
 Inverting Amplifier : Voltage Gain
• The negative voltage gain
implies that there is a 1800
phase shift between both dc
and sinusoidal input and output
signals.
• The gain magnitude can be
greater than 1 if R2 > R1
• The gain magnitude can be less
than 1 if R1 > R2
• The inverting input of the op
amp is at ground potential
But is= i2 and v- = 0 (since vid= v+ - v-= 0) (although it is not connected
directly to ground) and is said to
and
be at virtual ground.
Inverting Amplifier: Input and Output
Resistances
Rout is found by applying a test current
(or voltage) source to the amplifier
output and determining the voltage (or
current) after turning off all
independent sources. Hence, vs = 0

But i1=i2

Since v- = 0, i1=0. Therefore vx = 0

irrespective of the value of ix .
 Inverting Amplifier: Example
• Problem: Design an inverting amplifier
• Given Data: Av= 40 dB, Rin = 20kΩ,
• Assumptions: Ideal op amp
• Analysis: Input resistance is controlled by R1 and voltage gain is set by
R 2 / R 1.
and Av = -100

A minus sign is added since the amplifier is inverting.

 The Non-inverting Amplifier:
Configuration

• The input signal is applied to the non-inverting input

terminal.
• A portion of the output signal is fed back to the negative
input terminal.
• Analysis is done by relating the voltage at v1 to input voltage
vs and output voltage vo .
 Non-inverting Amplifier: Voltage Gain, Input
Resistance and Output Resistance
Since i-=0 and

But vid =0

Since i+=0

Rout is found by applying a test current source to the amplifier output

after setting vs = 0. It is identical to the output resistance of the inverting
amplifier i.e. Rout = 0.
 Non-inverting Amplifier: Example
• Problem: Determine the output voltage and current for the given
non-inverting amplifier.
• Given Data: R1= 3kΩ, R2 = 43kΩ, vs= +0.1 V
• Assumptions: Ideal op amp
• Analysis:

Since i-=0,
Differential Amplifier:-
Frequency Response Analysis of
op-amp
• Ideally op-amp should have an infinite bandwidth
• It means if the open loop gain is 90dB with dc signal then it’s
gain remains same through audio and to high frequency radio
frequencies
• The practical op-amp gain, however decreases at higher
frequencies
• What cause for this? – Capacitive component in the equivalent
circuit
• This capacitance is due to the physical characteristics of the
devices (BJT or FET) used in the internal construction of op-amp
• For an op-amp with one break frequency , all the capacitor
effects can be represented by a single capacitor C as shown in
the following Figure. – high frequency model of op-amp
• One pole due to RoC
• Roll of rate -20dB/dec
• Open loop gain is obtained
as

• f1 is the corner frequency , the magnitude and phase angle

of the open gain are function of frequency
• Magnitude and phase angle are given as

• For frequency f<< f1 the magnitude of the gain is 20logAoL

in dB
• At f = f1 gain is 3 dB less than AOL , f1 is corner frequency
• For frequency f >> f1 the gain roll-off rate is -20 dB/decade
• From the phase characteristics – phase angle is zero at f = 0 and
at corner frequency -45° and at infinite frequency -90°
• Maximum phase change = -90° due to one break frequency
• The voltage transfer function is written as,

• A Practical op-amp has number of stages, each stage produce a

capacitive component.
• So op-amp may have different number of break frequencies
• Consider the T.F of an op-amp with three break frequencies
• Now,

• Frequency response is shown in figure

• From the figure we obtain that
• Frequency response is flat ( 90dB) from low frequencies to 200
kHz ( first break frequency)
• From 200 kHz to 2 MHz gain drops from 90 dB to 70 dB ( - 20
dB/decade roll – off rate)
• From 2 MHz to 20 MHz the roll – off rate is - 40 dB/decade
• As frequency is increasing , cascading effect of RC pole pair
come into effect and roll – off rate increases successively by -
20 dB/decade at each corner frequency
• Each RC pole pair introduces a lagging phase of maximum -90°
• In closed loop operation
• Characteristic equation
• Stability of op-amp will be affected during low gain operation
• Frequency compensation is required to avoid stability
problem in closed loop operation
 Frequency Compensation:-
(i) Dominant pole (ii) Pole-zero compensation
• Figure shows dominant pole configuration

(i) Now the T.F becomes

Applications of op-amp
Summing Amplifier

By choosing RF = Rin, we get Vout = - (V1+V2+V3)

If we choose, 3RF = Rin we get Vout = - (V1+V2+V3)/3
• Non – Inverting summing amplifier
Subtractor
Vo due to V2 alone
= - (R2/R1)V2
Vo due to V1 alone
= [1 + (R2/R1)]V+

Finally, Vo due to both inputs are the addition of above

individual outputs

If R1 = R2 then Vo = V1 – V2
• Voltage Follower:-

• Find the output voltage of the following Summing

Amplifier circuit.
 Integrator, V to I and I to V
converter and precession Rectifiers
Op-amp Integrator:-
• Fig shows the circuit of op-amp integrator

• Node B is at virtual ground and the current I is flowing through R

• Integrating both sides yield,
• Take Laplace transform of the above equation

• fb is the frequency at which gain of the integrator is 0 dB.

• At ω = 0 , The magnitude of the integrator T.F is ∞ and
capacitor Cf behaves as open circuit. At dc signal there won’t
be any –ve feedback hence, practical integrator is considered
Practical Integrator
• Gain of the integrator is limited at low frequency by shunting
the feedback capacitor Cf by resistance Rf

• Parallel combination of Rf and Cf acts as a practical capacitor. It

is called lossy integrator
• The resistance Rf limits the low frequency gain Rf /R1
• Nodal equation at the inverting input terminal is given by
• For s = jω gain of the integrator becomes,

• If ω = 0 now,
• The feedback resistor Rf limits the gain and prevents it from
becoming infinite for dc signals.
• The output signal of integrator is linear not like an ordinary
RC circuit (Exponential for normal RC network)
• It is explained as follows
• Charge on the capacitor

• In terms of voltage

• So

• The above equation resembles straight line equation y=mx

• Here,
• Ic = Iin , so Iin is constant so Ic charges the capacitor linearly
 voltage to current converter
1. Floating load type
2. Grounded load type
Floating load type V to I converter
Grounded load type V to I Converter
Current to voltage converter
• Photodiode, photocell and photovoltaic cell give an output
current that is proportional to an incident radiant energy or
light
• The current through the device can be converted into
voltage by I to V converter

• Cf is shunted to reduce high frequency noise

• An ordinary diode cannot rectify voltages less than 0.7 V cut-in
voltage of diode
• A circuit that acts like an ideal diode can be designed by
placing a diode in the feedback loop of an op-amp
• Now the cut-in voltage is divided by open loop gain of an op
amp 0.7/∞ = 0
• This circuit is called precession diode and is capable of
rectifying input signals of the order of milli volts
• It is called precession rectifier
Half wave Rectifier
Precession full wave rectifier

Case-1
• If Vi > 0,
Case-2 if Vi < 0 then the circuit can be redrawn as follows
Clipper and Clamper
Clipper: - Positive clipper
• Circuit that removes the positive part of the input signal is
called positive clipper
• Figure shows the circuit of positive clipper and its waveform
• Clipping level is set by Vref
• For input voltage < Vref diode conducts and op-amp act as a
voltage follower hence, Vo = Vin
• For Vin > Vref diode reverse biased and circuit operate in open
loop mode, which drive op-amp to saturation
• Now Vo remains at Vref and entire waveform above Vref gets
clipped off.
Negative clipper:-
Clamper:-
• Sometimes it is necessary to add a dc level to the ac output
signal. The circuit which is doing the same is called clamper
circuit it is also called as a restorer
• If the clamped dc level is +ve, the circuit is called positive
clamper and if clamped dc level is –ve , the circuit is called
negative clamper
• In this circuit, the input waveform peak is clamped at V ref. For this
reason, the circuit is called the peak clamper.
• First consider the input voltage Vref at the (+) input: since this
volt is +ve, V0 is also +ve which forward biases D1. This closed the
feedback loop.
• Voltage Vin at the (-) input: During its –ve half cycle, diode
D1 conducts, charging c; to the –ve peak value of Vp. During the
+ve half cycle, diode D1 in reverse biased.
• Since this voltage Vp is in series
with the +ve peak volt Vp the o/p
volt V0 = 2 Vp.
• Thus the nett o/p is Vref plus 2 Vp.
• So the – ve peak of 2 Vp is at Vref
Peak detector:-
• Compute the peak value of the input signal
• The circuit follows the voltage peaks of a signal and stores the
highest value on a capacitor
• This value is stored until capacitor is discharged

• When Vi exceeds Vc ( voltage across the capacitor) the diode D

gets forward biased and the circuit becomes voltage follower
• Now Vo follows Vi hence, the capacitor charged to a new peak
• When Vi drops below Vc the diode becomes reverse biased and
the capacitor holds the charge till the input voltage again
attains a value greater than Vc
• The circuit can be reset by closing the low leakage MOSFET
switch
• Used in communication and measurement and instrumentation
circuits.
Sample and Hold Circuit:-
• This circuit samples an input signal and holds on to its last
sampled value until the input signal is sampled again
• In this circuit, n channel E-MOSFET is used as a switch and
controlled by a control voltage Vc
• The capacitor C stores the charge
• The analog signal Vi to be sampled is applied to the drain of
E-Mosfet and Vc is applied to gate

• When Vc is +ve, E- MOSFET turns on and the capacitor charged

to a instantaneous value of input Vi with time constant [Ro+
rDS(on)]C
• When Vc is zero E-MOSFET is OFF. now capacitor C faces high
input impedance of the voltage follower A2 and cannot
discharge . The capacitor holds the voltage across it.
• Time period Ts is the time during which voltage across the
capacitor is equal to input voltage is called sample period
• Time period TH of Vc during which the voltage across the
capacitor is held constant is called hold period
• Frequency of Vc > 2 time signal frequency (sampling theorem)
Log and Antilog Amplifiers
Log Amplifier:-

• Grounded base transistor is placed in the feedback path

• The transistor voltage current relationship is given by
• Is will vary from transistor to
transistor , Vref is set externally
Antilog Amplifier:-
• Input Vi for antilog amplifier is fed into the temperature
compensating voltage divider circuit
• The base to emitter voltage of
Transistor Q1 and Q2 can be
written as

• Since base of Q1 is grounded

Comparator and Schmitt Trigger
Schmitt Trigger:-
Schmitt Trigger with Different UTP and LTP Levels:
• The circuit diagram is shown below where additional voltage
source is connected
Triangular wave generator
• Initially consider the output of comparator A1 is at +Vsat and the
output of A2 will be a negative going ramp as shown in Fig.b
• At time t = t1, when the – ve going ramp attains the value of –Vramp
the effective voltage at point ‘P’ becomes slightly less than 0 V.
• This switches the output of A1 from +Vsat to – Vsat
• During the time when the o/p of A1 is at – Vsat , the output of A2
increases in the +ve direction
• At instant t = t2 the voltage at point ‘P’ becomes just above 0 V
thereby switching the output of A1 from – Vsat to + Vsat and this
cycle repeats and generate triangular waveform
• Frequency of triangular waveform depends on the frequency
of square waveform
• Triangular wave amplitude depends on the RC value of the
integrator
• The effective voltage at point P during the time when output of
A1 is at +Vsat is given by
Oscillators
Oscillators:

• Barkhausen criterion

∠βA should be 0◦ or 360◦

Weinbridge Oscillator:
• Simplified diagram of Wein bridge oscillator is shown below

• Feedback network is connected in the form of bridge

• When the bridge is balanced the phase shift becomes zero
and the circuit is set to oscillation.
• The series and parallel combination of RC network form a lead
lag network and it results in zero phase shift
• Here the negative feed back is used for stability gain
• Apply voltage divider rule in the feedback path, results in
• Now,
• -ve Feedback yields,
• Now,
RC Phase Shift Oscillator:-
• Substitute in the above equation yields,

• Conditions for sustained oscillations, Barkhausens criteria

• Now,