UNIT 2

EMBEDDED HARDWARE DESIGN

Syllabus:

Analog and digital electronic components, I/O types and examples, Serial communication
devices, Parallel device ports, Wireless devices, Timer and counting devices, Watchdog timer,
Real time clock.

Introduction to Embedded hardware:

The hardware of embedded system is built around analog electronic components and circuits,
digital electronic components and circuits, and integrated circuits. A printed circuit board
provides a plat form for placing all the necessary hardware components for building an
embedded product.

For commercial product you cannot go for a bread board as an interconnection platform since
they make your product bulky and the bread board connections are highly unstable back bone of
embedded hardware. In this chapter is organized in such a way to refresh the student knowledge
on various analog and digital electronic components and circuits, familiarize them with
integrated circuit designing and provide them fundamentals of printed circuit boards, its design
and development using electronic design automation.

Analog Electronic components and circuits

Resistors, capacitors, diodes, inductors, operational amplifiers (OpAmps), transistors, etc. are the
commonly used analog electronic components in embedded hardware design.

A resistor limits the current flowing through a circuit. Interfacing of LEDs, buzzer, etc. with the
port pins of microcontroller through current limiting resistors is a typical example for the usage
of resistors in embedded application.

Capacitors & Inductors

 Capacitors and inductors are used in signal filtering and resonating circuits.
  Reset circuit implementation, matching circuits for RF designs, power supply
decoupling, etc. are examples for the usage of capacitors in embedded hardware circuit.
 Electrolytic capacitors, ceramic capacitors, tantalum capacitors, etc. are the commonly
used capacitors in embedded hardware design
 Inductors are widely used for filtering the power supply from ripples and noise signals.
 Inductors with inductance value in the microhenry (𝜇𝐻) range are commonly used in
embedded applications for filter and matching circuit implementation.
Diodes

 P-N Junction diode, Schottky diode, Zener diode, etc. are the commonly used diodes in
embedded hardware circuits
 A schottky diode is same as a P-N Junction diode except that its forward voltage drop
(voltage drop across diode when conducting) is very low (of the order of 0.15V to 0.45)
when compared to ordinary P-N junction diode (of the order of 0.7V to 1.7V).
 Also the current switching time of schottky diode is very small compared to the ordinary
P-N junction diode
 A zener diode acts as normal P-N junction diode when forward biased
 It also permits current flow in the reverse direction, if the voltage is greater than the
junction breakdown voltage
 It is normally used for voltage clamping applications
 Reverse polarity protection, voltage rectification (AC-DC converters), freewheeling of
current produced in inductive circuits, clamping of voltages to a desired level (e.g.,
Brown- out protection circuit implementation using zener diode), etc. are examples for
the usage of diodes in embedded applications.
Transistors

 Transistors in embedded applications are used for either switching or amplification

purpose.
 In switching application, the transistor is in either ON or OFF state.
 In amplification operation, the transistor is always in the ON state (partially ON).
 The common emitter configuration of NPN transistor is widely used in switching and
driving circuits in embedded applications
 Relay, buzzer and stepper motor driving circuits are examples for common emitter
configuration based driver circuit implementation using transistor.

DIGITAL ELECTRONIC COMPONENTS

 Digital electronics deal with digital or discrete signals. Microprocessors, microcontrollers

and system on chips (SoCs) work on digital principles. They interact with the rest of the
world through digital I/O interfaces and process digital data. Embedded systems employ
various digital electronic circuits for 'Glue logic' implementation. 'Glue logic' is the
custom digital electronic circuitry required to achieve compatible interface between two
different integrated circuit chips. Address decoders, latches, encoders/decoders, etc. are
examples for glue logic circuits. Transistor Transistor Logic (TTL), Complementary
Metal Oxide Semiconductor (CMOS) logic etc are some of the standards describing the
electrical characteristics of digital signals in a digital system. The following sections give
an overview of the various digital I/O interface standards and the digital
circuits/components used in embedded system development.

Open Collector and Tri-State Output

 Open collector is an I/0 interface standard in digital system design. The term 'open
collector' is commonly used in conjunction with the output of an Integrated Circuit (IC)
chip. It facilitates the interfacing of IC output to other systems which operate at different
voltage levels. In the open collector configuration, the output line from an IC circuit is
connected to the base of an NPN transistor. The collector of the transistor is left
unconnected (floating) and the emitter is internally connected to the ground signal of IC.
Figure 8.1 illustrates an open collector output configuration.
 For the output pin to function properly, the output pin should be pulled, to the desired
voltage for the oip device, through a pull-up resistor. The output signal of the IC is fed to
the base of an open collector transistor. When the base drive to the transistor is ON and
the collector is in open state, the oip pin floats. This state is also known as 'high
impedance' state. Here the output is neither driven to logic 'high' nor logic 'low'. If a pull-
up resistor is connected to the oip pin, when the base drive is ON, the o/p pin becomes at
logic 0 (0V). With a pull-up resistor, if the base driver is 0, the o/p will be at logic high
(Voltage = lc). The advantage of open collector output in embedded system design is
listed below.
 I. It facilitates the interfacing of devices, operating at a voltage different from the IC, with
the IC. Thereby, it eliminates the need for additional interface circuits for connecting
devices at different voltage levels,
 An open collector configuration supports multi-drop connection, i.e., connecting more
than one open collector output to a single line. It is a common requirement in modern
embedded systems supporting communication interfaces like I2C, 1-Wire, etc. Please
refer to the various interfaces described in Chapter 2 under the section 'Onboard
Communication Interfaces'.
 It is easy to build 'Wired AND' and 'Wired OR' configuration using open collector output
lines.
 The output of a standard logic device has two states, namely 'Logic 0 (LOW)' and 'Logic
1 (HIGH), and the output will be at any one of these states at a given point of time, where
as tri-state devices have three states for the output, namely, `Logic 0 (LOW)', 'Logic I
(HIGH) and 'High Impedance (FLOAT)'. A tri-state logic device contains a device
activation line called 'Device Enable'. When the 'Device Enable' line is activated (set at
'Logic l' for an active 'HIGH' enable input and at 'Logic 0' for an active 'LOW' enable
input), the device acts like a normal logic device and the output will be in any one of the
logic conditions, 'Logic 0 (LOW)' or 'Logic I (HIGH)'. When the 'Device Enable' line is
de-activated (set at 'Logic 0' for an active 'HIGH' enable input and at 'Logic I' for an
active 'LOW' enable input), the output of the logic device enters in a high impedance
state and the device is said to be in the floating state. The tri-stated output condition
produces the effect of 'removing' the device from a circuit and allows more than one
 devices to share a common bus. With multiple "tri-stated' devices share a common bus,
only one 'device' is allowed to drive the bus (drive the bus to either 'Logic 0' or 'Logic 1')
at any given point of time and rest of the devices should be in the ‘tri-stated' condition.

Logic Gates:

 Logic gates are the building blocks of digital circuits. Logic gates control the flow of
digital information by performing a logical operation of the input signals. Depending on
the logical operation, the logic gates used in digital design are classified into—AND, OR,
XOR, NOT, NAND, NOR and XNOR. The logical relationship between the output signal
and the input signals for a logic gate is represented using a truth table.

Buffer:

A buffer circuit is a logic circuit for amplifying the current or power. It increases the driving
capability of a logic circuit. A tri-state buffer is a buffer with Output Enable control. When the
Output Enable control is active (Low for Active low enable and High for Active high enable),
the in-state buffer functions as a buffer. If the Output Enable is not active, the output of the
buffer remains at high impedance state (Tr-stated). Tr-state buffers are commonly used as drivers
for address bus and to select the required device among multiple devices connected to a shared
data bus. Tr-state buffers are available as either unidirectional or bi-directional buffers.
74LS244/74HC244 is an example of unidirectional octal buffer. It contains 8 individual buffers
which are grouped into two. Each buffer group has its own output enable line, Figure 8.3
illustrates the 74LS244 buffer device.

IC 74LS245 is an example of hi-directional tri-state buffer. It allows data flow in both directions,
one at a time. The data flow direction can be set by the direction control line. One buffer is
allocated for the data line associated with each direction. Figure 8.4 illustrates the 74LS245 octal
bi-directional buffer.

Latch:

A latch is used for storing binary data. It contains an input data line, clock or gating control line
for triggering the latching operation and an output line. The gating signal can be either a positive
edge (raising edge) or a negative edge (falling edge). Whenever a latch trigger happens , the data
present on the input line is latched. The latched data is available on the output line of the latch
until the next trigger. D flip flop is a typical example of a latch. In electronic circuits, latches are
commonly used for latching data, which is available only for a short duration. A typical example
is the lower order address information in a multiplexed address data bus system. Latches are
available as integrated circuits, IC 74LS373 being a typical example. It contains 8 individual D
latches.

The 74LS373 latch IC is commonly used for latching the lower order address byte in a
multiplexed address data bus system. The address latch enable pulse generated by the processor,
when the address bits are available on the multiplex bus is used as the latch trigger.
Decoder:

A Decoder is a logic circuit which generates all the possible combinations of the input signals.
Decoders are named with their input line numbers and the possible combinations of the input as
output.
 Input Output

0
A1 A1 Ao E1\ E2\ E\ 0OI\ 02\ 03\ 04\ 05\ 06\ 07\
\

0 0 0 0 0 1 01 1 1 1 1 1 1

0 0 1 0 0 1 0 1 1 1 1 1 1

0 1 0 0 0 I 11 0 1 1 1 1 1

0 1 1 0 0 1 11 1 0 1 1 1 1

1 0 0 0 0 1 1I 1 1 0 1 1 1

1 0 1 0 0 1 I1 1 1 1 0 1 1

1 1 0 0 0 1 11 1 1 1 1 0 1

1 1 1 0 0 1 11 1 1 1 1 1 0

The decoder output is enabled only when the 'Output Enable' signal lines EIA, E2\ and E3 are at
logic levels 0, 0 and 1 respectively. If the output-enable signals are not at the required logic state,
all the output lines are forced to the inactive (High) state. The output line corresponding to the
input state is asserted 'Low' when the 'Output Enable' signal lines are at the required logic state
(Here El\=E2\=0 and E3 =1). The output line can be directly connected to the chip select pin of a
device, if the chip select logic of the device is active low.

Encoder:

An encoder performs the reverse operation of decoder. The encoder encodes the corresponding
input state to a particular output format. The binary encoder encodes the input to the
corresponding binary format. Encoders are named with their input line numbers and the encoder
output format. Examples are 4 to 2 encoder, 8 to 3 encoder and 16 to 4 encoder. The 8 to 3
encoder contains 8 input signal lines and it is possible to generate a 3 bit binary output
corresponding to the input (e.g. inputs 0 to 7 are encoded to binary 111 to 000 in the output
lines). The corresponding output line is asserted in accordance with the input signals. For
example, if the input line 1 is asserted, the output lines AO. Al and A2 are asserted as 0, 1 and I
respectively. Encoders are mainly used for address decoding and chip select signal generation in
electronic circuits and are available as integrated circuits. 74F148/74LS148 is an example of 8 to
3 encoder IC. Figure 8.8 illustrates the 74F148/74LS148 encoder and the function table for it.

The encoder output is enabled only when the 'Enable Input (El)' signal line is at logic 0. A 'High'
on the Enable Input (El) forces all outputs to the inactive (High) state and allows new data to
settle without producing erroneous information at the outputs. The group signal (GS) is active-
Low when any input is Low: this indicates when any input is active. The Enable Output (EO) is
active-Low when all inputs are at logic 'High'. 74LS148/74F148 is a priority encoder and it
provides priority encoding of the inputs to ensure that only the highest order data line is encoded
when multiple data lines are asserted (e.g., when both input lines 1 and 6 are asserted, only 6 is
encoded and the output will be It should be noted that the encoded output is an inverted value of
the corresponding binary data. (e.g., the output lines A2, Al and AO will be at logic levels 000
when the input 7 is asserted). Encoding of keypress in a keyboard is a typical example for an
application requiring encoder. The encoder converts each keypress to a binary code.

Multiplexer

A multiplexer (MUX) can be considered as a digital switch which connects one input line from a
set of input lines, to an output line at a given point of time. It contains multiple input lines and a
single output line. The inputs of a MUX are said to be multiplexed. It is possible to connect one
input with the output line at a time The input line is selected through the MUX control lines
74S151 is an example for 8 to 1 multiplexer IC.

De-MUX

A de-multiplexer performs the reverse operation of multiplexer. De-multiplexer switches the

input sig¬nal to the selected output line among a number of output lines. The output line to
which the input is to be switched is selected by the output selector control lines. The 1 to 2 de-
multiplexer, NL7SZ I 8 is a typical example for l to 2 de-multiplexer IC. It contains a single
input line and two output lines to switch the input line. The output switching is controlled by the
output selector control. Figure 8.10 illustrates the NL7SZ 18 de-multiplexer and the function
table for it.

Combinational Circuits

In digital system design, a combinational circuit is a combination of the logic gates. The output
of the combinational circuit, at a given point of time, is dependent only on the state of the inputs
at the given point of time. Encoders, decoders, multiplexers, de-multiplexers, adder circuits,
comparators, multiple input gates, etc. are examples of digital combinational circuits. The design
requirements for a combi-national circuit are expressed as 'A set of statements' or 'Truth Table' or
'Boolean Expressions'. The combinational circuit can be implemented either by simplifying the
Boolean expression/Truth table and realizing the simplified expression using logic gates or by
directly implementing the logic expressions using an 'Off-the-shelf Medium Scale Integrated
Circuit Chip. Various logic simplification techniques like `Karnaugh Map (K Map)', 'Algebraic
method', 'Variable Entered Mapping (VEP)' and 'Quine-Mc-Cluskey method,' etc. are used for
the simplification of logic expressions.
In digital system design, logical functions representing a combinational circuit are expressed as
either 'Sum of Products (SOP)' or 'Product of Sums (POS)' form. The SOP form represents the
logic as the sum of the products of the logical variables whereas the POS form represents the
logic as the product of sums of the logical variable.

The expression Y= AB + BC+ AC is an example for SOP form representation of the logical
function. Here Y is the output signal and A, B and C are the input signals.

The expression Y = (A+B) (LOC) (A+C) is an example for POS form representation of the
logical function. Here Y is the output signal and A, B and C are the input signals.

‘Karnaugh map' or K-map is the easiest logic simplification technique for arriving at the logic
ex- pression when the 'Truth Table' of the combinational circuit is given. Depending on the
number of input signal variables. K-maps are named as 2-variable, 3-variable, 4-variable, etc. K-

map is the most suitable for handling input variables upto 6

Sequential Circuits

Digital logic circuit, whose output at any given point of time depends on both the present and
past inputs, is known as sequential circuits. Hence sequential circuits contain a memory element
for holding the previous input states.
Flip-flops act as the basic building blocks of sequential circuits. Sequential circuits are of two
types, namely—synchronous Inputs and asynchronous sequential circuits. The operation of a
synchronous sequential circuit is synchronized to a clock signal, whereas an asynchronous
sequential circuit does Elements not require a clock for operation.

For an asynchronous sequential circuit, the response depends upon the sequence in which the
input. The memory capability to asynchronous Sequential Circuit is provided through feedback.
Register, synchronous counters, etc. are examples of synchronous serial circuits, whereas ripple
or asynchronous counter is an example for asynchronous sequential circuits.

Now let us have a look at how a flip-flop circuit acts as a memory storage element. The name
flip- flop is conveying its intended purpose. It tumbles the output based on the input and other
controlling signals. As a starting point on the discussion of flip-flops, let us talk about Set Reset
(S-R) flip-flop. The logic circuit and the I/0 states for an S-R flip-flop .

The S-R flip-flop is built using 2 NOR gates. The output of each NOR gate is fed back as input to
the other NOR gate, This ensures that if the output of one NOR gate is at logic 1, the output of
the other NOR gate will be at logic 0. The S-R flip-flop works in the following way.

1. If the Set input (S) is at logic high and Reset input (R) is at logic low, the output
remains at logic high regardless of the previous output state.

2. If the Set input (S) is at logic low and Reset input (R) is at logic high, the output
remains at logic low regardless of the previous output state.

3. If both the Set input (S) and Reset input (R) are at logic low, the output remains at the
previous logic state.
 4. The condition Set input (S) = Reset input (R) = Logic high (1) will lead to race
condition and the state of the circuit becomes undefined or indeterminate (x).

A clock signal can be used for triggering the state change of flip-flops. The clock signal can be
either level triggered or edge triggered. For level triggered flip-flops, the output responds to any
changes in input signal, if the clock signal is active (i.e., if the clock signal is at logic 1 for
'HIGH' level triggered and at logic 0 for 'LOW' level triggered clock signal). For edge triggered
flip-flops, the output state changes only when a clock trigger happens regardless of the changes
in the input signal state. The clock trigger signal can be either a positive edge (A 0 to 1
transition) or a negative edge (A 1 to 0 transitions). Figure 8.16 illustrates the implementation of
an edge triggered S-R flip-flop.

IO port types - Serial and serial and parallel IO ports parallel IO ports

• A port is a device to receive the bytes from external peripheral(s) [or device(s) or
processor(s) or controllers] for reading them later using instructions executed on the
processor to send the bytes to external peripheral or device or processor using
instructions executed on processor.

• A Port connects to the processor using address decoder and system buses. The processor
uses the addresses of the port-registers for programming the port functions or modes,
reading port status and for writing or reading bytes.

• A port is a device to receive the bytes from external peripheral(s) [or device(s) or
processor(s) or controllers] for reading them later using instructions executed on the
processor or to send the bytes to external peripheral or device or processor using
instructions executed on processor.
• A Port connects to the processor using address decoder and system buses. The processor
uses the addresses of the port-registers for programming the port functions or modes,
reading port status and for writing or reading bytes.
Types of Serial ports

 Synchronous Serial Input

 Synchronous Serial Output
 Asynchronous Serial UART input
 Asynchronous Serial UART output
 Both as input and as output, for example, modem.
Types of parallel ports

 Parallel port one bit Input

 Parallel one bit output
 Parallel Port multi-bit Input
 Parallel Port multi-bit Output
Synchronous Serial Input Example

Inter-processor data transfer, reading from CD or hard disk, audio input, video input, dial tone,
network input, transceiver input, scanner input, remote controller input, serial I/O bus input,
writing to flash memory using SDIO (Secure Data Association IO based card)

Synchronous Serial Input

 The sender along with the serial bits also sends the clock pulses SCLK (serial clock) to
the receiver port pin. The port synchronizes the serial datainput bits with clock bits. Each
bit in each byte as well as each byte in synchronization
  Synchronization means separation by a constant interval or phase difference. If clock
period = T, then each byte at the port is received at input in period = 8T.
 The bytes are received at constant rates. Each byte at input port separates by 8T and data
transfer rate for the serial line bits is (1/T) bps. [1bps = 1 bit per s]
Serial data and clock pulse –inputs

 On same input line − when clock pulses either encode or modulate serial data input
bits suitably. Receiver detects the clock pulses and receives data bits after decoding
or demodulating.
 On separate input line − When a separate SCLK input is sent, the receiver detects at
the middle or + ve edge or –ve edge of the clock pulses that whether the data-input is
1 or 0 and saves the bits in an 8-bit shift register. The processing element at the port
(peripheral) saves the byte at a port register from where the microprocessor reads the
byte.
Master output slave input (MOSI) and Master input slave output (MISO)

 MOSI when the SCLK is sent from the sender to the receiver and slave is forced to
synchronize sent inputs from the master as per the inputs from master clock.
 MISO when the SCLK is sent to the sender (slave) from the receiver (master) and slave is
forced to synchronize for sending the inputs to master as per the master clock outputs.
 Synchronous serial input is used for interprocessor transfers, audio inputs and streaming
data inputs.

Synchronous Serial Output

  Each bit in each byte sent in synchronization with a clock.
 Bytes sent at constant rates. If clock period = T, then data transfer rate is (1/T) bps.
 Sender either sends the clock pulses at SCLK pin or sends the serial data output and
clock pulse-input through same output line with clock pulses either suitably modulate
or encode the serial output bits.
Synchronous serial output using shift register

 The processing element at the port (peripheral) sends the byte through a shift register at
the port to where the microprocessor writes the byte.
 Synchronous serial output is used for interprocessor transfers, audio outputs and
streaming data outputs.

Synchronous Serial Input/Output

 Each bit in each byte is in synchronization at input and each bit in each byte is in
synchronization at output with the master clock output .
 The bytes are sent or received at constant rates. The I/Os can also be on same I/O line
when input/output clock pulses either suitably modulate or encode the serial input/output,
respectively. If clock period = T, then data transfer rate is (1/T) bps.
 The processing element at the port (peripheral) sends and receives the byte at a port
register to or from where the microprocessor writes or reads the byte
Asynchronous Serial port line RxD (receive (receive data).

 Does not receive the clock pulses or clock information along with the bits.
 Each bit is received in each byte at fixed intervals but each received byte is not in
synchronization.
  Bytes separate by the variable intervals or phase differences
 Asynchronous serial input also called UART input if serial input is according to UART
protocol
 Asynchronous serial input is used for keypad inputs and modem inputs in computers
 Keypad controller serial data-in, mice, keyboard controller, modem input, character send
inputs on serial line [also called UART (universal receiver and transmitter) input when
according to UART mode]

UART protocol serial line format

 Starting point of receiving the bits for each byte is indicated by a line transition from 1 to
0 for a period = T. [T − 1 called baud rate.]
 If sender’s shift-clock period = T, then a byte at the port is received at input in period =
10.T or 11.T due to use of additional bits at start and end of each byte.
UART protocol serial line format

 Receiver detects n bits at the intervals of T from the middle of the start indicating bit. The
n = 0, 1, …, 10 or 11 and finds whether the data-input is 1 or 0 and saves the bits in an 8-
bit shift register.
 Processing element at the port (peripheral) saves the byte at a port register from where
the microprocessor reads the byte.
Asynchronous Serial Output

 Asynchronous output serial port line TxD (transmit data).

 Each bit in each byte transmit at fixed intervals but each output byte is not in
synchronization (separates by a variable interval or phase difference). Minimum
separation is 1 stop bit interval
TxD

 Does not send the clock pulses along with the bits.
 Sender transmits the bytes at the minimum intervals of n.T. Bits receiving starts from the
middle of the start indicating bit,
 n = 0, 1, …, 10 or 11 and sender sends the bits through a 10 or 11 -bit shift register.
 The processing element at the port (peripheral) sends the byte at a port register to where
the microprocessor is to write the byte.
  Synchronous serial output is also called UART output if serial output is according to
UART protocol
 Eg: Output from modem, output for printer, the output on a serial line [also called UART
output when according to UART]
Half Duplex

 Half duplex means as follows: at an instant communication can only be one way (input or
output) on a bi-directional line.
 An example of half-duplex mode ─ telephone communication. On one telephone line, the
talk can only in the halfduplex way mode.
Full Duplex

 Full duplex means that at an instant, the communication can be both ways. An example
of the full duplex asynchronous mode of communication is the communication between
the modem and the computer though TxD and RxD lines or communication using SI in
modes 1, 2 and 3 in 8051.
Parallel Port single bit input

 Completion of a revolution of a wheel,

 Achieving preset pressure in a boiler,
 Exceeding the upper limit of permitted weight over the pan of an electronic balance,
 Presence of a magnetic piece in the vicinity of or within reach of a robot arm to its end
point and
 Filling of a liquid up to a fixed level.
Parallel Port Output- single bit single bit

 PWM output for a DAC, which controls liquid level, or temperature, or pressure, or speed
or angular position of a rotating shaft or a linear displacement of an object or a d.c. motor
control
 Pulses to an external circuit
 Control signal to an external circuit
Parallel Port Input- multi-bit

 ADC input from liquid level measuring sensor or temperature sensor or pressure sensor
or speed sensor or d.c. motor rpm sensor
 Encoder inputs for bits for angular position of a rotating shaft or a linear displacement of
an object
Parallel Port Output- multi-bit

 LCD controller for Multilane LCD display matrix unit in a cellular phone to display on
the screen the phone number, time, messages, character outputs or pictogram bit-images
for display screen or e-mail or web page
 Print controller output
 Stepper-motor coil driving bits
Parallel Port Input-Output

 PPI 8255
 Touch screen in mobile phone
Timer and counting devices:

Like a computer system, all embedded system need at least one timing device (for system clock)
Real Time Clock, Pulse Accumulator Counter, Watchdog Timer, Serial Communication rate
control timer, OS timer for task scheduling Both hardware timers and software timers are used in
the systems.

Timer

A device, which counts the input at T) using clock pulsesregular interval ( at its input. The
counts increment on each pulse . Store in a register, called count register. Output bits (in a count
register or at the output pins) for the present counts. The counts multiplied by the interval T give
the time. initial counts). The (present counts T interval gives the time interval between two
instances when present count bits are read and initial counts were read or set. It has an input pin
(or a control bit in control register) for resetting it for all count bits = 0s. Has an output pin (or a
status bit in status register) for output when all count bits = 0s after reaching the maximum
value, which also means after timeout or overflow.
Uses of a Timer

Real Time Clock Ticks (System Heart Beats) Real Time clock:

A clock does not stop once the system starts, cannot be reset and its count value cannot be
reloaded. Initiating an event after a preset delay time. Delay is as per count value loaded.
Initiating an event after a comparison between the preset time with a counted value. Preset time
is loaded in comparison register. Capturing a count value at the timer on an event. The
information time is stored in capture register. Finding a time interval between two events. Time
is captured at each event and intervals are then found. Wait for a message from a queue or
mailbox or semaphore for a preset time when using RTOS. There is a predefined waiting period
before RTOS starts to run. Watchdog timer. It resets the system after a define time. Baud or Bit
rate control for serial communication on a line or network. Timer timeout interrupts define the
time δT of each baud or ΔT for each bit. Input pulse counting when using a timer, which is
ticked by giving non- periodic inputs instead of clock inputs. The timer acts as a counter for the
inputs given to it for each instance to be counted.
Scheduling of various tasks. A chain of software timers interrupt & RTOS uses these interrupts
to schedule the tasks. Time slicing of various tasks. RTOS switches after preset time delay from
one running task to the next. Each task can therefore run in predefined slot of time. Time
Division

Multiplexing. Timer used for multiplexing the input from a number of channels. Each channel
input is allotted a distinct and fixed- time slot to get a TDM output.

Hardware Timers

There can be limited number of hardware present in the system. The system has at least one
hardware timer. The system clock is configured from this. A microcontroller may have 2, 3 or 4
hardware timers. One of the hardware timers ticks from the inputs from the internal clock of the
processor and generates the system clock. Using the systems clock or internal clock, the number
of hardware timers that are present cab be driven. These timers are programmable by the device
driver programs.

Counter

It is a device which counts the input due to the events at irregular or regular intervals. The counts
give the number of input events or pulses since it was last read. It has a register to enable read of
present counts. It functions as timer when counting regular interval clock pulses. It has an input
pin (or a control bit in control register) for resetting it for all count bits = 0s. Has an output pin
(or a status bit in status register) for output when all count bits = 0s after reaching the maximum
value, which also means after timeout or overflow.

Free Running Counter

It is useful

 for action or initiating chain of actions,

 processor interrupts at the preset instances noting the instances of occurrences of the
events
 processor interrupts for requesting the processor to use the capturing of counts at the
input instance
 comparing of counts on the events for future actions
Watchdog timer

A timing device such that it is set for a preset time interval and an event must occur during that
interval else the device will generate the timeout signal on failure to get that event in the watched
time interval. On that event, the watchdog timer is disabled to disable generation of timeout or
reset .Timeout may result in processor start a service routine or start from beginning .Assume
that we anticipate that a set of tasks must finish in 100 ms interval. The watchdog timer is
disabled and stopped by the program instruction in case the tasks finish within 100 ms interval.
In case task does not finish (not disabled by the program instruction), watchdog timer generates
interrupts after 100 ms and executes a routine, which is programmed to run because there is
failure of finishing the task in anticipated interval.

A watchdog timer (WDT; sometimes called a computer operating properly or COP timer, or
simply a watchdog) is an electronic timer that is used to detect and recover from computer
malfunctions. During normal operation, the computer regularly restarts the watchdog timer to
prevent it from elapsing, or "timing out". If, due to a hardware fault or program error, the
computer fails to restart the watchdog, the timer will elapse and generate a timeout signal. The
timeout signal is used to initiate corrective action or actions. The corrective actions typically
include placing the computer system in a safe state and restoring normal system operation.
Watchdog timers are commonly found in embedded systems and other computer-controlled
equipment where humans cannot easily access the equipment or would be unable to react to
faults in a timely manner. In such systems, the computer cannot depend on a human to reboot it
if it hangs; it must be self-reliant. For example, remote embedded systems such as space probes
are not physically accessible to human operators; these could become permanently disabled if
they were unable to autonomously recover from faults. A watchdog timer is usually employed in
cases like these. Watchdog timers may also be used when running untrusted code in a sandbox,
to limit the CPU time available to the code and thus prevent some types of denial-of-service
attacks.

Application :

An application in mobile phone is that display is off in case no GUI interaction takes place
within a watched time interval. The interval is usually set at 15 s, 20 s, 25 s, 30 s in mobile phone
.This saves power.

Real time clock

A real-time clock (RTC) is a computer clock (most often in the form of an integrated circuit) that
keeps track of the current time. Although the term often refers to the devices in personal
computers, servers and embedded systems, RTCs are present in almost any electronic device
which needs to keep accurate time. It is a

 A clock based on the interrupts at preset intervals

 An interrupt service routine executes on each timeout (overflow) of this clock
 A timing device once started never resets or never reloaded with another value
 Once it is set, it is not modified later.
 Used in a system to save the time and date.
 Used in a system to initiate return of control to the system (OS) after the set system clock
period

RTC Application

 Assume that a hardware timer of an RTC for calendar is programmed to interrupt after
every 5.15 ms (=1 day period/ 2 24)
  Assume each tick (interrupt) a service routine runs and updates at a memory location.
Within one day (86400 s) there will be 2 24 ticks, the memory location will reach
0x000000 after reaching the maximum value 0xFFFFFF.
RTC with 5.5 ms tick

 Within 256 days there will be 2 32 ticks, the memory location will reach 0x00000000
after reaching the maximum value 0xFFFFFFFF.
 A battery is used to protect the memory for long period
The system component responsible for keeping track of time. RTC holds information like current
time (In hour, minutes and seconds) in 12 hour /24 hour format, date, month, year, day of the
week etc and supplies timing reference to the system. RTC is intended to function even in the
absence of power. RTCs are available in the form of Integrated Circuits from different
semiconductor manufacturers like Maxim/Dallas, ST Microelectronics etc. The RTC chip
contains a microchip for holding the time and date related information and backup battery cell
for functioning in the absence of power, in a single IC package. The RTC chip is interfaced to
the processor or controller of the embedded system. For Operating System based embedded
devices, a timing reference is essential for synchronizing the operations of the OS kernel. The
RTC can interrupt the OS kernel by asserting the interrupt line of the processor/controller to
which the RTC interrupt line is connected. The OS kernel identifies the interrupt in terms of the
Interrupt Request (IRQ) number generated by an interrupt controller. One IRQ can be assigned
to the RTC interrupt and the kernel can perform necessary operations like system date time
updation, managing software timers etc when an RTC timer tick interrupt occurs